RE: [PATCH] OMAP3: Fix McBSP poll read and write for 32bit reg access
> -Original Message-
> From: Varadarajan, Charu Latha
> Sent: Thursday, October 15, 2009 10:59 AM
> To: Shilimkar, Santosh; linux-omap@vger.kernel.org
> Cc: Syed, Rafiuddin
> Subject: RE: [PATCH] OMAP3: Fix McBSP poll read and write for 32bit reg
> access
>
> __
>
> > > > Subject: RE: [PATCH] OMAP3: Fix McBSP poll read and write for
> > > > 32bit reg access
> > > >
> > > > Charu,
> > > >
> > > > > -Original Message-
> > > > > From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
> > > > > ow...@vger.kernel.org] On Behalf Of Varadarajan, Charu Latha
> > > > > Sent: Wednesday, October 14, 2009 3:00 PM
> > > > > To: linux-omap@vger.kernel.org
> > > > > Cc: Varadarajan, Charu Latha; Syed, Rafiuddin
> > > > > Subject: [PATCH] OMAP3: Fix McBSP poll read and write for
> > > > 32bit reg access
> > > > >
> > > > > omap_mcbsp_pollwrite and omap_mcbsp_pollread functions access
> > > > > McBSP registers as 16-bit registers.
> > > > >
> > > > > The McBSP registers (DRR_REG and DXR_REG) are limited to
> > > > > 32-bit data accesses (L4 Interconnect). 16-bit and 8-bit is
> > > > > not allowed and can corrupt register content.
> > > > >
> > > > > This patch modifies omap_mcbsp_pollwrite and
> > > > > omap_mcbsp_pollread functions to do 32 bit access for above
> > > > > mentioned McBSP registers. Data accepted by these
> > > > > functions is also modified to 32-bit.
> > > > >
> > > > > Signed-off-by: Charulatha V
> > > > > Signed-off-by: Syed Rafiuddin
> > > > > ---
> > > > > arch/arm/plat-omap/include/mach/mcbsp.h |4 +-
> > > > > arch/arm/plat-omap/mcbsp.c | 46
> > > > ++
> > > > > -
> > > > > 2 files changed, 23 insertions(+), 27 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h
> > > > b/arch/arm/plat-
> > > > > omap/include/mach/mcbsp.h
> > > > > index 7e9cae3..05b0d8d 100644
> > > > > --- a/arch/arm/plat-omap/include/mach/mcbsp.h
> > > > > +++ b/arch/arm/plat-omap/include/mach/mcbsp.h
> > > > > @@ -455,8 +455,8 @@ int
> > > > omap_mcbsp_spi_master_recv_word_poll(unsigned int
> > > > > id, u32 * word);
> > > > > void omap_mcbsp_set_spi_mode(unsigned int id, const struct
> > > > > omap_mcbsp_spi_cfg * spi_cfg);
> > > > >
> > > > > /* Polled read/write functions */
> > > > > -int omap_mcbsp_pollread(unsigned int id, u16 * buf);
> > > > > -int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
> > > > > +int omap_mcbsp_pollread(unsigned int id, u32 *buf);
> > > > > +int omap_mcbsp_pollwrite(unsigned int id, u32 buf);
> > > > If the issue is with DRR_REG and DXR_REG, why are you
> > > > changing the signature of the generic API. You can handle
> > > > these registers as a exceptions in the code.
> > > If 32 bit data could be read and written on McBSP, why should we
> restrict
> > > poll read and
> > > poll write functions only for 16 bit data read and write?
> > If these API's are only accessing the DXR and DRR regs then this is OK.
> >
> > > > > int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t
> > > > > io_type);
> > > > >
> > > > > #endif
> > > > > diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-
> omap/mcbsp.c
> > > > > index 88ac976..1f278a2 100644
> > > > > --- a/arch/arm/plat-omap/mcbsp.c
> > > > > +++ b/arch/arm/plat-omap/mcbsp.c
> > > > > @@ -613,7 +613,7 @@ void omap_mcbsp_stop(unsigned int id,
> > > > int tx, int rx)
> > > > > EXPORT_SYMBOL(omap_mcbsp_stop);
> > > > >
> > > > > /* polled mcbsp i/o operations */
> > > > > -int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
> > > > > +int omap_mcbsp_pollwrite(unsigned int id, u32 buf)
> > > > > {
> > > > > struct omap_mcbsp *mcbsp;
> > > > > void __iomem *base;
> > > > > @@ -626,26 +626,24 @@ int omap_mcbsp_pollwrite(unsigned int
> > > > id, u16 buf)
> > > > > mcbsp = id_to_mcbsp_ptr(id);
> > > > > base = mcbsp->io_base;
> > > > >
> > > > > - writew(buf, base + OMAP_MCBSP_REG_DXR1);
> > > > > + OMAP_MCBSP_WRITE(base, DXR, buf);
> > > > Why do you need this? Is writew()/readw() not doing 16 bit
> > > > operations ?
> > > The intension is to use 32 bit access and not 16 bit access
> > Use readl() / writel() then.
> >
> Yes, OMAP_MCBSP_WRITE macro makes use of readl() / writel() for OMAP3
Good!! Then get rid of this macro and directly use kernel standard API- readl()
/ writel()
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RE: [PATCH] OMAP3: Fix McBSP poll read and write for 32bit reg access
> > -Original Message-
> > From: linux-omap-ow...@vger.kernel.org
> > [mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of vimal singh
> > Sent: Wednesday, October 14, 2009 3:23 PM
> > To: Varadarajan, Charu Latha
> > Cc: linux-omap@vger.kernel.org; Syed, Rafiuddin
> > Subject: Re: [PATCH] OMAP3: Fix McBSP poll read and write for
> > 32bit reg access
> >
> > On Wed, Oct 14, 2009 at 3:00 PM, wrote:
> > > omap_mcbsp_pollwrite and omap_mcbsp_pollread functions access
> > > McBSP registers as 16-bit registers.
> > >
> > > The McBSP registers (DRR_REG and DXR_REG) are limited to
> > > 32-bit data accesses (L4 Interconnect). 16-bit and 8-bit is
> > > not allowed and can corrupt register content.
> > >
> > > This patch modifies omap_mcbsp_pollwrite and
> > > omap_mcbsp_pollread functions to do 32 bit access for above
> > > mentioned McBSP registers. Data accepted by these
> > > functions is also modified to 32-bit.
> > >
> > > Signed-off-by: Charulatha V
> > > Signed-off-by: Syed Rafiuddin
> > > ---
> > > arch/arm/plat-omap/include/mach/mcbsp.h |4 +-
> > > arch/arm/plat-omap/mcbsp.c | 46
> > ++-
> > > 2 files changed, 23 insertions(+), 27 deletions(-)
> > >
> > > diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h
> > b/arch/arm/plat-omap/include/mach/mcbsp.h
> > > index 7e9cae3..05b0d8d 100644
> > > --- a/arch/arm/plat-omap/include/mach/mcbsp.h
> > > +++ b/arch/arm/plat-omap/include/mach/mcbsp.h
> > > @@ -455,8 +455,8 @@ int
> > omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
> > > void omap_mcbsp_set_spi_mode(unsigned int id, const struct
> > omap_mcbsp_spi_cfg * spi_cfg);
> > >
> > > /* Polled read/write functions */
> > > -int omap_mcbsp_pollread(unsigned int id, u16 * buf);
> > > -int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
> > > +int omap_mcbsp_pollread(unsigned int id, u32 *buf);
> > > +int omap_mcbsp_pollwrite(unsigned int id, u32 buf);
> > > int omap_mcbsp_set_io_type(unsigned int id,
> > omap_mcbsp_io_type_t io_type);
> > >
> > > #endif
> > > diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
> > > index 88ac976..1f278a2 100644
> > > --- a/arch/arm/plat-omap/mcbsp.c
> > > +++ b/arch/arm/plat-omap/mcbsp.c
> > > @@ -613,7 +613,7 @@ void omap_mcbsp_stop(unsigned int id,
> > int tx, int rx)
> > > EXPORT_SYMBOL(omap_mcbsp_stop);
> > >
> > > /* polled mcbsp i/o operations */
> > > -int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
> > > +int omap_mcbsp_pollwrite(unsigned int id, u32 buf)
> > > {
> > >struct omap_mcbsp *mcbsp;
> > >void __iomem *base;
> > > @@ -626,26 +626,24 @@ int omap_mcbsp_pollwrite(unsigned int
> > id, u16 buf)
> > >mcbsp = id_to_mcbsp_ptr(id);
> > >base = mcbsp->io_base;
> > >
> > > - writew(buf, base + OMAP_MCBSP_REG_DXR1);
> > > + OMAP_MCBSP_WRITE(base, DXR, buf);
> > >/* if frame sync error - clear the error */
> > > - if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
> > > + if (OMAP_MCBSP_READ(base, SPCR2) & XSYNC_ERR) {
> > >/* clear error */
> > > - writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
> > (~XSYNC_ERR),
> > > - base + OMAP_MCBSP_REG_SPCR2);
> > > + OMAP_MCBSP_WRITE(base, SPCR2,
> > OMAP_MCBSP_READ(base , SPCR2)
> >
> > remove extra space: 'base ,'
> > checkpatch.pl should catch these kind of issues.
checkpatch.pl has not captured this error
Anyways, I will modify the same in my next version of patch
> >
> > -vimal
> >
> > > + & (~XSYNC_ERR));
> > >/* resend */
> > >return -1;
> > >} else {
> > >/* wait for transmit confirmation */
> > >int attemps = 0;
> > > - while (!(readw(base + OMAP_MCBSP_REG_SPCR2)
> > & XRDY)) {
> > > + while (!(OMAP_MCBSP_READ(base, SPCR2) & XRDY)) {
> > >if (attemps++ > 1000) {
> > > - writew(readw(base +
> > OMAP_MCBSP_REG_SPCR2) &
> > > - (~XRST),
> > > - base + OMAP_MCBSP_REG_SPCR2);
> > > + OMAP_MCBSP_WRITE(base, SPCR2,
> > > +
> > OMAP_MCBSP_READ(base, SPCR2) & (~XRST));
> > >udelay(10);
> > > - writew(readw(base +
> > OMAP_MCBSP_REG_SPCR2) |
> > > - (XRST),
> > > - base + OMAP_MCBSP_REG_SPCR2);
> > > + OMAP_MCBSP_WRITE(base, SPCR2,
> > > +
> > OMAP_MCBSP_READ(base, SPCR2) | (XRST));
> > >udelay(10);
> > >dev_err(mcbsp->dev, "Could
> > not write to"
> > >" McBSP%d
> > Register\n", mcbsp->id);
> > > @@ -658,7 +656,7 @@ int omap_mcbsp_pollwr
RE: [PATCH] OMAP3: Fix McBSP poll read and write for 32bit reg access
__
> > > Subject: RE: [PATCH] OMAP3: Fix McBSP poll read and write for
> > > 32bit reg access
> > >
> > > Charu,
> > >
> > > > -Original Message-
> > > > From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
> > > > ow...@vger.kernel.org] On Behalf Of Varadarajan, Charu Latha
> > > > Sent: Wednesday, October 14, 2009 3:00 PM
> > > > To: linux-omap@vger.kernel.org
> > > > Cc: Varadarajan, Charu Latha; Syed, Rafiuddin
> > > > Subject: [PATCH] OMAP3: Fix McBSP poll read and write for
> > > 32bit reg access
> > > >
> > > > omap_mcbsp_pollwrite and omap_mcbsp_pollread functions access
> > > > McBSP registers as 16-bit registers.
> > > >
> > > > The McBSP registers (DRR_REG and DXR_REG) are limited to
> > > > 32-bit data accesses (L4 Interconnect). 16-bit and 8-bit is
> > > > not allowed and can corrupt register content.
> > > >
> > > > This patch modifies omap_mcbsp_pollwrite and
> > > > omap_mcbsp_pollread functions to do 32 bit access for above
> > > > mentioned McBSP registers. Data accepted by these
> > > > functions is also modified to 32-bit.
> > > >
> > > > Signed-off-by: Charulatha V
> > > > Signed-off-by: Syed Rafiuddin
> > > > ---
> > > > arch/arm/plat-omap/include/mach/mcbsp.h |4 +-
> > > > arch/arm/plat-omap/mcbsp.c | 46
> > > ++
> > > > -
> > > > 2 files changed, 23 insertions(+), 27 deletions(-)
> > > >
> > > > diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h
> > > b/arch/arm/plat-
> > > > omap/include/mach/mcbsp.h
> > > > index 7e9cae3..05b0d8d 100644
> > > > --- a/arch/arm/plat-omap/include/mach/mcbsp.h
> > > > +++ b/arch/arm/plat-omap/include/mach/mcbsp.h
> > > > @@ -455,8 +455,8 @@ int
> > > omap_mcbsp_spi_master_recv_word_poll(unsigned int
> > > > id, u32 * word);
> > > > void omap_mcbsp_set_spi_mode(unsigned int id, const struct
> > > > omap_mcbsp_spi_cfg * spi_cfg);
> > > >
> > > > /* Polled read/write functions */
> > > > -int omap_mcbsp_pollread(unsigned int id, u16 * buf);
> > > > -int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
> > > > +int omap_mcbsp_pollread(unsigned int id, u32 *buf);
> > > > +int omap_mcbsp_pollwrite(unsigned int id, u32 buf);
> > > If the issue is with DRR_REG and DXR_REG, why are you
> > > changing the signature of the generic API. You can handle
> > > these registers as a exceptions in the code.
> > If 32 bit data could be read and written on McBSP, why should we restrict
> > poll read and
> > poll write functions only for 16 bit data read and write?
> If these API's are only accessing the DXR and DRR regs then this is OK.
>
> > > > int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t
> > > > io_type);
> > > >
> > > > #endif
> > > > diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
> > > > index 88ac976..1f278a2 100644
> > > > --- a/arch/arm/plat-omap/mcbsp.c
> > > > +++ b/arch/arm/plat-omap/mcbsp.c
> > > > @@ -613,7 +613,7 @@ void omap_mcbsp_stop(unsigned int id,
> > > int tx, int rx)
> > > > EXPORT_SYMBOL(omap_mcbsp_stop);
> > > >
> > > > /* polled mcbsp i/o operations */
> > > > -int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
> > > > +int omap_mcbsp_pollwrite(unsigned int id, u32 buf)
> > > > {
> > > > struct omap_mcbsp *mcbsp;
> > > > void __iomem *base;
> > > > @@ -626,26 +626,24 @@ int omap_mcbsp_pollwrite(unsigned int
> > > id, u16 buf)
> > > > mcbsp = id_to_mcbsp_ptr(id);
> > > > base = mcbsp->io_base;
> > > >
> > > > - writew(buf, base + OMAP_MCBSP_REG_DXR1);
> > > > + OMAP_MCBSP_WRITE(base, DXR, buf);
> > > Why do you need this? Is writew()/readw() not doing 16 bit
> > > operations ?
> > The intension is to use 32 bit access and not 16 bit access
> Use readl() / writel() then.
>
Yes, OMAP_MCBSP_WRITE macro makes use of readl() / writel() for OMAP3
> > > > /* if frame sync error - clear the error */
> > > > - if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
> > > > + if (OMAP_MCBSP_READ(base, SPCR2) & XSYNC_ERR) {
> > > > /* clear error */
> > > > - writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
> > > (~XSYNC_ERR),
> > > > - base + OMAP_MCBSP_REG_SPCR2);
> > > > + OMAP_MCBSP_WRITE(base, SPCR2,
> > > OMAP_MCBSP_READ(base , SPCR2)
> > > > + & (~XSYNC_ERR));
> > > > /* resend */
> > > > return -1;
> > > > } else {
> > > > /* wait for transmit confirmation */
> > > > int attemps = 0;
> > > > - while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
> > > > + while (!(OMAP_MCBSP_READ(base, SPCR2) & XRDY)) {
> > > > if (attemps++ > 1000) {
> > > > - writew(readw(base +
> > > OMAP_MCBSP_REG_SPCR2) &
> > > > - (~XRST),
> > > > - base + OMAP_MCBSP_REG_SPCR2);
> > > > + OMAP_MCBSP_WRITE(base, SPCR2,
> > > > +
RE: [PATCH] ARM: OMAP: SDMA: Fix omap_stop_dma() API for channel linking
> -Original Message-
> From: Tony Lindgren [mailto:t...@atomide.com]
> Sent: Wednesday, October 14, 2009 10:36 PM
> To: Shilimkar, Santosh
> Cc: linux-omap@vger.kernel.org; S, Venkatraman; Hari n; Jarkko Nikula
> Subject: Re: [PATCH] ARM: OMAP: SDMA: Fix omap_stop_dma() API for channel
> linking
>
> * Santosh Shilimkar [091013 23:14]:
> > OMAP sDMA driver API omap_stop_dma() doesn't really stop the dma when
> used
> > in linking scenario. This patch fixes the same.
>
> To me it looks like this will break things for omap1 as the DMA channel
> interrupt is not disabled first. I guess the fix is to move the
> "Disable all interrupts on the channel" part above clearing the
> link mappings.
Indeed it will break OMAP1. Initially I thought of putting this change at this
place so that it takes care of both normal and linking scenario.
I will rework this and send v2.
> This fix should be tested in linux-omap before we send this to mainline.
Yes ofcourse. That what I meant by merge.
> > Signed-off-by: Santosh Shilimkar
> > Signed-off-by: Venkatraman S
> > CC: Hari n
> > CC: Jarkko Nikula
> > ---
> > arch/arm/plat-omap/dma.c |9 +
> > 1 files changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
> > index fd3154a..633c123 100644
> > --- a/arch/arm/plat-omap/dma.c
> > +++ b/arch/arm/plat-omap/dma.c
> > @@ -975,6 +975,11 @@ void omap_stop_dma(int lch)
> > {
> > u32 l;
> >
> > + /* Disable the DMA channel */
> > + l = dma_read(CCR(lch));
> > + l &= ~OMAP_DMA_CCR_EN;
> > + dma_write(l, CCR(lch));
> > +
> > if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
> > int next_lch, cur_lch = lch;
> > char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
> > @@ -1000,10 +1005,6 @@ void omap_stop_dma(int lch)
> > if (cpu_class_is_omap1())
> > dma_write(0, CICR(lch));
> >
> > - l = dma_read(CCR(lch));
> > - l &= ~OMAP_DMA_CCR_EN;
> > - dma_write(l, CCR(lch));
> > -
> > dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
> > }
> > EXPORT_SYMBOL(omap_stop_dma);
> > --
> > 1.5.4.7
> >
Regards,
Santosh
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RE: SMP: BUG with PREEMPT enabled
> -Original Message- > From: Russell King - ARM Linux [mailto:li...@arm.linux.org.uk] > Sent: Thursday, October 15, 2009 1:44 AM > To: Shilimkar, Santosh > Cc: linux-omap@vger.kernel.org; linux-arm-ker...@lists.infradead.org > Subject: Re: SMP: BUG with PREEMPT enabled > > On Wed, Oct 14, 2009 at 04:56:18PM +0530, Shilimkar, Santosh wrote: > > Here is the patch I used to fix this BUG. > > Patch is good. Could you send it to the patch system. Please note that > the patch system now almost accepts standard patch submissions (in other > words, it no longer requires the "PATCH FOLLOWS" tag.) However, it still > requires the "KernelVersion:" tag to appear somewhere before the patch. Sure !! Regards, Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] omap fixes for v2.6.32-rc4
Linus, Please pull omap fixes from: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git omap-fixes-for-linus Regards, Tony The following changes since commit 161291396e76e0832c08f617eb9bd364d1648148: Linus Torvalds (1): Linux 2.6.32-rc4 are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git omap-fixes-for-linus Aaro Koskinen (1): omap: RX-51: Drop I2C-1 speed to 2200 Anuj Aggarwal (1): omap: SDMA: Fixing bug in omap_dma_set_global_params() Jarkko Nikula (1): omap: McBSP: Fix incorrect receiver stop in omap_mcbsp_stop Kalle Jokiniemi (1): OMAP: Fix race condition with autodeps Paul Walmsley (1): OMAP2xxx clock: set up clockdomain pointer in struct clk Sanjeev Premi (1): omap: CONFIG_ISP1301_OMAP redefined in Beagle defconfig Teerth Reddy (1): omap: Initialization of SDRC params on Zoom2 Tony Lindgren (1): Merge branch '2_6_32rc4_fixes' of git://git.pwsan.com/linux-2.6 into omap-fixes-for-linus arch/arm/configs/omap3_beagle_defconfig |1 - arch/arm/mach-omap2/board-rx51-peripherals.c |2 +- arch/arm/mach-omap2/board-zoom2.c|4 +- arch/arm/mach-omap2/clock24xx.c |1 + arch/arm/mach-omap2/clockdomain.c| 74 +++-- arch/arm/plat-omap/dma.c | 15 +++-- arch/arm/plat-omap/mcbsp.c |2 +- 7 files changed, 59 insertions(+), 40 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] OMAP clock and clockdomain fixes for 2.6.29-rc5
* Paul Walmsley [091014 15:36]: > Hello, > > This series contains: > > - one OMAP2 clock fix that allows N800 to boot further (there are unrelated > problems with both the current linux-omap head and omap-fixes branch that > cause booting to fail due to other reasons), and > > - one OMAP2/3 clockdomain fix that can cause clockdomain transitions to be > missed by the clockdomain code -- this mostly affects OMAP3 OFF mode. > > These patches are also available as a git branch (based on Tony's omap-fixes > branch) from > > git://git.pwsan.com/linux-2.6 2_6_32rc4_fixes I've pulled these on top of the fixes I posted yesterday. Regards, Tony > > - Paul > > --- > > Kalle Jokiniemi (1): > OMAP: Fix race condition with autodeps > > Paul Walmsley (1): > OMAP2xxx clock: set up clockdomain pointer in struct clk > > > arch/arm/mach-omap2/clock24xx.c |1 + > arch/arm/mach-omap2/clockdomain.c | 74 > ++--- > 2 files changed, 45 insertions(+), 30 deletions(-) > > size: >text data bss dec hex filename > 3588474198624 105152 3892250 3b641a vmlinux.omap3beagle.orig > 3588562198624 105152 3892338 3b6472 vmlinux.omap3beagle.patched > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/17] Massive OMAP730/OMAP850 cleanup
* Alistair Buxton [091014 17:13]: > 2009/10/14 Tony Lindgren : > > * Alistair Buxton [091014 13:03]: > >> Reposting the full series for review. Assuming this is all OK would it > >> be a good idea to merge the config variables into a single > >> CONFIG_ARCH_OMAP7XX? There doesn't seem to be any reason to have both. > >> Original description follows. > > > > Yeah, those should be merged too. Let's do that as a separate patch. > > On a related note, the omap850.h and omap730.h should go away too, > when everyone is happy with the new omap7xx.h. Perhaps we should add a > #warning to them so people know they will be removed at some point? OK, let's do that, but let's first get all the recently posted patches merged into the omap for-next branch. After that we can have some static commit on which to create more patches. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/17] Massive OMAP730/OMAP850 cleanup
2009/10/14 Tony Lindgren : > * Alistair Buxton [091014 13:03]: >> Reposting the full series for review. Assuming this is all OK would it >> be a good idea to merge the config variables into a single >> CONFIG_ARCH_OMAP7XX? There doesn't seem to be any reason to have both. >> Original description follows. > > Yeah, those should be merged too. Let's do that as a separate patch. On a related note, the omap850.h and omap730.h should go away too, when everyone is happy with the new omap7xx.h. Perhaps we should add a #warning to them so people know they will be removed at some point? -- Alistair Buxton a.j.bux...@gmail.com -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] OMAP clock and clockdomain fixes for 2.6.29-rc5
Time for a subject line correction of my own: Kevin kindly pointed out that the subject should read "2.6.32-rc5" - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] OMAP3: PM: Fix for MPU power domain MEM BANK position
Hi Thara,
I regret the delay. A comment:
On Fri, 28 Aug 2009, Thara Gopinath wrote:
> MPU power domain bank 0 bits are displayed in position of bank 1
> in PWRSTS and PREPWRSTS registers. So read them from correct
> position
Indeed. What do you think about a slightly different approach: changing
powerdomains34xx.h to be correct? In other words, instead of
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET,
},
.pwrsts_mem_on= {
[0] = PWRSTS_OFF_ON,
},
we would use:
.pwrsts_mem_ret = {
[1] = PWRSTS_OFF_RET,
},
.pwrsts_mem_on= {
[1] = PWRSTS_OFF_ON,
},
We have to deal with the bank count field in struct powerdomain - we could
just convert it into a bitmap representing available banks. So instead
of:
.banks = 1,
use maybe:
.banks = PWRDM_BANK_1, /* | PWRDM_BANK_0, etc */
Can you foresee any problems with the above approach?
- Paul
> Patch refresh issue.
>
> arch/arm/mach-omap2/powerdomain.c | 19 +++
> 1 files changed, 19 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/powerdomain.c
> b/arch/arm/mach-omap2/powerdomain.c
> index 2594cbf..6c5fee9 100644
> --- a/arch/arm/mach-omap2/powerdomain.c
> +++ b/arch/arm/mach-omap2/powerdomain.c
> @@ -971,6 +971,16 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8
> bank)
> return -EEXIST;
>
> /*
> + * In 3430, for MPU domain bank 0 status bits
> + * are displayed in the position of bank1 status bits
> + * in PWST . So the hack. Think of a cleaner
> + * way of doing this
> + */
> + if (cpu_is_omap34xx())
> + if (!strcmp("mpu_pwrdm", pwrdm->name))
> + bank = 1;
> +
> + /*
>* The register bit names below may not correspond to the
>* actual names of the bits in each powerdomain's register,
>* but the type of value returned is the same for each
> @@ -1018,6 +1028,15 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain
> *pwrdm, u8 bank)
> return -EEXIST;
>
> /*
> + * In 3430, for MPU domain bank 0 status bits
> + * are displayed in the position of bank1 status bits
> + * in PREPWST . So the hack. Think of a cleaner
> + * way of doing this
> + */
> + if (cpu_is_omap34xx())
> + if (!strcmp("mpu_pwrdm", pwrdm->name))
> + bank = 1;
> + /*
>* The register bit names below may not correspond to the
>* actual names of the bits in each powerdomain's register,
>* but the type of value returned is the same for each
> --
> 1.5.4.7
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
- Paul
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Re: [PATCH 1/6] omap: headers: Add mach patch to include files
* Tony Lindgren [091014 14:55]: > This is to prepare for moving hardware.h to live under plat > instead of mach. The subject should say "add mach path" instead of "add mach patch".. > Signed-off-by: Tony Lindgren > --- > > arch/arm/plat-omap/include/mach/hardware.h | 12 ++-- > 1 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/plat-omap/include/mach/hardware.h > b/arch/arm/plat-omap/include/mach/hardware.h > index 26c1fbf..f746c9d 100644 > --- a/arch/arm/plat-omap/include/mach/hardware.h > +++ b/arch/arm/plat-omap/include/mach/hardware.h > @@ -280,11 +280,11 @@ > * > --- > */ > > -#include "omap730.h" > -#include "omap1510.h" > -#include "omap16xx.h" > -#include "omap24xx.h" > -#include "omap34xx.h" > -#include "omap44xx.h" > +#include > +#include > +#include > +#include > +#include > +#include > > #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] OMAP2xxx clock: set up clockdomain pointer in struct clk
clock24xx.c is missing a omap2_init_clk_clkdm() in its
omap2_clk_init() function. Among other bad effects, this causes the
OMAP hwmod layer to oops on boot.
Thanks to Carlos Aguiar and Stefano
Panella for reporting this bug. Thanks to Tony
Lindgren for N800 booting advice.
Signed-off-by: Paul Walmsley
Cc: Carlos Aguiar
Cc: Stefano Panella
Cc: Tony Lindgren
---
arch/arm/mach-omap2/clock24xx.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index bc5d3ac..e2dbedd 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -769,6 +769,7 @@ int __init omap2_clk_init(void)
if (c->cpu & cpu_mask) {
clkdev_add(&c->lk);
clk_register(c->lk.clk);
+ omap2_init_clk_clkdm(c->lk.clk);
}
/* Check the MPU rate set by bootloader */
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[PATCH 0/2] OMAP clock and clockdomain fixes for 2.6.29-rc5
Hello, This series contains: - one OMAP2 clock fix that allows N800 to boot further (there are unrelated problems with both the current linux-omap head and omap-fixes branch that cause booting to fail due to other reasons), and - one OMAP2/3 clockdomain fix that can cause clockdomain transitions to be missed by the clockdomain code -- this mostly affects OMAP3 OFF mode. These patches are also available as a git branch (based on Tony's omap-fixes branch) from git://git.pwsan.com/linux-2.6 2_6_32rc4_fixes - Paul --- Kalle Jokiniemi (1): OMAP: Fix race condition with autodeps Paul Walmsley (1): OMAP2xxx clock: set up clockdomain pointer in struct clk arch/arm/mach-omap2/clock24xx.c |1 + arch/arm/mach-omap2/clockdomain.c | 74 ++--- 2 files changed, 45 insertions(+), 30 deletions(-) size: textdata bss dec hex filename 3588474 198624 105152 3892250 3b641a vmlinux.omap3beagle.orig 3588562 198624 105152 3892338 3b6472 vmlinux.omap3beagle.patched -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] OMAP: Fix race condition with autodeps
From: Kalle Jokiniemi
There is a possible race condition in clockdomain
code handling hw supported idle transitions.
When multiple autodeps dependencies are being added
or removed, a transition of still remaining dependent
powerdomain can result in false readings of the
state counter. This is especially fatal for off mode
state counter, as it could result in a driver not
noticing a context loss.
Fixed by disabling hw supported state transitions
when autodeps are being changed.
Signed-off-by: Kalle Jokiniemi
Signed-off-by: Paul Walmsley
---
arch/arm/mach-omap2/clockdomain.c | 74 ++---
1 files changed, 44 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index 4ef7b4f..58aff84 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -137,6 +137,36 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
}
}
+/*
+ * _omap2_clkdm_set_hwsup - set the hwsup idle transition bit
+ * @clkdm: struct clockdomain *
+ * @enable: int 0 to disable, 1 to enable
+ *
+ * Internal helper for actually switching the bit that controls hwsup
+ * idle transitions for clkdm.
+ */
+static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
+{
+ u32 v;
+
+ if (cpu_is_omap24xx()) {
+ if (enable)
+ v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
+ else
+ v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
+ } else if (cpu_is_omap34xx()) {
+ if (enable)
+ v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
+ else
+ v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
+ } else {
+ BUG();
+ }
+
+ cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
+ v << __ffs(clkdm->clktrctrl_mask),
+ clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
+}
static struct clockdomain *_clkdm_lookup(const char *name)
{
@@ -456,8 +486,6 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
*/
void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
{
- u32 v;
-
if (!clkdm)
return;
@@ -473,18 +501,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_add_autodeps(clkdm);
- if (cpu_is_omap24xx())
- v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
- else if (cpu_is_omap34xx())
- v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
- else
- BUG();
-
-
- cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
- v << __ffs(clkdm->clktrctrl_mask),
- clkdm->pwrdm.ptr->prcm_offs,
- CM_CLKSTCTRL);
+ _omap2_clkdm_set_hwsup(clkdm, 1);
pwrdm_clkdm_state_switch(clkdm);
}
@@ -500,8 +517,6 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
*/
void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
{
- u32 v;
-
if (!clkdm)
return;
@@ -514,16 +529,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
clkdm->name);
- if (cpu_is_omap24xx())
- v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
- else if (cpu_is_omap34xx())
- v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
- else
- BUG();
-
- cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
- v << __ffs(clkdm->clktrctrl_mask),
- clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
+ _omap2_clkdm_set_hwsup(clkdm, 0);
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_del_autodeps(clkdm);
@@ -569,10 +575,14 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm,
struct clk *clk)
v = omap2_clkdm_clktrctrl_read(clkdm);
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
- (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
+ (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
+ /* Disable HW transitions when we are changing deps */
+ _omap2_clkdm_set_hwsup(clkdm, 0);
_clkdm_add_autodeps(clkdm);
- else
+ _omap2_clkdm_set_hwsup(clkdm, 1);
+ } else {
omap2_clkdm_wakeup(clkdm);
+ }
pwrdm_wait_transition(clkdm->pwrdm.ptr);
pwrdm_clkdm_state_switch(clkdm);
@@ -623,10 +633,14 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm,
struct clk *clk)
v = omap2_clkdm_clktrctrl_read(clkdm);
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
- (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
+ (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
+ /* Disable HW transitio
Re: [PATCH 08/27] OMAP3: PM: handle PER/NEON/CORE in idle
* Kevin Hilman [091014 15:15]:
> From: Rajendra Nayak
Might be worth checking the descriptions in the whole series :)
> Signed-off-by: Rajendra Nayak
> Signed-off-by: Kevin Hilman
> ---
> arch/arm/mach-omap2/pm34xx.c | 64 +++--
> 1 files changed, 54 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 9dbb5a0..7eab539 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -49,7 +49,10 @@ static LIST_HEAD(pwrst_list);
>
> static void (*_omap_sram_idle)(u32 *addr, int save_state);
>
> -static struct powerdomain *mpu_pwrdm;
> +static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
> +static struct powerdomain *core_pwrdm, *per_pwrdm;
> +
> +static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
>
> /*
> * PRCM Interrupt Handler Helper Function
> @@ -169,13 +172,22 @@ static void omap_sram_idle(void)
> /* save_state = 1 => Only L1 and logic lost */
> /* save_state = 2 => Only L2 lost */
> /* save_state = 3 => L1, L2 and logic lost */
> - int save_state = 0, mpu_next_state;
> + int save_state = 0;
> + int mpu_next_state = PWRDM_POWER_ON;
> + int per_next_state = PWRDM_POWER_ON;
> + int core_next_state = PWRDM_POWER_ON;
>
> if (!_omap_sram_idle)
> return;
>
> + pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
> + pwrdm_clear_all_prev_pwrst(neon_pwrdm);
> + pwrdm_clear_all_prev_pwrst(core_pwrdm);
> + pwrdm_clear_all_prev_pwrst(per_pwrdm);
> +
> mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
> switch (mpu_next_state) {
> + case PWRDM_POWER_ON:
> case PWRDM_POWER_RET:
> /* No need to save context */
> save_state = 0;
> @@ -187,18 +199,37 @@ static void omap_sram_idle(void)
> }
> pwrdm_pre_transition();
>
> - omap2_gpio_prepare_for_retention();
> - omap_uart_prepare_idle(0);
> - omap_uart_prepare_idle(1);
> - omap_uart_prepare_idle(2);
> + /* NEON control */
> + if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
> + set_pwrdm_state(neon_pwrdm, mpu_next_state);
> +
> + /* CORE & PER */
> + core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
> + if (core_next_state < PWRDM_POWER_ON) {
> + omap2_gpio_prepare_for_retention();
> + omap_uart_prepare_idle(0);
> + omap_uart_prepare_idle(1);
> + /* PER changes only with core */
> + per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
> + if (per_next_state < PWRDM_POWER_ON)
> + omap_uart_prepare_idle(2);
> + /* Enable IO-PAD wakeup */
> + prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
> + }
>
> _omap_sram_idle(NULL, save_state);
> cpu_init();
>
> - omap_uart_resume_idle(2);
> - omap_uart_resume_idle(1);
> - omap_uart_resume_idle(0);
> - omap2_gpio_resume_after_retention();
> + if (core_next_state < PWRDM_POWER_ON) {
> + if (per_next_state < PWRDM_POWER_ON)
> + omap_uart_resume_idle(2);
> + omap_uart_resume_idle(1);
> + omap_uart_resume_idle(0);
> +
> + /* Disable IO-PAD wakeup */
> + prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
> + omap2_gpio_resume_after_retention();
> + }
>
> pwrdm_post_transition();
>
> @@ -791,6 +822,10 @@ static int __init omap3_pm_init(void)
> goto err2;
> }
>
> + neon_pwrdm = pwrdm_lookup("neon_pwrdm");
> + per_pwrdm = pwrdm_lookup("per_pwrdm");
> + core_pwrdm = pwrdm_lookup("core_pwrdm");
> +
> omap_push_sram_idle();
> #ifdef CONFIG_SUSPEND
> suspend_set_ops(&omap_pm_ops);
> @@ -798,6 +833,15 @@ static int __init omap3_pm_init(void)
>
> pm_idle = omap3_pm_idle;
>
> + pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
> + /*
> + * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
> + * IO-pad wakeup. Otherwise it will unnecessarily waste power
> + * waking up PER with every CORE wakeup - see
> + * http://marc.info/?l=linux-omap&m=121852150710062&w=2
> + */
> + pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
> +
> err1:
> return ret;
> err2:
> --
> 1.6.4.3
>
>
> ___
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Re: [PATCH 07/27] OMAP3: PM: SRAM restore function
* Kevin Hilman [091014 15:09]:
> From: Rajendra Nayak
Description missing here.
> Signed-off-by: Rajendra Nayak
> Signed-off-by: Kevin Hilman
> ---
> arch/arm/mach-omap2/pm34xx.c | 10 +++---
> arch/arm/plat-omap/include/mach/sram.h |1 +
> arch/arm/plat-omap/sram.c |6 +++---
> 3 files changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 378c2f6..9dbb5a0 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -748,6 +748,12 @@ static int __init clkdms_setup(struct clockdomain
> *clkdm, void *unused)
> return 0;
> }
>
> +void omap_push_sram_idle(void)
> +{
> + _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
> + omap34xx_cpu_suspend_sz);
> +}
> +
> static int __init omap3_pm_init(void)
> {
> struct power_state *pwrst, *tmp;
> @@ -785,9 +791,7 @@ static int __init omap3_pm_init(void)
> goto err2;
> }
>
> - _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
> - omap34xx_cpu_suspend_sz);
> -
> + omap_push_sram_idle();
> #ifdef CONFIG_SUSPEND
> suspend_set_ops(&omap_pm_ops);
> #endif /* CONFIG_SUSPEND */
> diff --git a/arch/arm/plat-omap/include/mach/sram.h
> b/arch/arm/plat-omap/include/mach/sram.h
> index 8974e3f..a943014 100644
> --- a/arch/arm/plat-omap/include/mach/sram.h
> +++ b/arch/arm/plat-omap/include/mach/sram.h
> @@ -67,5 +67,6 @@ extern u32 omap3_sram_configure_core_dpll(
> u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
> extern unsigned long omap3_sram_configure_core_dpll_sz;
> +extern void omap_push_sram_idle(void);
>
> #endif
> diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
> index 4144f81..b20ec87 100644
> --- a/arch/arm/plat-omap/sram.c
> +++ b/arch/arm/plat-omap/sram.c
> @@ -396,14 +396,14 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll,
> u32 f, u32 inc,
> sdrc_actim_ctrl_b_1, sdrc_mr_1);
> }
>
> -/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
> -void restore_sram_functions(void)
> +void omap3_sram_restore_context(void)
> {
> omap_sram_ceil = omap_sram_base + omap_sram_size;
>
> _omap3_sram_configure_core_dpll =
> omap_sram_push(omap3_sram_configure_core_dpll,
> omap3_sram_configure_core_dpll_sz);
> + omap_push_sram_idle();
> }
>
> int __init omap34xx_sram_init(void)
> @@ -411,7 +411,7 @@ int __init omap34xx_sram_init(void)
> _omap3_sram_configure_core_dpll =
> omap_sram_push(omap3_sram_configure_core_dpll,
> omap3_sram_configure_core_dpll_sz);
> -
> + omap_push_sram_idle();
> return 0;
> }
> #else
> --
> 1.6.4.3
>
>
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Re: [PATCH 03/27] OMAP3: PM: INTC context save/restore
* Kevin Hilman [091014 15:10]:
> From: Rajendra Nayak
>
> Signed-off-by: Rajendra Nayak
> Signed-off-by: Kevin Hilman
> ---
> arch/arm/mach-omap2/irq.c | 66
>
> arch/arm/plat-omap/include/mach/irqs.h |5 ++
> 2 files changed, 71 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
> index 8db0e3a..fa2524d 100644
> --- a/arch/arm/mach-omap2/irq.c
> +++ b/arch/arm/mach-omap2/irq.c
> @@ -25,6 +25,10 @@
> #define INTC_SYSSTATUS 0x0014
> #define INTC_SIR 0x0040
> #define INTC_CONTROL 0x0048
> +#define INTC_PROTECTION 0x004C
> +#define INTC_IDLE0x0050
> +#define INTC_THRESHOLD 0x0068
> +#define INTC_MIR00x0084
> #define INTC_MIR_CLEAR0 0x0088
> #define INTC_MIR_SET00x008c
> #define INTC_PENDING_IRQ00x0098
> @@ -48,6 +52,18 @@ static struct omap_irq_bank {
> },
> };
>
> +/* Structure to save interrupt controller context */
> +struct omap3_intc_regs {
> + u32 sysconfig;
> + u32 protection;
> + u32 idle;
> + u32 threshold;
> + u32 ilr[INTCPS_NR_IRQS];
> + u32 mir[INTCPS_NR_MIR_REGS];
> +};
> +
> +static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
> +
> /* INTC bank register get/set */
>
> static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
> @@ -201,3 +217,53 @@ void __init omap_init_irq(void)
> }
> }
>
> +#ifdef CONFIG_ARCH_OMAP3
> +void omap3_intc_save_context(void)
> +{
> + int ind = 0, i = 0;
> + for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
> + struct omap_irq_bank *bank = irq_banks + ind;
> + intc_context[ind].sysconfig =
> + intc_bank_read_reg(bank, INTC_SYSCONFIG);
> + intc_context[ind].protection =
> + intc_bank_read_reg(bank, INTC_PROTECTION);
> + intc_context[ind].idle =
> + intc_bank_read_reg(bank, INTC_IDLE);
> + intc_context[ind].threshold =
> + intc_bank_read_reg(bank, INTC_THRESHOLD);
> + for (i = 0; i < INTCPS_NR_IRQS; i++)
> + intc_context[ind].ilr[i] =
> + intc_bank_read_reg(bank, (0x100 + 0x4*ind));
> + for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
> + intc_context[ind].mir[i] =
> + intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
> + (0x20 * i));
> + }
> +}
> +
These too look like they should work on 24xx and 34xx?
> +void omap3_intc_restore_context(void)
> +{
> + int ind = 0, i = 0;
> +
> + for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
> + struct omap_irq_bank *bank = irq_banks + ind;
> + intc_bank_write_reg(intc_context[ind].sysconfig,
> + bank, INTC_SYSCONFIG);
> + intc_bank_write_reg(intc_context[ind].sysconfig,
> + bank, INTC_SYSCONFIG);
> + intc_bank_write_reg(intc_context[ind].protection,
> + bank, INTC_PROTECTION);
> + intc_bank_write_reg(intc_context[ind].idle,
> + bank, INTC_IDLE);
> + intc_bank_write_reg(intc_context[ind].threshold,
> + bank, INTC_THRESHOLD);
> + for (i = 0; i < INTCPS_NR_IRQS; i++)
> + intc_bank_write_reg(intc_context[ind].ilr[i],
> + bank, (0x100 + 0x4*ind));
> + for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
> + intc_bank_write_reg(intc_context[ind].mir[i],
> + &irq_banks[0], INTC_MIR0 + (0x20 * i));
> + }
> + /* MIRs are saved and restore with other PRCM registers */
> +}
> +#endif /* CONFIG_ARCH_OMAP3 */
> diff --git a/arch/arm/plat-omap/include/mach/irqs.h
> b/arch/arm/plat-omap/include/mach/irqs.h
> index 6a6d028..2473910 100644
> --- a/arch/arm/plat-omap/include/mach/irqs.h
> +++ b/arch/arm/plat-omap/include/mach/irqs.h
> @@ -477,9 +477,14 @@
>
> #define OMAP_IRQ_BIT(irq)(1 << ((irq) % 32))
>
> +#define INTCPS_NR_MIR_REGS 3
> +#define INTCPS_NR_IRQS 96
> +
> #ifndef __ASSEMBLY__
> extern void omap_init_irq(void);
> extern int omap_irq_pending(void);
> +void omap3_intc_save_context(void);
> +void omap3_intc_restore_context(void);
> #endif
>
> #include
> --
> 1.6.4.3
>
>
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Re: [PATCH] OMAP: PM: Export functions from OMAP NOOP PM interface
Ameya Palande writes:
> Without this patch, a driver which uses these symbols will break when user
> selects NOOP PM interface.
>
> Signed-off-by: Ameya Palande
I initially pulled this into the PM branch but will now be dropping
it.
Drivers should not be calling these functions directly, but rather using
hooks in pdata as described in Documentation/arm/OMAP/omap_pm.
Kevin
> ---
> arch/arm/plat-omap/omap-pm-noop.c |8 +++-
> 1 files changed, 7 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/plat-omap/omap-pm-noop.c
> b/arch/arm/plat-omap/omap-pm-noop.c
> index 3b075de..10463a4 100644
> --- a/arch/arm/plat-omap/omap-pm-noop.c
> +++ b/arch/arm/plat-omap/omap-pm-noop.c
> @@ -157,6 +157,7 @@ const struct omap_opp *omap_pm_dsp_get_opp_table(void)
>
> return NULL;
> }
> +EXPORT_SYMBOL(omap_pm_dsp_get_opp_table);
>
> void omap_pm_dsp_set_min_opp(u8 opp_id)
> {
> @@ -181,7 +182,7 @@ void omap_pm_dsp_set_min_opp(u8 opp_id)
>*
>*/
> }
> -
> +EXPORT_SYMBOL(omap_pm_dsp_set_min_opp);
>
> u8 omap_pm_dsp_get_opp(void)
> {
> @@ -197,6 +198,7 @@ u8 omap_pm_dsp_get_opp(void)
>
> return 0;
> }
> +EXPORT_SYMBOL(omap_pm_dsp_get_opp);
>
> u8 omap_pm_vdd1_get_opp(void)
> {
> @@ -208,6 +210,7 @@ u8 omap_pm_vdd1_get_opp(void)
>
> return 0;
> }
> +EXPORT_SYMBOL(omap_pm_vdd1_get_opp);
>
> u8 omap_pm_vdd2_get_opp(void)
> {
> @@ -219,6 +222,7 @@ u8 omap_pm_vdd2_get_opp(void)
>
> return 0;
> }
> +EXPORT_SYMBOL(omap_pm_vdd2_get_opp);
>
> /*
> * CPUFreq-originated constraint
> @@ -259,6 +263,7 @@ void omap_pm_cpu_set_freq(unsigned long f)
>* CDP should just be able to set the VDD1 OPP clock rate here.
>*/
> }
> +EXPORT_SYMBOL(omap_pm_cpu_set_freq);
>
> unsigned long omap_pm_cpu_get_freq(void)
> {
> @@ -270,6 +275,7 @@ unsigned long omap_pm_cpu_get_freq(void)
>
> return 0;
> }
> +EXPORT_SYMBOL(omap_pm_cpu_get_freq);
>
> /*
> * Device context loss tracking
> --
> 1.6.2.4
>
> --
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Re: [PATCH 02/27] OMAP3: PM: GPIO context save/restore
* Kevin Hilman [091014 15:08]:
> From: Rajendra Nayak
This one should have a description of the patch here.
Also one comment below.
> Signed-off-by: Rajendra Nayak
> Signed-off-by: Kevin Hilman
> ---
> arch/arm/plat-omap/gpio.c | 93
>
> arch/arm/plat-omap/include/mach/gpio.h |3 +-
> 2 files changed, 95 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
> index b1af0c2..48ce218 100644
> --- a/arch/arm/plat-omap/gpio.c
> +++ b/arch/arm/plat-omap/gpio.c
> @@ -260,6 +260,23 @@ static struct gpio_bank gpio_bank_34xx[6] = {
> { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
> METHOD_GPIO_24XX },
> };
>
> +struct omap3_gpio_regs {
> + u32 sysconfig;
> + u32 irqenable1;
> + u32 irqenable2;
> + u32 wake_en;
> + u32 ctrl;
> + u32 oe;
> + u32 leveldetect0;
> + u32 leveldetect1;
> + u32 risingdetect;
> + u32 fallingdetect;
> + u32 dataout;
> + u32 setwkuena;
> + u32 setdataout;
> +};
> +
> +static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
> #endif
>
> #ifdef CONFIG_ARCH_OMAP4
> @@ -2002,6 +2019,82 @@ void omap2_gpio_resume_after_retention(void)
>
> #endif
>
> +#ifdef CONFIG_ARCH_OMAP34XX
> +/* save the registers of bank 2-6 */
> +void omap3_gpio_save_context(void)
> +{
> + int i;
> +
> + /* saving banks from 2-6 only since GPIO1 is in WKUP */
> + for (i = 1; i < gpio_bank_count; i++) {
> + struct gpio_bank *bank = &gpio_bank[i];
> + gpio_context[i].sysconfig =
> + __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
> + gpio_context[i].irqenable1 =
> + __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
> + gpio_context[i].irqenable2 =
> + __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
> + gpio_context[i].wake_en =
> + __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
> + gpio_context[i].ctrl =
> + __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
> + gpio_context[i].oe =
> + __raw_readl(bank->base + OMAP24XX_GPIO_OE);
> + gpio_context[i].leveldetect0 =
> + __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
> + gpio_context[i].leveldetect1 =
> + __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
> + gpio_context[i].risingdetect =
> + __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
> + gpio_context[i].fallingdetect =
> + __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
> + gpio_context[i].dataout =
> + __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
> + gpio_context[i].setwkuena =
> + __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
> + gpio_context[i].setdataout =
> + __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
> + }
> +}
> +EXPORT_SYMBOL(omap3_gpio_save_context);
This function looks like it should work on most omaps.
Maybe it should be named just omap_gpio_save_context()?
> +
> +/* restore the required registers of bank 2-6 */
> +void omap3_gpio_restore_context(void)
> +{
> + int i;
> + for (i = 1; i < gpio_bank_count; i++) {
> + struct gpio_bank *bank = &gpio_bank[i];
> + __raw_writel(gpio_context[i].sysconfig,
> + bank->base + OMAP24XX_GPIO_SYSCONFIG);
> + __raw_writel(gpio_context[i].irqenable1,
> + bank->base + OMAP24XX_GPIO_IRQENABLE1);
> + __raw_writel(gpio_context[i].irqenable2,
> + bank->base + OMAP24XX_GPIO_IRQENABLE2);
> + __raw_writel(gpio_context[i].wake_en,
> + bank->base + OMAP24XX_GPIO_WAKE_EN);
> + __raw_writel(gpio_context[i].ctrl,
> + bank->base + OMAP24XX_GPIO_CTRL);
> + __raw_writel(gpio_context[i].oe,
> + bank->base + OMAP24XX_GPIO_OE);
> + __raw_writel(gpio_context[i].leveldetect0,
> + bank->base + OMAP24XX_GPIO_LEVELDETECT0);
> + __raw_writel(gpio_context[i].leveldetect1,
> + bank->base + OMAP24XX_GPIO_LEVELDETECT1);
> + __raw_writel(gpio_context[i].risingdetect,
> + bank->base + OMAP24XX_GPIO_RISINGDETECT);
> + __raw_writel(gpio_context[i].fallingdetect,
> + bank->base + OMAP24XX_GPIO_FALLINGDETECT);
> + __raw_writel(gpio_context[i].dataout,
> + bank->base + OMAP24XX_GPIO_DATAOUT);
> + __raw_writel(gpio_context[i].setwkuena,
> +
[PATCH 24/27] PM: Disable usb host HW save and restore
From: Kalle Jokiniemi
The hardware SAVEANDRESTORE mechanism seems to leave
USB HOST power domain permanently into active state
after one transition from off to active state.
Disabling for now.
Signed-off-by: Kalle Jokiniemi
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/powerdomains34xx.h |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h
b/arch/arm/mach-omap2/powerdomains34xx.h
index 4dcf94b..aa557b2 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -338,7 +338,13 @@ static struct powerdomain usbhost_pwrdm = {
.sleepdep_srcs= dss_per_usbhost_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
- .flags= PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */
+ /*
+* REVISIT: Enabling usb host save and restore mechanism seems to
+* leave the usb host domain permanently in ACTIVE mode after
+* changing the usb host power domain state from OFF to active once.
+* Disabling for now.
+*/
+ /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
.banks= 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
--
1.6.4.3
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[PATCH 01/27] OMAP3: PM: GPMC context save/restore
From: Rajendra Nayak
This patch adds the context save restore functions for GPMC
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/gpmc.c | 98 +++-
arch/arm/plat-omap/include/mach/gpmc.h |3 +
2 files changed, 98 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 1587682..6ae189d 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -62,6 +62,33 @@
#define ENABLE_PREFETCH(0x1 << 7)
#define DMA_MPU_MODE 2
+/* Structure to save gpmc cs context */
+struct gpmc_cs_config {
+ u32 config1;
+ u32 config2;
+ u32 config3;
+ u32 config4;
+ u32 config5;
+ u32 config6;
+ u32 config7;
+ int is_valid;
+};
+
+/*
+ * Structure to save/restore gpmc context
+ * to support core off on OMAP3
+ */
+struct omap3_gpmc_regs {
+ u32 sysconfig;
+ u32 irqenable;
+ u32 timeout_ctrl;
+ u32 config;
+ u32 prefetch_config1;
+ u32 prefetch_config2;
+ u32 prefetch_control;
+ struct gpmc_cs_config cs_context[GPMC_CS_NUM];
+};
+
static struct resource gpmc_mem_root;
static struct resource gpmc_cs_mem[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
@@ -261,7 +288,7 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
l &= ~(0x0f << 8);
l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
- l |= 1 << 6;/* CSVALID */
+ l |= GPMC_CONFIG7_CSVALID;
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}
@@ -270,7 +297,7 @@ static void gpmc_cs_disable_mem(int cs)
u32 l;
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
- l &= ~(1 << 6); /* CSVALID */
+ l &= ~GPMC_CONFIG7_CSVALID;
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}
@@ -290,7 +317,7 @@ static int gpmc_cs_mem_enabled(int cs)
u32 l;
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
- return l & (1 << 6);
+ return l & GPMC_CONFIG7_CSVALID;
}
int gpmc_cs_set_reserved(int cs, int reserved)
@@ -516,3 +543,68 @@ void __init gpmc_init(void)
gpmc_write_reg(GPMC_SYSCONFIG, l);
gpmc_mem_init();
}
+
+#ifdef CONFIG_ARCH_OMAP3
+static struct omap3_gpmc_regs gpmc_context;
+
+void omap3_gpmc_save_context()
+{
+ int i;
+ gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
+ gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
+ gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
+ gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
+ gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
+ gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
+ gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
+ for (i = 0; i < GPMC_CS_NUM; i++) {
+ gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
+ if (gpmc_context.cs_context[i].is_valid) {
+ gpmc_context.cs_context[i].config1 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
+ gpmc_context.cs_context[i].config2 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
+ gpmc_context.cs_context[i].config3 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
+ gpmc_context.cs_context[i].config4 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
+ gpmc_context.cs_context[i].config5 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
+ gpmc_context.cs_context[i].config6 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
+ gpmc_context.cs_context[i].config7 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
+ }
+ }
+}
+
+void omap3_gpmc_restore_context()
+{
+ int i;
+ gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
+ gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
+ gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
+ gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
+ gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
+ for (i = 0; i < GPMC_CS_NUM; i++) {
+ if (gpmc_context.cs_context[i].is_valid) {
+ gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
+ gpmc_context.cs_context[i].config1);
+ gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
+ gpmc_context.cs_context[i].config2);
+ gpmc_cs_wr
[PATCH 20/27] OMAP: PM: Clear DMA channel state after a wakeup
From: Aaro Koskinen
Clear DMA channel states so that users can assume a known initial state.
Signed-off-by: Aaro Koskinen
Signed-off-by: Kevin Hilman
---
arch/arm/plat-omap/dma.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index f911bfd..ee9c02a 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2358,6 +2358,8 @@ EXPORT_SYMBOL(omap_dma_global_context_save);
void omap_dma_global_context_restore(void)
{
+ int ch;
+
dma_write(omap_dma_global_context.dma_gcr, GCR);
dma_write(omap_dma_global_context.dma_ocp_sysconfig,
OCP_SYSCONFIG);
@@ -2372,6 +2374,10 @@ void omap_dma_global_context_restore(void)
*/
if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
dma_write(0x3 , IRQSTATUS_L0);
+
+ for (ch = 0; ch < dma_chan_count; ch++)
+ if (dma_chan[ch].dev_id != -1)
+ omap_clear_dma(ch);
}
EXPORT_SYMBOL(omap_dma_global_context_restore);
--
1.6.4.3
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[PATCH 27/27] PM debug: allow configurable wakeup from suspend on OMAP GPtimer
Using debugfs, export a configurable wakeup timer to be used to
wakeup system from suspend.
If a non-zero value is written to
/debug/pm_debug/wakeup_timer_seconds, A timer wakeup event will wake
the system and resume after the configured number of seconds.
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm-debug.c |2 ++
arch/arm/mach-omap2/pm.h |3 +++
arch/arm/mach-omap2/pm34xx.c | 21 +
arch/arm/mach-omap2/timer-gp.c |2 ++
4 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 4e05d29..b45d79d 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -596,6 +596,8 @@ static int __init pm_dbg_init(void)
&enable_off_mode, &pm_dbg_option_fops);
(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
&sleep_while_idle, &pm_dbg_option_fops);
+ (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
+ &wakeup_timer_seconds, &pm_dbg_option_fops);
pm_dbg_init_done = 1;
return 0;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index e47508c..c163b77 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -22,6 +22,9 @@ extern void omap3_pm_off_mode_enable(int);
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
+extern u32 wakeup_timer_seconds;
+extern struct omap_dm_timer *gptimer_wakeup;
+
#ifdef CONFIG_PM_DEBUG
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
extern int omap2_pm_debug;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 6fc..209672f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -37,6 +37,7 @@
#include
#include
#include
+#include
#include
@@ -61,6 +62,7 @@
u32 enable_off_mode;
u32 sleep_while_idle;
+u32 wakeup_timer_seconds;
struct power_state {
struct powerdomain *pwrdm;
@@ -536,6 +538,22 @@ out:
#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state;
+static void omap2_pm_wakeup_on_timer(u32 seconds)
+{
+ u32 tick_rate, cycles;
+
+ if (!seconds)
+ return;
+
+ tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
+ cycles = tick_rate * seconds;
+ omap_dm_timer_stop(gptimer_wakeup);
+ omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0x - cycles);
+
+ pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n",
+ seconds, cycles, tick_rate);
+}
+
static int omap3_pm_prepare(void)
{
disable_hlt();
@@ -547,6 +565,9 @@ static int omap3_pm_suspend(void)
struct power_state *pwrst;
int state, ret = 0;
+ if (wakeup_timer_seconds)
+ omap2_pm_wakeup_on_timer(wakeup_timer_seconds);
+
/* Read current next_pwrsts */
list_for_each_entry(pwrst, &pwrst_list, node)
pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 95a2176..9c056ff 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -47,6 +47,7 @@ static struct omap_dm_timer *gptimer;
static struct clock_event_device clockevent_gpt;
static u8 __initdata gptimer_id = 1;
static u8 __initdata inited;
+struct omap_dm_timer *gptimer_wakeup;
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
@@ -134,6 +135,7 @@ static void __init omap2_gp_clockevent_init(void)
gptimer = omap_dm_timer_request_specific(gptimer_id);
BUG_ON(gptimer == NULL);
+ gptimer_wakeup = gptimer;
#if defined(CONFIG_OMAP_32K_TIMER)
src = OMAP_TIMER_SRC_32_KHZ;
--
1.6.4.3
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[PATCH 19/27] OMAP3: PM: Fix PLL_MOD CLKEN offset in scratchpad
From: Kalle Jokiniemi The CM_CLKEN_PLL register saved in scratchpad memory was wrongly using offset of 0x0004 instead of 0x. The effect of this was that boot ROM code would restore the wrong value when waking up from off mode. This wrong value, however, will be overwritten by prcm context restore. Still, a short period of wrong clock settings in CM_CLKEN_PLL remained between ROM code and prcm context restore. This is fixed by the patch. Problem reported by: Jouni Högander Signed-off-by: Kalle Jokiniemi Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/control.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 6c462c7..50b3afc 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -228,7 +228,7 @@ void omap3_save_scratchpad_contents(void) prcm_block_contents.cm_clksel_wkup = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); prcm_block_contents.cm_clken_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKEN_PLL); + cm_read_mod_reg(PLL_MOD, CM_CLKEN); prcm_block_contents.cm_autoidle_pll = cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); prcm_block_contents.cm_clksel1_pll = -- 1.6.4.3 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 18/27] ARM: OMAP: Add missing SMS_SYSCONFIG save/restore
From: Kalle Jokiniemi
SMS_SYSCONFIG register gets reset in off mode, added
a save/restore mechanism for that.
Signed-off-by: Kalle Jokiniemi
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm34xx.c |1 +
arch/arm/mach-omap2/sdrc.c | 27 +++
arch/arm/plat-omap/include/mach/sdrc.h |2 ++
3 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 93f5988..80934c3 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -400,6 +400,7 @@ static void omap_sram_idle(void)
omap3_core_restore_context();
omap3_prcm_restore_context();
omap3_sram_restore_context();
+ omap2_sms_restore_context();
}
if (per_next_state < PWRDM_POWER_ON) {
per_prev_state =
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 9e3bd4f..1a4f132 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -37,12 +37,38 @@ static struct omap_sdrc_params *sdrc_init_params_cs0,
*sdrc_init_params_cs1;
void __iomem *omap2_sdrc_base;
void __iomem *omap2_sms_base;
+struct omap2_sms_regs {
+ u32 sms_sysconfig;
+};
+
+static struct omap2_sms_regs sms_context;
+
/* SDRC_POWER register bits */
#define SDRC_POWER_EXTCLKDIS_SHIFT 3
#define SDRC_POWER_PWDENA_SHIFT2
#define SDRC_POWER_PAGEPOLICY_SHIFT0
/**
+ * omap2_sms_save_context - Save SMS registers
+ *
+ * Save SMS registers that need to be restored after off mode.
+ */
+void omap2_sms_save_context(void)
+{
+ sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
+}
+
+/**
+ * omap2_sms_restore_context - Restore SMS registers
+ *
+ * Restore SMS registers that need to be Restored after off mode.
+ */
+void omap2_sms_restore_context(void)
+{
+ sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
+}
+
+/**
* omap2_sdrc_get_params - return SDRC register values for a given clock rate
* @r: SDRC clock rate (in Hz)
* @sdrc_cs0: chip select 0 ram timings **
@@ -132,4 +158,5 @@ void __init omap2_sdrc_init(struct omap_sdrc_params
*sdrc_cs0,
l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
sdrc_write_reg(l, SDRC_POWER);
+ omap2_sms_save_context();
}
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h
b/arch/arm/plat-omap/include/mach/sdrc.h
index 7b58a5f..772b71e 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -120,6 +120,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params
*sdrc_cs0,
int omap2_sdrc_get_params(unsigned long r,
struct omap_sdrc_params **sdrc_cs0,
struct omap_sdrc_params **sdrc_cs1);
+void omap2_sms_save_context(void);
+void omap2_sms_restore_context(void);
#ifdef CONFIG_ARCH_OMAP2
--
1.6.4.3
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[PATCH 17/27] OMAP3: PM: Fix secure SRAM context save/restore
From: Kalle Jokiniemi
The secure sram context save uses dma channels 0 and 1.
In order to avoid collision between kernel DMA transfers and
ROM code dma transfers, we need to reserve DMA channels 0
1 on high security devices.
A bug in ROM code leaves dma irq status bits uncleared.
Hence those irq status bits need to be cleared when restoring
DMA context after off mode.
There was also a faulty parameter given to PPA in the secure
ram context save assembly code, which caused interrupts to
be enabled during secure ram context save. This caused the
save to fail sometimes, which resulted the saved context
to be corrupted, but also left DMA channels in secure mode.
The secure mode DMA channels caused "DMA secure error with
device 0" errors to be displayed.
Signed-off-by: Kalle Jokiniemi
Signed-off-by: Jouni Hogander
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm34xx.c|3 ---
arch/arm/mach-omap2/sleep34xx.S |2 +-
arch/arm/plat-omap/dma.c| 21 +
3 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 9247639..93f5988 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -131,9 +131,6 @@ static void omap3_save_secure_ram_context(u32
target_mpu_state)
u32 ret;
if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
- /* Disable dma irq before calling secure rom code API */
- omap_dma_disable_irq(0);
- omap_dma_disable_irq(1);
/*
* MPU next state must be set to POWER_ON temporarily,
* otherwise the WFI executed inside the ROM code
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index a099816..34a55f1 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -68,7 +68,7 @@ save_secure_ram_debug:
mov r0, #25 @ set service ID for PPA
mov r12, r0 @ copy secure service ID in r12
mov r1, #0 @ set task id for ROM code in r1
- mov r2, #7 @ set some flags in r2, r6
+ mov r2, #4 @ set some flags in r2, r6
mov r6, #0xff
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 4cb2aab..f911bfd 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2358,14 +2358,20 @@ EXPORT_SYMBOL(omap_dma_global_context_save);
void omap_dma_global_context_restore(void)
{
- dma_write(0x2, OCP_SYSCONFIG);
- while (!__raw_readl(omap_dma_base + OMAP_DMA4_SYSSTATUS))
- ;
dma_write(omap_dma_global_context.dma_gcr, GCR);
dma_write(omap_dma_global_context.dma_ocp_sysconfig,
OCP_SYSCONFIG);
dma_write(omap_dma_global_context.dma_irqenable_l0,
IRQENABLE_L0);
+
+ /*
+* A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
+* after secure sram context save and restore. Hence we need to
+* manually clear those IRQs to avoid spurious interrupts. This
+* affects only secure devices.
+*/
+ if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+ dma_write(0x3 , IRQSTATUS_L0);
}
EXPORT_SYMBOL(omap_dma_global_context_restore);
@@ -2510,8 +2516,8 @@ static int __init omap_init_dma(void)
setup_irq(irq, &omap24xx_dma_irq);
}
- /* Enable smartidle idlemodes and autoidle */
if (cpu_is_omap34xx()) {
+ /* Enable smartidle idlemodes and autoidle */
u32 v = dma_read(OCP_SYSCONFIG);
v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
DMA_SYSCONFIG_SIDLEMODE_MASK |
@@ -2520,6 +2526,13 @@ static int __init omap_init_dma(void)
DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
DMA_SYSCONFIG_AUTOIDLE);
dma_write(v , OCP_SYSCONFIG);
+ /* reserve dma channels 0 and 1 in high security devices */
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
+ printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
+ "HS ROM code\n");
+ dma_chan[0].dev_id = 0;
+ dma_chan[1].dev_id = 1;
+ }
}
--
1.6.4.3
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[PATCH 14/27] OMAP3: PM: save secure RAM only during init
From: Tero Kristo
The function omap3_save_secure_ram() is now called only once during
the initialization of the device and consequent sleep cycles will
re-use the same saved contents for secure RAM. Users who need secure
services should do secure RAM saving before entering off-mode, if a
secure service has been accessed after last save.
There are both latency and reliability issues with saving secure RAM
context in the idle path. The context save uses a hardware resource
which takes an order of hundreds of milliseconds to initialize after a
wake up from off-mode, and also there is no way of checking whether it
is ready from kernel side or not. It just crashes if you use it too
quickly
Signed-off-by: Tero Kristo
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm34xx.c | 19 ++-
1 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b8055f9..ab8f66a 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -113,6 +113,12 @@ static void omap3_core_restore_context(void)
omap_dma_global_context_restore();
}
+/*
+ * FIXME: This function should be called before entering off-mode after
+ * OMAP3 secure services have been accessed. Currently it is only called
+ * once during boot sequence, but this works as we are not using secure
+ * services.
+ */
static void omap3_save_secure_ram_context(u32 target_mpu_state)
{
u32 ret;
@@ -338,7 +344,6 @@ static void omap_sram_idle(void)
if (core_next_state == PWRDM_POWER_OFF) {
omap3_core_save_context();
omap3_prcm_save_context();
- omap3_save_secure_ram_context(mpu_next_state);
}
/* Enable IO-PAD wakeup */
prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
@@ -1002,6 +1007,18 @@ static int __init omap3_pm_init(void)
}
omap3_save_scratchpad_contents();
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
+ local_irq_disable();
+ local_fiq_disable();
+
+ omap_dma_global_context_save();
+ omap3_save_secure_ram_context(PWRDM_POWER_ON);
+ omap_dma_global_context_restore();
+
+ local_irq_enable();
+ local_fiq_enable();
+ }
+
err1:
return ret;
err2:
--
1.6.4.3
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[PATCH 16/27] OMAP3: PM: Save and restore also CM_CLKSEL1_PLL_IVA2
From: Jouni Hogander
CM_CLKSEL1_PLL_IVA2 is not saved/restored currently. This patch is
adding save and restore for it.
Signed-off-by: Jouni Hogander
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/prcm.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 9322447..99ff439 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -39,6 +39,7 @@ static void __iomem *cm_base;
struct omap3_prcm_regs {
u32 control_padconf_sys_nirq;
+ u32 iva2_cm_clksel1;
u32 iva2_cm_clksel2;
u32 cm_sysconfig;
u32 sgx_cm_clksel;
@@ -261,6 +262,8 @@ void omap3_prcm_save_context(void)
{
prcm_context.control_padconf_sys_nirq =
omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
+ prcm_context.iva2_cm_clksel1 =
+cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
prcm_context.iva2_cm_clksel2 =
cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
@@ -414,6 +417,8 @@ void omap3_prcm_restore_context(void)
{
omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
OMAP343X_CONTROL_PADCONF_SYSNIRQ);
+ cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
+CM_CLKSEL1);
cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
CM_CLKSEL2);
__raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
--
1.6.4.3
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[PATCH 11/27] OMAP3: PM: CORE domain off-mode support
From: Rajendra Nayak
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm34xx.c | 73 +++-
arch/arm/plat-omap/include/mach/sram.h |1 +
2 files changed, 73 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 4eef146..b1d90e5 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -5,6 +5,9 @@
* Tony Lindgren
* Jouni Hogander
*
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Rajendra Nayak
+ *
* Copyright (C) 2005 Texas Instruments, Inc.
* Richard Woodruff
*
@@ -24,11 +27,13 @@
#include
#include
+#include
#include
#include
#include
#include
#include
+#include
#include
@@ -39,6 +44,11 @@
#include "prm.h"
#include "pm.h"
+/* Scratchpad offsets */
+#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
+#define OMAP343X_TABLE_VALUE_OFFSET 0x30
+#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
+
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
@@ -57,6 +67,46 @@ static struct powerdomain *core_pwrdm, *per_pwrdm;
static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
+static inline void omap3_per_save_context(void)
+{
+ omap3_gpio_save_context();
+}
+
+static inline void omap3_per_restore_context(void)
+{
+ omap3_gpio_restore_context();
+}
+
+static void omap3_core_save_context(void)
+{
+ u32 control_padconf_off;
+
+ /* Save the padconf registers */
+ control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
+ control_padconf_off |= START_PADCONF_SAVE;
+ omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
+ /* wait for the save to complete */
+ while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
+ & PADCONF_SAVE_DONE)
+ ;
+ /* Save the Interrupt controller context */
+ omap3_intc_save_context();
+ /* Save the GPMC context */
+ omap3_gpmc_save_context();
+ /* Save the system control module context, padconf already save above*/
+ omap3_control_save_context();
+}
+
+static void omap3_core_restore_context(void)
+{
+ /* Restore the control module context, padconf restored by h/w */
+ omap3_control_restore_context();
+ /* Restore the GPMC context */
+ omap3_gpmc_restore_context();
+ /* Restore the interrupt controller context */
+ omap3_intc_restore_context();
+}
+
/*
* PRCM Interrupt Handler Helper Function
*
@@ -208,6 +258,7 @@ static void omap_sram_idle(void)
int mpu_next_state = PWRDM_POWER_ON;
int per_next_state = PWRDM_POWER_ON;
int core_next_state = PWRDM_POWER_ON;
+ int core_prev_state, per_prev_state;
if (!_omap_sram_idle)
return;
@@ -246,8 +297,15 @@ static void omap_sram_idle(void)
omap_uart_prepare_idle(1);
/* PER changes only with core */
per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
- if (per_next_state < PWRDM_POWER_ON)
+ if (per_next_state < PWRDM_POWER_ON) {
omap_uart_prepare_idle(2);
+ if (per_next_state == PWRDM_POWER_OFF)
+ omap3_per_save_context();
+ }
+ if (core_next_state == PWRDM_POWER_OFF) {
+ omap3_core_save_context();
+ omap3_prcm_save_context();
+ }
/* Enable IO-PAD wakeup */
prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
}
@@ -272,6 +330,18 @@ static void omap_sram_idle(void)
/* Disable IO-PAD wakeup */
prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
+ core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
+ if (core_prev_state == PWRDM_POWER_OFF) {
+ omap3_core_restore_context();
+ omap3_prcm_restore_context();
+ omap3_sram_restore_context();
+ }
+ if (per_next_state < PWRDM_POWER_ON) {
+ per_prev_state =
+ pwrdm_read_prev_pwrst(per_pwrdm);
+ if (per_prev_state == PWRDM_POWER_OFF)
+ omap3_per_restore_context();
+ }
omap2_gpio_resume_after_retention();
}
@@ -842,6 +912,7 @@ static int __init omap3_pm_init(void)
/* XXX prcm_setup_regs needs to be before enabling hw
* supervised mode for powerdomains */
prcm_setup_regs();
+ omap3_save_scratchpad_contents();
ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
(irq_handler_t)prcm_interrupt_handler,
diff --git a/arch/arm/plat-omap/include/mach/sram.h
b/arch/arm/plat-omap/include/mach/sram.h
[PATCH 10/27] OMAP3: PM: MPU off-mode support
From: Rajendra Nayak
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm34xx.c| 11 ++-
arch/arm/mach-omap2/sleep34xx.S | 11 ---
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 8c9a036..4eef146 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include
@@ -223,6 +224,9 @@ static void omap_sram_idle(void)
/* No need to save context */
save_state = 0;
break;
+ case PWRDM_POWER_OFF:
+ save_state = 3;
+ break;
default:
/* Invalid state */
printk(KERN_ERR "Invalid mpu state in sram_idle\n");
@@ -248,7 +252,12 @@ static void omap_sram_idle(void)
prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
}
- _omap_sram_idle(NULL, save_state);
+ /*
+* omap3_arm_context is the location where ARM registers
+* get saved. The restore path then reads from this
+* location and restores them back.
+*/
+ _omap_sram_idle(omap3_arm_context, save_state);
cpu_init();
/* Restore table entry modified during MMU restoration */
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index e5e2553..5e761ec 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -36,12 +36,11 @@
OMAP3430_PM_PREPWSTST)
#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
OMAP3430_PM_PREPWSTST)
-#define PM_PWSTCTRL_MPU_P OMAP34XX_PRM_REGADDR(MPU_MOD, PM_PWSTCTRL)
+#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL
#define SCRATCHPAD_MEM_OFFS0x310 /* Move this as correct place is
* available */
-#define SCRATCHPAD_BASE_P OMAP343X_CTRL_REGADDR(\
- OMAP343X_CONTROL_MEM_WKUP +\
- SCRATCHPAD_MEM_OFFS)
+#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
+ + SCRATCHPAD_MEM_OFFS)
#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
.text
@@ -96,7 +95,7 @@ loop:
ldmfd sp!, {r0-r12, pc} @ restore regs and return
restore:
- /* b restore*/ @ Enable to debug restore code
+ /* b restore*/ @ Enable to debug restore code
/* Check what was the reason for mpu reset and store the reason in r9*/
/* 1 - Only L1 and logic lost */
/* 2 - Only L2 lost - In this case, we wont be here */
@@ -416,8 +415,6 @@ scratchpad_base:
.word SCRATCHPAD_BASE_P
sdrc_power:
.word SDRC_POWER_V
-context_mem:
- .word 0x803E3E14
clk_stabilize_delay:
.word 0x01FF
assoc_mask:
--
1.6.4.3
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[PATCH 26/27] OMAP3: PM debug: allow runtime toggle of PM features
Allow enable/disable of low-power states during idle. To
enable low-power idle:
echo 1 > /debug/pm_debug/sleep_while_idle
to disable:
echo 0 > /debug/pm_debug/sleep_while_idle
Also allow enable/disable of OFF-mode. To enable:
echo 1 > /debug/pm_debug/enable_off_mode
to disable:
echo 0 > /debug/pm_debug/enable_off_mode
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm-debug.c | 27 +++
arch/arm/mach-omap2/pm.h |4
arch/arm/mach-omap2/pm34xx.c | 22 ++
arch/arm/mach-omap2/serial.c |2 --
4 files changed, 53 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index deed1dd..4e05d29 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -527,6 +527,29 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm,
void *dir)
return 0;
}
+static int option_get(void *data, u64 *val)
+{
+ u32 *option = data;
+
+ *val = *option;
+
+ return 0;
+}
+
+static int option_set(void *data, u64 val)
+{
+ u32 *option = data;
+
+ *option = val;
+
+ if (option == &enable_off_mode)
+ omap3_pm_off_mode_enable(val);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
+
static int __init pm_dbg_init(void)
{
int i;
@@ -569,6 +592,10 @@ static int __init pm_dbg_init(void)
}
+ (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
+ &enable_off_mode, &pm_dbg_option_fops);
+ (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
+ &sleep_while_idle, &pm_dbg_option_fops);
pm_dbg_init_done = 1;
return 0;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index f1d0214..e47508c 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -13,7 +13,11 @@
#include
+extern u32 enable_off_mode;
+extern u32 sleep_while_idle;
+
extern void *omap3_secure_ram_storage;
+extern void omap3_pm_off_mode_enable(int);
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 80934c3..6fc 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include
@@ -58,6 +59,9 @@
#define OMAP343X_TABLE_VALUE_OFFSET 0x30
#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
+u32 enable_off_mode;
+u32 sleep_while_idle;
+
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
@@ -457,6 +461,8 @@ static int omap3_fclks_active(void)
static int omap3_can_sleep(void)
{
+ if (!sleep_while_idle)
+ return 0;
if (!omap_uart_can_sleep())
return 0;
if (omap3_fclks_active())
@@ -900,6 +906,22 @@ static void __init prcm_setup_regs(void)
omap3_d2d_idle();
}
+void omap3_pm_off_mode_enable(int enable)
+{
+ struct power_state *pwrst;
+ u32 state;
+
+ if (enable)
+ state = PWRDM_POWER_OFF;
+ else
+ state = PWRDM_POWER_RET;
+
+ list_for_each_entry(pwrst, &pwrst_list, node) {
+ pwrst->next_state = state;
+ set_pwrdm_state(pwrst->pwrdm, state);
+ }
+}
+
int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
{
struct power_state *pwrst;
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index b1ebef4..5fe7684 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -169,8 +169,6 @@ static inline void __init omap_uart_reset(struct
omap_uart_state *uart)
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
-static int enable_off_mode; /* to be removed by full off-mode patches */
-
static void omap_uart_save_context(struct omap_uart_state *uart)
{
u16 lcr = 0;
--
1.6.4.3
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[PATCH 25/27] OMAP3: PM: Wait for SDRC ready iso a blind delay
From: Peter 'p2' De Schrijver
This patch improves the wakeup SRAM code polling the SDRC to become ready
instead of just waiting for a fixed amount of time.
Signed-off-by: Peter 'p2' De Schrijver
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/sleep34xx.S | 48 +-
1 files changed, 36 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 3868ae4..0d33916 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -29,6 +29,7 @@
#include
#include
+#include "cm.h"
#include "prm.h"
#include "sdrc.h"
@@ -38,6 +39,7 @@
#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
OMAP3430_PM_PREPWSTST)
#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL
+#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
#define SRAM_BASE_P0x4020
#define CONTROL_STAT 0x480022F0
#define SCRATCHPAD_MEM_OFFS0x310 /* Move this as correct place is
@@ -52,6 +54,8 @@
#define SDRC_MR_1_P(OMAP343X_SDRC_BASE + SDRC_MR_1)
#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
#define SDRC_MANUAL_1_P(OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
+#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
+#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
.text
/* Function call to get the restore pointer for resume from OFF */
@@ -187,7 +191,7 @@ loop:
nop
nop
nop
- bl i_dll_wait
+ bl wait_sdrc_ok
ldmfd sp!, {r0-r12, pc} @ restore regs and return
restore_es3:
@@ -539,21 +543,41 @@ skip_l2_inval:
nop
nop
nop
- bl i_dll_wait
+ bl wait_sdrc_ok
/* restore regs and return */
ldmfd sp!, {r0-r12, pc}
-i_dll_wait:
- ldr r4, clk_stabilize_delay
+/* Make sure SDRC accesses are ok */
+wait_sdrc_ok:
+ldr r4, cm_idlest1_core
+ldr r5, [r4]
+and r5, r5, #0x2
+cmp r5, #0
+bne wait_sdrc_ok
+ldr r4, sdrc_power
+ldr r5, [r4]
+bic r5, r5, #0x40
+str r5, [r4]
+wait_dll_lock:
+/* Is dll in lock mode? */
+ldr r4, sdrc_dlla_ctrl
+ldr r5, [r4]
+tst r5, #0x4
+bxnelr
+/* wait till dll locks */
+ldr r4, sdrc_dlla_status
+ldr r5, [r4]
+and r5, r5, #0x4
+cmp r5, #0x4
+bne wait_dll_lock
+bx lr
-i_dll_delay:
- subsr4, r4, #0x1
- bne i_dll_delay
- ldr r4, sdrc_power
- ldr r5, [r4]
- bic r5, r5, #0x40
- str r5, [r4]
- bx lr
+cm_idlest1_core:
+ .word CM_IDLEST1_CORE_V
+sdrc_dlla_status:
+ .word SDRC_DLLA_STATUS_V
+sdrc_dlla_ctrl:
+ .word SDRC_DLLA_CTRL_V
pm_prepwstst_core:
.word PM_PREPWSTST_CORE_V
pm_prepwstst_core_p:
--
1.6.4.3
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[PATCH 07/27] OMAP3: PM: SRAM restore function
From: Rajendra Nayak
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm34xx.c | 10 +++---
arch/arm/plat-omap/include/mach/sram.h |1 +
arch/arm/plat-omap/sram.c |6 +++---
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 378c2f6..9dbb5a0 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -748,6 +748,12 @@ static int __init clkdms_setup(struct clockdomain *clkdm,
void *unused)
return 0;
}
+void omap_push_sram_idle(void)
+{
+ _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
+ omap34xx_cpu_suspend_sz);
+}
+
static int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
@@ -785,9 +791,7 @@ static int __init omap3_pm_init(void)
goto err2;
}
- _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
-omap34xx_cpu_suspend_sz);
-
+ omap_push_sram_idle();
#ifdef CONFIG_SUSPEND
suspend_set_ops(&omap_pm_ops);
#endif /* CONFIG_SUSPEND */
diff --git a/arch/arm/plat-omap/include/mach/sram.h
b/arch/arm/plat-omap/include/mach/sram.h
index 8974e3f..a943014 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -67,5 +67,6 @@ extern u32 omap3_sram_configure_core_dpll(
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
extern unsigned long omap3_sram_configure_core_dpll_sz;
+extern void omap_push_sram_idle(void);
#endif
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 4144f81..b20ec87 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -396,14 +396,14 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32
f, u32 inc,
sdrc_actim_ctrl_b_1, sdrc_mr_1);
}
-/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
-void restore_sram_functions(void)
+void omap3_sram_restore_context(void)
{
omap_sram_ceil = omap_sram_base + omap_sram_size;
_omap3_sram_configure_core_dpll =
omap_sram_push(omap3_sram_configure_core_dpll,
omap3_sram_configure_core_dpll_sz);
+ omap_push_sram_idle();
}
int __init omap34xx_sram_init(void)
@@ -411,7 +411,7 @@ int __init omap34xx_sram_init(void)
_omap3_sram_configure_core_dpll =
omap_sram_push(omap3_sram_configure_core_dpll,
omap3_sram_configure_core_dpll_sz);
-
+ omap_push_sram_idle();
return 0;
}
#else
--
1.6.4.3
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[PATCH 06/27] OMAP3: PM: SCM context save/restore
From: Rajendra Nayak
This patch adds the System control module context save/restore
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/control.c | 151 +
arch/arm/plat-omap/include/mach/control.h |2 +
2 files changed, 153 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 060fc19..58ba6ee 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -92,6 +92,46 @@ struct omap3_scratchpad_sdrc_block {
*/
u32 omap3_arm_context[128];
+struct omap3_control_regs {
+ u32 sysconfig;
+ u32 devconf0;
+ u32 mem_dftrw0;
+ u32 mem_dftrw1;
+ u32 msuspendmux_0;
+ u32 msuspendmux_1;
+ u32 msuspendmux_2;
+ u32 msuspendmux_3;
+ u32 msuspendmux_4;
+ u32 msuspendmux_5;
+ u32 sec_ctrl;
+ u32 devconf1;
+ u32 csirxfe;
+ u32 iva2_bootaddr;
+ u32 iva2_bootmod;
+ u32 debobs_0;
+ u32 debobs_1;
+ u32 debobs_2;
+ u32 debobs_3;
+ u32 debobs_4;
+ u32 debobs_5;
+ u32 debobs_6;
+ u32 debobs_7;
+ u32 debobs_8;
+ u32 prog_io0;
+ u32 prog_io1;
+ u32 dss_dpll_spreading;
+ u32 core_dpll_spreading;
+ u32 per_dpll_spreading;
+ u32 usbhost_dpll_spreading;
+ u32 pbias_lite;
+ u32 temp_sensor;
+ u32 sramldo4;
+ u32 sramldo5;
+ u32 csi;
+};
+
+static struct omap3_control_regs control_context;
+
#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
@@ -264,4 +304,115 @@ void omap3_save_scratchpad_contents(void)
sizeof(sdrc_block_contents), &arm_context_addr, 4);
}
+void omap3_control_save_context(void)
+{
+ control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
+ control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+ control_context.mem_dftrw0 =
+ omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
+ control_context.mem_dftrw1 =
+ omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
+ control_context.msuspendmux_0 =
+ omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
+ control_context.msuspendmux_1 =
+ omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
+ control_context.msuspendmux_2 =
+ omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
+ control_context.msuspendmux_3 =
+ omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
+ control_context.msuspendmux_4 =
+ omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
+ control_context.msuspendmux_5 =
+ omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
+ control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
+ control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
+ control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
+ control_context.iva2_bootaddr =
+ omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
+ control_context.iva2_bootmod =
+ omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
+ control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
+ control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
+ control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
+ control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
+ control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
+ control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
+ control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
+ control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
+ control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
+ control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
+ control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
+ control_context.dss_dpll_spreading =
+ omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
+ control_context.core_dpll_spreading =
+ omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
+ control_context.per_dpll_spreading =
+ omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
+ control_context.usbhost_dpll_spreading =
+ omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
+ control_context.pbias_lite =
+ omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
+ control_context.temp_sensor =
+ omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
+ control_context.sramldo4 = omap_ctrl_readl(OMA
[PATCH 02/27] OMAP3: PM: GPIO context save/restore
From: Rajendra Nayak
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
---
arch/arm/plat-omap/gpio.c | 93
arch/arm/plat-omap/include/mach/gpio.h |3 +-
2 files changed, 95 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index b1af0c2..48ce218 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -260,6 +260,23 @@ static struct gpio_bank gpio_bank_34xx[6] = {
{ OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
METHOD_GPIO_24XX },
};
+struct omap3_gpio_regs {
+ u32 sysconfig;
+ u32 irqenable1;
+ u32 irqenable2;
+ u32 wake_en;
+ u32 ctrl;
+ u32 oe;
+ u32 leveldetect0;
+ u32 leveldetect1;
+ u32 risingdetect;
+ u32 fallingdetect;
+ u32 dataout;
+ u32 setwkuena;
+ u32 setdataout;
+};
+
+static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
#endif
#ifdef CONFIG_ARCH_OMAP4
@@ -2002,6 +2019,82 @@ void omap2_gpio_resume_after_retention(void)
#endif
+#ifdef CONFIG_ARCH_OMAP34XX
+/* save the registers of bank 2-6 */
+void omap3_gpio_save_context(void)
+{
+ int i;
+
+ /* saving banks from 2-6 only since GPIO1 is in WKUP */
+ for (i = 1; i < gpio_bank_count; i++) {
+ struct gpio_bank *bank = &gpio_bank[i];
+ gpio_context[i].sysconfig =
+ __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
+ gpio_context[i].irqenable1 =
+ __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
+ gpio_context[i].irqenable2 =
+ __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
+ gpio_context[i].wake_en =
+ __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
+ gpio_context[i].ctrl =
+ __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
+ gpio_context[i].oe =
+ __raw_readl(bank->base + OMAP24XX_GPIO_OE);
+ gpio_context[i].leveldetect0 =
+ __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+ gpio_context[i].leveldetect1 =
+ __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+ gpio_context[i].risingdetect =
+ __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
+ gpio_context[i].fallingdetect =
+ __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+ gpio_context[i].dataout =
+ __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
+ gpio_context[i].setwkuena =
+ __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
+ gpio_context[i].setdataout =
+ __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
+ }
+}
+EXPORT_SYMBOL(omap3_gpio_save_context);
+
+/* restore the required registers of bank 2-6 */
+void omap3_gpio_restore_context(void)
+{
+ int i;
+ for (i = 1; i < gpio_bank_count; i++) {
+ struct gpio_bank *bank = &gpio_bank[i];
+ __raw_writel(gpio_context[i].sysconfig,
+ bank->base + OMAP24XX_GPIO_SYSCONFIG);
+ __raw_writel(gpio_context[i].irqenable1,
+ bank->base + OMAP24XX_GPIO_IRQENABLE1);
+ __raw_writel(gpio_context[i].irqenable2,
+ bank->base + OMAP24XX_GPIO_IRQENABLE2);
+ __raw_writel(gpio_context[i].wake_en,
+ bank->base + OMAP24XX_GPIO_WAKE_EN);
+ __raw_writel(gpio_context[i].ctrl,
+ bank->base + OMAP24XX_GPIO_CTRL);
+ __raw_writel(gpio_context[i].oe,
+ bank->base + OMAP24XX_GPIO_OE);
+ __raw_writel(gpio_context[i].leveldetect0,
+ bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+ __raw_writel(gpio_context[i].leveldetect1,
+ bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+ __raw_writel(gpio_context[i].risingdetect,
+ bank->base + OMAP24XX_GPIO_RISINGDETECT);
+ __raw_writel(gpio_context[i].fallingdetect,
+ bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+ __raw_writel(gpio_context[i].dataout,
+ bank->base + OMAP24XX_GPIO_DATAOUT);
+ __raw_writel(gpio_context[i].setwkuena,
+ bank->base + OMAP24XX_GPIO_SETWKUENA);
+ __raw_writel(gpio_context[i].setdataout,
+ bank->base + OMAP24XX_GPIO_SETDATAOUT);
+ }
+}
+EXPORT_SYMBOL(omap3_gpio_restore_context);
+#endif
+
/*
* This may get called early from board specific init
* for bo
[PATCH 23/27] OMAP3: PM: Fix INTC context save/restore
From: Aaro Koskinen Wrong index was used for ILR. Signed-off-by: Aaro Koskinen Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/irq.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index fa2524d..aceedd8 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -233,7 +233,7 @@ void omap3_intc_save_context(void) intc_bank_read_reg(bank, INTC_THRESHOLD); for (i = 0; i < INTCPS_NR_IRQS; i++) intc_context[ind].ilr[i] = - intc_bank_read_reg(bank, (0x100 + 0x4*ind)); + intc_bank_read_reg(bank, (0x100 + 0x4*i)); for (i = 0; i < INTCPS_NR_MIR_REGS; i++) intc_context[ind].mir[i] = intc_bank_read_reg(&irq_banks[0], INTC_MIR0 + @@ -259,7 +259,7 @@ void omap3_intc_restore_context(void) bank, INTC_THRESHOLD); for (i = 0; i < INTCPS_NR_IRQS; i++) intc_bank_write_reg(intc_context[ind].ilr[i], - bank, (0x100 + 0x4*ind)); + bank, (0x100 + 0x4*i)); for (i = 0; i < INTCPS_NR_MIR_REGS; i++) intc_bank_write_reg(intc_context[ind].mir[i], &irq_banks[0], INTC_MIR0 + (0x20 * i)); -- 1.6.4.3 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 22/27] OMAP3: PM: SDRC auto-refresh workaround for off-mode
From: Tero Kristo
Errata: ES3.0 SDRC not sending auto-refresh when OMAP wakes-up from OFF mode
Signed-off-by: Tero Kristo
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/control.c |8 ++-
arch/arm/mach-omap2/sleep34xx.S | 84 -
arch/arm/plat-omap/include/mach/control.h |1 +
3 files changed, 90 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 50b3afc..ca9a739 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -207,8 +207,12 @@ void omap3_save_scratchpad_contents(void)
/* Populate the Scratchpad contents */
scratchpad_contents.boot_config_ptr = 0x0;
- scratchpad_contents.public_restore_ptr =
-virt_to_phys(get_restore_pointer());
+ if (system_rev != OMAP3430_REV_ES3_0)
+ scratchpad_contents.public_restore_ptr =
+ virt_to_phys(get_restore_pointer());
+ else
+ scratchpad_contents.public_restore_ptr =
+ virt_to_phys(get_es3_restore_pointer());
if (omap_type() == OMAP2_DEVICE_TYPE_GP)
scratchpad_contents.secure_ram_restore_ptr = 0x0;
else
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 34a55f1..3868ae4 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -34,6 +34,7 @@
#define PM_PREPWSTST_CORE_VOMAP34XX_PRM_REGADDR(CORE_MOD, \
OMAP3430_PM_PREPWSTST)
+#define PM_PREPWSTST_CORE_P0x48306AE8
#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
OMAP3430_PM_PREPWSTST)
#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL
@@ -44,6 +45,13 @@
#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
+ SCRATCHPAD_MEM_OFFS)
#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
+#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
+#define SDRC_MR_0_P(OMAP343X_SDRC_BASE + SDRC_MR_0)
+#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
+#define SDRC_MANUAL_0_P(OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
+#define SDRC_MR_1_P(OMAP343X_SDRC_BASE + SDRC_MR_1)
+#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
+#define SDRC_MANUAL_1_P(OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
.text
/* Function call to get the restore pointer for resume from OFF */
@@ -52,7 +60,59 @@ ENTRY(get_restore_pointer)
adr r0, restore
ldmfd sp!, {pc} @ restore regs and return
ENTRY(get_restore_pointer_sz)
-.word . - get_restore_pointer_sz
+.word . - get_restore_pointer
+
+ .text
+/* Function call to get the restore pointer for for ES3 to resume from OFF */
+ENTRY(get_es3_restore_pointer)
+ stmfd sp!, {lr} @ save registers on stack
+ adr r0, restore_es3
+ ldmfd sp!, {pc} @ restore regs and return
+ENTRY(get_es3_restore_pointer_sz)
+ .word . - get_es3_restore_pointer
+
+ENTRY(es3_sdrc_fix)
+ ldr r4, sdrc_syscfg @ get config addr
+ ldr r5, [r4]@ get value
+ tst r5, #0x100 @ is part access blocked
+ it eq
+ biceq r5, r5, #0x100 @ clear bit if set
+ str r5, [r4]@ write back change
+ ldr r4, sdrc_mr_0 @ get config addr
+ ldr r5, [r4]@ get value
+ str r5, [r4]@ write back change
+ ldr r4, sdrc_emr2_0 @ get config addr
+ ldr r5, [r4]@ get value
+ str r5, [r4]@ write back change
+ ldr r4, sdrc_manual_0 @ get config addr
+ mov r5, #0x2@ autorefresh command
+ str r5, [r4]@ kick off refreshes
+ ldr r4, sdrc_mr_1 @ get config addr
+ ldr r5, [r4]@ get value
+ str r5, [r4]@ write back change
+ ldr r4, sdrc_emr2_1 @ get config addr
+ ldr r5, [r4]@ get value
+ str r5, [r4]@ write back change
+ ldr r4, sdrc_manual_1 @ get config addr
+ mov r5, #0x2@ autorefresh command
+ str r5, [r4]@ kick off refreshes
+ bx lr
+sdrc_syscfg:
+ .word SDRC_SYSCONFIG_P
+sdrc_mr_0:
+ .word SDRC_MR_0_P
+sdrc_emr2_0:
+ .word SDRC_EMR2_0_P
+sdrc_manual_0:
+ .word SDRC_MANUAL_0_P
+sdrc_mr_1:
+ .word SDRC_MR_1_P
+sdrc_emr2_1:
+ .word SDRC_EMR2_1_P
+sdrc_manual_1:
+ .word SDRC_MANUAL_1_P
+ENTRY(es3_sdrc_fix_sz)
+ .word . - e
[PATCH 21/27] OMAP: Store reboot mode in scratchpad on OMAP34xx
From: Juha Yrjola
The reboot mode can be communicated to a bootloader (or the
kernel itself) with a scratchpad register. This functionality
is especially useful, if userspace is allowed to change
the reboot mode.
Signed-off-by: Juha Yrjola
Acked-by: Kevin Hilman
Signed-off-by: Tony Lindgren
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/prcm.c | 13 +++--
1 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 99ff439..ce17eb1 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -134,9 +134,18 @@ void omap_prcm_arch_reset(char mode)
if (cpu_is_omap24xx())
prcm_offs = WKUP_MOD;
- else if (cpu_is_omap34xx())
+ else if (cpu_is_omap34xx()) {
+ u32 l;
+
prcm_offs = OMAP3430_GR_MOD;
- else
+ l = ('B' << 24) | ('M' << 16) | mode;
+ /* Reserve the first word in scratchpad for communicating
+* with the boot ROM. A pointer to a data structure
+* describing the boot process can be stored there,
+* cf. OMAP34xx TRM, Initialization / Software Booting
+* Configuration. */
+ omap_writel(l, OMAP343X_SCRATCHPAD + 4);
+ } else
WARN_ON(1);
prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
--
1.6.4.3
--
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[PATCH 13/27] OMAP3 PM: off-mode support for HS/EMU devices
From: Tero Kristo
Signed-off-by: Tero Kristo
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/control.c |8 -
arch/arm/mach-omap2/pm.h|3 ++
arch/arm/mach-omap2/pm34xx.c| 44 ++-
arch/arm/mach-omap2/sleep34xx.S | 75 ++-
4 files changed, 127 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 58ba6ee..6c462c7 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -84,6 +84,8 @@ struct omap3_scratchpad_sdrc_block {
u32 block_size;
};
+void *omap3_secure_ram_storage;
+
/*
* This is used to store ARM registers in SDRAM before attempting
* an MPU OFF. The save and restore happens from the SRAM sleep code.
@@ -207,7 +209,11 @@ void omap3_save_scratchpad_contents(void)
scratchpad_contents.boot_config_ptr = 0x0;
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_restore_pointer());
- scratchpad_contents.secure_ram_restore_ptr = 0x0;
+ if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+ scratchpad_contents.secure_ram_restore_ptr = 0x0;
+ else
+ scratchpad_contents.secure_ram_restore_ptr =
+ (u32) __pa(omap3_secure_ram_storage);
scratchpad_contents.sdrc_module_semaphore = 0x0;
scratchpad_contents.prcm_block_offset = 0x2C;
scratchpad_contents.sdrc_block_offset = 0x64;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 8400f57..f1d0214 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -13,6 +13,8 @@
#include
+extern void *omap3_secure_ram_storage;
+
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
@@ -36,6 +38,7 @@ extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem
*sdrc_dlla_ctrl,
void __iomem *sdrc_power);
extern void omap34xx_cpu_suspend(u32 *addr, int save_state);
extern void save_secure_ram_context(u32 *addr);
+extern void omap3_save_scratchpad_contents(void);
extern unsigned int omap24xx_idle_loop_suspend_sz;
extern unsigned int omap34xx_suspend_sz;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 764bf2c..b8055f9 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
@@ -63,6 +64,8 @@ static LIST_HEAD(pwrst_list);
static void (*_omap_sram_idle)(u32 *addr, int save_state);
+static int (*_omap_save_secure_sram)(u32 *addr);
+
static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm;
@@ -110,6 +113,33 @@ static void omap3_core_restore_context(void)
omap_dma_global_context_restore();
}
+static void omap3_save_secure_ram_context(u32 target_mpu_state)
+{
+ u32 ret;
+
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
+ /* Disable dma irq before calling secure rom code API */
+ omap_dma_disable_irq(0);
+ omap_dma_disable_irq(1);
+ /*
+* MPU next state must be set to POWER_ON temporarily,
+* otherwise the WFI executed inside the ROM code
+* will hang the system.
+*/
+ pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
+ ret = _omap_save_secure_sram((u32 *)
+ __pa(omap3_secure_ram_storage));
+ pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
+ /* Following is for error tracking, it should not happen */
+ if (ret) {
+ printk(KERN_ERR "save_secure_sram() returns %08x\n",
+ ret);
+ while (1)
+ ;
+ }
+ }
+}
+
/*
* PRCM Interrupt Handler Helper Function
*
@@ -308,6 +338,7 @@ static void omap_sram_idle(void)
if (core_next_state == PWRDM_POWER_OFF) {
omap3_core_save_context();
omap3_prcm_save_context();
+ omap3_save_secure_ram_context(mpu_next_state);
}
/* Enable IO-PAD wakeup */
prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
@@ -900,6 +931,9 @@ void omap_push_sram_idle(void)
{
_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
omap34xx_cpu_suspend_sz);
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP)
+ _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
+ save_secure_ram_context_sz);
}
static int __init omap3_pm_init(void)
@@ -915,7 +949,6 @@ static int __init omap3_pm_init(void)
/* XXX prcm_setup_r
[PATCH 15/27] OMAP3: PM: Enable SDRAM auto-refresh during sleep
From: Tero Kristo
Fix for ES3.0 bug: SDRC not sending auto-refresh when OMAP wakes-up from OFF
mode (warning for HS devices.)
Signed-off-by: Tero Kristo
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm34xx.c | 29 +
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index ab8f66a..9247639 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -45,6 +45,13 @@
#include "prm.h"
#include "pm.h"
+#include "sdrc.h"
+
+#define SDRC_POWER_AUTOCOUNT_SHIFT 8
+#define SDRC_POWER_AUTOCOUNT_MASK (0x << SDRC_POWER_AUTOCOUNT_SHIFT)
+#define SDRC_POWER_CLKCTRL_SHIFT 4
+#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
+#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
/* Scratchpad offsets */
#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
@@ -298,6 +305,7 @@ static void omap_sram_idle(void)
int per_next_state = PWRDM_POWER_ON;
int core_next_state = PWRDM_POWER_ON;
int core_prev_state, per_prev_state;
+ u32 sdrc_pwr = 0;
if (!_omap_sram_idle)
return;
@@ -350,6 +358,21 @@ static void omap_sram_idle(void)
}
/*
+* Force SDRAM controller to self-refresh mode after timeout on
+* autocount. This is needed on ES3.0 to avoid SDRAM controller
+* hang-ups.
+*/
+ if (system_rev >= OMAP3430_REV_ES3_0 &&
+ omap_type() != OMAP2_DEVICE_TYPE_GP &&
+ core_next_state == PWRDM_POWER_OFF) {
+ sdrc_pwr = sdrc_read_reg(SDRC_POWER);
+ sdrc_write_reg((sdrc_pwr &
+ ~(SDRC_POWER_AUTOCOUNT_MASK|SDRC_POWER_CLKCTRL_MASK)) |
+ (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
+ SDRC_SELF_REFRESH_ON_AUTOCOUNT, SDRC_POWER);
+ }
+
+ /*
* omap3_arm_context is the location where ARM registers
* get saved. The restore path then reads from this
* location and restores them back.
@@ -357,6 +380,12 @@ static void omap_sram_idle(void)
_omap_sram_idle(omap3_arm_context, save_state);
cpu_init();
+ /* Restore normal SDRAM settings */
+ if (system_rev >= OMAP3430_REV_ES3_0 &&
+ omap_type() != OMAP2_DEVICE_TYPE_GP &&
+ core_next_state == PWRDM_POWER_OFF)
+ sdrc_write_reg(sdrc_pwr, SDRC_POWER);
+
/* Restore table entry modified during MMU restoration */
if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
restore_table_entry();
--
1.6.4.3
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[PATCH 12/27] OMAP: PM: DMA context save/restore for off-mode support
From: Tero Kristo
For HS/EMU devices, these additional features are also used:
- DMA interrupt disable routine added
- Added DMA controller reset to DMA context restore
Signed-off-by: Tero Kristo
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm34xx.c |3 ++
arch/arm/plat-omap/dma.c | 41 +
arch/arm/plat-omap/include/mach/dma.h |5
3 files changed, 49 insertions(+), 0 deletions(-)
mode change 100644 => 100755 arch/arm/plat-omap/include/mach/dma.h
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b1d90e5..764bf2c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#include
@@ -95,6 +96,7 @@ static void omap3_core_save_context(void)
omap3_gpmc_save_context();
/* Save the system control module context, padconf already save above*/
omap3_control_save_context();
+ omap_dma_global_context_save();
}
static void omap3_core_restore_context(void)
@@ -105,6 +107,7 @@ static void omap3_core_restore_context(void)
omap3_gpmc_restore_context();
/* Restore the interrupt controller context */
omap3_intc_restore_context();
+ omap_dma_global_context_restore();
}
/*
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 8227312..4cb2aab 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -54,6 +54,12 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
static int enable_1510_mode;
+static struct omap_dma_global_context_registers {
+ u32 dma_irqenable_l0;
+ u32 dma_ocp_sysconfig;
+ u32 dma_gcr;
+} omap_dma_global_context;
+
struct omap_dma_lch {
int next_lch;
int dev_id;
@@ -2340,6 +2346,41 @@ void omap_stop_lcd_dma(void)
}
EXPORT_SYMBOL(omap_stop_lcd_dma);
+void omap_dma_global_context_save(void)
+{
+ omap_dma_global_context.dma_irqenable_l0 =
+ dma_read(IRQENABLE_L0);
+ omap_dma_global_context.dma_ocp_sysconfig =
+ dma_read(OCP_SYSCONFIG);
+ omap_dma_global_context.dma_gcr = dma_read(GCR);
+}
+EXPORT_SYMBOL(omap_dma_global_context_save);
+
+void omap_dma_global_context_restore(void)
+{
+ dma_write(0x2, OCP_SYSCONFIG);
+ while (!__raw_readl(omap_dma_base + OMAP_DMA4_SYSSTATUS))
+ ;
+ dma_write(omap_dma_global_context.dma_gcr, GCR);
+ dma_write(omap_dma_global_context.dma_ocp_sysconfig,
+ OCP_SYSCONFIG);
+ dma_write(omap_dma_global_context.dma_irqenable_l0,
+ IRQENABLE_L0);
+}
+EXPORT_SYMBOL(omap_dma_global_context_restore);
+
+void omap_dma_disable_irq(int lch)
+{
+ u32 val;
+
+ if (cpu_class_is_omap2()) {
+ /* Disable interrupts */
+ val = dma_read(IRQENABLE_L0);
+ val &= ~(1 << lch);
+ dma_write(val, IRQENABLE_L0);
+ }
+}
+
/**/
static int __init omap_init_dma(void)
diff --git a/arch/arm/plat-omap/include/mach/dma.h
b/arch/arm/plat-omap/include/mach/dma.h
old mode 100644
new mode 100755
index 72f680b..1c017b2
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -633,6 +633,11 @@ extern void omap_set_dma_dst_endian_type(int lch, enum
end_type etype);
extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
extern int omap_get_dma_index(int lch, int *ei, int *fi);
+void omap_dma_global_context_save(void);
+void omap_dma_global_context_restore(void);
+
+extern void omap_dma_disable_irq(int lch);
+
/* Chaining APIs */
#ifndef CONFIG_ARCH_OMAP1
extern int omap_request_dma_chain(int dev_id, const char *dev_name,
--
1.6.4.3
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[PATCH 09/27] OMAP3: PM: Restore MMU table entry
From: Rajendra Nayak
During the MMU restoration on the restore path from MPU OFF, the page
table entry for the page consisting of the code being executed is
modified to make MMU return VA=PA.
The MMU is then enabled and the original entry is being stored in
scratchpad. This patch reads the original values stored in
scratchpad, and restores them back.
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm34xx.c | 35 +++
1 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7eab539..8c9a036 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -29,6 +29,8 @@
#include
#include
+#include
+
#include "cm.h"
#include "cm-regbits-34xx.h"
#include "prm-regbits-34xx.h"
@@ -164,6 +166,35 @@ static irqreturn_t prcm_interrupt_handler (int irq, void
*dev_id)
return IRQ_HANDLED;
}
+static void restore_control_register(u32 val)
+{
+ __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
+}
+
+/* Function to restore the table entry that was modified for enabling MMU */
+static void restore_table_entry(void)
+{
+ u32 *scratchpad_address;
+ u32 previous_value, control_reg_value;
+ u32 *address;
+
+ scratchpad_address = OMAP2_IO_ADDRESS(OMAP343X_SCRATCHPAD);
+
+ /* Get address of entry that was modified */
+ address = (u32 *)__raw_readl(scratchpad_address +
+OMAP343X_TABLE_ADDRESS_OFFSET);
+ /* Get the previous value which needs to be restored */
+ previous_value = __raw_readl(scratchpad_address +
+OMAP343X_TABLE_VALUE_OFFSET);
+ address = __va(address);
+ *address = previous_value;
+ flush_tlb_all();
+ control_reg_value = __raw_readl(scratchpad_address
+ + OMAP343X_CONTROL_REG_VALUE_OFFSET);
+ /* This will enable caches and prediction */
+ restore_control_register(control_reg_value);
+}
+
static void omap_sram_idle(void)
{
/* Variable to tell what needs to be saved and restored
@@ -220,6 +251,10 @@ static void omap_sram_idle(void)
_omap_sram_idle(NULL, save_state);
cpu_init();
+ /* Restore table entry modified during MMU restoration */
+ if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
+ restore_table_entry();
+
if (core_next_state < PWRDM_POWER_ON) {
if (per_next_state < PWRDM_POWER_ON)
omap_uart_resume_idle(2);
--
1.6.4.3
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[PATCH 05/27] OMAP3: PM: Populate scratchpad contents
From: Rajendra Nayak
This patch populates the scratchpad contents as expected by the
bootROM code.
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/control.c | 203 +
arch/arm/plat-omap/include/mach/control.h |9 ++
2 files changed, 212 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 5f3aad9..060fc19 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -17,9 +17,81 @@
#include
#include
+#include
+#include "cm-regbits-34xx.h"
+#include "prm-regbits-34xx.h"
+#include "cm.h"
+#include "prm.h"
+#include "sdrc.h"
static void __iomem *omap2_ctrl_base;
+struct omap3_scratchpad {
+ u32 boot_config_ptr;
+ u32 public_restore_ptr;
+ u32 secure_ram_restore_ptr;
+ u32 sdrc_module_semaphore;
+ u32 prcm_block_offset;
+ u32 sdrc_block_offset;
+};
+
+struct omap3_scratchpad_prcm_block {
+ u32 prm_clksrc_ctrl;
+ u32 prm_clksel;
+ u32 cm_clksel_core;
+ u32 cm_clksel_wkup;
+ u32 cm_clken_pll;
+ u32 cm_autoidle_pll;
+ u32 cm_clksel1_pll;
+ u32 cm_clksel2_pll;
+ u32 cm_clksel3_pll;
+ u32 cm_clken_pll_mpu;
+ u32 cm_autoidle_pll_mpu;
+ u32 cm_clksel1_pll_mpu;
+ u32 cm_clksel2_pll_mpu;
+ u32 prcm_block_size;
+};
+
+struct omap3_scratchpad_sdrc_block {
+ u16 sysconfig;
+ u16 cs_cfg;
+ u16 sharing;
+ u16 err_type;
+ u32 dll_a_ctrl;
+ u32 dll_b_ctrl;
+ u32 power;
+ u32 cs_0;
+ u32 mcfg_0;
+ u16 mr_0;
+ u16 emr_1_0;
+ u16 emr_2_0;
+ u16 emr_3_0;
+ u32 actim_ctrla_0;
+ u32 actim_ctrlb_0;
+ u32 rfr_ctrl_0;
+ u32 cs_1;
+ u32 mcfg_1;
+ u16 mr_1;
+ u16 emr_1_1;
+ u16 emr_2_1;
+ u16 emr_3_1;
+ u32 actim_ctrla_1;
+ u32 actim_ctrlb_1;
+ u32 rfr_ctrl_1;
+ u16 dcdl_1_ctrl;
+ u16 dcdl_2_ctrl;
+ u32 flags;
+ u32 block_size;
+};
+
+/*
+ * This is used to store ARM registers in SDRAM before attempting
+ * an MPU OFF. The save and restore happens from the SRAM sleep code.
+ * The address is stored in scratchpad, so that it can be used
+ * during the restore path.
+ */
+u32 omap3_arm_context[128];
+
#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
@@ -62,3 +134,134 @@ void omap_ctrl_writel(u32 val, u16 offset)
__raw_writel(val, OMAP_CTRL_REGADDR(offset));
}
+#ifdef CONFIG_ARCH_OMAP3
+/*
+ * Clears the scratchpad contents in case of cold boot-
+ * called during bootup
+ */
+void omap3_clear_scratchpad_contents(void)
+{
+ u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
+ u32 *v_addr;
+ u32 offset = 0;
+ v_addr = OMAP2_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
+ if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
+ OMAP3430_GLOBAL_COLD_RST) {
+ for ( ; offset <= max_offset; offset += 0x4)
+ __raw_writel(0x0, (v_addr + offset));
+ prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,
+ OMAP3_PRM_RSTST_OFFSET);
+ }
+}
+
+/* Populate the scratchpad structure with restore structure */
+void omap3_save_scratchpad_contents(void)
+{
+ void * __iomem scratchpad_address;
+ u32 arm_context_addr;
+ struct omap3_scratchpad scratchpad_contents;
+ struct omap3_scratchpad_prcm_block prcm_block_contents;
+ struct omap3_scratchpad_sdrc_block sdrc_block_contents;
+
+ /* Populate the Scratchpad contents */
+ scratchpad_contents.boot_config_ptr = 0x0;
+ scratchpad_contents.public_restore_ptr =
+virt_to_phys(get_restore_pointer());
+ scratchpad_contents.secure_ram_restore_ptr = 0x0;
+ scratchpad_contents.sdrc_module_semaphore = 0x0;
+ scratchpad_contents.prcm_block_offset = 0x2C;
+ scratchpad_contents.sdrc_block_offset = 0x64;
+
+ /* Populate the PRCM block contents */
+ prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
+ OMAP3_PRM_CLKSRC_CTRL_OFFSET);
+ prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
+ OMAP3_PRM_CLKSEL_OFFSET);
+ prcm_block_contents.cm_clksel_core =
+ cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
+ prcm_block_contents.cm_clksel_wkup =
+ cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
+ prcm_block_contents.cm_clken_pll =
+ cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKEN_PLL);
+ prcm_block_contents.cm_autoidle_pll =
+ cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
+ prcm_block_contents.cm_clksel1_pll =
+ cm_read_mod_reg(PLL_MOD,
[PATCH 08/27] OMAP3: PM: handle PER/NEON/CORE in idle
From: Rajendra Nayak
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm34xx.c | 64 +++--
1 files changed, 54 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 9dbb5a0..7eab539 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -49,7 +49,10 @@ static LIST_HEAD(pwrst_list);
static void (*_omap_sram_idle)(u32 *addr, int save_state);
-static struct powerdomain *mpu_pwrdm;
+static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
+static struct powerdomain *core_pwrdm, *per_pwrdm;
+
+static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
/*
* PRCM Interrupt Handler Helper Function
@@ -169,13 +172,22 @@ static void omap_sram_idle(void)
/* save_state = 1 => Only L1 and logic lost */
/* save_state = 2 => Only L2 lost */
/* save_state = 3 => L1, L2 and logic lost */
- int save_state = 0, mpu_next_state;
+ int save_state = 0;
+ int mpu_next_state = PWRDM_POWER_ON;
+ int per_next_state = PWRDM_POWER_ON;
+ int core_next_state = PWRDM_POWER_ON;
if (!_omap_sram_idle)
return;
+ pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
+ pwrdm_clear_all_prev_pwrst(neon_pwrdm);
+ pwrdm_clear_all_prev_pwrst(core_pwrdm);
+ pwrdm_clear_all_prev_pwrst(per_pwrdm);
+
mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
switch (mpu_next_state) {
+ case PWRDM_POWER_ON:
case PWRDM_POWER_RET:
/* No need to save context */
save_state = 0;
@@ -187,18 +199,37 @@ static void omap_sram_idle(void)
}
pwrdm_pre_transition();
- omap2_gpio_prepare_for_retention();
- omap_uart_prepare_idle(0);
- omap_uart_prepare_idle(1);
- omap_uart_prepare_idle(2);
+ /* NEON control */
+ if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
+ set_pwrdm_state(neon_pwrdm, mpu_next_state);
+
+ /* CORE & PER */
+ core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
+ if (core_next_state < PWRDM_POWER_ON) {
+ omap2_gpio_prepare_for_retention();
+ omap_uart_prepare_idle(0);
+ omap_uart_prepare_idle(1);
+ /* PER changes only with core */
+ per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
+ if (per_next_state < PWRDM_POWER_ON)
+ omap_uart_prepare_idle(2);
+ /* Enable IO-PAD wakeup */
+ prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
+ }
_omap_sram_idle(NULL, save_state);
cpu_init();
- omap_uart_resume_idle(2);
- omap_uart_resume_idle(1);
- omap_uart_resume_idle(0);
- omap2_gpio_resume_after_retention();
+ if (core_next_state < PWRDM_POWER_ON) {
+ if (per_next_state < PWRDM_POWER_ON)
+ omap_uart_resume_idle(2);
+ omap_uart_resume_idle(1);
+ omap_uart_resume_idle(0);
+
+ /* Disable IO-PAD wakeup */
+ prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
+ omap2_gpio_resume_after_retention();
+ }
pwrdm_post_transition();
@@ -791,6 +822,10 @@ static int __init omap3_pm_init(void)
goto err2;
}
+ neon_pwrdm = pwrdm_lookup("neon_pwrdm");
+ per_pwrdm = pwrdm_lookup("per_pwrdm");
+ core_pwrdm = pwrdm_lookup("core_pwrdm");
+
omap_push_sram_idle();
#ifdef CONFIG_SUSPEND
suspend_set_ops(&omap_pm_ops);
@@ -798,6 +833,15 @@ static int __init omap3_pm_init(void)
pm_idle = omap3_pm_idle;
+ pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
+ /*
+* REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
+* IO-pad wakeup. Otherwise it will unnecessarily waste power
+* waking up PER with every CORE wakeup - see
+* http://marc.info/?l=linux-omap&m=121852150710062&w=2
+ */
+ pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
+
err1:
return ret;
err2:
--
1.6.4.3
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[PATCH 04/27] OMAP3: PM: PRCM context save/restore
From: Rajendra Nayak
Additional registers (CM_CLKSEL4, CM_CLKEN, CM_CLKEN2) added by Tero
Kristo.
Signed-off-by: Rajendra Nayak
Signed-off-by: Tero Kristo
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/prcm.c| 384 +
arch/arm/plat-omap/include/mach/control.h |2 +
arch/arm/plat-omap/include/mach/prcm.h|5 +
3 files changed, 391 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index ced555a..9322447 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -7,6 +7,9 @@
*
* Written by Tony Lindgren
*
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Rajendra Nayak
+ *
* Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -21,8 +24,11 @@
#include
#include
+#include
+#include
#include "clock.h"
+#include "cm.h"
#include "prm.h"
#include "prm-regbits-24xx.h"
@@ -31,6 +37,87 @@ static void __iomem *cm_base;
#define MAX_MODULE_ENABLE_WAIT 10
+struct omap3_prcm_regs {
+ u32 control_padconf_sys_nirq;
+ u32 iva2_cm_clksel2;
+ u32 cm_sysconfig;
+ u32 sgx_cm_clksel;
+ u32 wkup_cm_clksel;
+ u32 dss_cm_clksel;
+ u32 cam_cm_clksel;
+ u32 per_cm_clksel;
+ u32 emu_cm_clksel;
+ u32 emu_cm_clkstctrl;
+ u32 pll_cm_autoidle2;
+ u32 pll_cm_clksel4;
+ u32 pll_cm_clksel5;
+ u32 pll_cm_clken;
+ u32 pll_cm_clken2;
+ u32 cm_polctrl;
+ u32 iva2_cm_fclken;
+ u32 core_cm_fclken1;
+ u32 core_cm_fclken3;
+ u32 sgx_cm_fclken;
+ u32 wkup_cm_fclken;
+ u32 dss_cm_fclken;
+ u32 cam_cm_fclken;
+ u32 per_cm_fclken;
+ u32 usbhost_cm_fclken;
+ u32 core_cm_iclken1;
+ u32 core_cm_iclken2;
+ u32 core_cm_iclken3;
+ u32 sgx_cm_iclken;
+ u32 wkup_cm_iclken;
+ u32 dss_cm_iclken;
+ u32 cam_cm_iclken;
+ u32 per_cm_iclken;
+ u32 usbhost_cm_iclken;
+ u32 iva2_cm_autiidle2;
+ u32 mpu_cm_autoidle2;
+ u32 pll_cm_autoidle;
+ u32 iva2_cm_clkstctrl;
+ u32 mpu_cm_clkstctrl;
+ u32 core_cm_clkstctrl;
+ u32 sgx_cm_clkstctrl;
+ u32 dss_cm_clkstctrl;
+ u32 cam_cm_clkstctrl;
+ u32 per_cm_clkstctrl;
+ u32 neon_cm_clkstctrl;
+ u32 usbhost_cm_clkstctrl;
+ u32 core_cm_autoidle1;
+ u32 core_cm_autoidle2;
+ u32 core_cm_autoidle3;
+ u32 wkup_cm_autoidle;
+ u32 dss_cm_autoidle;
+ u32 cam_cm_autoidle;
+ u32 per_cm_autoidle;
+ u32 usbhost_cm_autoidle;
+ u32 sgx_cm_sleepdep;
+ u32 dss_cm_sleepdep;
+ u32 cam_cm_sleepdep;
+ u32 per_cm_sleepdep;
+ u32 usbhost_cm_sleepdep;
+ u32 cm_clkout_ctrl;
+ u32 prm_clkout_ctrl;
+ u32 sgx_pm_wkdep;
+ u32 dss_pm_wkdep;
+ u32 cam_pm_wkdep;
+ u32 per_pm_wkdep;
+ u32 neon_pm_wkdep;
+ u32 usbhost_pm_wkdep;
+ u32 core_pm_mpugrpsel1;
+ u32 iva2_pm_ivagrpsel1;
+ u32 core_pm_mpugrpsel3;
+ u32 core_pm_ivagrpsel3;
+ u32 wkup_pm_mpugrpsel;
+ u32 wkup_pm_ivagrpsel;
+ u32 per_pm_mpugrpsel;
+ u32 per_pm_ivagrpsel;
+ u32 wkup_pm_wken;
+};
+
+struct omap3_prcm_regs prcm_context;
+
u32 omap_prcm_get_reset_sources(void)
{
/* XXX This presumably needs modification for 34XX */
@@ -168,3 +255,300 @@ void __init omap2_set_globals_prcm(struct omap_globals
*omap2_globals)
prm_base = omap2_globals->prm;
cm_base = omap2_globals->cm;
}
+
+#ifdef CONFIG_ARCH_OMAP3
+void omap3_prcm_save_context(void)
+{
+ prcm_context.control_padconf_sys_nirq =
+omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
+ prcm_context.iva2_cm_clksel2 =
+cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
+ prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
+ prcm_context.sgx_cm_clksel =
+cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
+ prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
+ prcm_context.dss_cm_clksel =
+cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
+ prcm_context.cam_cm_clksel =
+cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
+ prcm_context.per_cm_clksel =
+cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
+ prcm_context.emu_cm_clksel =
+cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
+ prcm_context.emu_cm_clkstctrl =
+cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
+ prcm_context.pll_cm_autoidle2 =
+cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
+ prcm_context.pll_cm_clksel4 =
+ cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL
[PATCH 03/27] OMAP3: PM: INTC context save/restore
From: Rajendra Nayak
Signed-off-by: Rajendra Nayak
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/irq.c | 66
arch/arm/plat-omap/include/mach/irqs.h |5 ++
2 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 8db0e3a..fa2524d 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -25,6 +25,10 @@
#define INTC_SYSSTATUS 0x0014
#define INTC_SIR 0x0040
#define INTC_CONTROL 0x0048
+#define INTC_PROTECTION0x004C
+#define INTC_IDLE 0x0050
+#define INTC_THRESHOLD 0x0068
+#define INTC_MIR0 0x0084
#define INTC_MIR_CLEAR00x0088
#define INTC_MIR_SET0 0x008c
#define INTC_PENDING_IRQ0 0x0098
@@ -48,6 +52,18 @@ static struct omap_irq_bank {
},
};
+/* Structure to save interrupt controller context */
+struct omap3_intc_regs {
+ u32 sysconfig;
+ u32 protection;
+ u32 idle;
+ u32 threshold;
+ u32 ilr[INTCPS_NR_IRQS];
+ u32 mir[INTCPS_NR_MIR_REGS];
+};
+
+static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
+
/* INTC bank register get/set */
static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
@@ -201,3 +217,53 @@ void __init omap_init_irq(void)
}
}
+#ifdef CONFIG_ARCH_OMAP3
+void omap3_intc_save_context(void)
+{
+ int ind = 0, i = 0;
+ for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
+ struct omap_irq_bank *bank = irq_banks + ind;
+ intc_context[ind].sysconfig =
+ intc_bank_read_reg(bank, INTC_SYSCONFIG);
+ intc_context[ind].protection =
+ intc_bank_read_reg(bank, INTC_PROTECTION);
+ intc_context[ind].idle =
+ intc_bank_read_reg(bank, INTC_IDLE);
+ intc_context[ind].threshold =
+ intc_bank_read_reg(bank, INTC_THRESHOLD);
+ for (i = 0; i < INTCPS_NR_IRQS; i++)
+ intc_context[ind].ilr[i] =
+ intc_bank_read_reg(bank, (0x100 + 0x4*ind));
+ for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
+ intc_context[ind].mir[i] =
+ intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
+ (0x20 * i));
+ }
+}
+
+void omap3_intc_restore_context(void)
+{
+ int ind = 0, i = 0;
+
+ for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
+ struct omap_irq_bank *bank = irq_banks + ind;
+ intc_bank_write_reg(intc_context[ind].sysconfig,
+ bank, INTC_SYSCONFIG);
+ intc_bank_write_reg(intc_context[ind].sysconfig,
+ bank, INTC_SYSCONFIG);
+ intc_bank_write_reg(intc_context[ind].protection,
+ bank, INTC_PROTECTION);
+ intc_bank_write_reg(intc_context[ind].idle,
+ bank, INTC_IDLE);
+ intc_bank_write_reg(intc_context[ind].threshold,
+ bank, INTC_THRESHOLD);
+ for (i = 0; i < INTCPS_NR_IRQS; i++)
+ intc_bank_write_reg(intc_context[ind].ilr[i],
+ bank, (0x100 + 0x4*ind));
+ for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
+ intc_bank_write_reg(intc_context[ind].mir[i],
+&irq_banks[0], INTC_MIR0 + (0x20 * i));
+ }
+ /* MIRs are saved and restore with other PRCM registers */
+}
+#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/plat-omap/include/mach/irqs.h
b/arch/arm/plat-omap/include/mach/irqs.h
index 6a6d028..2473910 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -477,9 +477,14 @@
#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
+#define INTCPS_NR_MIR_REGS 3
+#define INTCPS_NR_IRQS 96
+
#ifndef __ASSEMBLY__
extern void omap_init_irq(void);
extern int omap_irq_pending(void);
+void omap3_intc_save_context(void);
+void omap3_intc_restore_context(void);
#endif
#include
--
1.6.4.3
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[PATCH 00/27] OMAP3: PM: base off-mode support
This series adds the base off-mode support to the OMAP3 PM core. The code originates from the OMAP PM branch[1] and has been tested broadly on a variety of OMAP3 platforms. It is currently based on Tony's for-next branch since it depends on the IO address space rework series. This series is also available in the branch 'pm-upstream/pm-off' in my linux-omap-pm git repo at git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git Kevin [1] http://elinux.org/OMAP_Power_Management Aaro Koskinen (2): OMAP: PM: Clear DMA channel state after a wakeup OMAP3: PM: Fix INTC context save/restore Jouni Hogander (1): OMAP3: PM: Save and restore also CM_CLKSEL1_PLL_IVA2 Juha Yrjola (1): OMAP: Store reboot mode in scratchpad on OMAP34xx Kalle Jokiniemi (4): OMAP3: PM: Fix secure SRAM context save/restore ARM: OMAP: Add missing SMS_SYSCONFIG save/restore OMAP3: PM: Fix PLL_MOD CLKEN offset in scratchpad PM: Disable usb host HW save and restore Kevin Hilman (2): OMAP3: PM debug: allow runtime toggle of PM features PM debug: allow configurable wakeup from suspend on OMAP GPtimer Peter 'p2' De Schrijver (1): OMAP3: PM: Wait for SDRC ready iso a blind delay Rajendra Nayak (11): OMAP3: PM: GPMC context save/restore OMAP3: PM: GPIO context save/restore OMAP3: PM: INTC context save/restore OMAP3: PM: PRCM context save/restore OMAP3: PM: Populate scratchpad contents OMAP3: PM: SCM context save/restore OMAP3: PM: SRAM restore function OMAP3: PM: handle PER/NEON/CORE in idle OMAP3: PM: Restore MMU table entry OMAP3: PM: MPU off-mode support OMAP3: PM: CORE domain off-mode support Tero Kristo (5): OMAP: PM: DMA context save/restore for off-mode support OMAP3 PM: off-mode support for HS/EMU devices OMAP3: PM: save secure RAM only during init OMAP3: PM: Enable SDRAM auto-refresh during sleep OMAP3: PM: SDRC auto-refresh workaround for off-mode arch/arm/mach-omap2/control.c | 364 ++ arch/arm/mach-omap2/gpmc.c| 98 +++- arch/arm/mach-omap2/irq.c | 66 + arch/arm/mach-omap2/pm-debug.c| 29 ++ arch/arm/mach-omap2/pm.h | 10 + arch/arm/mach-omap2/pm34xx.c | 321 ++- arch/arm/mach-omap2/powerdomains34xx.h|8 +- arch/arm/mach-omap2/prcm.c| 402 - arch/arm/mach-omap2/sdrc.c| 27 ++ arch/arm/mach-omap2/serial.c |2 - arch/arm/mach-omap2/sleep34xx.S | 218 ++-- arch/arm/mach-omap2/timer-gp.c|2 + arch/arm/plat-omap/dma.c | 62 +- arch/arm/plat-omap/gpio.c | 93 +++ arch/arm/plat-omap/include/mach/control.h | 14 + arch/arm/plat-omap/include/mach/dma.h |5 + arch/arm/plat-omap/include/mach/gpio.h|3 +- arch/arm/plat-omap/include/mach/gpmc.h|3 + arch/arm/plat-omap/include/mach/irqs.h|5 + arch/arm/plat-omap/include/mach/prcm.h|5 + arch/arm/plat-omap/include/mach/sdrc.h|2 + arch/arm/plat-omap/include/mach/sram.h|2 + arch/arm/plat-omap/sram.c |6 +- 23 files changed, 1700 insertions(+), 47 deletions(-) mode change 100644 => 100755 arch/arm/plat-omap/include/mach/dma.h -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/6] omap: headers: Create headers necessary for compile under mach-omap1 and mach-omap2
Create the headers needed for compiling under mach-omap1/include/mach and mach-omap2/include/mach. This was done with the following script: #!/bin/bash mach_files="clkdev.h gpio.h hardware.h io.h irqs.h memory.h \ smp.h system.h timex.h uncompress.h vmalloc.h" omaps="mach-omap1 mach-omap2" mach_dir_old="arch/arm/plat-omap/include/mach" plat_dir_new="arch/arm/plat-omap/include/plat" mkdir -p $plat_dir_new git add $plat_dir_new for dir in $omaps; do mach_dir_new="arch/arm/$dir/include/mach" for header in $mach_files; do file="$mach_dir_new/$header" echo -ne "/*\n * $file\n */\n\n#include \n" > $file git add $file git mv $mach_dir_old/$header $plat_dir_new/$header done done Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/include/mach/clkdev.h |5 arch/arm/mach-omap1/include/mach/gpio.h |5 arch/arm/mach-omap1/include/mach/hardware.h |5 arch/arm/mach-omap1/include/mach/io.h |5 arch/arm/mach-omap1/include/mach/irqs.h |5 arch/arm/mach-omap1/include/mach/memory.h |5 arch/arm/mach-omap1/include/mach/smp.h|5 arch/arm/mach-omap1/include/mach/system.h |5 arch/arm/mach-omap1/include/mach/timex.h |5 arch/arm/mach-omap1/include/mach/uncompress.h |5 arch/arm/mach-omap1/include/mach/vmalloc.h|5 arch/arm/mach-omap2/include/mach/clkdev.h |5 arch/arm/mach-omap2/include/mach/gpio.h |5 arch/arm/mach-omap2/include/mach/hardware.h |5 arch/arm/mach-omap2/include/mach/io.h |5 arch/arm/mach-omap2/include/mach/irqs.h |5 arch/arm/mach-omap2/include/mach/memory.h |5 arch/arm/mach-omap2/include/mach/smp.h|5 arch/arm/mach-omap2/include/mach/system.h |5 arch/arm/mach-omap2/include/mach/timex.h |5 arch/arm/mach-omap2/include/mach/uncompress.h |5 arch/arm/mach-omap2/include/mach/vmalloc.h|5 arch/arm/plat-omap/include/mach/clkdev.h | 13 - arch/arm/plat-omap/include/mach/gpio.h| 128 -- arch/arm/plat-omap/include/mach/hardware.h| 290 - arch/arm/plat-omap/include/mach/io.h | 241 --- arch/arm/plat-omap/include/mach/irqs.h| 568 - arch/arm/plat-omap/include/mach/memory.h | 96 arch/arm/plat-omap/include/mach/smp.h | 51 -- arch/arm/plat-omap/include/mach/system.h | 51 -- arch/arm/plat-omap/include/mach/timex.h | 41 -- arch/arm/plat-omap/include/mach/uncompress.h | 83 arch/arm/plat-omap/include/mach/vmalloc.h | 21 - arch/arm/plat-omap/include/plat/clkdev.h | 13 + arch/arm/plat-omap/include/plat/gpio.h| 128 ++ arch/arm/plat-omap/include/plat/hardware.h| 290 + arch/arm/plat-omap/include/plat/io.h | 241 +++ arch/arm/plat-omap/include/plat/irqs.h| 568 + arch/arm/plat-omap/include/plat/memory.h | 96 arch/arm/plat-omap/include/plat/smp.h | 51 ++ arch/arm/plat-omap/include/plat/system.h | 51 ++ arch/arm/plat-omap/include/plat/timex.h | 41 ++ arch/arm/plat-omap/include/plat/uncompress.h | 83 arch/arm/plat-omap/include/plat/vmalloc.h | 21 + 44 files changed, 1693 insertions(+), 1583 deletions(-) create mode 100644 arch/arm/mach-omap1/include/mach/clkdev.h create mode 100644 arch/arm/mach-omap1/include/mach/gpio.h create mode 100644 arch/arm/mach-omap1/include/mach/hardware.h create mode 100644 arch/arm/mach-omap1/include/mach/io.h create mode 100644 arch/arm/mach-omap1/include/mach/irqs.h create mode 100644 arch/arm/mach-omap1/include/mach/memory.h create mode 100644 arch/arm/mach-omap1/include/mach/smp.h create mode 100644 arch/arm/mach-omap1/include/mach/system.h create mode 100644 arch/arm/mach-omap1/include/mach/timex.h create mode 100644 arch/arm/mach-omap1/include/mach/uncompress.h create mode 100644 arch/arm/mach-omap1/include/mach/vmalloc.h create mode 100644 arch/arm/mach-omap2/include/mach/clkdev.h create mode 100644 arch/arm/mach-omap2/include/mach/gpio.h create mode 100644 arch/arm/mach-omap2/include/mach/hardware.h create mode 100644 arch/arm/mach-omap2/include/mach/io.h create mode 100644 arch/arm/mach-omap2/include/mach/irqs.h create mode 100644 arch/arm/mach-omap2/include/mach/memory.h create mode 100644 arch/arm/mach-omap2/include/mach/smp.h create mode 100644 arch/arm/mach-omap2/include/mach/system.h create mode 100644 arch/arm/mach-omap2/include/mach/timex.h create mode 100644 arch/arm/mach-omap2/include/mach/uncompress.h create mode 100644 arch/arm/mach-omap2/include/mach/vmalloc.h delete mode 100644 arch/arm/plat-omap/include/mach/clkdev.h delete mode 100644 arch/arm/plat-omap/include/mach/gpio.h delete mode 100644 arch/arm/plat-omap/include/mach/hardware.h delete mode 100644 arch/arm/plat
[PATCH 3/6] omap: headers: Split entry-macro.S for mach-omap1 and mach-omap2
Split entry-macro.S for mach-omap1 and mach-omap2 Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/include/mach/entry-macro.S | 58 arch/arm/mach-omap2/include/mach/entry-macro.S | 122 + arch/arm/plat-omap/include/mach/entry-macro.S | 172 3 files changed, 180 insertions(+), 172 deletions(-) create mode 100644 arch/arm/mach-omap1/include/mach/entry-macro.S create mode 100644 arch/arm/mach-omap2/include/mach/entry-macro.S delete mode 100644 arch/arm/plat-omap/include/mach/entry-macro.S diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S new file mode 100644 index 000..2e98f86 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/entry-macro.S @@ -0,0 +1,58 @@ +/* + * arch/arm/mach-omap1/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for OMAP-based platforms + * + * Copyright (C) 2009 Texas Instruments + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include + +#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \ + (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) +#error "FIXME: OMAP730 doesn't support multiple-OMAP" +#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) +#define INT_IH2_IRQINT_730_IH2_IRQ +#elif defined(CONFIG_ARCH_OMAP15XX) +#define INT_IH2_IRQINT_1510_IH2_IRQ +#elif defined(CONFIG_ARCH_OMAP16XX) +#define INT_IH2_IRQINT_1610_IH2_IRQ +#else +#warning "IH2 IRQ defaulted" +#define INT_IH2_IRQINT_1510_IH2_IRQ +#endif + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE) + ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET] + ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET] + mov \irqstat, #0x + bic \tmp, \irqstat, \tmp + tst \irqnr, \tmp + beq 1510f + + ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET] + cmp \irqnr, #0 + ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] + cmpeq \irqnr, #INT_IH2_IRQ + ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE) + ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] + addeqs \irqnr, \irqnr, #32 +1510: + .endm + diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S similarity index 73% rename from arch/arm/plat-omap/include/mach/entry-macro.S rename to arch/arm/mach-omap2/include/mach/entry-macro.S index a559299..aafa0f6 100644 --- a/arch/arm/plat-omap/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -15,54 +15,6 @@ #include #include -#if defined(CONFIG_ARCH_OMAP1) - -#if defined(CONFIG_ARCH_OMAP730) && \ - (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) -#error "FIXME: OMAP730 doesn't support multiple-OMAP" -#elif defined(CONFIG_ARCH_OMAP730) -#define INT_IH2_IRQINT_730_IH2_IRQ -#elif defined(CONFIG_ARCH_OMAP15XX) -#define INT_IH2_IRQINT_1510_IH2_IRQ -#elif defined(CONFIG_ARCH_OMAP16XX) -#define INT_IH2_IRQINT_1610_IH2_IRQ -#else -#warning "IH2 IRQ defaulted" -#define INT_IH2_IRQINT_1510_IH2_IRQ -#endif - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE) - ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET] - ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET] - mov \irqstat, #0x - bic \tmp, \irqstat, \tmp - tst \irqnr, \tmp - beq 1510f - - ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET] - cmp \irqnr, #0 - ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] - cmpeq \irqnr, #INT_IH2_IRQ - ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE) - ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] - addeqs \irqnr, \irqnr, #32 -1510: - .endm - -#endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) - #include #incl
[PATCH 4/6] omap: headers: Move mtd-xip.h to be mach-omap1 specific
These registers are omap1 specific. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/include/mach/mtd-xip.h | 61 arch/arm/plat-omap/include/mach/mtd-xip.h | 61 2 files changed, 61 insertions(+), 61 deletions(-) create mode 100644 arch/arm/mach-omap1/include/mach/mtd-xip.h delete mode 100644 arch/arm/plat-omap/include/mach/mtd-xip.h diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/mach-omap1/include/mach/mtd-xip.h similarity index 100% rename from arch/arm/plat-omap/include/mach/mtd-xip.h rename to arch/arm/mach-omap1/include/mach/mtd-xip.h -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/6] omap: headers: Split debug-macro.S for mach-omap1 and mach-omap2
This also creates the include/mach subdirectories under mach-omap1 and mach-omap2. REVISIT: Remove "OMAP-730 only" parts in mach-omap2 version Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/include/mach/debug-macro.S | 45 +++ arch/arm/mach-omap2/include/mach/debug-macro.S | 59 arch/arm/plat-omap/include/mach/debug-macro.S | 70 3 files changed, 104 insertions(+), 70 deletions(-) create mode 100644 arch/arm/mach-omap1/include/mach/debug-macro.S create mode 100644 arch/arm/mach-omap2/include/mach/debug-macro.S delete mode 100644 arch/arm/plat-omap/include/mach/debug-macro.S diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S new file mode 100644 index 000..aedb746 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/debug-macro.S @@ -0,0 +1,45 @@ +/* arch/arm/mach-omap1/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0xff00@ physical base address + movne \rx, #0xfe00@ virtual base + orr \rx, \rx, #0x00fb +#ifdef CONFIG_OMAP_LL_DEBUG_UART3 + orr \rx, \rx, #0x9000 @ UART 3 +#endif +#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3) + orr \rx, \rx, #0x0800 @ UART 2 & 3 +#endif + .endm + + .macro senduart,rd,rx + strb\rd, [\rx] + .endm + + .macro busyuart,rd,rx +1001: ldrb\rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends + and \rd, \rd, #0x60 + teq \rd, #0x60 + beq 1002f + ldrb\rd, [\rx, #(0x5 << 0)] @ OMAP-730 only + and \rd, \rd, #0x60 + teq \rd, #0x60 + bne 1001b +1002: + .endm + + .macro waituart,rd,rx + .endm diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S similarity index 76% rename from arch/arm/plat-omap/include/mach/debug-macro.S rename to arch/arm/mach-omap2/include/mach/debug-macro.S index ac24050..271b9d8 100644 --- a/arch/arm/plat-omap/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -1,4 +1,4 @@ -/* arch/arm/plat-omap/include/mach/debug-macro.S +/* arch/arm/mach-omap2/include/mach/debug-macro.S * * Debugging macro include header * @@ -14,18 +14,7 @@ .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? -#ifdef CONFIG_ARCH_OMAP1 - moveq \rx, #0xff00@ physical base address - movne \rx, #0xfe00@ virtual base - orr \rx, \rx, #0x00fb -#ifdef CONFIG_OMAP_LL_DEBUG_UART3 - orr \rx, \rx, #0x9000 @ UART 3 -#endif -#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3) - orr \rx, \rx, #0x0800 @ UART 2 & 3 -#endif - -#elif CONFIG_ARCH_OMAP2 +#ifdef CONFIG_ARCH_OMAP2 moveq \rx, #0x4800@ physical base address movne \rx, #0xd800@ virtual base orr \rx, \rx, #0x0006a000 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/6] omap: headers: Add mach patch to include files
This is to prepare for moving hardware.h to live under plat instead of mach. Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/mach/hardware.h | 12 ++-- 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h index 26c1fbf..f746c9d 100644 --- a/arch/arm/plat-omap/include/mach/hardware.h +++ b/arch/arm/plat-omap/include/mach/hardware.h @@ -280,11 +280,11 @@ * --- */ -#include "omap730.h" -#include "omap1510.h" -#include "omap16xx.h" -#include "omap24xx.h" -#include "omap34xx.h" -#include "omap44xx.h" +#include +#include +#include +#include +#include +#include #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/6] Reorganize omap headers to have include/plat
Hi all, Here is a series for the merge window after 2.6.32 to reorganize the omap headers as suggested by Russell earlier at [1]. Basically we currently have everything under a single mach directory: arch/arm/plat-omap/include/mach This series creates the common plat, and separate mach directories: arch/arm/plat-omap/include/plat arch/arm/mach-omap1/include/mach arch/arm/mach-omap2/include/mach This series is intentionally mostly search and replace, and only splits a few headers in the first few patches to keep things compiling. The rest is done with shell scripts. I obviously will need to refresh these patches and other patches that will get added on top of these, but those changes should be quite minimal. After this series further work on the headers can be done easily. Regards, Tony [1] http://www.mail-archive.com/linux-omap@vger.kernel.org/msg15085.html --- Tony Lindgren (6): omap: headers: Move remaining headers from include/mach to include/plat omap: headers: Create headers necessary for compile under mach-omap1 and mach-omap2 omap: headers: Move mtd-xip.h to be mach-omap1 specific omap: headers: Split entry-macro.S for mach-omap1 and mach-omap2 omap: headers: Split debug-macro.S for mach-omap1 and mach-omap2 omap: headers: Add mach patch to include files arch/arm/mach-omap1/board-ams-delta.c | 12 arch/arm/mach-omap1/board-fsample.c| 14 arch/arm/mach-omap1/board-generic.c|8 arch/arm/mach-omap1/board-h2-mmc.c |2 arch/arm/mach-omap1/board-h2.c | 16 arch/arm/mach-omap1/board-h3-mmc.c |2 arch/arm/mach-omap1/board-h3.c | 14 arch/arm/mach-omap1/board-innovator.c | 14 arch/arm/mach-omap1/board-nokia770.c | 22 arch/arm/mach-omap1/board-osk.c| 10 arch/arm/mach-omap1/board-palmte.c | 16 arch/arm/mach-omap1/board-palmtt.c | 18 arch/arm/mach-omap1/board-palmz71.c| 18 arch/arm/mach-omap1/board-perseus2.c | 14 arch/arm/mach-omap1/board-sx1-mmc.c|4 arch/arm/mach-omap1/board-sx1.c| 18 arch/arm/mach-omap1/board-voiceblue.c |8 arch/arm/mach-omap1/clock.c|8 arch/arm/mach-omap1/devices.c |8 arch/arm/mach-omap1/fpga.c |2 arch/arm/mach-omap1/id.c |2 arch/arm/mach-omap1/include/mach/clkdev.h |5 arch/arm/mach-omap1/include/mach/debug-macro.S | 45 + arch/arm/mach-omap1/include/mach/entry-macro.S | 58 + arch/arm/mach-omap1/include/mach/gpio.h|5 arch/arm/mach-omap1/include/mach/hardware.h|5 arch/arm/mach-omap1/include/mach/io.h |5 arch/arm/mach-omap1/include/mach/irqs.h|5 arch/arm/mach-omap1/include/mach/memory.h |5 arch/arm/mach-omap1/include/mach/mtd-xip.h | 61 + arch/arm/mach-omap1/include/mach/smp.h |5 arch/arm/mach-omap1/include/mach/system.h |5 arch/arm/mach-omap1/include/mach/timex.h |5 arch/arm/mach-omap1/include/mach/uncompress.h |5 arch/arm/mach-omap1/include/mach/vmalloc.h |5 arch/arm/mach-omap1/io.c |4 arch/arm/mach-omap1/irq.c |2 arch/arm/mach-omap1/leds-h2p2-debug.c |2 arch/arm/mach-omap1/leds.c |2 arch/arm/mach-omap1/mailbox.c |2 arch/arm/mach-omap1/mcbsp.c| 10 arch/arm/mach-omap1/mux.c |2 arch/arm/mach-omap1/pm.c | 14 arch/arm/mach-omap1/serial.c |6 arch/arm/mach-omap1/timer32k.c |2 arch/arm/mach-omap2/board-2430sdp.c| 12 arch/arm/mach-omap2/board-3430sdp.c| 22 arch/arm/mach-omap2/board-4430sdp.c|8 arch/arm/mach-omap2/board-apollon.c| 14 arch/arm/mach-omap2/board-generic.c|8 arch/arm/mach-omap2/board-h4.c | 18 arch/arm/mach-omap2/board-ldp.c| 14 arch/arm/mach-omap2/board-n8x0.c | 10 arch/arm/mach-omap2/board-omap3beagle.c| 14 arch/arm/mach-omap2/board-omap3evm.c | 12 arch/arm/mach-omap2/board-omap3pandora.c | 12 arch/arm/mach-omap2/board-overo.c | 14 arch/arm/mach-omap2/board-rx51-peripherals.c | 18 arch/arm/mach-omap2/board-rx51.c | 16 arch/arm/mach-omap2/board-zoom-debugboard.c|2 arch/arm/mach-omap2/board-zoom2.c |6
Re: [PATCH 00/17] Massive OMAP730/OMAP850 cleanup
* Alistair Buxton [091014 13:03]:
> Reposting the full series for review. Assuming this is all OK would it
> be a good idea to merge the config variables into a single
> CONFIG_ARCH_OMAP7XX? There doesn't seem to be any reason to have both.
> Original description follows.
Yeah, those should be merged too. Let's do that as a separate patch.
Regards,
Tony
>
>
> Hello from the Linwizard project,
>
> We have been working on supporting omap850 smartphones from HTC such
> as Wizard, Herald etc. We have found that omap730 and omap850 are
> almost exactly the same. As far as what is supported in linux-omap so
> far, they are identical. Currently there are seperate code paths for
> 730 and 850, and this is causing us a lot of problems when one is
> changed and the other isn't. I also noticed that OMAP F-Sample board
> uses ARCH_OMAP730 even though it has a OMAP850 SoC.
>
> In order to try to clean this up I have produced a patch series which
> removes all cpu_is_omap730/850 and replaces them with unified
> cpu_is_omap7xx() blocks, and similarly merges CONFIG checks. Here is a
> random example:
>
> -#ifdef CONFIG_ARCH_OMAP730
> - if (cpu_is_omap730()) {
> +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
> + if (cpu_is_omap7xx()) {
> irq_banks = omap730_irq_banks;
> irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
> }
> #endif
> -#ifdef CONFIG_ARCH_OMAP850
> - if (cpu_is_omap850()) {
> - irq_banks = omap850_irq_banks;
> - irq_bank_count = ARRAY_SIZE(omap850_irq_banks);
> - }
> -#endif
>
> Drilling down through the variables shows they are always equivalent
> for 730 and 850, except where there is a bug.
>
> This makes several bugs go away for us on omap850, including the
> MPUIO_VBASE bug, and the lack of working IRQs - since these bugs arn't
> in the 730 paths. It would hopefully prevent similar bugs from showing
> up in the future too.
>
> Alistair Buxton (16):
> OMAP7XX: Serial: Remove duplicate omap850 code
> OMAP7XX: GPIO: Remove duplicate omap850 code
> OMAP7XX: IO: Remove duplicate omap850 code
> OMAP7XX: Mux: Remove duplicate omap850 code
> OMAP7XX: USB: Remove duplicate omap850 code
> OMAP7XX: IRQ: Remove duplicate omap850 code
> OMAP7XX: PM: Add omap850 support
> OMAP7XX: Clocks: Add omap850 support
> OMAP7XX: McBSP: Add omap850 support
> OMAP7XX: Create omap7xx.h
> OMAP7XX: Update core omap1 files to use omap7xx.h
> OMAP7XX: Replace omap730 references in irqs.h and all users
> OMAP7XX: Rename all the rest of the omap730 references in omap1 core
> OMAP7XX: omap_uwire.c: Convert to omap7xx.h
> OMAP850: PM: Add an ARCH_OMAP850 check
> OMAP850: Fix zImage booting
>
> Angelo Arrifano (1):
> OMAP7XX: Clocks: Add ck_ref and armxor
>
> arch/arm/mach-omap1/board-fsample.c | 18 +-
> arch/arm/mach-omap1/board-perseus2.c | 18 +-
> arch/arm/mach-omap1/clock.c | 24 ++--
> arch/arm/mach-omap1/io.c | 45 ++
> arch/arm/mach-omap1/irq.c | 32 +---
> arch/arm/mach-omap1/mcbsp.c | 32 ++--
> arch/arm/mach-omap1/mux.c | 70 +++-
> arch/arm/mach-omap1/pm.c | 100 ++--
> arch/arm/mach-omap1/pm.h | 53 +++---
> arch/arm/mach-omap1/serial.c | 13 +-
> arch/arm/mach-omap1/sleep.S | 22 ++--
> arch/arm/plat-omap/devices.c | 22 ++--
> arch/arm/plat-omap/gpio.c | 227
> +++--
> arch/arm/plat-omap/include/mach/entry-macro.S |8 +-
> arch/arm/plat-omap/include/mach/hardware.h|2 +-
> arch/arm/plat-omap/include/mach/irqs.h| 229
> -
> arch/arm/plat-omap/include/mach/mcbsp.h |6 +-
> arch/arm/plat-omap/include/mach/mux.h | 100 +++
> arch/arm/plat-omap/include/mach/omap7xx.h | 104 +++
> arch/arm/plat-omap/include/mach/uncompress.h |3 +-
> arch/arm/plat-omap/io.c | 14 +-
> arch/arm/plat-omap/usb.c | 10 +-
> drivers/spi/omap_uwire.c |8 +-
> 23 files changed, 480 insertions(+), 680 deletions(-)
> create mode 100644 arch/arm/plat-omap/include/mach/omap7xx.h
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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Re: SMP: BUG with PREEMPT enabled
On Wed, Oct 14, 2009 at 04:56:18PM +0530, Shilimkar, Santosh wrote: > Here is the patch I used to fix this BUG. Patch is good. Could you send it to the patch system. Please note that the patch system now almost accepts standard patch submissions (in other words, it no longer requires the "PATCH FOLLOWS" tag.) However, it still requires the "KernelVersion:" tag to appear somewhere before the patch. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: stable kernel version
Tony Lindgren schrieb: >> Hi Tony, >> >> the 2.6.30 head booted fine until the point where it >> waited for the SD-Card to get ready. There it just hung >> forever. >> > > Hmm, 2.6.30 may not have all the core stuff in it yet. > > >> the 2.6.31 head crashed instantly after the uncompression >> of the kernel image. >> > > There are few patches still pending to get to mainline > via other mailing lists, you can see them in omap-testing > branch. > > >> I will try out the 2.6.31 mainline kernel tommorw. >> > > OK, also I just pushed updated omap-debug branch that > I forgot to rebase on top of current linux-omap master > branch (Thanks Paul for letting me know!). > > Tony > > I just realized, that I made myself not clear about the kernels I tested. I used omap-2.6.30 head and omap-2.6.31 head. Janosch -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 17/17] OMAP850: Fix zImage booting
This adds the OMAP850 JTAG ID to the IDs checked by OMAP uncompress.h putc. Without this putc hangs up trying to check the uarts and zImage crashes. Signed-off-by: Alistair Buxton --- arch/arm/plat-omap/include/mach/uncompress.h |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/arm/plat-omap/include/mach/uncompress.h b/arch/arm/plat-omap/include/mach/uncompress.h index 0814c5f..ddf7b88 100644 --- a/arch/arm/plat-omap/include/mach/uncompress.h +++ b/arch/arm/plat-omap/include/mach/uncompress.h @@ -25,6 +25,7 @@ unsigned int system_rev; #define UART_OMAP_MDR1 0x08/* mode definition register */ #define OMAP_ID_7300x355F +#define OMAP_ID_8500x362C #define ID_MASK0x7fff #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) #define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK @@ -53,7 +54,7 @@ static void putc(int c) /* MMU is not on, so cpu_is_omap() won't work here */ unsigned int omap_id = omap_get_id(); - if (omap_id == OMAP_ID_730) + if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850) shift = 0; if (check_port(uart, shift)) -- 1.6.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 16/17] OMAP850: PM: Add an ARCH_OMAP850 check
This just makes the same warning be printed on omap850 and omap730. Signed-off-by: Alistair Buxton --- arch/arm/mach-omap1/pm.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h index 0f20aed..56a6479 100644 --- a/arch/arm/mach-omap1/pm.h +++ b/arch/arm/mach-omap1/pm.h @@ -105,6 +105,7 @@ #define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00 #if !defined(CONFIG_ARCH_OMAP730) && \ + !defined(CONFIG_ARCH_OMAP850) && \ !defined(CONFIG_ARCH_OMAP15XX) && \ !defined(CONFIG_ARCH_OMAP16XX) #warning "Power management for this processor not implemented yet" -- 1.6.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 15/17] OMAP7XX: Clocks: Add ck_ref and armxor
These clocks are required for booting.
Signed-off-by: Angelo Arrifano
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/mach-omap1/clock.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index d2b00a5..5f77b83 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -75,7 +75,7 @@ struct omap_clk {
static struct omap_clk omap_clks[] = {
/* non-ULPD clocks */
- CLK(NULL, "ck_ref", &ck_ref,CK_16XX | CK_1510 |
CK_310),
+ CLK(NULL, "ck_ref", &ck_ref,CK_16XX | CK_1510 |
CK_310 | CK_7XX),
CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 |
CK_310),
/* CK_GEN1 clocks */
CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
@@ -83,7 +83,7 @@ static struct omap_clk omap_clks[] = {
CLK(NULL, "arm_ck", &arm_ck,CK_16XX | CK_1510 |
CK_310),
CLK(NULL, "armper_ck",&armper_ck.clk, CK_16XX | CK_1510 |
CK_310),
CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310),
- CLK(NULL, "armxor_ck",&armxor_ck.clk, CK_16XX | CK_1510 |
CK_310),
+ CLK(NULL, "armxor_ck",&armxor_ck.clk, CK_16XX | CK_1510 |
CK_310 | CK_7XX),
CLK(NULL, "armtim_ck",&armtim_ck.clk, CK_16XX | CK_1510 |
CK_310),
CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 |
CK_310),
CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
--
1.6.5
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[PATCH 14/17] OMAP7XX: omap_uwire.c: Convert to omap7xx.h
This also replaces CPU checks with cpu_is_omap7xx()
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
drivers/spi/omap_uwire.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/omap_uwire.c b/drivers/spi/omap_uwire.c
index e75ba9b..7bcf409 100644
--- a/drivers/spi/omap_uwire.c
+++ b/drivers/spi/omap_uwire.c
@@ -52,7 +52,7 @@
#include
#include
-#include /* OMAP730_IO_CONF registers */
+#include /* OMAP7XX_IO_CONF registers */
/* FIXME address is now a platform device resource,
@@ -504,7 +504,7 @@ static int __init uwire_probe(struct platform_device *pdev)
}
clk_enable(uwire->ck);
- if (cpu_is_omap730())
+ if (cpu_is_omap7xx())
uwire_idx_shift = 1;
else
uwire_idx_shift = 2;
@@ -573,8 +573,8 @@ static int __init omap_uwire_init(void)
}
if (machine_is_omap_perseus2()) {
/* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
- int val = omap_readl(OMAP730_IO_CONF_9) & ~0x00EEE000;
- omap_writel(val | 0x00AAA000, OMAP730_IO_CONF_9);
+ int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
+ omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
}
return platform_driver_probe(&uwire_driver, uwire_probe);
--
1.6.5
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[PATCH 13/17] OMAP7XX: Rename all the rest of the omap730 references in omap1 core
This patch is part of a series which removes references to omap730 in code
which is shared with omap850, replacing them with references to omap7xx.
This updates all the remaining omap730 references in miscellaneous local
variables, macros and similar.
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/mach-omap1/clock.c |8 +-
arch/arm/mach-omap1/io.c|4 +-
arch/arm/mach-omap1/irq.c |6 +-
arch/arm/mach-omap1/mcbsp.c | 18 +++---
arch/arm/mach-omap1/mux.c | 42 +++---
arch/arm/mach-omap1/pm.c| 70
arch/arm/mach-omap1/pm.h| 52 +-
arch/arm/mach-omap1/sleep.S | 22
arch/arm/plat-omap/devices.c| 22
arch/arm/plat-omap/gpio.c | 92 +++---
arch/arm/plat-omap/include/mach/mcbsp.h |4 +-
arch/arm/plat-omap/include/mach/mux.h | 42 +++---
12 files changed, 191 insertions(+), 191 deletions(-)
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index c24cc28..d2b00a5 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -69,7 +69,7 @@ struct omap_clk {
}
#define CK_310 (1 << 0)
-#define CK_730 (1 << 1)
+#define CK_7XX (1 << 1)
#define CK_1510(1 << 2)
#define CK_16XX(1 << 3)
@@ -97,7 +97,7 @@ static struct omap_clk omap_clks[] = {
CLK(NULL, "dspxor_ck",&dspxor_ck, CK_16XX | CK_1510 |
CK_310),
CLK(NULL, "dsptim_ck",&dsptim_ck, CK_16XX | CK_1510 |
CK_310),
/* CK_GEN3 clocks */
- CLK(NULL, "tc_ck",&tc_ck.clk, CK_16XX | CK_1510 |
CK_310 | CK_730),
+ CLK(NULL, "tc_ck",&tc_ck.clk, CK_16XX | CK_1510 |
CK_310 | CK_7XX),
CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck,CK_16XX),
CLK(NULL, "tc1_ck", &tc1_ck,CK_16XX),
@@ -108,7 +108,7 @@ static struct omap_clk omap_clks[] = {
CLK(NULL, "lb_ck",&lb_ck.clk, CK_1510 | CK_310),
CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
- CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_730),
+ CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
/* ULPD clocks */
CLK(NULL, "uart1_ck", &uart1_1510,CK_1510 | CK_310),
@@ -784,7 +784,7 @@ int __init omap1_clk_init(void)
if (cpu_is_omap1510())
cpu_mask |= CK_1510;
if (cpu_is_omap7xx())
- cpu_mask |= CK_730;
+ cpu_mask |= CK_7XX;
if (cpu_is_omap310())
cpu_mask |= CK_310;
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 157d508..a27df2c 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -37,7 +37,7 @@ static struct map_desc omap_io_desc[] __initdata = {
};
#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
-static struct map_desc omap730_io_desc[] __initdata = {
+static struct map_desc omap7xx_io_desc[] __initdata = {
{
.virtual= OMAP7XX_DSP_BASE,
.pfn= __phys_to_pfn(OMAP7XX_DSP_START),
@@ -106,7 +106,7 @@ void __init omap1_map_common_io(void)
#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
if (cpu_is_omap7xx()) {
- iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc));
+ iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 704a80c..8f98b58 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -138,7 +138,7 @@ static void omap_irq_set_cfg(int irq, int fiq, int
priority, int trigger)
}
#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
-static struct omap_irq_bank omap730_irq_banks[] = {
+static struct omap_irq_bank omap7xx_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE,.trigger_map = 0xb3f8e22f },
{ .base_reg = OMAP_IH2_BASE,.trigger_map = 0xfdb9c1f2 },
{ .base_reg = OMAP_IH2_BASE + 0x100,.trigger_map = 0x800040f3 },
@@ -180,8 +180,8 @@ void __init omap_init_irq(void)
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
if (cpu_is_omap7xx()) {
- irq_banks = omap730_irq_banks;
- irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
+ irq_banks = omap7xx_irq_banks;
+ irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
diff --git a/arch/
[PATCH 12/17] OMAP7XX: Replace omap730 references in irqs.h and all users
This patch is part of a series which removes references to omap730 in code
which is shared with omap850, replacing them with references to omap7xx.
Turns INT_730_* to INT_7XX_* for definitions in irqs.h and all users.
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/mach-omap1/board-fsample.c |6 +-
arch/arm/mach-omap1/board-perseus2.c |6 +-
arch/arm/mach-omap1/irq.c |2 +-
arch/arm/mach-omap1/mcbsp.c |8 +-
arch/arm/mach-omap1/pm.c | 10 +-
arch/arm/mach-omap1/serial.c |4 +-
arch/arm/plat-omap/gpio.c | 14 +-
arch/arm/plat-omap/include/mach/entry-macro.S |2 +-
arch/arm/plat-omap/include/mach/irqs.h| 148
arch/arm/plat-omap/usb.c |4 +-
10 files changed, 102 insertions(+), 102 deletions(-)
diff --git a/arch/arm/mach-omap1/board-fsample.c
b/arch/arm/mach-omap1/board-fsample.c
index e53f774..74720e6 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -107,7 +107,7 @@ static struct resource smc91x_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = INT_730_MPU_EXT_NIRQ,
+ .start = INT_7XX_MPU_EXT_NIRQ,
.end= 0,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
@@ -196,8 +196,8 @@ static struct platform_device smc91x_device = {
static struct resource kp_resources[] = {
[0] = {
- .start = INT_730_MPUIO_KEYPAD,
- .end= INT_730_MPUIO_KEYPAD,
+ .start = INT_7XX_MPUIO_KEYPAD,
+ .end= INT_7XX_MPUIO_KEYPAD,
.flags = IORESOURCE_IRQ,
},
};
diff --git a/arch/arm/mach-omap1/board-perseus2.c
b/arch/arm/mach-omap1/board-perseus2.c
index ec22838..2f897cf 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -74,7 +74,7 @@ static struct resource smc91x_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = INT_730_MPU_EXT_NIRQ,
+ .start = INT_7XX_MPU_EXT_NIRQ,
.end= 0,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
@@ -163,8 +163,8 @@ static struct platform_device smc91x_device = {
static struct resource kp_resources[] = {
[0] = {
- .start = INT_730_MPUIO_KEYPAD,
- .end= INT_730_MPUIO_KEYPAD,
+ .start = INT_7XX_MPUIO_KEYPAD,
+ .end= INT_7XX_MPUIO_KEYPAD,
.flags = IORESOURCE_IRQ,
},
};
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index c05999c..704a80c 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -234,7 +234,7 @@ void __init omap_init_irq(void)
/* Unmask level 2 handler */
if (cpu_is_omap7xx())
- omap_unmask_irq(INT_730_IH2_IRQ);
+ omap_unmask_irq(INT_7XX_IH2_IRQ);
else if (cpu_is_omap15xx())
omap_unmask_irq(INT_1510_IH2_IRQ);
else if (cpu_is_omap16xx())
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 06f380b..7ccca00 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -85,16 +85,16 @@ static struct omap_mcbsp_platform_data
omap730_mcbsp_pdata[] = {
.phys_base = OMAP730_MCBSP1_BASE,
.dma_rx_sync= OMAP_DMA_MCBSP1_RX,
.dma_tx_sync= OMAP_DMA_MCBSP1_TX,
- .rx_irq = INT_730_McBSP1RX,
- .tx_irq = INT_730_McBSP1TX,
+ .rx_irq = INT_7XX_McBSP1RX,
+ .tx_irq = INT_7XX_McBSP1TX,
.ops= &omap1_mcbsp_ops,
},
{
.phys_base = OMAP730_MCBSP2_BASE,
.dma_rx_sync= OMAP_DMA_MCBSP3_RX,
.dma_tx_sync= OMAP_DMA_MCBSP3_TX,
- .rx_irq = INT_730_McBSP2RX,
- .tx_irq = INT_730_McBSP2TX,
+ .rx_irq = INT_7XX_McBSP2RX,
+ .tx_irq = INT_7XX_McBSP2TX,
.ops= &omap1_mcbsp_ops,
},
};
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 12f246e..58479c7 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -184,8 +184,8 @@ static void omap_pm_wakeup_setup(void)
* wake up to a GPIO interrupt.
*/
if (cpu_is_omap7xx())
- level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
- OMAP_IRQ_BIT(INT_730_IH2_IRQ);
+ level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
+ OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
else if (cpu_is_omap15xx())
[PATCH 10/17] OMAP7XX: Create omap7xx.h
This patch is part of a series which removes references to omap730 in code which is shared with omap850, replacing them with references to omap7xx. This include file is intended to replace omap730.h and omap850.h All values defined herein are identical to those in both the old files. Signed-off-by: Alistair Buxton Reviewed-by: Zebediah C. McClure --- arch/arm/plat-omap/include/mach/omap7xx.h | 104 + 1 files changed, 104 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-omap/include/mach/omap7xx.h diff --git a/arch/arm/plat-omap/include/mach/omap7xx.h b/arch/arm/plat-omap/include/mach/omap7xx.h new file mode 100644 index 000..53f5241 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/omap7xx.h @@ -0,0 +1,104 @@ +/* arch/arm/plat-omap/include/mach/omap7xx.h + * + * Hardware definitions for TI OMAP7XX processor. + * + * Cleanup for Linux-2.6 by Dirk Behme + * Adapted for omap850 by Zebediah C. McClure + * Adapted for omap7xx by Alistair Buxton + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP7XX_H +#define __ASM_ARCH_OMAP7XX_H + +/* + * + * Base addresses + * + */ + +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ + +#define OMAP7XX_DSP_BASE 0xE000 +#define OMAP7XX_DSP_SIZE 0x5 +#define OMAP7XX_DSP_START 0xE000 + +#define OMAP7XX_DSPREG_BASE0xE100 +#define OMAP7XX_DSPREG_SIZESZ_128K +#define OMAP7XX_DSPREG_START 0xE100 + +/* + * + * OMAP7XX specific configuration registers + * + */ +#define OMAP7XX_CONFIG_BASE0xfffe1000 +#define OMAP7XX_IO_CONF_0 0xfffe1070 +#define OMAP7XX_IO_CONF_1 0xfffe1074 +#define OMAP7XX_IO_CONF_2 0xfffe1078 +#define OMAP7XX_IO_CONF_3 0xfffe107c +#define OMAP7XX_IO_CONF_4 0xfffe1080 +#define OMAP7XX_IO_CONF_5 0xfffe1084 +#define OMAP7XX_IO_CONF_6 0xfffe1088 +#define OMAP7XX_IO_CONF_7 0xfffe108c +#define OMAP7XX_IO_CONF_8 0xfffe1090 +#define OMAP7XX_IO_CONF_9 0xfffe1094 +#define OMAP7XX_IO_CONF_10 0xfffe1098 +#define OMAP7XX_IO_CONF_11 0xfffe109c +#define OMAP7XX_IO_CONF_12 0xfffe10a0 +#define OMAP7XX_IO_CONF_13 0xfffe10a4 + +#define OMAP7XX_MODE_1 0xfffe1010 +#define OMAP7XX_MODE_2 0xfffe1014 + +/* CSMI specials: in terms of base + offset */ +#define OMAP7XX_MODE2_OFFSET 0x14 + +/* + * + * OMAP7XX traffic controller configuration registers + * + */ +#define OMAP7XX_FLASH_CFG_00xfffecc10 +#define OMAP7XX_FLASH_ACFG_0 0xfffecc50 +#define OMAP7XX_FLASH_CFG_10xfffecc14 +#define OMAP7XX_FLASH_ACFG_1 0xfffecc54 + +/* + * + * OMAP7XX DSP control registers + * + */ +#define OMAP7XX_ICR_BASE 0xfffbb800 +#define OMAP7XX_DSP_M_CTL 0xfffbb804 +#define OMAP7XX_DSP_MMU_BASE 0xfffed200 + +/* + * + * OMAP7XX PCC_UPLD configuration registers + * + */ +#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900) +#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00) + +#endif /* __ASM_ARCH_OMAP7XX_H */ + -- 1.6.5 -- To unsubscribe from
[PATCH 11/17] OMAP7XX: Update core omap1 files to use omap7xx.h
This patch is part of a series which removes references to omap730 in code
which is shared with omap850, replacing them with references to omap7xx.
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/mach-omap1/board-fsample.c| 12 ++--
arch/arm/mach-omap1/board-perseus2.c | 12 ++--
arch/arm/mach-omap1/clock.c|2 +-
arch/arm/mach-omap1/io.c | 12 ++--
arch/arm/plat-omap/include/mach/hardware.h |2 +-
arch/arm/plat-omap/include/mach/mux.h | 14 +++---
arch/arm/plat-omap/io.c| 12 ++--
7 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/arch/arm/mach-omap1/board-fsample.c
b/arch/arm/mach-omap1/board-fsample.c
index a7ead1b..e53f774 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -309,7 +309,7 @@ static void __init omap_fsample_map_io(void)
/*
* Hold GSM Reset until needed
*/
- omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
+ omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
/*
* UARTs -> done automagically by 8250 driver
@@ -320,21 +320,21 @@ static void __init omap_fsample_map_io(void)
*/
/* Flash: CS0 timings setup */
- omap_writel(0xfff3, OMAP730_FLASH_CFG_0);
- omap_writel(0x0088, OMAP730_FLASH_ACFG_0);
+ omap_writel(0xfff3, OMAP7XX_FLASH_CFG_0);
+ omap_writel(0x0088, OMAP7XX_FLASH_ACFG_0);
/*
* Ethernet support through the debug board
* CS1 timings setup
*/
- omap_writel(0xfff3, OMAP730_FLASH_CFG_1);
- omap_writel(0x, OMAP730_FLASH_ACFG_1);
+ omap_writel(0xfff3, OMAP7XX_FLASH_CFG_1);
+ omap_writel(0x, OMAP7XX_FLASH_ACFG_1);
/*
* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
* It is used as the Ethernet controller interrupt
*/
- omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFF,
OMAP730_IO_CONF_9);
+ omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFF,
OMAP7XX_IO_CONF_9);
}
MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
diff --git a/arch/arm/mach-omap1/board-perseus2.c
b/arch/arm/mach-omap1/board-perseus2.c
index 8340669..ec22838 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -270,7 +270,7 @@ static void __init omap_perseus2_map_io(void)
/*
* Hold GSM Reset until needed
*/
- omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
+ omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
/*
* UARTs -> done automagically by 8250 driver
@@ -281,21 +281,21 @@ static void __init omap_perseus2_map_io(void)
*/
/* Flash: CS0 timings setup */
- omap_writel(0xfff3, OMAP730_FLASH_CFG_0);
- omap_writel(0x0088, OMAP730_FLASH_ACFG_0);
+ omap_writel(0xfff3, OMAP7XX_FLASH_CFG_0);
+ omap_writel(0x0088, OMAP7XX_FLASH_ACFG_0);
/*
* Ethernet support through the debug board
* CS1 timings setup
*/
- omap_writel(0xfff3, OMAP730_FLASH_CFG_1);
- omap_writel(0x, OMAP730_FLASH_ACFG_1);
+ omap_writel(0xfff3, OMAP7XX_FLASH_CFG_1);
+ omap_writel(0x, OMAP7XX_FLASH_ACFG_1);
/*
* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
* It is used as the Ethernet controller interrupt
*/
- omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFF,
OMAP730_IO_CONF_9);
+ omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFF,
OMAP7XX_IO_CONF_9);
}
MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index fcbea61..c24cc28 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -862,7 +862,7 @@ int __init omap1_clk_init(void)
#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
/* Select slicer output as OMAP input clock */
- omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1,
OMAP730_PCC_UPLD_CTRL);
+ omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
OMAP7XX_PCC_UPLD_CTRL);
#endif
/* Amstrad Delta wants BCLK high when inactive */
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 19de57f..157d508 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -39,14 +39,14 @@ static struct map_desc omap_io_desc[] __initdata = {
#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
static struct map_desc omap730_io_desc[] __initdata = {
{
- .virtual= OMAP730_DSP_BASE,
- .pfn= __phys_to_pfn(OMAP730_DSP_START),
- .length = OMAP730_DSP_SIZE,
+
[PATCH 09/17] OMAP7XX: McBSP: Add omap850 support
This patch is part of a series which unifies all duplicated code between
omap730 and omap850. All cpu checks are converted to cpu_is_omap7xx() and
CONFIG_ARCH_OMAP850 is added to all CONFIG_ARCH_OMAP730 checks.
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/mach-omap1/mcbsp.c |6 +++---
arch/arm/plat-omap/include/mach/mcbsp.h |2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 505d98c..06f380b 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -79,7 +79,7 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
.free = omap1_mcbsp_free,
};
-#ifdef CONFIG_ARCH_OMAP730
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
{
.phys_base = OMAP730_MCBSP1_BASE,
@@ -172,7 +172,7 @@ static struct omap_mcbsp_platform_data
omap16xx_mcbsp_pdata[] = {
int __init omap1_mcbsp_init(void)
{
- if (cpu_is_omap730())
+ if (cpu_is_omap7xx())
omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ;
if (cpu_is_omap15xx())
omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
@@ -184,7 +184,7 @@ int __init omap1_mcbsp_init(void)
if (!mcbsp_ptr)
return -ENOMEM;
- if (cpu_is_omap730())
+ if (cpu_is_omap7xx())
omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
OMAP730_MCBSP_PDATA_SZ);
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h
b/arch/arm/plat-omap/include/mach/mcbsp.h
index e0d6eca..0b476b9 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -58,7 +58,7 @@
#define OMAP44XX_MCBSP3_BASE 0x49026000
#define OMAP44XX_MCBSP4_BASE 0x48074000
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) ||
defined(CONFIG_ARCH_OMAP730)
+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) ||
defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
#define OMAP_MCBSP_REG_DRR20x00
#define OMAP_MCBSP_REG_DRR10x02
--
1.6.5
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[PATCH 08/17] OMAP7XX: Clocks: Add omap850 support
This patch is part of a series which unifies all duplicated code between omap730 and omap850. All cpu checks are converted to cpu_is_omap7xx() and CONFIG_ARCH_OMAP850 is added to all CONFIG_ARCH_OMAP730 checks. This file had no omap850 specific code. Initial clock support was done in the Linwizard tree by Zebediah C. McClure. Signed-off-by: Alistair Buxton Reviewed-by: Zebediah C. McClure --- arch/arm/mach-omap1/clock.c | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 436eed2..fcbea61 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -398,7 +398,7 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate) * Reprogramming the DPLL is tricky, it must be done from SRAM. * (on 730, bit 13 must always be 1) */ - if (cpu_is_omap730()) + if (cpu_is_omap7xx()) omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); else omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); @@ -783,7 +783,7 @@ int __init omap1_clk_init(void) cpu_mask |= CK_16XX; if (cpu_is_omap1510()) cpu_mask |= CK_1510; - if (cpu_is_omap730()) + if (cpu_is_omap7xx()) cpu_mask |= CK_730; if (cpu_is_omap310()) cpu_mask |= CK_310; @@ -800,7 +800,7 @@ int __init omap1_clk_init(void) crystal_type = info->system_clock_type; } -#if defined(CONFIG_ARCH_OMAP730) +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) ck_ref.rate = 1300; #elif defined(CONFIG_ARCH_OMAP16XX) if (crystal_type == 2) @@ -847,7 +847,7 @@ int __init omap1_clk_init(void) printk(KERN_ERR "System frequencies not set. Check your config.\n"); /* Guess sane values (60MHz) */ omap_writew(0x2290, DPLL_CTL); - omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); + omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); ck_dpll1.rate = 6000; } #endif @@ -873,7 +873,7 @@ int __init omap1_clk_init(void) /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ /* (on 730, bit 13 must not be cleared) */ - if (cpu_is_omap730()) + if (cpu_is_omap7xx()) omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); else omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); -- 1.6.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 07/17] OMAP7XX: PM: Add omap850 support
This patch is part of a series which unifies all duplicated code between
omap730 and omap850. All cpu checks are converted to cpu_is_omap7xx() and
CONFIG_ARCH_OMAP850 is added to all CONFIG_ARCH_OMAP730 checks.
This file had no omap850 specific code. Original omap850 support in Linwizard
was done by cloning the omap730 code. That work was done by Zebediah C. McClure.
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/mach-omap1/pm.c | 20 ++--
1 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 5218943..12f246e 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -183,7 +183,7 @@ static void omap_pm_wakeup_setup(void)
* drivers must still separately call omap_set_gpio_wakeup() to
* wake up to a GPIO interrupt.
*/
- if (cpu_is_omap730())
+ if (cpu_is_omap7xx())
level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
OMAP_IRQ_BIT(INT_730_IH2_IRQ);
else if (cpu_is_omap15xx())
@@ -195,7 +195,7 @@ static void omap_pm_wakeup_setup(void)
omap_writel(~level1_wake, OMAP_IH1_MIR);
- if (cpu_is_omap730()) {
+ if (cpu_is_omap7xx()) {
omap_writel(~level2_wake, OMAP_IH2_0_MIR);
omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
@@ -253,7 +253,7 @@ void omap1_pm_suspend(void)
* Save interrupt, MPUI, ARM and UPLD control registers.
*/
- if (cpu_is_omap730()) {
+ if (cpu_is_omap7xx()) {
MPUI730_SAVE(OMAP_IH1_MIR);
MPUI730_SAVE(OMAP_IH2_0_MIR);
MPUI730_SAVE(OMAP_IH2_1_MIR);
@@ -306,7 +306,7 @@ void omap1_pm_suspend(void)
omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
/* shut down dsp_ck */
- if (!cpu_is_omap730())
+ if (!cpu_is_omap7xx())
omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK),
ARM_CKCTL);
/* temporarily enabling api_ck to access DSP registers */
@@ -383,7 +383,7 @@ void omap1_pm_suspend(void)
ULPD_RESTORE(ULPD_CLOCK_CTRL);
ULPD_RESTORE(ULPD_STATUS_REQ);
- if (cpu_is_omap730()) {
+ if (cpu_is_omap7xx()) {
MPUI730_RESTORE(EMIFS_CONFIG);
MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
MPUI730_RESTORE(OMAP_IH1_MIR);
@@ -461,7 +461,7 @@ static int omap_pm_read_proc(
ULPD_SAVE(ULPD_DPLL_CTRL);
ULPD_SAVE(ULPD_POWER_CTRL);
- if (cpu_is_omap730()) {
+ if (cpu_is_omap7xx()) {
MPUI730_SAVE(MPUI_CTRL);
MPUI730_SAVE(MPUI_DSP_STATUS);
MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
@@ -517,7 +517,7 @@ static int omap_pm_read_proc(
ULPD_SHOW(ULPD_STATUS_REQ),
ULPD_SHOW(ULPD_POWER_CTRL));
- if (cpu_is_omap730()) {
+ if (cpu_is_omap7xx()) {
my_buffer_offset += sprintf(my_base + my_buffer_offset,
"MPUI730_CTRL_REG 0x%-8x \n"
"MPUI730_DSP_STATUS_REG: 0x%-8x \n"
@@ -668,7 +668,7 @@ static int __init omap_pm_init(void)
* These routines need to be in SRAM as that's the only
* memory the MPU can see when it wakes up.
*/
- if (cpu_is_omap730()) {
+ if (cpu_is_omap7xx()) {
omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
omap730_cpu_suspend_sz);
} else if (cpu_is_omap15xx()) {
@@ -686,7 +686,7 @@ static int __init omap_pm_init(void)
pm_idle = omap1_pm_idle;
- if (cpu_is_omap730())
+ if (cpu_is_omap7xx())
setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
else if (cpu_is_omap16xx())
setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
@@ -700,7 +700,7 @@ static int __init omap_pm_init(void)
omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
/* Configure IDLECT3 */
- if (cpu_is_omap730())
+ if (cpu_is_omap7xx())
omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
else if (cpu_is_omap16xx())
omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
--
1.6.5
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[PATCH 05/17] OMAP7XX: USB: Remove duplicate omap850 code
This patch is part of a series which unifies all duplicated code between
omap730 and omap850. All cpu checks are converted to cpu_is_omap7xx() and
CONFIG_ARCH_OMAP850 is added to all CONFIG_ARCH_OMAP730 checks.
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/plat-omap/usb.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 509f2ed..980d2eb 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -614,7 +614,7 @@ omap_otg_init(struct omap_usb_config *config)
if (config->otg || config->register_host) {
syscon &= ~HST_IDLE_EN;
ohci_device.dev.platform_data = config;
- if (cpu_is_omap730())
+ if (cpu_is_omap7xx())
ohci_resources[1].start = INT_730_USB_HHC_1;
status = platform_device_register(&ohci_device);
if (status)
@@ -626,7 +626,7 @@ omap_otg_init(struct omap_usb_config *config)
if (config->otg) {
syscon &= ~OTG_IDLE_EN;
otg_device.dev.platform_data = config;
- if (cpu_is_omap730())
+ if (cpu_is_omap7xx())
otg_resources[1].start = INT_730_USB_OTG;
status = platform_device_register(&otg_device);
if (status)
@@ -731,7 +731,7 @@ static inline void omap_1510_usb_init(struct
omap_usb_config *config) {}
void __init omap_usb_init(struct omap_usb_config *pdata)
{
- if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx())
+ if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx())
omap_otg_init(pdata);
else if (cpu_is_omap15xx())
omap_1510_usb_init(pdata);
--
1.6.5
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[PATCH 04/17] OMAP7XX: Mux: Remove duplicate omap850 code
This patch is part of a series which unifies all duplicated code between
omap730 and omap850. All cpu checks are converted to cpu_is_omap7xx() and
CONFIG_ARCH_OMAP850 is added to all CONFIG_ARCH_OMAP730 checks.
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/mach-omap1/mux.c | 28 +-
arch/arm/plat-omap/include/mach/mux.h | 50 -
2 files changed, 2 insertions(+), 76 deletions(-)
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 721e0d9..f9d45a3 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -35,7 +35,7 @@
static struct omap_mux_cfg arch_mux_cfg;
-#ifdef CONFIG_ARCH_OMAP730
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
static struct pin_config __initdata_or_module omap730_pins[] = {
MUX_CFG_730("E2_730_KBR0",12, 21,0, 20, 1, 0)
MUX_CFG_730("J7_730_KBR1",12, 25,0, 24, 1, 0)
@@ -58,25 +58,6 @@ MUX_CFG_730("W17_730_USB_VBUSI", 2, 29,0,
28, 0, 0)
#define OMAP730_PINS_SZ0
#endif /* CONFIG_ARCH_OMAP730 */
-#ifdef CONFIG_ARCH_OMAP850
-struct pin_config __initdata_or_module omap850_pins[] = {
-MUX_CFG_850("E2_850_KBR0",12, 21,0, 20, 1, 0)
-MUX_CFG_850("J7_850_KBR1",12, 25,0, 24, 1, 0)
-MUX_CFG_850("E1_850_KBR2",12, 29,0, 28, 1, 0)
-MUX_CFG_850("F3_850_KBR3",13,1,0,0, 1, 0)
-MUX_CFG_850("D2_850_KBR4",13,5,0,4, 1, 0)
-MUX_CFG_850("C2_850_KBC0",13,9,0,8, 1, 0)
-MUX_CFG_850("D3_850_KBC1",13, 13,0, 12, 1, 0)
-MUX_CFG_850("E4_850_KBC2",13, 17,0, 16, 1, 0)
-MUX_CFG_850("F4_850_KBC3",13, 21,0, 20, 1, 0)
-MUX_CFG_850("E3_850_KBC4",13, 25,0, 24, 1, 0)
-
-MUX_CFG_850("AA17_850_USB_DM", 2, 21,0, 20, 0, 0)
-MUX_CFG_850("W16_850_USB_PU_EN", 2, 25,0, 24, 0, 0)
-MUX_CFG_850("W17_850_USB_VBUSI", 2, 29,0, 28, 0, 0)
-};
-#endif
-
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
static struct pin_config __initdata_or_module omap1xxx_pins[] = {
/*
@@ -438,11 +419,6 @@ int __init_or_module omap1_cfg_reg(const struct
pin_config *cfg)
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pull_name, cfg->pull_reg, pull_orig, pull);
}
-
-#ifdef CONFIG_ARCH_OMAP850
- omap_mux_register(omap850_pins, ARRAY_SIZE(omap850_pins));
-#endif
-
#endif
#ifdef CONFIG_OMAP_MUX_ERRORS
@@ -454,7 +430,7 @@ int __init_or_module omap1_cfg_reg(const struct
pin_config *cfg)
int __init omap1_mux_init(void)
{
- if (cpu_is_omap730()) {
+ if (cpu_is_omap7xx()) {
arch_mux_cfg.pins = omap730_pins;
arch_mux_cfg.size = OMAP730_PINS_SZ;
arch_mux_cfg.cfg_reg= omap1_cfg_reg;
diff --git a/arch/arm/plat-omap/include/mach/mux.h
b/arch/arm/plat-omap/include/mach/mux.h
index 0f49d2d..587fb63 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -61,16 +61,6 @@
.pull_bit = bit, \
.pull_val = status,
-#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name =
"OMAP850_IO_CONF_"#reg, \
- .mux_reg = OMAP850_IO_CONF_##reg, \
- .mask_offset = mode_offset, \
- .mask = mode,
-
-#define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \
- .pull_reg = OMAP850_IO_CONF_##reg, \
- .pull_bit = bit, \
- .pull_val = status,
-
#else
#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
@@ -93,15 +83,6 @@
.pull_bit = bit, \
.pull_val = status,
-#define MUX_REG_850(reg, mode_offset, mode) \
- .mux_reg = OMAP850_IO_CONF_##reg, \
- .mask_offset = mode_offset, \
- .mask = mode,
-
-#define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \
- .pull_bit = bit, \
- .pull_val = status,
-
#endif /* CONFIG_OMAP_MUX_DEBUG */
#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
@@ -133,17 +114,6 @@
PU_PD_REG(NA, 0)\
},
-#define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \
- pull_bit, pull_status, debug_status)\
-{ \
- .name = desc, \
- .debug = debug_status,
[PATCH 03/17] OMAP7XX: IO: Remove duplicate omap850 code
This patch is part of a series which unifies all duplicated code between
omap730 and omap850. All cpu checks are converted to cpu_is_omap7xx() and
CONFIG_ARCH_OMAP850 is added to all CONFIG_ARCH_OMAP730 checks.
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/mach-omap1/io.c | 29 +++--
arch/arm/plat-omap/io.c |2 +-
2 files changed, 4 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 7030f92..19de57f 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -36,7 +36,7 @@ static struct map_desc omap_io_desc[] __initdata = {
}
};
-#ifdef CONFIG_ARCH_OMAP730
+#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
static struct map_desc omap730_io_desc[] __initdata = {
{
.virtual= OMAP730_DSP_BASE,
@@ -52,22 +52,6 @@ static struct map_desc omap730_io_desc[] __initdata = {
};
#endif
-#ifdef CONFIG_ARCH_OMAP850
-static struct map_desc omap850_io_desc[] __initdata = {
- {
- .virtual= OMAP850_DSP_BASE,
- .pfn= __phys_to_pfn(OMAP850_DSP_START),
- .length = OMAP850_DSP_SIZE,
- .type = MT_DEVICE
- }, {
- .virtual= OMAP850_DSPREG_BASE,
- .pfn= __phys_to_pfn(OMAP850_DSPREG_START),
- .length = OMAP850_DSPREG_SIZE,
- .type = MT_DEVICE
- }
-};
-#endif
-
#ifdef CONFIG_ARCH_OMAP15XX
static struct map_desc omap1510_io_desc[] __initdata = {
{
@@ -120,18 +104,11 @@ void __init omap1_map_common_io(void)
*/
omap_check_revision();
-#ifdef CONFIG_ARCH_OMAP730
- if (cpu_is_omap730()) {
+#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
+ if (cpu_is_omap7xx()) {
iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc));
}
#endif
-
-#ifdef CONFIG_ARCH_OMAP850
- if (cpu_is_omap850()) {
- iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc));
- }
-#endif
-
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap15xx()) {
iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index b6defa2..388fd94 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -33,7 +33,7 @@ void __iomem *omap_ioremap(unsigned long p, size_t
size, unsigned int type)
if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
}
- if (cpu_is_omap730()) {
+ if (cpu_is_omap7xx()) {
if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START);
--
1.6.5
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[PATCH 06/17] OMAP7XX: IRQ: Remove duplicate omap850 code
This patch is part of a series which unifies all duplicated code between
omap730 and omap850. All cpu checks are converted to cpu_is_omap7xx() and
CONFIG_ARCH_OMAP850 is added to all CONFIG_ARCH_OMAP730 checks.
This fixes a bug which prevents IRQs from being enabled on omap850 due to
a missing check in entry-macro.S, which was found by Cory Maccarrone.
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/mach-omap1/irq.c | 24 +--
arch/arm/plat-omap/include/mach/entry-macro.S |6 +-
arch/arm/plat-omap/include/mach/irqs.h| 81 -
3 files changed, 7 insertions(+), 104 deletions(-)
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index de03c84..c05999c 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -137,7 +137,7 @@ static void omap_irq_set_cfg(int irq, int fiq, int
priority, int trigger)
irq_bank_writel(val, bank, offset);
}
-#ifdef CONFIG_ARCH_OMAP730
+#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
static struct omap_irq_bank omap730_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE,.trigger_map = 0xb3f8e22f },
{ .base_reg = OMAP_IH2_BASE,.trigger_map = 0xfdb9c1f2 },
@@ -145,14 +145,6 @@ static struct omap_irq_bank omap730_irq_banks[] = {
};
#endif
-#ifdef CONFIG_ARCH_OMAP850
-static struct omap_irq_bank omap850_irq_banks[] = {
- { .base_reg = OMAP_IH1_BASE,.trigger_map = 0xb3f8e22f },
- { .base_reg = OMAP_IH2_BASE,.trigger_map = 0xfdb9c1f2 },
- { .base_reg = OMAP_IH2_BASE + 0x100,.trigger_map = 0x800040f3 },
-};
-#endif
-
#ifdef CONFIG_ARCH_OMAP15XX
static struct omap_irq_bank omap1510_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE,.trigger_map = 0xb3febfff },
@@ -186,18 +178,12 @@ void __init omap_init_irq(void)
{
int i, j;
-#ifdef CONFIG_ARCH_OMAP730
- if (cpu_is_omap730()) {
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+ if (cpu_is_omap7xx()) {
irq_banks = omap730_irq_banks;
irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
}
#endif
-#ifdef CONFIG_ARCH_OMAP850
- if (cpu_is_omap850()) {
- irq_banks = omap850_irq_banks;
- irq_bank_count = ARRAY_SIZE(omap850_irq_banks);
- }
-#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
irq_banks = omap1510_irq_banks;
@@ -247,10 +233,8 @@ void __init omap_init_irq(void)
/* Unmask level 2 handler */
- if (cpu_is_omap730())
+ if (cpu_is_omap7xx())
omap_unmask_irq(INT_730_IH2_IRQ);
- else if (cpu_is_omap850())
- omap_unmask_irq(INT_850_IH2_IRQ);
else if (cpu_is_omap15xx())
omap_unmask_irq(INT_1510_IH2_IRQ);
else if (cpu_is_omap16xx())
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S
b/arch/arm/plat-omap/include/mach/entry-macro.S
index a559299..bcf7158 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -17,10 +17,10 @@
#if defined(CONFIG_ARCH_OMAP1)
-#if defined(CONFIG_ARCH_OMAP730) && \
+#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \
(defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
-#error "FIXME: OMAP730 doesn't support multiple-OMAP"
-#elif defined(CONFIG_ARCH_OMAP730)
+#error "FIXME: OMAP7XX doesn't support multiple-OMAP"
+#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
#define INT_IH2_IRQINT_730_IH2_IRQ
#elif defined(CONFIG_ARCH_OMAP15XX)
#define INT_IH2_IRQINT_1510_IH2_IRQ
diff --git a/arch/arm/plat-omap/include/mach/irqs.h
b/arch/arm/plat-omap/include/mach/irqs.h
index 28a1650..7f338f0 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -108,29 +108,6 @@
#define INT_730_SPGIO_WR 29
/*
- * OMAP-850 specific IRQ numbers for interrupt handler 1
- */
-#define INT_850_IH2_FIQ0
-#define INT_850_IH2_IRQ1
-#define INT_850_USB_NON_ISO2
-#define INT_850_USB_ISO3
-#define INT_850_ICR4
-#define INT_850_EAC5
-#define INT_850_GPIO_BANK1 6
-#define INT_850_GPIO_BANK2 7
-#define INT_850_GPIO_BANK3 8
-#define INT_850_McBSP2TX 10
-#define INT_850_McBSP2RX 11
-#define INT_850_McBSP2RX_OVF 12
-#define INT_850_LCD_LINE 14
-#define INT_850_GSM_PROTECT15
-#define INT_850_TIMER3 16
-#define INT_850_GPIO_BANK5 17
-#define INT_850_GPIO_BANK6 18
-#define INT_850_SPGIO_WR 29
-
-
-/*
* IRQ numbers for interrupt handler 2
*
* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
@@ -263,64 +240,6 @@
#define INT_730_DMA_CH15 (62 + IH2_BASE)
#define INT_730_NAND (63 + IH2_BASE)
-/*
- * OMAP-850 specif
[PATCH 02/17] OMAP7XX: GPIO: Remove duplicate omap850 code
This patch is part of a series which unifies all duplicated code between
omap730 and omap850. All cpu checks are converted to cpu_is_omap7xx() and
CONFIG_ARCH_OMAP850 is added to all CONFIG_ARCH_OMAP730 checks.
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/plat-omap/gpio.c | 133 +
1 files changed, 14 insertions(+), 119 deletions(-)
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 71ebd7f..665ca05 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -83,22 +83,6 @@
#define OMAP730_GPIO_INT_MASK 0x10
#define OMAP730_GPIO_INT_STATUS0x14
-/*
- * OMAP850 specific GPIO registers
- */
-#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
-#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
-#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
-#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
-#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
-#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
-#define OMAP850_GPIO_DATA_INPUT0x00
-#define OMAP850_GPIO_DATA_OUTPUT 0x04
-#define OMAP850_GPIO_DIR_CONTROL 0x08
-#define OMAP850_GPIO_INT_CONTROL 0x0c
-#define OMAP850_GPIO_INT_MASK 0x10
-#define OMAP850_GPIO_INT_STATUS0x14
-
#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
/*
@@ -216,7 +200,6 @@ struct gpio_bank {
#define METHOD_GPIO_1510 1
#define METHOD_GPIO_1610 2
#define METHOD_GPIO_7303
-#define METHOD_GPIO_8504
#define METHOD_GPIO_24XX 5
#ifdef CONFIG_ARCH_OMAP16XX
@@ -236,7 +219,7 @@ static struct gpio_bank gpio_bank_1510[2] = {
};
#endif
-#ifdef CONFIG_ARCH_OMAP730
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
static struct gpio_bank gpio_bank_730[7] = {
{ OMAP1_MPUIO_VBASE,INT_730_MPUIO, IH_MPUIO_BASE,
METHOD_MPUIO },
{ OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE,
METHOD_GPIO_730 },
@@ -248,19 +231,6 @@ static struct gpio_bank gpio_bank_730[7] = {
};
#endif
-#ifdef CONFIG_ARCH_OMAP850
-static struct gpio_bank gpio_bank_850[7] = {
- { OMAP1_MPUIO_VBASE, INT_850_MPUIO, IH_MPUIO_BASE,
METHOD_MPUIO },
- { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE,
METHOD_GPIO_850 },
- { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE +
32, METHOD_GPIO_850 },
- { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE +
64, METHOD_GPIO_850 },
- { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE +
96, METHOD_GPIO_850 },
- { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128,
METHOD_GPIO_850 },
- { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160,
METHOD_GPIO_850 },
-};
-#endif
-
-
#ifdef CONFIG_ARCH_OMAP24XX
static struct gpio_bank gpio_bank_242x[4] = {
@@ -402,16 +372,11 @@ static void _set_gpio_direction(struct gpio_bank
*bank, int gpio, int is_input)
reg += OMAP1610_GPIO_DIRECTION;
break;
#endif
-#ifdef CONFIG_ARCH_OMAP730
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
case METHOD_GPIO_730:
reg += OMAP730_GPIO_DIR_CONTROL;
break;
#endif
-#ifdef CONFIG_ARCH_OMAP850
- case METHOD_GPIO_850:
- reg += OMAP850_GPIO_DIR_CONTROL;
- break;
-#endif
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_OE;
@@ -469,7 +434,7 @@ static void _set_gpio_dataout(struct gpio_bank
*bank, int gpio, int enable)
l = 1 << gpio;
break;
#endif
-#ifdef CONFIG_ARCH_OMAP730
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
case METHOD_GPIO_730:
reg += OMAP730_GPIO_DATA_OUTPUT;
l = __raw_readl(reg);
@@ -479,16 +444,6 @@ static void _set_gpio_dataout(struct gpio_bank
*bank, int gpio, int enable)
l &= ~(1 << gpio);
break;
#endif
-#ifdef CONFIG_ARCH_OMAP850
- case METHOD_GPIO_850:
- reg += OMAP850_GPIO_DATA_OUTPUT;
- l = __raw_readl(reg);
- if (enable)
- l |= 1 << gpio;
- else
- l &= ~(1 << gpio);
- break;
-#endif
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
if (enable)
@@ -537,16 +492,11 @@ static int _get_gpio_datain(struct gpio_bank
*bank, int gpio)
reg += OMAP1610_GPIO_DATAIN;
break;
#endif
-#ifdef CONFIG_ARCH_OMAP730
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
case METHOD_GPIO_730:
[PATCH 01/17] OMAP7XX: Serial: Remove duplicate omap850 code
This patch is part of a series which unifies all duplicated code between
omap730 and omap850. All cpu checks are converted to cpu_is_omap7xx() and
CONFIG_ARCH_OMAP850 is added to all CONFIG_ARCH_OMAP730 checks.
Signed-off-by: Alistair Buxton
Reviewed-by: Zebediah C. McClure
---
arch/arm/mach-omap1/serial.c |9 +
1 files changed, 1 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index d496e50..49381e2 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -110,20 +110,13 @@ void __init omap_serial_init(void)
{
int i;
- if (cpu_is_omap730()) {
+ if (cpu_is_omap7xx()) {
serial_platform_data[0].regshift = 0;
serial_platform_data[1].regshift = 0;
serial_platform_data[0].irq = INT_730_UART_MODEM_1;
serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
}
- if (cpu_is_omap850()) {
- serial_platform_data[0].regshift = 0;
- serial_platform_data[1].regshift = 0;
- serial_platform_data[0].irq = INT_850_UART_MODEM_1;
- serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2;
- }
-
if (cpu_is_omap15xx()) {
serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
--
1.6.5
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[PATCH 00/17] Massive OMAP730/OMAP850 cleanup
Reposting the full series for review. Assuming this is all OK would it
be a good idea to merge the config variables into a single
CONFIG_ARCH_OMAP7XX? There doesn't seem to be any reason to have both.
Original description follows.
Hello from the Linwizard project,
We have been working on supporting omap850 smartphones from HTC such
as Wizard, Herald etc. We have found that omap730 and omap850 are
almost exactly the same. As far as what is supported in linux-omap so
far, they are identical. Currently there are seperate code paths for
730 and 850, and this is causing us a lot of problems when one is
changed and the other isn't. I also noticed that OMAP F-Sample board
uses ARCH_OMAP730 even though it has a OMAP850 SoC.
In order to try to clean this up I have produced a patch series which
removes all cpu_is_omap730/850 and replaces them with unified
cpu_is_omap7xx() blocks, and similarly merges CONFIG checks. Here is a
random example:
-#ifdef CONFIG_ARCH_OMAP730
- if (cpu_is_omap730()) {
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+ if (cpu_is_omap7xx()) {
irq_banks = omap730_irq_banks;
irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
}
#endif
-#ifdef CONFIG_ARCH_OMAP850
- if (cpu_is_omap850()) {
- irq_banks = omap850_irq_banks;
- irq_bank_count = ARRAY_SIZE(omap850_irq_banks);
- }
-#endif
Drilling down through the variables shows they are always equivalent
for 730 and 850, except where there is a bug.
This makes several bugs go away for us on omap850, including the
MPUIO_VBASE bug, and the lack of working IRQs - since these bugs arn't
in the 730 paths. It would hopefully prevent similar bugs from showing
up in the future too.
Alistair Buxton (16):
OMAP7XX: Serial: Remove duplicate omap850 code
OMAP7XX: GPIO: Remove duplicate omap850 code
OMAP7XX: IO: Remove duplicate omap850 code
OMAP7XX: Mux: Remove duplicate omap850 code
OMAP7XX: USB: Remove duplicate omap850 code
OMAP7XX: IRQ: Remove duplicate omap850 code
OMAP7XX: PM: Add omap850 support
OMAP7XX: Clocks: Add omap850 support
OMAP7XX: McBSP: Add omap850 support
OMAP7XX: Create omap7xx.h
OMAP7XX: Update core omap1 files to use omap7xx.h
OMAP7XX: Replace omap730 references in irqs.h and all users
OMAP7XX: Rename all the rest of the omap730 references in omap1 core
OMAP7XX: omap_uwire.c: Convert to omap7xx.h
OMAP850: PM: Add an ARCH_OMAP850 check
OMAP850: Fix zImage booting
Angelo Arrifano (1):
OMAP7XX: Clocks: Add ck_ref and armxor
arch/arm/mach-omap1/board-fsample.c | 18 +-
arch/arm/mach-omap1/board-perseus2.c | 18 +-
arch/arm/mach-omap1/clock.c | 24 ++--
arch/arm/mach-omap1/io.c | 45 ++
arch/arm/mach-omap1/irq.c | 32 +---
arch/arm/mach-omap1/mcbsp.c | 32 ++--
arch/arm/mach-omap1/mux.c | 70 +++-
arch/arm/mach-omap1/pm.c | 100 ++--
arch/arm/mach-omap1/pm.h | 53 +++---
arch/arm/mach-omap1/serial.c | 13 +-
arch/arm/mach-omap1/sleep.S | 22 ++--
arch/arm/plat-omap/devices.c | 22 ++--
arch/arm/plat-omap/gpio.c | 227 +++--
arch/arm/plat-omap/include/mach/entry-macro.S |8 +-
arch/arm/plat-omap/include/mach/hardware.h|2 +-
arch/arm/plat-omap/include/mach/irqs.h| 229 -
arch/arm/plat-omap/include/mach/mcbsp.h |6 +-
arch/arm/plat-omap/include/mach/mux.h | 100 +++
arch/arm/plat-omap/include/mach/omap7xx.h | 104 +++
arch/arm/plat-omap/include/mach/uncompress.h |3 +-
arch/arm/plat-omap/io.c | 14 +-
arch/arm/plat-omap/usb.c | 10 +-
drivers/spi/omap_uwire.c |8 +-
23 files changed, 480 insertions(+), 680 deletions(-)
create mode 100644 arch/arm/plat-omap/include/mach/omap7xx.h
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Re: stable kernel version
* Janosch Machowinski [091014 10:40]: > Tony Lindgren schrieb: >> * Janosch Machowinski [091014 01:48]: >> >>> Hi, >>> I'm looking for an stable omap kernel, >>> for an gumstix board. I tried the 2.6.30 >>> and 2.6.31 git heads, but they both >>> resulted in an unbootable system. >>> Any advices, on which version to take ? >>> >> >> Starting with 2.6.31, the stable omap kernel latest released >> kernel from Linus. So 2.6.31 in this case. >> >> Of course you may still need to patch in some things you need, >> like PM, EHCI and dspbridge. >> >> What do you get when booting? Overo boots just fine for me. > > Hi Tony, > > the 2.6.30 head booted fine until the point where it > waited for the SD-Card to get ready. There it just hung > forever. Hmm, 2.6.30 may not have all the core stuff in it yet. > the 2.6.31 head crashed instantly after the uncompression > of the kernel image. There are few patches still pending to get to mainline via other mailing lists, you can see them in omap-testing branch. > I will try out the 2.6.31 mainline kernel tommorw. OK, also I just pushed updated omap-debug branch that I forgot to rebase on top of current linux-omap master branch (Thanks Paul for letting me know!). Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: Discussion: OMAP: PM: opp table handling
> From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- > ow...@vger.kernel.org] On Behalf Of Menon, Nishanth > Sent: Wednesday, October 14, 2009 11:12 AM > > I think we should as well change the naming and use the less confusing > > naming we are using on OMAP3630/4430. > > OPPs are now named using the performance delta from the nominal frequency. > > OPP25, OPP50, OPP80, OPP100, OPP120... > NAK for two reasons: I wouldn't NAK too quickly. What does the load predictor use? Does it want to know about a million combinations? Not really. It is interesting to see if I'm on a 3GHz machine vs. a 1GHz one. But the predictor shouldn't care. What the predictor may care about is percentages and possible spacing between performance points. A well written user space program hopefully doesn't care in general either. I can recall the days when old apple games were ported and they were unusable for a bit because of all kinds of hardcoded timing loops. They were certainly not portable. Some drivers may practically care about frequency if they need to calculate some kind of QOS parameter but that is not the MPU. I do agree the hardware definition does at times change based on characterization data. We know that not every new OPP is even generally useful if its spacing is bad. A typical system might skip over some OPPs in actual use if spacing is not good. > a) h/w changes language of OPP definitions every other silicons -> OPP100 is > not more informative than OPP1 or OPPX for that matter - with proper comments, > even something like > /* OPP25 - 25% of nominal performance */ > #define VDD1_OPP_RELLLY_SLOW_OPP 1 > Makes sense. > b) if you look at discussion - we really DON'T want to use OPP definitions > anymore - we would like folks to use frequency for precisely that reason - it > is frequency that matters in the system. > c) the field for OPP idx is probably redundant once we have proper APIs in > place. At the lower level I do practically like some use of validated sets. Validation of every possible combination doesn't happen. There are 10 ways to program your DPLL for a similar output range. We should stick with what has been validated not create very big generalized functions. This functions get complex and many times miss out on obscure DPLL errata. At the high level use of percentage might be ideal then comes frequency. These values then are translated into discrete units which can be well tested. I'm not say ack or nak. Just that its not such a black & white choice. Regards, Richard W. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: Memory performance / Cache problem
> From: Siarhei Siamashka [mailto:siarhei.siamas...@nokia.com] > Sent: Wednesday, October 14, 2009 12:37 PM > To: ext e...@gmx.de > What you see is just a (fake) performance boost because you have a single > physical page shared between all the virtual pages in the source buffer. So > you get no cache misses on read operations and everything seems fast. > > This is unlikely to happen on real use, and it does not reflect real memory > performance. So the benchmark is inadequate. Yep, benchmark is only useful so far. If you control factors it can be useful but it's far from 1-1, to extrapolate it to something meaningful at system level. You can actually get even 'better' numbers if you take the DDR part geometry into mind and SDRC (sdram-controller) scheduler. Our silicon validation people report out of this world numbers for very specific test cases. These are component tests for the memory controller to make sure it behaves. If you alternate between open banks you can do really fast operations. A good amount of that test is not practical to count on at HLOS level. It can help explain some anomalies and help in designing a fair test. Regards, Richard W. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: stable kernel version
Tony Lindgren schrieb: * Janosch Machowinski [091014 01:48]: Hi, I'm looking for an stable omap kernel, for an gumstix board. I tried the 2.6.30 and 2.6.31 git heads, but they both resulted in an unbootable system. Any advices, on which version to take ? Starting with 2.6.31, the stable omap kernel latest released kernel from Linus. So 2.6.31 in this case. Of course you may still need to patch in some things you need, like PM, EHCI and dspbridge. What do you get when booting? Overo boots just fine for me. Hi Tony, the 2.6.30 head booted fine until the point where it waited for the SD-Card to get ready. There it just hung forever. the 2.6.31 head crashed instantly after the uncompression of the kernel image. I will try out the 2.6.31 mainline kernel tommorw. Regards, Janosch -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: RE: RE: RE: Memory performance / Cache problem
> From: e...@gmx.de [mailto:e...@gmx.de] > Sent: Wednesday, October 14, 2009 12:23 PM > To: Woodruff, Richard; Premi, Sanjeev; linux-omap@vger.kernel.org > Subject: Re: RE: RE: RE: Memory performance / Cache problem > > Yes aligned buffers can make a difference. But probably more so for small > > copies. Of course you must touch the memory or mprotect() it so its > > faulted in, but indications are you have done this. > > Mh, alignment (to an address) is done with malloc already. Probably you mean > something different. I don't understand the difference. For me is > malloc+memset=calloc. > I'll send you the benchmark code, if you like. Ok, if it compiles I could try on sdp3430 or sdp3630. Alignment to a cache line is always best. This is 64 bytes in A8. Better yet, being 4K aligned is a good thing to reduce MMU effects. > In both kernels I used the same rootfs (via NFS). Indeed I used CS2009q1 and > its libs, but we are talking about factor 2..6. This must be something > serious. 2009 pay version has optimized thrumb2 and arm mode libraries you download separately. I don't recall if free/lite version integrated this. > What is your feeling? Does the 22 something strange or are the newer kernels > slower that they have to be. There are a lot of differences between 22 kernel and current ones. First things I'd check would be around MMU settings, special ARM cp15 memory control regs, then omap memory and clock settings. Also some bad device could undercut you. Always good to cat /proc/interrupts and make sure something isn't spewing. > Would be interesting to see results on other Omap3 boards with both old an new > kernels. I've not noticed anything on sdp on somewhat recent kernels. Regards, Richard W. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Memory performance / Cache problem
On Wednesday 14 October 2009 17:48:39 ext e...@gmx.de wrote: > Mem clock is both times 166MHz. I don't know whether are differences in > cycle access and timing, but memclock is fine. > > Following Siarhei hints of initialize the buffers (around 1.2 MByte each) > I get different results in 22kernel for use of > malloc alone > memcpy = 473.764, loop4 = 448.430, loop1 = 102.770, rand =29.641 > calloc alone > memcpy = 405.947, loop4 = 361.550, loop1 =95.441, rand =21.853 > malloc+memset: > memcpy = 239.294, loop4 = 188.617, loop1 =80.871, rand = 4.726 > > In 31kernel all 3 measures are about the same (unfortunatly low) level of > malloc+memset in 22. > > First of all: What performance can be expected? > Does 22 make failures if it is so much faster? > Can the later kernels get a boost in memory handling? What you see is just a (fake) performance boost because you have a single physical page shared between all the virtual pages in the source buffer. So you get no cache misses on read operations and everything seems fast. This is unlikely to happen on real use, and it does not reflect real memory performance. So the benchmark is inadequate. You can get some basic information here: http://en.wikipedia.org/wiki/Copy-on-write Regarding the difference in behavior between .22 and recent kernels. It may be some regression in copy-on-write implementation, or just some change done on purpose. That is assuming that the userspace stuff was identical in both tests. -- Best regards, Siarhei Siamashka -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: stable kernel version
* Janosch Machowinski [091014 01:48]: > Hi, > I'm looking for an stable omap kernel, > for an gumstix board. I tried the 2.6.30 > and 2.6.31 git heads, but they both > resulted in an unbootable system. > Any advices, on which version to take ? Starting with 2.6.31, the stable omap kernel latest released kernel from Linus. So 2.6.31 in this case. Of course you may still need to patch in some things you need, like PM, EHCI and dspbridge. What do you get when booting? Overo boots just fine for me. At least CONFIG_MUSB had issues, you can see the details by checking out the omap-debug branch and enabling CONFIG_DEBUG_LL. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: RE: RE: RE: Memory performance / Cache problem
> > Mem clock is both times 166MHz. I don't know whether are differences in > cycle > > access and timing, but memclock is fine. > > How did you physically verify this? Oszi show 166MHz, also the kernel message about freq are in both kernels the same. > > Following Siarhei hints of initialize the buffers (around 1.2 MByte > each) > > I get different results in 22kernel for use of > > malloc alone > > memcpy = 473.764, loop4 = 448.430, loop1 = 102.770, rand = > 29.641 > > calloc alone > > memcpy = 405.947, loop4 = 361.550, loop1 =95.441, rand = > 21.853 > > malloc+memset: > > memcpy = 239.294, loop4 = 188.617, loop1 =80.871, rand = > 4.726 > > > > In 31kernel all 3 measures are about the same (unfortunatly low) level > of > > malloc+memset in 22. > > Yes aligned buffers can make a difference. But probably more so for small > copies. Of course you must touch the memory or mprotect() it so its > faulted in, but indications are you have done this. Mh, alignment (to an address) is done with malloc already. Probably you mean something different. I don't understand the difference. For me is malloc+memset=calloc. I'll send you the benchmark code, if you like. > > I used a standard memcpy (think this is glib and hence not neonbased)? > > To be neonbased I guess it has to be recompiled? > > The version of glibc in use can make a difference. CodeSourcery in 2009 > release added PLD's to mem operations. This can give a good benefit. It > might be you have optimized library in one case and a non-optimized in > another. In both kernels I used the same rootfs (via NFS). Indeed I used CS2009q1 and its libs, but we are talking about factor 2..6. This must be something serious. What is your feeling? Does the 22 something strange or are the newer kernels slower that they have to be. Would be interesting to see results on other Omap3 boards with both old an new kernels. Best regards Steffen -- GRATIS für alle GMX-Mitglieder: Die maxdome Movie-FLAT! Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: Discussion: OMAP: PM: opp table handling
>-Original Message- >From: Menon, Nishanth > >> -Original Message- >> From: Cousson, Benoit >> Sent: Wednesday, October 14, 2009 11:06 AM >> To: Pandita, Vikram; linux-omap@vger.kernel.org >> >> >From: Pandita, Vikram >> > >> > >> >Proposals for OPP table handling for OMAP34xx/35xx/36xx/44xx >> > >> >Thanks to all the community members for taking time for this discussion. >> >This will aid upsteaming of 35xx/36xx/44xx in coming future. >> > >> >Attendees: Kevin Hilman, Paul, Nishant M, Santosh, Madhu, Benoit, >> Rajendra, >> >Benoit, Vikram >> > >> >Problem Statement: >> >OMAP34xx has certain opp requirements (3420/3430/3440) >> >OMAP35xx reuses the opp's from 34xx >> >OMAP36xx has a totally new set of opps >> >OMAP44xx has a totally new set of opps >> > >> >Solution: >> >Align on a common approach to take for the Opp table definitions. >> > >> >Define Separate Tables for each family as follows: >> >Step 1: Go with this approach: >> >3420(65nm) : new arrays [defer for now] >> >3430/35xx(65nm) : new arrays ** >> >3440(65nm) : new arrays [defer for now] >> >3630(45nm) : new arrays >> >Omap4(45nm) : new arrays >> > >> >* new arrays = (mpu, dsp, l3) >> >** Check this valid flag. Kevin can take this base on comments >> >http://marc.info/?l=linux-omap&m=125512448216071&w=2 >> >between 3430/35xx, opp's can be managed with a flag and same >> >table re-used >> >35xx has requirement for 720Mhz opp >> > >> >Step 2: >> >Kevin suggestion: >> >Define accessor APIs get the OPPs >> >Check Users of accessor API >> >DVFS >> >constraints >> >sysfs debug >> >Define accessor api's eg: >> >index = get_opp(VDD1_OPP1); >> >num = get_max_opp(VDD1); >> >set_opp(index); >> >> I think we should as well change the naming and use the less confusing >> naming we are using on OMAP3630/4430. >> OPPs are now named using the performance delta from the nominal frequency. >> OPP25, OPP50, OPP80, OPP100, OPP120... >NAK for two reasons: >a) h/w changes language of OPP definitions every other silicons -> OPP100 >is not more informative than OPP1 or OPPX for that matter - with proper >comments, even something like >/* OPP25 - 25% of nominal performance */ >#define VDD1_OPP_RELLLY_SLOW_OPP 1 >Makes sense. Well, this is your point of view, but having a define named OPP100 is a little bit more informative, for my point of view, than OPP3 especially when the same OPP was named OPP1 in previous ES. Nevermind, it was just a quick and non intrusive fix to do but the next point will make it useless. >b) if you look at discussion - we really DON'T want to use OPP definitions >anymore - we would like folks to use frequency for precisely that reason - >it is frequency that matters in the system. I agree it is even better. FYI, and if you look at the discussion, that direction is not obvious at all... There is even a get_opp(VDD1_OPP1) in the email... What part of the email is explaining that? Maybe I missed it. >c) the field for OPP idx is probably redundant once we have proper APIs in >place. Agree. Regards, Benoit >> >> >Step 3: >> >Paul suggestion: >> >VSEL values in opp table should be in terms of voltage >> >Non TWL IC's need this >> > >> >Step4: >> >Paul suggestion: >> >VDD1 VDD2 dependencies for different chips >> >Inter-connect load predictor is absent on omap3 and hence VDD1-vdd2 >> >dependency >> >OMAP4 >> >interconnect loading can be measured from registers >> >Multi-cores dependency >> > >> >Step 5: >> >Paul suggestion: >> >Board files adding OPPs, Modifying OPPs >> >Eg: Pendora passing its own opp >> >> > > >Regards, >Nishanth Menon -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [PATCH 5/8] board-rx51-peripherals: split vaux3 and vmmc2 supplies
* Mark Brown [091012 02:18]:
> On Mon, Oct 12, 2009 at 11:08:58AM +0300, Eduardo Valentin wrote:
>
> > I'm afraid using dev_name is not that easy. The mmc driver generates device
> > name at runtime. That's why this board file setups .dev at runtime as well.
>
> > rx51_twlgpio_setup -> twl4030_mmc_init -> omap2_init_mmc
>
> > So, changing this supply to something static using .dev_name it is not
> > possible with current code. That would need refactoring the whole mmc and
> > hsmmc setup. And the device naming procedure is dependent on cpu as well.
> > Check arch/arm/mach-omap2/device.c:omap2_init_mmc.
>
> Oh, dear - that sounds broken for hardware that's fixed on the board.
> That said, the code there looks like it's supposed to come out with the
> same answer each time it's run? How does this work with the clock API?
The clocks are matched using clkdev. Basically the driver just requests
functional clock (fck) and interface clock (ick):
$ grep mmci arch/arm/*omap*/clock*.c
arch/arm/mach-omap1/clock.c:CLK("mmci-omap.0", "fck", &mmc1_ck,
CK_16XX | CK_1510 | CK_310),
arch/arm/mach-omap1/clock.c:CLK("mmci-omap.0", "ick", &armper_ck.clk,
CK_16XX | CK_1510 | CK_310),
arch/arm/mach-omap1/clock.c:CLK("mmci-omap.1", "fck", &mmc2_ck,
CK_16XX),
arch/arm/mach-omap1/clock.c:CLK("mmci-omap.1", "ick", &armper_ck.clk,
CK_16XX),
arch/arm/mach-omap2/clock24xx.c:CLK("mmci-omap.0", "ick",
&mmc_ick, CK_242X),
arch/arm/mach-omap2/clock24xx.c:CLK("mmci-omap.0", "fck",
&mmc_fck, CK_242X),
arch/arm/mach-omap2/clock24xx.c:CLK("mmci-omap-hs.0", "ick",
&mmchs1_ick,CK_243X),
arch/arm/mach-omap2/clock24xx.c:CLK("mmci-omap-hs.0", "fck",
&mmchs1_fck,CK_243X),
arch/arm/mach-omap2/clock24xx.c:CLK("mmci-omap-hs.1", "ick",
&mmchs2_ick,CK_243X),
arch/arm/mach-omap2/clock24xx.c:CLK("mmci-omap-hs.1", "fck",
&mmchs2_fck,CK_243X),
arch/arm/mach-omap2/clock24xx.c:CLK("mmci-omap-hs.0", "mmchsdb_fck",
&mmchsdb1_fck, CK_243X),
arch/arm/mach-omap2/clock24xx.c:CLK("mmci-omap-hs.1", "mmchsdb_fck",
&mmchsdb2_fck, CK_243X),
arch/arm/mach-omap2/clock34xx.c:CLK("mmci-omap-hs.2", "fck",
&mmchs3_fck,CK_3430ES2),
arch/arm/mach-omap2/clock34xx.c:CLK("mmci-omap-hs.1", "fck",
&mmchs2_fck,CK_343X),
arch/arm/mach-omap2/clock34xx.c:CLK("mmci-omap-hs.0", "fck",
&mmchs1_fck,CK_343X),
arch/arm/mach-omap2/clock34xx.c:CLK("mmci-omap-hs.2", "ick",
&mmchs3_ick,CK_3430ES2),
arch/arm/mach-omap2/clock34xx.c:CLK("mmci-omap-hs.1", "ick",
&mmchs2_ick,CK_343X),
arch/arm/mach-omap2/clock34xx.c:CLK("mmci-omap-hs.0", "ick",
&mmchs1_ick,CK_343X),
Regards,
Tony
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Re: [PATCH] ARM: OMAP: SDMA: Fix omap_stop_dma() API for channel linking
* Santosh Shilimkar [091013 23:14]:
> OMAP sDMA driver API omap_stop_dma() doesn't really stop the dma when used
> in linking scenario. This patch fixes the same.
To me it looks like this will break things for omap1 as the DMA channel
interrupt is not disabled first. I guess the fix is to move the
"Disable all interrupts on the channel" part above clearing the
link mappings.
This fix should be tested in linux-omap before we send this to mainline.
Tony
> Signed-off-by: Santosh Shilimkar
> Signed-off-by: Venkatraman S
> CC: Hari n
> CC: Jarkko Nikula
> ---
> arch/arm/plat-omap/dma.c |9 +
> 1 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
> index fd3154a..633c123 100644
> --- a/arch/arm/plat-omap/dma.c
> +++ b/arch/arm/plat-omap/dma.c
> @@ -975,6 +975,11 @@ void omap_stop_dma(int lch)
> {
> u32 l;
>
> + /* Disable the DMA channel */
> + l = dma_read(CCR(lch));
> + l &= ~OMAP_DMA_CCR_EN;
> + dma_write(l, CCR(lch));
> +
> if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
> int next_lch, cur_lch = lch;
> char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
> @@ -1000,10 +1005,6 @@ void omap_stop_dma(int lch)
> if (cpu_class_is_omap1())
> dma_write(0, CICR(lch));
>
> - l = dma_read(CCR(lch));
> - l &= ~OMAP_DMA_CCR_EN;
> - dma_write(l, CCR(lch));
> -
> dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
> }
> EXPORT_SYMBOL(omap_stop_dma);
> --
> 1.5.4.7
>
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Re: [PATCH 1/6] omap: Fix Unlikely(x) < y
* Tony Lindgren [091013 17:21]:
> From: Roel Kluin
>
> The closing parenthesis was not on the right location.
Looks like this one is in the -mm now, so dropping from
mine.
Tony
> Signed-off-by: Roel Kluin
> Signed-off-by: Tony Lindgren
> ---
> arch/arm/plat-omap/gpio.c |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
> index 71ebd7f..7c345b7 100644
> --- a/arch/arm/plat-omap/gpio.c
> +++ b/arch/arm/plat-omap/gpio.c
> @@ -373,7 +373,7 @@ static inline int gpio_valid(int gpio)
>
> static int check_gpio(int gpio)
> {
> - if (unlikely(gpio_valid(gpio)) < 0) {
> + if (unlikely(gpio_valid(gpio) < 0)) {
> printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
> dump_stack();
> return -1;
>
> --
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RE: Discussion: OMAP: PM: opp table handling
> -Original Message- > From: Cousson, Benoit > Sent: Wednesday, October 14, 2009 11:06 AM > To: Pandita, Vikram; linux-omap@vger.kernel.org > > >From: Pandita, Vikram > > > > > >Proposals for OPP table handling for OMAP34xx/35xx/36xx/44xx > > > >Thanks to all the community members for taking time for this discussion. > >This will aid upsteaming of 35xx/36xx/44xx in coming future. > > > >Attendees: Kevin Hilman, Paul, Nishant M, Santosh, Madhu, Benoit, > Rajendra, > >Benoit, Vikram > > > >Problem Statement: > > OMAP34xx has certain opp requirements (3420/3430/3440) > > OMAP35xx reuses the opp's from 34xx > > OMAP36xx has a totally new set of opps > > OMAP44xx has a totally new set of opps > > > >Solution: > > Align on a common approach to take for the Opp table definitions. > > > >Define Separate Tables for each family as follows: > >Step 1: Go with this approach: > > 3420(65nm) : new arrays [defer for now] > > 3430/35xx(65nm) : new arrays ** > > 3440(65nm) : new arrays [defer for now] > > 3630(45nm) : new arrays > > Omap4(45nm) : new arrays > > > > * new arrays = (mpu, dsp, l3) > > ** Check this valid flag. Kevin can take this base on comments > > http://marc.info/?l=linux-omap&m=125512448216071&w=2 > > between 3430/35xx, opp's can be managed with a flag and same > >table re-used > > 35xx has requirement for 720Mhz opp > > > >Step 2: > >Kevin suggestion: > >Define accessor APIs get the OPPs > >Check Users of accessor API > > DVFS > > constraints > > sysfs debug > > Define accessor api's eg: > > index = get_opp(VDD1_OPP1); > > num = get_max_opp(VDD1); > > set_opp(index); > > I think we should as well change the naming and use the less confusing > naming we are using on OMAP3630/4430. > OPPs are now named using the performance delta from the nominal frequency. > OPP25, OPP50, OPP80, OPP100, OPP120... NAK for two reasons: a) h/w changes language of OPP definitions every other silicons -> OPP100 is not more informative than OPP1 or OPPX for that matter - with proper comments, even something like /* OPP25 - 25% of nominal performance */ #define VDD1_OPP_RELLLY_SLOW_OPP 1 Makes sense. b) if you look at discussion - we really DON'T want to use OPP definitions anymore - we would like folks to use frequency for precisely that reason - it is frequency that matters in the system. c) the field for OPP idx is probably redundant once we have proper APIs in place. > > Regards, > Benoit > > >Step 3: > > Paul suggestion: > > VSEL values in opp table should be in terms of voltage > > Non TWL IC's need this > > > >Step4: > > Paul suggestion: > > VDD1 VDD2 dependencies for different chips > > Inter-connect load predictor is absent on omap3 and hence VDD1-vdd2 > >dependency > > OMAP4 > > interconnect loading can be measured from registers > > Multi-cores dependency > > > >Step 5: > > Paul suggestion: > > Board files adding OPPs, Modifying OPPs > > Eg: Pendora passing its own opp > > Regards, Nishanth Menon -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: Discussion: OMAP: PM: opp table handling
>From: Pandita, Vikram > > >Proposals for OPP table handling for OMAP34xx/35xx/36xx/44xx > >Thanks to all the community members for taking time for this discussion. >This will aid upsteaming of 35xx/36xx/44xx in coming future. > >Attendees: Kevin Hilman, Paul, Nishant M, Santosh, Madhu, Benoit, Rajendra, >Benoit, Vikram > >Problem Statement: > OMAP34xx has certain opp requirements (3420/3430/3440) > OMAP35xx reuses the opp's from 34xx > OMAP36xx has a totally new set of opps > OMAP44xx has a totally new set of opps > >Solution: > Align on a common approach to take for the Opp table definitions. > >Define Separate Tables for each family as follows: >Step 1: Go with this approach: > 3420(65nm) : new arrays [defer for now] > 3430/35xx(65nm) : new arrays ** > 3440(65nm) : new arrays [defer for now] > 3630(45nm) : new arrays > Omap4(45nm) : new arrays > > * new arrays = (mpu, dsp, l3) > ** Check this valid flag. Kevin can take this base on comments > http://marc.info/?l=linux-omap&m=125512448216071&w=2 > between 3430/35xx, opp's can be managed with a flag and same >table re-used > 35xx has requirement for 720Mhz opp > >Step 2: >Kevin suggestion: >Define accessor APIs get the OPPs >Check Users of accessor API > DVFS > constraints > sysfs debug > Define accessor api's eg: > index = get_opp(VDD1_OPP1); > num = get_max_opp(VDD1); > set_opp(index); I think we should as well change the naming and use the less confusing naming we are using on OMAP3630/4430. OPPs are now named using the performance delta from the nominal frequency. OPP25, OPP50, OPP80, OPP100, OPP120... Regards, Benoit >Step 3: > Paul suggestion: > VSEL values in opp table should be in terms of voltage > Non TWL IC's need this > >Step4: > Paul suggestion: > VDD1 VDD2 dependencies for different chips > Inter-connect load predictor is absent on omap3 and hence VDD1-vdd2 >dependency > OMAP4 > interconnect loading can be measured from registers > Multi-cores dependency > >Step 5: > Paul suggestion: > Board files adding OPPs, Modifying OPPs > Eg: Pendora passing its own opp -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: RE: RE: Memory performance / Cache problem
> From: e...@gmx.de [mailto:e...@gmx.de] > Sent: Wednesday, October 14, 2009 9:49 AM > To: Woodruff, Richard; linux-omap@vger.kernel.org; Premi, Sanjeev > Subject: Re: RE: RE: Memory performance / Cache problem > > Mem clock is both times 166MHz. I don't know whether are differences in cycle > access and timing, but memclock is fine. How did you physically verify this? > Following Siarhei hints of initialize the buffers (around 1.2 MByte each) > I get different results in 22kernel for use of > malloc alone > memcpy = 473.764, loop4 = 448.430, loop1 = 102.770, rand =29.641 > calloc alone > memcpy = 405.947, loop4 = 361.550, loop1 =95.441, rand =21.853 > malloc+memset: > memcpy = 239.294, loop4 = 188.617, loop1 =80.871, rand = 4.726 > > In 31kernel all 3 measures are about the same (unfortunatly low) level of > malloc+memset in 22. Yes aligned buffers can make a difference. But probably more so for small copies. Of course you must touch the memory or mprotect() it so its faulted in, but indications are you have done this. > I used a standard memcpy (think this is glib and hence not neonbased)? > To be neonbased I guess it has to be recompiled? The version of glibc in use can make a difference. CodeSourcery in 2009 release added PLD's to mem operations. This can give a good benefit. It might be you have optimized library in one case and a non-optimized in another. Regards, Richard W. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: RE: RE: Memory performance / Cache problem
Mem clock is both times 166MHz. I don't know whether are differences in cycle access and timing, but memclock is fine. Following Siarhei hints of initialize the buffers (around 1.2 MByte each) I get different results in 22kernel for use of malloc alone memcpy = 473.764, loop4 = 448.430, loop1 = 102.770, rand =29.641 calloc alone memcpy = 405.947, loop4 = 361.550, loop1 =95.441, rand =21.853 malloc+memset: memcpy = 239.294, loop4 = 188.617, loop1 =80.871, rand = 4.726 In 31kernel all 3 measures are about the same (unfortunatly low) level of malloc+memset in 22. First of all: What performance can be expected? Does 22 make failures if it is so much faster? Can the later kernels get a boost in memory handling? I used a standard memcpy (think this is glib and hence not neonbased)? To be neonbased I guess it has to be recompiled? How can I find out that neon and cache settings are ok? Using a Omap3530 on EVM board Unfortunatly I don't have a Lauterbach, just a Spectrum Digital which works only until Linux kernel is booting. Best regards Steffen Original-Nachricht > Datum: Wed, 14 Oct 2009 08:59:05 -0500 > Von: "Woodruff, Richard" > An: "e...@gmx.de" , "Premi, Sanjeev" , > "linux-omap@vger.kernel.org" > Betreff: RE: RE: Memory performance / Cache problem > > There is no newer u-boot from TI available. There is a SDK 02.01.03.11 > > but it contains the same uboot 2008.10 with the only addition of the > second > > generation of EVM boards with another network chip. > > > > So I checked the uboot from git, but this doesn't support Microns NAND > Flash > > anymore. It is just working with ONENAND. > > > > I found a patch which shows the L2 Cache status while kernel boot and > > implemented it : L2 Cache seems to be already enabled - so this is not > the > > reason. > > > > So any other ideas? > > Are you confident your memory bus isn't running at 1/2 speed? > > I recall there was a couple day window during wtbu kernel upgrades where > memory bus speed with pm was running 1/2 speed after kernel started up. > This was somewhat a side effect of constraints frame work and a regression in > forward porting. It seems unlikely psp kernel would have shipped with this > bug but its something to check. This would match your results. > > If your memcpy() is neon based then I might be worried about > l1neon-caching effects along with factors of (exlcusive-l1-l2-read-allocate > cache + pld > not being effective on l1 only l2). > > Which memcpy test are you using? Something in lmbench or just one you > wrote. Generally results are a little hard to interpret with exclusive cache > behavior in 3430's r1px core. 3630's r3p2 core gives more traditional > results as exclusive feature has been removed by arm. > > If you have the ability using Lauterbach + per file will allow internal > space dump which will show all critical parameters during test. It's a 1 > minute check for someone who has done it before to ensure the few parameters > needed are in line. I can send an example off line of how to do capture. I > won't have time to expand on all relevant parameters. > > Regards, > Richard W. -- Neu: GMX DSL bis 50.000 kBit/s und 200,- Euro Startguthaben! http://portal.gmx.net/de/go/dsl02 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] twl4030: Initial support for twl5031
Hi,
>From: ext G, Manjunath Kondaiah [mailto:manj...@ti.com]
>Sent: 14 October, 2009 13:51
>> -Original Message-
>> From: linux-omap-ow...@vger.kernel.org
>> [mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of Ilkka Koskinen
>> Sent: Thursday, September 24, 2009 9:24 PM
>> To: linux-ker...@vger.kernel.org; sa...@linux.intel.com
>> Cc: linux-omap@vger.kernel.org; felipe.ba...@nokia.com;
>> dbrown...@users.sourceforge.net; ilkka.koski...@nokia.com
>> Subject: [PATCH] twl4030: Initial support for twl5031
>>
>> TWL5031 introduces two new interrupts in PIH. Moreover, BCI
>> has changed remarkably and, thus, it's disabled when TWL5031
>> is in use.
>>
>> Signed-off-by: Ilkka Koskinen
>> ---
>> drivers/mfd/twl4030-core.c | 15 +-
>> drivers/mfd/twl4030-irq.c | 126
>> --
>> include/linux/i2c/twl4030.h | 47 ++--
>> 3 files changed, 175 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/mfd/twl4030-core.c b/drivers/mfd/twl4030-core.c
>> index cd1008c..952bea5 100644
>> --- a/drivers/mfd/twl4030-core.c
>> +++ b/drivers/mfd/twl4030-core.c
>> @@ -134,6 +134,9 @@
>> #define TWL4030_BASEADD_PWMB0x00F1
>> #define TWL4030_BASEADD_KEYPAD 0x00D2
>>
>> +#define TWL5031_BASEADD_ACCESSORY 0x0074 /* Replaces Main
>> Charge */
>> +#define TWL5031_BASEADD_INTERRUPTS 0x00B9 /* Different to
>> TWL4030's one */
>> +
>> /* subchip/slave 3 - POWER ID */
>> #define TWL4030_BASEADD_BACKUP 0x0014
>> #define TWL4030_BASEADD_INT 0x002E
>> @@ -164,6 +167,7 @@
>> /* chip-specific feature flags, for i2c_device_id.driver_data */
>> #define TWL4030_VAUX2 BIT(0) /* pre-5030
>> voltage ranges */
>> #define TPS_SUBSET BIT(1) /* tps659[23]0 have
>> fewer LDOs */
>> +#define TWL5031 BIT(2) /* twl5031 has
>> different registers */
>>
>>
>> /*
>> --*/
>>
>> @@ -216,6 +220,8 @@ static struct twl4030mapping
>> twl4030_map[TWL4030_MODULE_LAST + 1] = {
>> { 2, TWL4030_BASEADD_PWM1 },
>> { 2, TWL4030_BASEADD_PWMA },
>> { 2, TWL4030_BASEADD_PWMB },
>> +{ 2, TWL5031_BASEADD_ACCESSORY },
>> +{ 2, TWL5031_BASEADD_INTERRUPTS },
>>
>> { 3, TWL4030_BASEADD_BACKUP },
>> { 3, TWL4030_BASEADD_INT },
>> @@ -464,7 +470,8 @@ add_children(struct twl4030_platform_data
>> *pdata, unsigned long features)
>> struct device *child;
>> struct device *usb_transceiver = NULL;
>>
>> -if (twl_has_bci() && pdata->bci && !(features & TPS_SUBSET)) {
>> +if (twl_has_bci() && pdata->bci &&
>> +!((features & TPS_SUBSET) || (features & TWL5031))) {
>> child = add_child(3, "twl4030_bci",
>> pdata->bci, sizeof(*pdata->bci),
>> false,
>> @@ -707,6 +714,7 @@ static void clocks_init(struct device *dev)
>>
>> int twl_init_irq(int irq_num, unsigned irq_base, unsigned irq_end);
>> int twl_exit_irq(void);
>> +int twl_init_chip_irq(const char *chip);
>>
>> static int twl4030_remove(struct i2c_client *client)
>> {
>> @@ -780,6 +788,10 @@ twl4030_probe(struct i2c_client *client,
>> const struct i2c_device_id *id)
>> if (client->irq
>> && pdata->irq_base
>> && pdata->irq_end > pdata->irq_base) {
>> +status = twl_init_chip_irq(id->name);
>> +if (status < 0)
>> +goto fail;
>
>No need to check since status is always zero.
Right, I'll remove the check.
>> +
>> status = twl_init_irq(client->irq,
>> pdata->irq_base, pdata->irq_end);
>> if (status < 0)
>> goto fail;
>> @@ -795,6 +807,7 @@ fail:
>> static const struct i2c_device_id twl4030_ids[] = {
>> { "twl4030", TWL4030_VAUX2 }, /* "Triton 2" */
>> { "twl5030", 0 }, /* T2 updated */
>> +{ "twl5031", TWL5031 }, /* TWL5030 updated */
>> { "tps65950", 0 }, /* catalog version of twl5030 */
>> { "tps65930", TPS_SUBSET }, /* fewer LDOs and DACs;
>> no charger */
>> { "tps65920", TPS_SUBSET }, /* fewer LDOs; no codec
>> or charger */
>> diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
>> index aca2670..d781788 100644
>> --- a/drivers/mfd/twl4030-irq.c
>> +++ b/drivers/mfd/twl4030-irq.c
>> @@ -61,6 +61,7 @@
>>
>> /* Linux could (eventually) use either IRQ line */
>> static int irq_line;
>> +static int chip_is_twl5031;
>>
>> struct sih {
>> charname[8];
>> @@ -82,6 +83,9 @@ struct sih {
>> /* + 2 bytes padding */
>> };
>>
>> +static const struct sih *sih_modules;
>> +static int nr_sih_modules;
>> +
>> #define SIH_INITIALIZER(modname, nbits) \
>> .module = TWL4030_MODULE_ ## modname, \
>> .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
>> @@ -107,7 +111,7 @@ str
Re: mux strategy (was RE: [PATCH] [OMAP1] mux: Add MMC mux pins for omap7xx)
On Wed, Oct 7, 2009 at 10:47 AM, Tony Lindgren wrote: > * Kevin Hilman [091006 15:18]: >> "Menon, Nishanth" writes: >> >> >> -Original Message- >> >> From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- >> >> ow...@vger.kernel.org] On Behalf Of Kevin Hilman >> >> >> >> >>> W17_7XX_USB_VBUSI, >> >> >>> + >> >> >>> + /* MMC */ >> >> >>> + MMC_7XX_CMD, >> >> >>> + MMC_7XX_CLK, >> >> >>> + MMC_7XX_DAT0, >> >> >> >> >> >> probably a dumb question -> but should'nt these go off to bootloader >> >> >> perhaps? >> >> >> >> >> > >> >> > Perhaps, although we use either EOL (for HTC Wizard) or Haret to boot, >> >> > and they don't set up the right mux configuration for our board. >> >> > >> >> > This way though, we don't have to worry about the boot loader -- we >> >> > can set it up right regardless of who boots us. >> >> >> >> I agree with Cory. >> >> >> >> I prefer that mux settings go into the kernel, even if they are setup >> >> in the bootloader already. It's better to have redundancy than wonder >> >> what to do if changing boot loaders. >> >> >> > Probably opening up a can of worms.. Are the rules different for OMAP3? >> > Should'nt we have all mux done at kernel so that kernel is loader >> > independent? >> >> Yes, we should. My preference is to always have muxing in the kernel. > > Agreed. We still should support bootloader only muxing too. > > BTW, I've been thinking about the following sets of patches for the next > merge window: > > 1. Do the include directories for mach-omap1 and mach-omap2 as suggested > by Russell earlier > > 2. Move all mux code to only live under arch/arm/*omap*/ and make sure > drivers don't call omap_cfg_reg() any longer > > 3. Remove the enumeration for the mux and require all the boards to > register the pins they'll use > > After these it should be trivial to improve the mux code further. The > steps 2 & 3 above will be most likely breaking things for some boards, > so help will be needed with testing. > FYI... I've updated the pinmux section of the OMAP wishlist wiki with this rough plan from Tony. http://elinux.org/OMAP_wishlist Kevin -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: patch: add omap730 / omap850 rtc support
On Wed, Oct 14, 2009 at 4:09 PM, Christopher Friedt wrote: > I decided on using 31 because sorry, that should read '' because 1/32768 is between 30 and 31" -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: patch: add omap730 / omap850 rtc support
> -Original Message-
> From: Christopher Friedt [mailto:chrisfri...@gmail.com]
> Sent: Wednesday, October 14, 2009 6:58 PM
> To: G, Manjunath Kondaiah
> Cc: linux-omap@vger.kernel.org
> Subject: Re: patch: add omap730 / omap850 rtc support
>
> On Wed, Oct 14, 2009 at 11:52 AM, G, Manjunath Kondaiah
> wrote:
> > You can acheive the same using only enum with following:
> >
> > #define OMAP_RTC_REGISTER_SIZE (cpu_is_omap7xx()?1:4)
> > #define rtc_read(reg)
> > omap_readb(OMAP_RTC_BASE + (reg * OMAP_RTC_REGISTER_SIZE))
>
> That was my first instinct too, but then I thought that one of the
> register offsets wasn't related by a factor of 4 (when I made the
> patch originally it was ~ 2am and I was very tired), which convinced
> me to do a quick & easy static array implementation.
>
> Thanks for your suggestion.
You can add reserve register offsets into enum array to fix the issue
of register offsets not in sequence like:
enum omap_rtc_regs {
SECONDS_REG = 0,
MINUTES_REG,
HOURS_REG,
DAYS_REG,
MONTHS_REG,
YEARS_REG,
WEEKS_REG,
RESV_REG_1,
ALARM_SECONDS_REG,
ALARM_MINUTES_REG,
ALARM_HOURS_REG,
ALARM_DAYS_REG,
ALARM_MONTHS_REG,
ALARM_YEARS_REG,
RESV_REG_2,
RESV_REG_3,
CTRL_REG,
STATUS_REG,
INTERRUPTS_REG,
COMP_LSB_REG,
COMP_MSB_REG,
};
>
> Regarding the 50 -> 35 change, I think it's clearly safe to do. I have
> no objections.
>
> C
>
Ok. Change the value to 35.
-Manjunath
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Re: patch: add omap730 / omap850 rtc support
I decided on using 31 because
=
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c
index 0587d53..cc25f4f 100644
--- a/drivers/rtc/rtc-omap.c
+++ b/drivers/rtc/rtc-omap.c
@@ -22,6 +22,7 @@
#include
#include
+#include
/* The OMAP1 RTC is a year/month/day/hours/minutes/seconds BCD clock
@@ -40,28 +41,28 @@
#define OMAP_RTC_BASE 0xfffb4800
/* RTC registers */
-#define OMAP_RTC_SECONDS_REG 0x00
-#define OMAP_RTC_MINUTES_REG 0x04
-#define OMAP_RTC_HOURS_REG 0x08
-#define OMAP_RTC_DAYS_REG 0x0C
-#define OMAP_RTC_MONTHS_REG0x10
-#define OMAP_RTC_YEARS_REG 0x14
-#define OMAP_RTC_WEEKS_REG 0x18
-
-#define OMAP_RTC_ALARM_SECONDS_REG 0x20
-#define OMAP_RTC_ALARM_MINUTES_REG 0x24
-#define OMAP_RTC_ALARM_HOURS_REG 0x28
-#define OMAP_RTC_ALARM_DAYS_REG0x2c
-#define OMAP_RTC_ALARM_MONTHS_REG 0x30
-#define OMAP_RTC_ALARM_YEARS_REG 0x34
-
-#define OMAP_RTC_CTRL_REG 0x40
-#define OMAP_RTC_STATUS_REG0x44
-#define OMAP_RTC_INTERRUPTS_REG0x48
-
-#define OMAP_RTC_COMP_LSB_REG 0x4c
-#define OMAP_RTC_COMP_MSB_REG 0x50
-#define OMAP_RTC_OSC_REG 0x54
+#define OMAP_RTC_SECONDS_REG 0x00
+#define OMAP_RTC_MINUTES_REG 0x01
+#define OMAP_RTC_HOURS_REG 0x02
+#define OMAP_RTC_DAYS_REG 0x03
+#define OMAP_RTC_MONTHS_REG0x04
+#define OMAP_RTC_YEARS_REG 0x05
+#define OMAP_RTC_WEEKS_REG 0x06
+
+#define OMAP_RTC_ALARM_SECONDS_REG 0x08
+#define OMAP_RTC_ALARM_MINUTES_REG 0x09
+#define OMAP_RTC_ALARM_HOURS_REG 0x0a
+#define OMAP_RTC_ALARM_DAYS_REG0x0b
+#define OMAP_RTC_ALARM_MONTHS_REG 0x0c
+#define OMAP_RTC_ALARM_YEARS_REG 0x0d
+
+#define OMAP_RTC_CTRL_REG 0x10
+#define OMAP_RTC_STATUS_REG0x11
+#define OMAP_RTC_INTERRUPTS_REG0x12
+
+#define OMAP_RTC_COMP_LSB_REG 0x13
+#define OMAP_RTC_COMP_MSB_REG 0x14
+#define OMAP_RTC_OSC_REG 0x15
/* OMAP_RTC_CTRL_REG bit fields: */
#define OMAP_RTC_CTRL_SPLIT(1<<7)
@@ -87,10 +88,12 @@
#define OMAP_RTC_INTERRUPTS_IT_ALARM(1<<3)
#define OMAP_RTC_INTERRUPTS_IT_TIMER(1<<2)
+#define OMAP_RTC_REGISTER_SIZE (cpu_is_omap7xx()?1:4)
-#define rtc_read(addr) omap_readb(OMAP_RTC_BASE + (addr))
-#define rtc_write(val, addr) omap_writeb(val, OMAP_RTC_BASE + (addr))
-
+#define rtc_read(reg) \
+ omap_readb( OMAP_RTC_BASE + OMAP_RTC_REGISTER_SIZE * reg )
+#define rtc_write(val,reg) \
+ omap_writeb( val, OMAP_RTC_BASE + OMAP_RTC_REGISTER_SIZE * reg )
/* we rely on the rtc framework to handle locking (rtc->ops_lock),
* so the only other requirement is that register accesses which
@@ -102,7 +105,7 @@ static void rtc_wait_not_busy(void)
u8 status;
/* BUSY may stay active for 1/32768 second (~30 usec) */
- for (count = 0; count < 50; count++) {
+ for (count = 0; count < 31; count++) {
status = rtc_read(OMAP_RTC_STATUS_REG);
if ((status & (u8)OMAP_RTC_STATUS_BUSY) == 0)
break;
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RE: RE: Memory performance / Cache problem
> There is no newer u-boot from TI available. There is a SDK 02.01.03.11 > but it contains the same uboot 2008.10 with the only addition of the second > generation of EVM boards with another network chip. > > So I checked the uboot from git, but this doesn't support Microns NAND Flash > anymore. It is just working with ONENAND. > > I found a patch which shows the L2 Cache status while kernel boot and > implemented it : L2 Cache seems to be already enabled - so this is not the > reason. > > So any other ideas? Are you confident your memory bus isn't running at 1/2 speed? I recall there was a couple day window during wtbu kernel upgrades where memory bus speed with pm was running 1/2 speed after kernel started up. This was somewhat a side effect of constraints frame work and a regression in forward porting. It seems unlikely psp kernel would have shipped with this bug but its something to check. This would match your results. If your memcpy() is neon based then I might be worried about l1neon-caching effects along with factors of (exlcusive-l1-l2-read-allocate cache + pld not being effective on l1 only l2). Which memcpy test are you using? Something in lmbench or just one you wrote. Generally results are a little hard to interpret with exclusive cache behavior in 3430's r1px core. 3630's r3p2 core gives more traditional results as exclusive feature has been removed by arm. If you have the ability using Lauterbach + per file will allow internal space dump which will show all critical parameters during test. It's a 1 minute check for someone who has done it before to ensure the few parameters needed are in line. I can send an example off line of how to do capture. I won't have time to expand on all relevant parameters. Regards, Richard W. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: patch: add omap730 / omap850 rtc support
On Wed, Oct 14, 2009 at 11:52 AM, G, Manjunath Kondaiah wrote: > You can acheive the same using only enum with following: > > #define OMAP_RTC_REGISTER_SIZE (cpu_is_omap7xx()?1:4) > #define rtc_read(reg) > omap_readb(OMAP_RTC_BASE + (reg * OMAP_RTC_REGISTER_SIZE)) That was my first instinct too, but then I thought that one of the register offsets wasn't related by a factor of 4 (when I made the patch originally it was ~ 2am and I was very tired), which convinced me to do a quick & easy static array implementation. Thanks for your suggestion. Regarding the 50 -> 35 change, I think it's clearly safe to do. I have no objections. C -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH RESEND] I2C: OMAP: Add missing wakeup events
> > >> /* I2C WE wakeup enable register */ > > >> -#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ > > >> +#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakeup */ > > >> #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ > > >> +#define OMAP_I2C_WE_ROVR_WE (1 << 11) /* RX overflow wakeup */ > > >> +#define OMAP_I2C_WE_XUDF_WE (1 << 10) /* TX underflow wakeup > > >> */ > > > > > > These bits are not documented in OMAP3430, they are reserved. How can > > they be used? > > > > Hmm, that's a valid point. I will have to check if I can find more info on > > the background of this patch. > > AFAIK, these bits have been introduced in OMAP3630 as it has a new IP block > for I2C. But these bits are reserved bits for OMAP3430. Couple notes: - IP block is updated but it is not new. These should just be some reserved bits converted. New bits expand wakeup capability and enhance FIFO operation with DMA. - Driver for a while supported OMAP1/2420 style I2C and OMAP2430/3/4 style I2C. Definitions between broad class drivers are different. The interrupt handler is easiest to see this. This is not so relevant to above bits but is good to keep in mind. Regards, Richard W. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Broken cpuidle on PM branch?
On Wed, Oct 14, 2009 at 03:06:41PM +0200, ext Kevin Hilman wrote:
> Eduardo Valentin writes:
>
> > On Tue, Oct 13, 2009 at 06:25:17PM +0200, ext Kevin Hilman wrote:
> >> Eduardo Valentin writes:
> >>
> >> > Hello Amit,
> >> >
> >> > On Mon, Oct 12, 2009 at 09:23:47PM +0200, ext Amit Kucheria wrote:
> >> >> Hi,
> >> >>
> >> >> I am testing twl4030 script optimisations on the current PM branch. But
> >> >> I am
> >> >> seeing the board (RX51) freeze when CPU_IDLE is enabled in the config.
> >> >>
> >> >> Is it known to work on other boards?
> >> >
> >> > I'm actually seeing this same behavior. But the board actually does not
> >> > freeze. If you keep a key pressed of send a sysrq through serial line
> >> > then you eventually get it back.
> >> >
> >> > It seams to be something related to serial driver and wakeup ?
> >> >
> >>
> >> Do you see this problem after doing
> >>
> >> # echo 1 > /debug/pm_debug/sleep_while_idle
> >>
> >
> > No I don't. The problem is gone it seams.
> >
> > similar effect happens if we
> >
> > # echo 0 > /sys/devices/platform/serial8250.2/sleep_timeout
> >
> > Of course, this would prevent device go to sleep I guess.
> >
>
> Yes, there is a problem with UART3 (in PER) going idle independently
> of CORE/MPU that I have not yet found.
yeah, one possible fix would be preventing it if core is going to on
@@ -514,7 +514,9 @@ void omap_sram_idle(void)
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
- omap_uart_prepare_idle(2);
+ if (core_next_state != PWRDM_POWER_ON)
+ omap_uart_prepare_idle(2);
+
Needs to see what is the impact of this approach though
>
> Kevin
--
Eduardo Valentin
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