Re: Led astray? Xilinx ml410 + u-boot + Linux?

[Peter Ryser]

Joe,

please have a look at http://www.xilinx.com/ml410-p. The pages do 
contain information, documentation, and examples on how to use U-Boot 
and Linux 2.4 on the ML410.
There are Linux 2.6 solutions for the ML40x boards (ML403 and ML405) 
from MontaVista and Wind River. Since the ML40x boards are in key parts 
identical to the ML410 you can use those ports as a starting point for a 
port to the ML410.

- Peter


Joe wrote:
> I was told (by Xilinx reps!) that the Xilinx ML410 "supported" Linux.
>
> My goal is to have something "load" Linux and then execute it -- 
> preferably over NFS / Ethernet (for development purposes).
>
> As far as I can tell from searching the 'Net the ML403 is fairly well 
> supported but I have yet to see any level of confirmation that the 
> ML410 fully supports u-boot, Linux and Ethernet.
>
> When I download the u-boot file(s) from Xilinx they basically don't work:
>
>   0)  I get a u-boot command prompt via the serial port!! ;)
>   1)  The u-boot loadb command fails to accept any data via the kermit 
> protocol
>   2)  The u-boot 'dhcp' command fails to obtain an address -- either 
> by simply crashing or by sitting there indicating that it is re-trying 
> (in which case an Ethernet sniffer shows no activity from the Ethernet 
> ports).
>
> Linux 2.6.19 shows arc/ppc/configs/ml[403|300]_defconfig, but I see 
> *zero* indication that the 410 is supported.  Has anyone seen the 
> ML410 fully functional with Linux + a patch to enable the Ethernet ports?
> (I also note that on the mvi$ta site they list support for:  ML300 and 
> ML40x -- but NOT the ML410.)  My searches also seem to indicate that 
> the IP included for the 410 Ethernet MAC's is distinctly different 
> from the 403...
>
> My current project has a *very* short fuse -- I should have been 
> "running" (e.g. past init into a shell w/filesystem) two weeks ago.
>
> If someone could confirm that this platform *is* supported (and I'm 
> just missing this on my searches) I'd be quite grateful for some 
> pointers on where to re-direct my searches.
>
> OTOH, if someone could confirm that this platform is NOT currently 
> supported that would be just as useful -- decisions can be made and 
> actions taken.
>
> TIA.
>
> -- 
> Joe
>
>
>
>
> 
>
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Re: system ace programming xf60

[Peter Ryser]

Wade,

the v4fx60 has two PPC405. Please make sure that both PPC405 are 
connected to the jtagppc_cntrl in your MHS hardware project file. You 
might want to compare your setup with the ML410 reference design 
available at 
http://www.xilinx.com/products/boards/ml410/designs/ml410_bsb_design.zip.


The JTAG IR length of the v4fx60 is 14 (6 for the FPGA + 4 for each 
PPC405, i.e. for the 4vfx60 it's 6+4+4=14)


- Peter


Wade Maxfield wrote:


Hi,

  We are trying to generate a system ace file that will program an 
xf60 using Xilinx scripts,

(and even their impact GUI), using 8.1i, service pack 3 EDK.

  Unfortunately, if we choose the ml410 board from Xilinx's genace.tcl 
script
in their EDK/data/xmd directory, it errors with an invalid instruction 
register length.
The irlength is listed as 14 in the xilinx script files.  I looked and 
googled and could

not find the irlength listed for that xf60 part in any literature.

  Also, if we try to include the zImage.elf file, the script errors out.

  Conversely, if we choose an ml403 board (and switch the project to 
the xf12 chip),
we can combine the zImage.elf file and generate a system.ace file that 
loads on an

ml403 board.

  We can take the download.bit file that refuses to load when combined 
into the system.ace,

and load it over the jtag port.  It programs the xf60 just fine.

  If we create an empty system.ace file,  the system ace chip on our 
board signals everything is ok,
but of course, the xilinx chip is not programmed.  If we pull the 
compact flash out of the board,
the system ace chip signals that is can't find the compact flash by 
flashing the error light.


  Has anyone on this list had any experience with this that could lead 
us in a right direction?  We've

tried about 10 different combinations so far with no luck.

thanks,
wade



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Re: ML403 patch for UBOOT

[Peter Ryser]

You might want to start with XAPP542
http://direct.xilinx.com/bvdocs/appnotes/xapp542.pdf
http://direct.xilinx.com/bvdocs/appnotes/xapp542.zip

The zip file includes the U-Boot patch for Linux kernel 2.4.

- Peter



alayrac wrote:

>I'm new member of this mailing list an I'm looking for some information
>on UBOOT on ML403.
>
>stevea-mdi talk about a pacth from  Ameet
>(http://www.linux2knowmore.com) but I did not succeed to find this
>pacth.
>The one attached to the mail
>(http://patchwork.ozlabs.org/linuxppc/patch?id=6502)  seems to be for
>linux 2.6.17-4 and not for UBOOT.
>
>Is there something I'm doing wrong?
>
>Where can I found a pacth for UBOOT for ML403?
>
>Thank you in advance for any help
>
>Chris
>
>
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Re: Unable to boot linux on Xilinx ML403 board

[Peter Ryser]

>avail ram: 0077 0800
>  
>

The ML403 only has 64 MB of RAM, ie. 0x0400. For a start you can 
change the amount of memory Linux thinks it has available by adding
mem=0x400
to the kernel command line like
Linux/PPC load: console=tty1 console=ttyS0,9600 ip=off root=/dev/ram 
rw mem=0x400

Later, you want to change xparameters*.h in arch/ppc/platforms/xilinx_ocp

- Peter



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Re: PPC405 system slow boot

[Peter Ryser]

Clint,

check the interrupt sub-system of your design. What you describe
typically happens when the PPC does not get any interrupts from the
UART. It's most likely a mismatch between your hardware and the
xparameters.h.

- Peter


Clint Thomas wrote:

  
  
  Hey
guys,
  
I've run through the loops to try and figure what could be wrong with
this system. The board in question is modeled after the Xilinx ML300
board. It uses a Xilinx System ACE chip to load a FPGA / Kernel image
from compact flash. Originally, I was trying to use the CompactFlash as
the root file system, but because of issues in either the design or
software, this would only work if SysAce was in polled I/O mode. To
circumvent this, I built my root filesystem into an initrd image and
built a single ELF file with the Kernel and RFS, then strapped that to
the FPGA bit file to make a single FPGA/Kernel/RFS SysAce file.
  
Upon decompression, the Linux kernel boots quickly and loads all of the
device drivers. However when it gets to the prompt, it starts slowing
down. Output and input to and from the board becomes very very slow (it
displays 2 characters roughly every 20 seconds). Originally I believed
this to be the CPU still polling SystemAce, so I disabled the Linux
System ACE drivers to remove that as a possibility, however after doing
this, the problem still persists, even with the RFS in ram! Has anybody
encountered a similar situation to this before, with possible insight
towards a solution? Thank you for your time.
   
  Clinton Thomas
[EMAIL PROTECTED]
   
  

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PPC405 system slow boot

[Peter Ryser]

Clint,

check the interrupt sub-system of your design. What you describe 
typically happens when the PPC does not get any interrupts from the 
UART. It's most likely a mismatch between your hardware and the 
xparameters.h.

- Peter


Clint Thomas wrote:

> Hey guys,
>
> I've run through the loops to try and figure what could be wrong with 
> this system. The board in question is modeled after the Xilinx ML300 
> board. It uses a Xilinx System ACE chip to load a FPGA / Kernel image 
> from compact flash. Originally, I was trying to use the CompactFlash 
> as the root file system, but because of issues in either the design or 
> software, this would only work if SysAce was in polled I/O mode. To 
> circumvent this, I built my root filesystem into an initrd image and 
> built a single ELF file with the Kernel and RFS, then strapped that to 
> the FPGA bit file to make a single FPGA/Kernel/RFS SysAce file.
>
> Upon decompression, the Linux kernel boots quickly and loads all of 
> the device drivers. However when it gets to the prompt, it starts 
> slowing down. Output and input to and from the board becomes very very 
> slow (it displays 2 characters roughly every 20 seconds). Originally I 
> believed this to be the CPU still polling SystemAce, so I disabled the 
> Linux System ACE drivers to remove that as a possibility, however 
> after doing this, the problem still persists, even with the RFS in 
> ram! Has anybody encountered a similar situation to this before, with 
> possible insight towards a solution? Thank you for your time.
>  
> Clinton Thomas
> cthomas at soneticom.com
>  
>
>
>
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MontaVista 2.6 Kernel support for Xilinx ML40x

[Peter Ryser]

Wade,

are you sure that you did not build your hardware with evaluation cores 
of the licenses? If you are using the evaluation licenses the hardware 
(FPGA design) will stop working after a certain amount of time and you 
will see a lock-up.

- Peter


Wade Maxfield wrote:

>
>   I've got the LSP, and have booted it on the ML40X.
>  
>   In my opinion it is currently unstable, but that is my opinion.  
> I've not been able to keep it powered up for 24 hours without it 
> locking up on the RS232 serial terminal.  Also, running updatedb over 
> nfs causes it to abort with a kernel panic, although that might be an 
> interraction with the nfs server.  (Although even if the nfs server 
> dies (which it did not), I don't expect a kernel panic).
>
>I have had it run over 6 hours without issue, so I expect subtle 
> memory leaks, not serious problems.
>
>
>
> On 8/24/06, Claus Gindhart < claus.gindhart at kontron.com 
> > wrote:
>
> Frank,
>
> due to my understanding of the GPL (and i have already invested
> some time
> in understanding the various flavours of open source licences),
> you should
> contact Montavista, and ask them for the sources.
>
> This board adaption is derivative work of the GPL Kernel, so the
> result of
> this work also falls under the GPL, and has to be made freely
> available
> under the terms of the GPL.
>
> --
> Mit freundlichen Gruessen / Best regards
>
> Claus Gindhart
> SW R&D
> Kontron Modular Computers
> phone :++49 (0)8341-803-374
> mailto:claus.gindhart at kontron-modular.com
> 
> http://www.kontron.com
>
> -BEGIN GEEK CODE BLOCK-
>   Version: 3.1
>   GU d- s++:>++:+ a+ C++$ !U !P L++>$ E-- W+(-) N- o?
>   K? w !O !M V !PS PE- Y+ PGP+ t 5? X R* tv- b+ DI+++
>   D-- G e++> h--- !r x+++
> --END GEEK CODE BLOCK--
>
>
> -Original Message-
> From:
> linuxppc-embedded-bounces+claus.gindhart=kontron.com at ozlabs.org
> 
> [mailto:
> linuxppc-embedded-bounces+claus.gindhart=kontron.com at ozlabs.org
>  ozlabs.org>]
> On Behalf Of Frank D Lombardo
> Sent: Donnerstag, 24. August 2006 15:59
> To: linuxppc-embedded at ozlabs.org  ozlabs.org>
> Subject: MontaVista 2.6 Kernel support for Xilinx ML40x
>
>
> I noticed that MontaVista now has their Pro 4.0 version (2.6 Kernel)
> available for the Xilinx ML40x series of boards.  I would assume that
> means driver support for at least most of the hardware on the boards.
> Is this code that should be freely available?  How would one get a
> copy
> of these drivers?  I am interested in drivers for the ML403.
>
> Thanks,
> Frank
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Linux 2.4 Kernel on Xilinx Virtex4 FX100's PPC

[Peter Ryser]

It's a little bit more complicated than that but your statement is 
basically correct.

- Peter


Grant Likely wrote:

> On 6/1/06, Peter Ryser  wrote:
>
>> There are some silicon issues on the PPC405 in V4 with PVR 0x20011430
>> which are documented in Xilinx solution record 20658. All these issues
>> are fixed in silicon where the PPC405 has a PVR of 0x20011470.
>>
>> Said that it's not true that the caches cannot be used in silicon with
>> PVR 0x20011430. The problem is a corner case which does not show in
>> typical designs.
>
>
> If I understand correctly, the cache issue only shows up with RAM
> attached to the OPB (instead of PLB).  Is that correct?
>
> Cheers,
> g.
>
>

Linux 2.4 Kernel on Xilinx Virtex4 FX100's PPC

[Peter Ryser]

There are some silicon issues on the PPC405 in V4 with PVR 0x20011430 
which are documented in Xilinx solution record 20658. All these issues 
are fixed in silicon where the PPC405 has a PVR of 0x20011470.

Said that it's not true that the caches cannot be used in silicon with 
PVR 0x20011430. The problem is a corner case which does not show in 
typical designs.

- Peter


Aidan Williams wrote:

>Anantharaman Chetan-W16155 wrote:
>  
>
>>Has anyone successfully ported a Linux 2.4 Kernel on a Xilinx Virtex-4 
>>FX series FPGA?s, PPC405 processor?
>>
>>
>>
>
>Yes, see 
>http://ozlabs.org/pipermail/linuxppc-embedded/2006-April/022583.html
>
>Note that there are silicon bugs that prevent caches being used in some 
>chips.
>
>  
>
>>More specifically, the FX100 FPGA?
>>
>>
>
>I don't have one of those, sorry.
>
>- aidan
>
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Linux 2.4 Kernel on Xilinx Virtex4 FX100's PPC

[Peter Ryser]

We have Linux up and running on the Virtex-4 FX100. The PVR for the 
PPC405 in all FX100 is 0x20011470.

- Peter


Anantharaman Chetan-W16155 wrote:

>Was the port done on a FX100 FPGA? Also, what PVR number does the PPC405
>indicate?
>Thanks,
>Chetan
>
>-Original Message-
>From: glikely at gmail.com [mailto:glikely at gmail.com] On Behalf Of Grant
>Likely
>Sent: Wednesday, May 31, 2006 2:35 PM
>To: Anantharaman Chetan-W16155
>Cc: linuxppc-embedded at ozlabs.org
>Subject: Re: Linux 2.4 Kernel on Xilinx Virtex4 FX100's PPC
>
>On 5/31/06, Anantharaman Chetan-W16155
> wrote:
>  
>
>>Has anyone successfully ported a Linux 2.4 Kernel on a Xilinx Virtex-4
>>
>>
>FX
>  
>
>>series FPGA's, PPC405 processor?
>>
>>
>
>Linux on the V4-FX is well supported.  Xilinx has an app node
>describing how to modify the linuxppc-2.4 tree to work on the V4-FX.
>You can find out how to get the tree here:
>
>http://www.penguinppc.org/kernel/
>I've got both 2.4 & 2.6 happily running on my ML403 board here.
>
>Cheers,
>g.
>
>  
>

linux 2.4 on ml403

[Peter Ryser]

Jean-Francois,

follow the instructions in the ML403 Reference Design Users Guide (pg 
39). In particular, create the board support package with the Linux MLD 
and use the patch_linux script in the linux sub-directory of the ML403 
reference design. The patch sets bits 1 and 3 in CCR0 which is required 
for ES silicon, i.e. silicon where the PPC405 has a PVR of 0x20011430. 
After applying the patch the problem will be gone.

- Peter


Links:
- ML403 Web Page: http://www.xilinx.com/ml403
- ML403 Users Guide: http://www.xilinx.com/bvdocs/userguides/ug082.pdf
- ML403 reference design: 
http://www.xilinx.com/products/boards/ml403/files/ml403_emb_ref_ppc_81.zip


jean-francois.hasson at hispano-suiza-sa.com wrote:

>Hi,
>
>I have been trying to run a linux 2.4 devel from the montavista site on an
>ml403 following among other things some advice from BYU website. I managed
>to have Linux start on the ml403 after downaloading it with XMD but then I
>have an error message :
>
>Xilinx Virtex-II Pro port (C) 2002 MontaVista Software, Inc.
>(source at mvista.com)
>On node 0 totalpages: 16384
>zone(0): 16384 pages.
>zone(1): 0 pages.
>zone(2): 0 pages.
>Kernel command line: console=ttyS0,9600 root=/dev/xsysace/disc0/part3 rw
>Xilinx INTC #0 at 0x4120 mapped to 0xFDFFE000
>Calibrating delay loop... 99.73 BogoMIPS
>Oops: kernel access of bad area, sig: 11
>NIP:  XER: 005E LR:  SP: C0182E50 REGS: c0182da0 TRAP:
>0400
>   Not tainted
>MSR: 1030 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 11
>TASK = c0181020[0] 'swapper' Last syscall: 0
>last math  last altivec 
>GPR00:  C0182E50 C0181020 C0181020  0001 C0181120
>0048
>GPR08: 0048   0017 2422 CC60 
>
>GPR16:     1032 00182ED0 
>C000
>GPR24: C019DDB0 0001 C01A C01A 044AA234 0001 
>C0181020
>Call backtrace:
> C001C27C C0005F30 C00047C0 C0196064 C01943B8 C019154C
>C0002328
>Kernel panic: Aiee, killing interrupt handler!
>In interrupt handler - not syncing
> <0>Rebooting in 180 seconds..
>
>Does anyone have an idea as to what is wrong ? How could I investigate it ?
>I have turned on the xmon option while building the kernel and it indicates
>I have a kernel stack overflow. If it could help.
>
>Best regards,
>
>JF H
>
>
>
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Getting started with Xilinx V4 PPC?

[Peter Ryser]

Hi David,

you might want to have a look at the following documents beside the ones you 
mention in your email:
- XAPP765 (http://www.xilinx.com/bvdocs/appnotes/xapp765.pdf). This document 
describes on how to get started with EDK and the ML300 board. The approach for 
the ML403 board is the same as is for the Avnet board.
- UG080, pg. 37 (http://www.xilinx.com/bvdocs/userguides/ug082.pdf). This 
document contains a brief description on how to rebuild the Linux kernel for 
the ML403 board.

Start with rebuilding the reference design and Linux kernel for the ML403/Avnet 
board. All the necessary information can be found in the documents above and on 
 
http://www.xilinx.com/products/boards/ml403/reference_designs.htm (for the 
ML403 board)

At this time I recommend staying with the 2.4 Linux kernel as the support for 
ML300 (and the ML403 and the Avnet board) in the 2.6 kernel is very basic (UART 
only).

Since you only need Ethernet once the "project" returns from its flight you 
might want to consider to develop two hardware designs. The first one does not 
have Ethernet and is for the flight. The second one contains Ethernet but not 
some of the additional control logic and is for retrieving the data upon 
return. This might get you into a smaller device and I assume that size matters.

- Peter


David Summers wrote:

>I am starting a new project where I need to have a flash file system
>and an ethenet interface (HTTP and FTP).  The project is a solar
>physics experiment that will be launched on a sub-orbital rocket
>flight this fall.  The idea is that the experiment will write data
>files to the flash file system while in flight, and then I can
>download the data using ethernet after the experiment returns to
>earth.
>
>I think that Linux is the way to go for this project because of the
>JFFS2 filesystem and the strong networking support.  The only problem
>is that I am totally new to embedded linux.
>
>I am prototyping my system on an Avnet FX12 development board ( Specs
>here: http://tinyurl.com/4gfdv ) which is pretty similar to the Xilinx
>ML403 board except with less memory and no SystemACE slot.
>
>I will eventually build my own custom board with the same Xilinx
>Virtex 4 FX12 FPGA and additional flash memory and some custom
>interface hardware. My background is primarily as a hardware designer,
>and I am very confortable with the FPGA part of this project.   I am
>comfortable as a Linux user, and I am a pretty good C coder (for a
>hardware guy anyway :).  I have never built a linux system (embedded
>or desktop) before, and I need some help getting started with embedded
>linux.
>
>I have already found the following websites which have been a big help so far:
>
>http://www.klingauf.de/v2p/index.phtml
>http://splish.ee.byu.edu/projects/LinuxFPGA/configuring.htm
>http://www.crhc.uiuc.edu/IMPACT/gsrc/hardwarelab/docs/kernel-HOWTO.html#toc1
>
>I have a few questions that I hope someone can help me with:
>
>1. What is the best linux distribution to start out with?  I am
>currently working with the 2.4 kernel code from
>ppc.bkbits.net/linuxppc_2_4_devel, but I'm not sure that this version
>be being updated.  (MontaVista also seems to be making it rather
>difficult to download their free Linux Preview Kit, so I wouldn't mind
>finding another distribution)Does the DENX distribution have good
>PPC support?  Are there any others that I should look at, or should I
>just download the kernel source directly from kernel.org?
>
>
>2. kernel 2.4 or 2.6?
>
>It is my understanding that the latest version of MTD and JFFS2 have
>dropped support for kernel 2.4.  I would like to use JFFS2 on a NAND
>flash device, so it seems like I should use 2.6.  (Can I use JFFS2 on
>a NAND device with kernel v 2.4?)
>
>Being a complete newbie, am I biting off more that I can handle by
>trying to use 2.6?
>
>I have been lurking on the mailing list for a while, and I know that
>there are several people working on 2.6.x patches for the Xilinx
>virtex 4 parts.  Could someone point me to a list of the patches that
>I need to get me started?  I think that the ML403 patches should work
>with my board, but I don't know which ones I need to download.
>
>
>Thank you for your help,
>
>David Summers
>University of Colorado
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[PATCH 00/10] Updated ML300 & ML403 patches

[Peter Ryser]

You need to apply a patch to the 2.4 Linux kernel to make it work with 
U-Boot for the MLxxx boards. You can find that patch as part of Xilinx 
Application Note 542 (XAPP542, 
http://direct.xilinx.com/bvdocs/appnotes/xapp542.pdf, 
http://direct.xilinx.com/bvdocs/appnotes/xapp542.zip)

The process on how to apply the patch is described in that application note.

- Peter

PS: The application note is out of date for EDK tools newer than 6.2. 
The patch still works, though.


jeffer wrote:

> Hi at all
>
>
> Since two week I have this Problem and can't solve it. I allready read 
> DULG and search in
> Mailinglists but I can't run linux. Perhaps had the same problem and 
> can help me.
> My Problem:
> After I load the uImage (uImage at 0x0040 )
> from server, I try to run in with command bootm.
> => bootm 0040
>  Booting image at  0040...
>Image Name:   Linux-2.4.24-pre2
>Created:  2006-01-19   6:25:03 UTC
>Image Type:   PowerPC Linux Kernel Image (gzip compressed)
>Data Size:700730 Bytes = 684.3 kB
>Load Address: 
>Entry Point:  
>Verifying Checksum ... OK
>Uncompressing Kernel Image ... OK
>  
>  don't  start kernel
>   my board  :
>   sdram  16m  0ff
>   flash 4m   ffc0 ---fff
>  
>
> routing, so my current assumption is
> that I either have VIRTEX_UART defined improperly or I have the
> ppc_sys
> data structure created wrong.
>
>
> >
> >
>
>It would be really nice if the was either some comments in
> xparameters.h or in the Documents directory explaining what the Linux
> xparameters values are so that it it would be easy to know what items
> from xparameters_xxx.h have to be mapped or redefined.
>
>
>
> > This really isn't a big deal anyway; most of this discussion
> will become
> > moot in short order.  Sometime in the next few releases,
> linuxppc will
> > flip over to using a flattened device tree to pass device
> information
> > from the boot loader to the kernel.  xparameters will drop out
> of the
> > kernel proper entirely except for the edk-generated device drivers
> > (which is another issue entirely).  All the xparam stuff will be
> > extracted into a device tree by u-boot or the zImage wrapper.  The
> > kernel just won't care.  :)
>Where can we get more information on what is happening here ?
> I started the E12 port with most info in xparameters, but I have been
> moving towards getting things passed in board_info. I am not using
> u-boot as the E12 has a general purpose elf loader, and it was
> easier to
> add a fee lines for Linux. Regardless I would like to be
> compatible with
> whatever is coming - maybe even ahead fo the curve. The e12 is
> just the
> first of a family of products - the e14 already exists. There maybe
> revisions of each at different speeds with different memory.
>
>
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>
>
>
>
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>

[PATCH 00/10] Updated ML300 & ML403 patches

[Peter Ryser]

> Yeah, the head of Linus' tree is busted.  Doing a cg-seek 
> 67daf5f11f06b9b15f8320de1d237ccc2e74fe43 will work, but you first need 
> to remove the following line from arch/ppc/kernel/ppc_ksyms.c
>
> EXPORT_SYMBOL(get_wchan);
>
After applying your patches to the branch-point you mention above, 
removing that symbol, and configuring for the ML403 I can get to a boot 
prompt. Good.

Doing the same for the ML300, though, does not work, i.e. I get a single 
line saying:
"Data machine check in kernel mode."

Digging in the kernel configuration I don't seem to find a place where I 
can turn on more verbose output, i.e. a register dump at the time of the 
machine check exception. Any idea where I might find that?

- Peter

[PATCH 00/10] Updated ML300 & ML403 patches

[Peter Ryser]

> I don't understand what you mean.  It sounds like your suggesting I do 
> exactly opposite what you're arguing; hand modify one of the 
> xparameters_*.h files.  Are you saying that edk can't generate Linux 
> redefines for the ml403 at the moment? 

Yes, it can. It looks they are not present in the xparameters_ml403.h 
that you submitted as part of your patch. I'll send you the 
automatically generated file in a seperate email.

> I do *not* think I should replace the edk-generated 
> xparameters_ml403.h with a hacked xparameters_ml300.h file.  I'd 
> rather use the generated _ml403 file and change the infrastructure 
> when the Linux redefines are ready. 

See above. BTW, I'm not sure how familiar you are with the process in 
EDK. Let me know if I can help you step through it.

>> That's not a recommended flow. It's very easy to create an EDK design 
>> with the proper settings and since it is very likely that things 
>> change during the design process of the FPGA the small investment 
>> into making the proper settings in the tool will save a lot of time 
>> in the end.
>
>
> I understand that it's not *recommended*; I'm just saying it's not 
> always *reality*  :p 

Yeah, that's true for user projects. However, I hope that we can get the 
default included in the Linux 2.6 kernel right.

> Yes; but I already said that I'll change the patch to use the Xilinx 
> redefines.  My argument is simply that *if* changes are required, 
> there is a way for the user to do it.  In the normal (recommended) 
> case; nothing will need to be done.  (think Larry Wall's quote: "easy 
> things easy; hard things possible)
>
> When it is needed; the fixups will be in xparameters.h; not 
> xparameters_*.h; and they'll be for a specific port.  The fixups will 
> only need to be done once per project (most likely). 

I'm not sure that I follow your argument here.

> My point is that the Linux redefines are useful to more than just 
> Linux ports.  Don't you think standalone apps could also benefit from 
> a sane-set of defines for peripherals?  In other words; shouldn't the 
> Linux redefines be always available (and called something more generic)? 

I see what you mean and I tend to agree.

> okay, I'll change the patch to use those names. 

Great. Thanks.


- Peter

[PATCH 00/10] Updated ML300 & ML403 patches

[Peter Ryser]

> Hmm, did you use the ml403 and ml300 def configs?  What date did you 
> pull Linus' tree?  Kumar and Paul were talking today about some serial 
> subsystem breakage on the linux-2.6 tree this weekend... I'll fast 
> forward tonight and try it on my board. 

Okay, please let me know how this works for you.

> Try seeking to commit: 67daf5f11f06b9b15f8320de1d237ccc2e74fe43
> That's what I generated the latest patches against. 

Hmm, I only recently switched to using git. Is this number string some 
kind of a tag that I can synchronize my local git tree to? If so, how?

>> Anyway, there is another issue that I would like to bring up and it 
>> has to do with xparameters.h. The xparameters.h file, or more 
>> exactly, the xparameters_* file, is automatically generated by EDK 
>> and is then used to configure the devices in the Linux kernel at 
>> compile time. While I understand the desire to get away from a static 
>> device definition to device enumeration at run-time, the current set 
>> of patches is a step backwards for users from a useability point of 
>> view. Users will now have to modify xparameters*.h by hand which is 
>> an error-prone process. 
>
>
> Actually, users should *never* modifiy generated files.  The intent is 
> that board specific fixups go directly into the top level 
> xparameters.h so that newly generated files don't have to be touched.  
> But yes, I understand what you mean. 

An EDK user is free to choose arbitrary names for his peripherals. 
Additionally, Base System Builder uses different names for various 
boards (historically). With that it is impossible to make static 
assignments in xparameters.h. If you go back to the 2.4 kernel and have 
a look at xparameters_ml300.h you can see that the assignment of boards 
specific parameters to Linux specific parameters is done in there and 
that xparameters.h is basically used to chose the proper xparameters_* 
file for a given board.

>> Additionally, the original 'redefines' are now replaced with 
>> redefines in xparameters.h but differently for every board. I suggest 
>> we keep the 2.4 methodology until we can come up with a better 
>> approach to enumerate devices at run-time.
>
>
> Andrei & I are already discussing this.  I'm going to change the 
> xparameters redefines to provide a default set of mappings that can be 
> used if xparameters_*.h has the linux specific mappings. 

Thanks. Why not just use the xparameters_ml300.h file created by the 
system_linux.xmp in the EDK reference design for the ML403 and rename it 
to xparameters_ml403.h for inclusion into the kernel tree? We could then 
make a change in EDK, add a parameter that lets the user specify the 
board he uses, and with that automatically create an xparameters_ml403.h 
(or any other board for that matter).

> However, due to the fact that generated xparam files don't have the 
> Linux redefines if the FPGA engineer doesn't select a linux bsp.

That's not a recommended flow. It's very easy to create an EDK design 
with the proper settings and since it is very likely that things change 
during the design process of the FPGA the small investment into making 
the proper settings in the tool will save a lot of time in the end.

>   I think it's important to allow user defined 'fixups' for their 
> board. (I've personally worked on a couple of projects where the FPGA 
> engineer would not generate the Linux BSP).  Design specific fixups 
> can go into the top level xparameters.h without touching the generated 
> file 

I strongly believe that this approach fixes things in the wrong place. 
The correct thing to do is to use EDK to create a proper xparameters_*.h 
that matches the FPGA design. In your methodology, if the user decides 
to change the peripheral names in EDK he will have to go back and change 
the defines in xparameters.h. With the 2.4 kernel methodology that is 
not necessary as such changes will be represented in a regenerated 
board-specific xparameters_*.h

>  BTW; it really bugs me that edk will generate different xparam 
> files depending on the bsp; why isn't there a single standard set of 
> data that is loaded into all xparam files; regardless of software 
> target?  Some no-OS targets need the same information that a Linux 
> port needs.  

EDK creates an xparameters.h that matches the names of the parameters in 
the hardware design. However, EDK is capable of assuming other 
personalities than 'standalone', for example Linux. With the Linux 
personality it creates the proper files AND directory structure for 
inclusion into the Linux kernel. Ideally, the source files that are used 
to create the Linux bsp for a given FPGA design should be included in 
the kernel tree and be maintained in there (maybe, in the xparameters 
directory). I'm not so sure though how well this would be accepted in 
the community. Opinions?

> I've avoided using the same names as used by the Linux redefines 
> because I don't know how stable the linux bsp naming conven

Error: Three ML403 boards

[Peter Ryser]

Paula,

please verify that you are not running into the problem described in 
Xilinx Answer Record 22179 
(http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=22179).

- Peter


Paula Saame?o wrote:

> Hello,
>
> I have 3 Xilinx ML403 boards. I have implemented a 2.4 kernel with a 
> basic configuration, with network support, systemACE, IIC... and it 
> works perfectly in one of them.
>
> However, when I put the ACE card, without making any change, in other 
> ML403 board, it does not work. The .ace file is loaded ok but then the 
> network leds (6 leds) start blinking and nothing else happens.
>
> I have tried with two ML403 different boards, and I have no idea of 
> where the problem is. They should work in the same way, don't they?
>
> Any help would be great.
>
> Also, I am trying to load a 2.6 kernel, but I am still on the way. I 
> will let you know if I get it working.
>
> Thanks a lot!
> Paula
>
>
>
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>

linux 2.4 on Xilinx ml403

[Peter Ryser]

Make sure your system.mss contains something like:

BEGIN OS
 PARAMETER OS_NAME = linux_mvl31
 PARAMETER OS_VER = 1.01.a
 PARAMETER PROC_INSTANCE = ppc405_0
 PARAMETER MEM_SIZE = 0x400
 PARAMETER PLB_CLOCK_FREQ_HZ = 1
 PARAMETER connected_periphs = 
(RS232_Uart,IIC_EEPROM,SysACE_CompactFlash,Ethernet_MAC,opb_intc_0)
END

If it does not use XPS and in the menu select Platform Software 
Settings. Use linux as Operating System and linux_mvl31_v1_01_a as the 
MLD. The rerun the library generation. Also make sure that you have 
enabled the interrupts for System ACE CF in the hardware.

- Peter


Paulinha wrote:

> Hi all,
>
> I have been trying to run linux 2.4.26 on Virtex 4 for a while and 
> without success.
>
> I am trying to implement a simple design, with an UART, SystemACE and 
> everything interrupt driven. When I try to make bzImage, there is an 
> error in (SysACE) adapter.c file, because XPAR_INTC_0_SYSACE_0_VEC_ID 
> is not defined.
>
> I have applied the patch given by Xilinx for switching from the ml300 
> to the ml403, which copies the bsp, .config and xparameter files into 
> the kernel.
>
> I am stucked here, and do not know how to keep going from that.
> Could anyone help me a little bit?
>
> Thanks and have a good day!
>
>
>
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>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>

Source of xparameter_ml300.h

[Peter Ryser]

Please have a look at XAPP765 
(http://direct.xilinx.com/bvdocs/appnotes/xapp765.pdf) and the EDK 
documentation to see how this works. The latest MLD to create a BSP for 
a linuxppc-2.4 kernel is linuxppc_mvl31_v1_01_a. linuxppc_mvl31_v1_00_a 
works too but everything else is not up-to-date.

The documentation and tutorials for the ML310 board are also an 
excellent source of information how to get a Linux kernel up and running 
on Virtex-II Pro (see http://www.xilinx.com/ml310).

The reference design for the ML403 is yet another source of information 
(http://www.xilinx.com/ml403). Have a look at the reference design users 
guide.

Using the MLD (tcl script) is much less error-prone than any other 
method that involves changing the files by hand. It's a little bit of a 
learning curve but once mastered it just works.

- Peter



Andrei Konovalov wrote:

> Grant Likely wrote:
>
>> Does anyone know the origin of xparameter_ml300.h?  The
>> Xilinx EDK generates an xparameters.h file for each design, but the
>> structure of the file changes between releases.
>>
>> I want to know if xparameters_ml300.h is the exact output produced by
>> EDK or if stuff was changed before it was submitted to the mainline
>> tree.  (ie. all the stuff under the "linux redefines" comment block)
>
>
> EDK can also generate the "Linux BSP".
> In this case EDK uses the scripts from (depending on your setup)
> /opt/xilinx/edk/7.1/sw/ThirdParty/bsp/linux_v2_00_b/data/
> In particular, linux_v2_1_0.tcl adds those "linux redefines"
> and renames xparameters.h to xparameters_ml300.h.
>
>> Also, where can I get the bitstream/systemace file that matches
>> xparameters_ml300.h?
>
>
> The most reliable way is to generate both (bitstream and
> xparameters_ml300.h) by yourself. :)
>
> But if you are speaking about the xparameters_ml300.h in the community
> trees (linuxppc-2.4 and the 2.6 one from kernel.org), this file
> is for the reference design by Xilinx:
>
> http://www.xilinx.com/ise/embedded/edk6_2docs/ml300_edk3.zip
>
>> I've got a custom ml300 image that I'm regression
>> testing against, but I'd like to also test against some form of 'stock'
>> image. :)
>>
>> Thanks,
>> g.
>
>
> Thanks,
> Andrei
>
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>

linuxppc-2.4.30-pre1 crashes with root fs on Xilinx SystemACE

[Peter Ryser]

Some time ago we did some tests with bonnie++ on Linux running on the 
PPC405 in a Virtex-II Pro FPGA. You can expect the following performance:

Read peak: 629 KB/s
Write peak: 299 KB/s

Not considering network overhead, a 10MB file should take less than a 
minute to update.

- Peter


Tony Lee wrote:

> Keith, 
>
> Some suggestions, before you verify your hw board/FPGA works fine with 
> SYSACE,
> * don't use sysace as root fs.
> * use a ram fs as root fs.  
> * Next, load sysace driver a loadable driver module.  It works, I 
> tried it.
> * check mount read only and see if it works.
> * Next, mount it writable.
>
> We have some issues with sysace driver initially, everything works out 
> fine later.
> There were small errors in our HW layout.
>
> I had to hack the sysace driver left and right to id the problem.  But 
> at the
> end, after I fixed the layout problem from the fpga's ucf file, the 
> original driver
> run perfectly without any modification.
>
> In my experiences, the ppc linux distribution and its linux sysace 
> driver are good
> if everything is setup correctly.
>
> One minor issues:  The sysace driver's write performance sucks.  I 
> have to explain
> to others why the upgrade 10 MBytes files with usb flash writer takes 
> tens of
> seconds.  When we do it from linux (nfs or ftp), it tooks minutes to sync.
>
> Peter, maybe you can push the xilinx a bit on sysace write 
> performance? :-)
>
> -Tony
>
> On 8/29/05, Peter Ryser  <mailto:peter.ryser at xilinx.com>> wrote:
>
> Hi Keith,
>
> I sent you a private email but for other interested people:
> Downloading the latest linuxppc-2.4 kernel I could boot from and
> access
> System ACE CF without problems on a ML403 (Virtex-4, 4VFX12) and a
> ML310
> (Virtex-II Pro, 2VP30) using EDK 7.1.2. In both cases I started with
> config_xilinx_ml300.
>
> - Peter
>
>
>
> Keith J Outwater wrote:
>
> >Hello -
> >Per a previous suggestion from this list, I rsynced the linuxppc-2.4
> >kernel sources from MontaVista and modified the kernel to run on
> my custom
> >ppc405/VirtexII Pro based system with U-Boot as the bootloader.
> >When I try to use the SystemACE device as the root filesystem,
> the kernel
> >crashes with a sig 11.  Looking at the 'oops' output it appears  the
> >SystemACE driver may be to blame.  The crash is random -
> sometimes I get
> >all the way to login as root and then things crash on a file copy
> or a
> >file read.
> >Before I start digging deeper, is anyone running a VirtexIIPro based
> >system with the root filesystem in the CF card attached to a
> SystemACE?
> >I'm wondering if I really have the best kernel and SystemACE driver.
> >BTW, I'm developing the hardware design using Xilinx EDK 7.02i.
> >Thanks,
> >Keith
> >___
> >Linuxppc-embedded mailing list
> > Linuxppc-embedded at ozlabs.org <mailto:Linuxppc-embedded at ozlabs.org>
> >https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >
> >
> >
> >
>
>
>
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>
>
>
>
> -- 
> -Tony
> Having fun with FPGA HW + ppc + Linux

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linuxppc-2.4.30-pre1 crashes with root fs on Xilinx SystemACE

[Peter Ryser]

Hi Keith,

I sent you a private email but for other interested people:
Downloading the latest linuxppc-2.4 kernel I could boot from and access 
System ACE CF without problems on a ML403 (Virtex-4, 4VFX12) and a ML310 
(Virtex-II Pro, 2VP30) using EDK 7.1.2. In both cases I started with 
config_xilinx_ml300.

- Peter



Keith J Outwater wrote:

>Hello - 
>Per a previous suggestion from this list, I rsynced the linuxppc-2.4 
>kernel sources from MontaVista and modified the kernel to run on my custom 
>ppc405/VirtexII Pro based system with U-Boot as the bootloader.
>When I try to use the SystemACE device as the root filesystem, the kernel 
>crashes with a sig 11.  Looking at the 'oops' output it appears  the 
>SystemACE driver may be to blame.  The crash is random - sometimes I get 
>all the way to login as root and then things crash on a file copy or a 
>file read.
>Before I start digging deeper, is anyone running a VirtexIIPro based 
>system with the root filesystem in the CF card attached to a SystemACE? 
>I'm wondering if I really have the best kernel and SystemACE driver.
>BTW, I'm developing the hardware design using Xilinx EDK 7.02i.
>Thanks,
>Keith
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>
>
>  
>

Address mapping PPC 405

[Peter Ryser]

>Since there is no seperate IO memory space you can access the registers
>with simple pointers.
>
>Whether or not it is a good idea (based on coding conventions) I'll
>leave for someone else to answer.  :)
>
You want to use the read{b,w,l} and write{b,w,l} macros for two reasons:
1. Accesses to registers need to be synch'ed with 'eieio' or some other 
synchronizing instructions.
2. Portability of your driver if you ever should ever move it to a 
different architecture and/or change the endianness in your system

- Peter

Best kernel for Xilinx VirtexII Pro/PPC405 ?

[Peter Ryser]

Good to hear that you got everything working. Just as a note: XAPP542 
(http://direct.xilinx.com/bvdocs/appnotes/xapp542.pdf) contains a patch 
for the Linux kernel to make it work together with U-Boot.

Does linuxppc-2.4 still accept patches?

- Peter


Keith J Outwater wrote:

>Hi Peter - 
>Well, the good news is that it works, and works well.  In my humble 
>opinion, supporting it would be pretty simple, but I completely understand 
>why RHEL is the supported distribution.  I would much rather see effort 
>put into polishing up EDK under Linux than in supporting every Linux 
>distro out there.
>For me, the bottom line was this: do I want to migrate all of other 
>development activities from FC4 to RHEL for the sake of EDK, or try to run 
>EDK under FC4?  I tried the latter approach, and now that the Jungo 
>WinDriver v7.1 is out, parallel port debugging works by simply using 
>WinDriver 7.1 and patching the Xilinx XPC4 parport driver.
>I now have the kernel booting on a Memec 2VP50 eval board using U-Boot as 
>the bootloader.  I used the linuxppc-2.4 kernel rsynced from MontaVista. 
>That particular kernel did not have support for U-Boot but it did support 
>the ML300 and a Memec 2VP40/2VP70 board.  I had to modify the kernel to 
>accept a board description structure from U-Boot and I added a new board 
>type for my custom hardware.
>The approach I took was definitely the "roll your own approach", but then 
>again I've done this (Linux board ports) a couple times and I know U-Boot 
>well.
>Keith
>
>Peter Ryser  wrote on 08/18/2005 07:39:21 AM:
>
>  
>
>>>I am running all of my development tools (EDK, ISE, ELDK, etc...) 
>>>  
>>>
>under 
>  
>
>>>Fedora Core 4, so I am looking for a publicly accessible kernel source 
>>>tree that best supports the PPC405 in the Virtex II Pro.
>>>
>>>  
>>>
>>Keep in mind that EDK and ISE are not "officially" supported on FC4. 
>>Anyway, with EDK, ISE, and ELDK you seem to have all that is needed to 
>>get started with Linux on Virtex-II Pro and Virtex-4.
>>
>>- Peter
>>
>>
>>
>>
>
>
>  
>

Best kernel for Xilinx VirtexII Pro/PPC405 ?

[Peter Ryser]

> I am running all of my development tools (EDK, ISE, ELDK, etc...) under 
>Fedora Core 4, so I am looking for a publicly accessible kernel source 
>tree that best supports the PPC405 in the Virtex II Pro.
>
Keep in mind that EDK and ISE are not "officially" supported on FC4. 
Anyway, with EDK, ISE, and ELDK you seem to have all that is needed to 
get started with Linux on Virtex-II Pro and Virtex-4.

- Peter

[PATCH] Fix for TLB errata on early Xilinx Virtex-II Pro silicon

[Peter Ryser]

None of the ML300 will need this workaround as the core voltage is 
slightly higher than recommended in the data sheet of Virtex-II Pro. An 
increased core voltage is one way to fix the TLB problem in early parts 
but it is not the right way as it can have a negative impact on other 
V2P features.

Since the ML300 configuration is used as the base for other boards the 
patch is still useful. However, all Virtex-II Pro FPGAs that are 
shipping today are based on newer core versions and do not show the TLB 
problem.

- Peter


Andrei Konovalov wrote:

> Grant Likely wrote:
>
>> Early versions of the Xilinx Virtex-II Pro have a TLB errata where
>> only even numbered TLB entries work correctly.  Occurs on chips where
>> PVR == 0x20010820 || 0x20010860
>>
>> See Record #14052, solution #12 in the Xilinx answers database
>> http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14052
>>
>> This patch adds a config option to use only even TLB entries on the 
>> V2Pro
>> It also makes a trivial change to the Kconfig so that Xilinx options 
>> depend
>> on VIRTEX_II_PRO instead of XILINX_ML300
>>
>> Signed-off-by: Grant Likely 
>> ---
>>
>>  arch/ppc/kernel/head_4xx.S |   11 +++
>>  arch/ppc/platforms/4xx/Kconfig |   28 ++--
>>  2 files changed, 33 insertions(+), 6 deletions(-)
>>
>> 322a82cd190a777e4ebe728cad2a2a3759039260
>> diff --git a/arch/ppc/kernel/head_4xx.S b/arch/ppc/kernel/head_4xx.S
>> --- a/arch/ppc/kernel/head_4xx.S
>> +++ b/arch/ppc/kernel/head_4xx.S
>> @@ -769,7 +769,11 @@ finish_tlb_load:
>> /* load the next available TLB index.
>> */
>> lwz r9, tlb_4xx_index at l(0)
>> +#if defined(CONFIG_VIRTEX_II_PRO_TLB_FIX)
>> +   addir9, r9, 2
>> +#else
>> addir9, r9, 1
>> +#endif
>> andi.   r9, r9, (PPC4XX_TLB_SIZE-1)
>> stw r9, tlb_4xx_index at l(0)
>
>
> I would also fix the comment in this file
> (it has nothing to do with the TLB fix but...):
>
> @@ -915,10 +919,10 @@ initial_mmu:
> mtsprSPRN_PID,r0
> sync
>
> -/* Configure and load two entries into TLB slots 62 and 63.
> - * In case we are pinning TLBs, these are reserved in by the
> +/* Configure and load an entry into TLB slot 63.
> + * In case we are pinning TLBs, it is reserved in by the
>  * other TLB functions.  If not reserving, then it doesn't
> - * matter where they are loaded.
> + * matter where it is loaded.
>  */
> clrrwir4,r4,10/* Mask off the real page number */
> orir4,r4,(TLB_WR | TLB_EX)/* Set the write and execute 
> bits */
>
>> @@ -926,7 +930,14 @@ initial_mmu:
>> clrrwi  r3,r3,10/* Mask off the effective 
>> page number */ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
>>
>> +#if defined(CONFIG_VIRTEX_II_PRO_TLB_FIX)
>> +   /* Odd numbered TLB slots are broken on Xilinx V2Pro processors
>> +* where PVR = 20010820 | 20010860
>> +*/
>> +li  r0,62/* TLB slot 62 */
>> +#else
>>  li  r0,63/* TLB slot 63 */
>> +#endif
>>
>> tlbwe   r4,r0,TLB_DATA  /* Load the data portion of 
>> the entry */tlbwe   r3,r0,TLB_TAG   /* Load the tag 
>> portion of the entry */
>> diff --git a/arch/ppc/platforms/4xx/Kconfig 
>> b/arch/ppc/platforms/4xx/Kconfig
>> --- a/arch/ppc/platforms/4xx/Kconfig
>> +++ b/arch/ppc/platforms/4xx/Kconfig
>> @@ -161,11 +161,6 @@ config IBM_OCP
>> depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || 
>> EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
>> default y
>>
>> -config XILINX_OCP
>> -   bool
>> -   depends on XILINX_ML300
>> -   default y
>> -
>>  config IBM_EMAC4
>> bool
>> depends on 440GX || 440SP
>> @@ -201,6 +196,27 @@ config VIRTEX_II_PRO
>> depends on XILINX_ML300
>> default y
>>
>> +config VIRTEX_II_PRO_TLB_FIX
>> +   bool "Virtex-II Pro TLB bugfix"
>> +   depends on VIRTEX_II_PRO
>> +   default n
>> +   help
>> + Early versions of the Xilinx Virtex-II Pro have a TLB 
>> errata where
>> + only even numbered TLB entries work correctly.  Say Y here if
>> + PVR == 0x20010820 || 0x20010860, or if your board crashes 
>> early
>> + after enabling the MMU
>> +
>> + See Record #14052, solution #12 in the Xilinx answers database
>> + 
>> http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14052
>> +
>> + It is safe to say Y here, but there is a performance impact.
>> + Say N if unsure.
>> +
>> +config XILINX_OCP
>> +   bool
>> +   depends on VIRTEX_II_PRO
>> +   default y
>> +
>>  config STB03xxx
>> bool
>> depends on REDWOOD_5 || REDWOOD_6
>> @@ -208,7 +224,7 @@ config STB03xxx
>>
>>  config EMBEDDEDBOOT
>> bool
>> -   depends on EP405 || XILINX_ML300
>> +   depends on EP405 ||

Best kernel for Xilinx VirtexII Pro/PPC405 ?

[Peter Ryser]

You might want to look at Xilinx Application Note 765 (XAPP765, 
http://www.xilinx.com/bvdocs/appnotes/xapp765.pdf) for some instructions 
on how to get started with EDK and Linux. All source is published in 
linuxppc-2.4.

- Peter


Keith J Outwater wrote:

>Hello all - 
>I am designing an embedded system using a Xilinx Virtex II Pro FPGA.
>Can anyone point me to the "best" kernel source tree to use ?
>"Best" in this case means:
>1. A 2.4 series kernel with good support for Xilinx peripheral devices 
>(existing Xilinx ML300 support is fine).
>2. Good stability
>
>By default I'll use the Montavista linuxppc_2.4 tree unless there is a 
>better choice out there.
>
>Thanks!
>
>Keith
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>
>  
>

Fw: Montavista Patch for ml403

[Peter Ryser]

The linux/patch_linux script has some information on how to apply the 
patch. For the next release of the reference design we will include more 
information and also have updated the patch. The new release will be 
available within the next few days. Check 
http://www.xilinx.com/products/boards/ml403/reference_designs.htm for 
availability of the updates.

Further down find the updated instructions. I'll send you the updated 
patch in a private email.

- Peter


  Building the Linux BSP (PPC405 Systems Only)

The EDK design comes with MLD/TCL technology to generate a Linux BSP for 
ML40x and a script to patch a MontaVista Linux kernel from the ML300 LSP 
for use with this BSP.

To build a BSP for and to patch the Linux kernel, proceed as follows:

1. Start XPS and load the Linux XMP:
$ xps system_linux.xmp

2. Generate the Linux BSP with Tools->Generate Libraries and BSPs

The resulting Linux BSP is located in 
ppc405_0/libsrc/linux_mvl31_v1_00_a/linux.

3. Quit XPS

4. Create a copy of the MontaVista Linux kernel for the ML300 board.

The Linux kernel and the tools to build the Linux kernel are available 
from MontaVista (http://www.mvista.com). For further information about 
using Linux with EDK, refer to XAPP765: Getting Started with EDK and 
MontaVista Linux (http://www.xilinx.com/bvdocs/appnotes/xapp765.pdf).

5. Patch the Linux kernel for use with the ML40x board
$ cd linux
$ ./patch_linux 

This step copies the .config file from the linux directory to the Linux 
kernel, patches the Linux kernel with necessary changes for the ML40x 
board, and copies the Linux BSP into the Linux kernel.

Build the Linux kernel.
$ cd 
$ make oldconfig dep bzImage

The resulting Linux kernel resides in arch/ppc/boot/images/zImage.elf

6. To build an ACE file consisting of the FPGA bitstream and the Linux 
kernel, click Tools->Xygwin shell to run a shell, then type:
$ xmd ?tcl genace.tcl ?jprog ?hw implementation/download.bit ?elf  -ace implementation/system.ace



mcnernbm at notes.udayton.edu wrote:

>
> Contained with in the reference design for the xilinx ml403 board is a 
> patch for the montavista ml403 preview kit ot allow one to build the 
> kernel for the ml403 board. But I am having trouble applying the 
> patch. Does anyone know how to properly apply this patch. Also I tried 
> to follow the instrucions on coping the bsp files over but exactly 
> where to place them. Do I over write the folders with in the arch 
> directory and the drivers folder in the main kernel directory? Its not 
> 100% clear what files I need to over write.
> Any help would be greatly appreciated.
> Attached is the patch that come with the xilinx ml403 reference design
>
> Brett
>
>
>
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>

root fs mount issue: Xilinx System ACE on PCI bus

[Peter Ryser]

Is "Root on NFS" disabled?

- Peter


Sanjay Bajaj wrote:

>Hi! Gurus,
>
>Need some help in understanding root fs mounting. The setup we have here is 
>our hardware has Xilinx Virtex II pro chip that has System ACE hardware 
>connected to a compact flash. The Virtex II Pro is connected to Local PCI bus 
>which is run by PPC 440GX processor. I have ported the driver for xsysace from 
>ml300 config to our hardware (From OPB to PCI). When I boot over nfs, I can 
>easily mount the partictions on the compact flash. The nodes in /dev directory 
>are:
>
>brw-r--r--1 root root 254,   0 Jun  3 13:04 xsysacea
>brw-r--r--1 root root 254,   1 Jun  3 13:04 xsysacea1
>brw-r--r--1 root root 254,   2 Jun  3 13:04 xsysacea2
>
>When I try to boot from the commpact flash, the kernel panics. The edited boot 
>listing is as follows:
>
>=> bootm
>...
>...
>Kernel command line: root=/dev/xsysacea2 rw console=ttyS0,9600 mem=128M
>...
>...
>Partition check:
> xsysacea: xsysacea1 xsysacea2
>System ACE at 0xFFFC1000 mapped to 0xD207, irq=26, 500472KB
>...
>...
>VFS: Cannot open root device "xsysacea2" or 00:00
>Please append a correct "root=" boot option
>Kernel panic: VFS: Unable to mount root fs on 00:00
> <0>Rebooting in 180 seconds..
>
>---
>
>What am I missing here? Any help is appreciated.
>Thanks,
>Sanjay
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>
>
>  
>

connecting BDI2000 to ML403

[Peter Ryser]

If your debugger needs nTRST and HALT you can route the JTAG signals of 
the PPC405 processor through user IO pins to the expansion connector.

- Peter


Peter 'p2' De Schrijver wrote:

>Hi,
>
>I'm trying to figure out how to connect the BDI 2000 with a Xilinx ML403 
>development board. As far as I can see in the ML403 schematics, the JTAG
>connector lacks the nTRST and the HALT signals needed for JTAG
>debugging. Any ideas ?
>
>Thanks,
>
>Peter (p2).
>  
>
>
>
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>

Problems with MontaVista Linux on a Memec Virtex-II pro ff672 board

[Peter Ryser]

Also try to boot the first Linux kernel (the one without the Flash 
support) on the EDK design with Flash support. It will help narrow down 
the problem to the HW or the SW.

- Peter


S. van Beek wrote:

>>How did you add the Flash (EMC) peripheral? Did you use the Base System
>>Builder to generate your hardware?
>>
>>
>
>Yes, we started a new project using the base system builder with the same
>options as the previous (working) project and flash, so the address range
>should be ok. I'll check tomorrow, right now its time to go home ;)
>
>Regards,
>Sander
>
>- Original Message - 
>From: "Peter Ryser" 
>To: "S. van Beek" 
>Cc: 
>Sent: Thursday 17 March 2005 16:37
>Subject: Re: Problems with MontaVista Linux on a Memec Virtex-II pro ff672
>board
>
>
>  
>
>>How did you add the Flash (EMC) peripheral? Did you use the Base System
>>Builder to generate your hardware?
>>
>>If you configure the hardware manually and use the OPB EMC make sure
>>that you add the address range to the PLB2OPB bridge.
>>
>>- Peter
>>
>>
>>S. van Beek wrote:
>>
>>
>>
>>>Hello there,
>>>
>>>This is our first post on this list, hi all!
>>>We're two Dutch students working with a Virtex-II pro ff672 board from
>>>Memec with the Communications 2 module. We've compiled a simple kernel
>>>wich comes with MontaVista Linux 3.1 (2.4.20) with ethernet and a
>>>serial port. It mounts its root filesystem over NFS and everything
>>>seems to work nicely. The next step we wanted to make was
>>>adding support for the Flash on the com board. We added the IP to the
>>>hardware and loaded the new bitstream in the FPGA. Next thing, we
>>>enabled support for MTD devices in the kernel. After that, the kernel
>>>did not seem to boot anymore. It stopped at the message 'Now booting
>>>the kernel'. So we read some documentation about debugging. We
>>>recompiled this kernel with the -g -ggdb options and removed the -O
>>>(optimalization) flag. Then we did not even see the ppc boot loader
>>>messages anymore when trying to boot. So we tried to compile the first
>>>kernel (with only serial and ethernet support) -wich worked fine
>>>before- with debugging and it gave us the same result.. no output at
>>>  
>>>
>all.
>  
>
>>>Can anyone give us some hints on what we can try more to find out what
>>>is going wrong?
>>>
>>>Regards,
>>>Sander van Beek
>>>Daniel van Os
>>>
>>>
>>>
>>>___
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>>>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>>>
>>>  
>>>
>>
>>
>>
>
>
>
>
>  
>

Problems with MontaVista Linux on a Memec Virtex-II pro ff672 board

[Peter Ryser]

How did you add the Flash (EMC) peripheral? Did you use the Base System 
Builder to generate your hardware?

If you configure the hardware manually and use the OPB EMC make sure 
that you add the address range to the PLB2OPB bridge.

- Peter


S. van Beek wrote:

> Hello there,
>  
> This is our first post on this list, hi all!
> We're two Dutch students working with a Virtex-II pro ff672 board from 
> Memec with the Communications 2 module. We've compiled a simple kernel 
> wich comes with MontaVista Linux 3.1 (2.4.20) with ethernet and a 
> serial port. It mounts its root filesystem over NFS and everything 
> seems to work nicely. The next step we wanted to make was 
> adding support for the Flash on the com board. We added the IP to the 
> hardware and loaded the new bitstream in the FPGA. Next thing, we 
> enabled support for MTD devices in the kernel. After that, the kernel 
> did not seem to boot anymore. It stopped at the message 'Now booting 
> the kernel'. So we read some documentation about debugging. We 
> recompiled this kernel with the -g -ggdb options and removed the -O 
> (optimalization) flag. Then we did not even see the ppc boot loader 
> messages anymore when trying to boot. So we tried to compile the first 
> kernel (with only serial and ethernet support) -wich worked fine 
> before- with debugging and it gave us the same result.. no output at all.
> Can anyone give us some hints on what we can try more to find out what 
> is going wrong?
>  
> Regards,
> Sander van Beek
> Daniel van Os
>
>
>
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>

linux on xc2vp4

[Peter Ryser]

Have a look at http://direct.xilinx.com/bvdocs/appnotes/xapp765.pdf. 
This should get you started. Instead of targetting the ML300 board in 
the Base System Builder create a system for a customer board. Don't 
forget to modify the UCF file to constrain the pinout.

All the peripherals you mention are supported in the PowerPC Linux 
kernel tree for Virtex-II Pro FPGAs.

- Peter


T T wrote:

> Hi all,
>  
> I would like to port linux kernel to a custom board that contains 
> xc2vp4 (xilinx fpga) which it include powerpc 405 hard core, uartlite, 
> spi controller, sdram controller.  I don't how to start because I am 
> new to linux os.  Any help is welcome.
>  
> Thanks.
>
> __
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> Tired of spam? Yahoo! Mail has the best spam protection around
> http://mail.yahoo.com
>
>
>
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ML300 and Linux

[Peter Ryser]

Anne-Sophie,

Linux is fully ported for the ML300 board and the work has been 
integrated into the 2.4 linuxppc kernel tree by MontaVista. A few links 
that might you get started:
Free MontaVista Linux Preview Kit for ML300: 
http://www.mvista.com/previewkit
ML300 home page: http://www.xilinx.com/ml300
Linux site for PowerPC: http://www.penguinppc.org

- Peter


Harnois Anne-Sophie wrote:

>I am working on a new board which is based on a Virtex II Pro. I would like to 
>study the code for the ML300 which is the evaluation board from xilinx but I 
>can't find any port for this board. Could you help me? What version of Linux 
>should I use?
>Thanks a lot.
>Anne-Sophie.
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>
>  
>

uboot and ppc405

[Peter Ryser]

>I have every confidence that it works on the ML300, just not on other
>boards, including both the Memec board and our in house prototypes.
>
My web and mail server runs on a Memec board. I've seen our and customer 
boards up and running for extended periods of time without any problems 
with regard to System ACE CF.

>>There is now a MVL preview kit for the Memec board. You might want to
>>try it out and see whether the problems you observe persist.
>>
>>
>
>Is this the one which doesn't actually use the SystemACE for a filesystem?
>
System ACE CF can be turned on in the kernel configuration. Making a 
root filesystem on the CF or MD is straight forward.

>>Looking at the postings back in April I can only say that I never saw
>>any similar problems.
>>
>>
>
>Others have done so. I'll check with the hardware guys and see if I
>can't send you a simple hardware case that falls over at some point -
>I'm slightly constrained to release hardware designs and so on until
>after this thing is ready to ship.
>
Ok, that's a plan. When you are ready please file a web case and mention 
my name so that the problem resolution gets tracked properly.

- Peter

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uboot and ppc405

[Peter Ryser]

>This appnote assumes that he's using the ML300, has the Montavista
>tree, and a few other general assumptions that might well not be true
>here, but is otherwise interesting if they decide to heed our
>suggestions of using the SystemACE in the design.
>
The app note concentrates on one example, however, it is generic enough 
and applies to different setups. The MontaVista Linux preview kit for 
the ML300 is free but you can use other distributions if you wish to do 
so. The only thing you need for u-boot is the PowerPC cross-compiler. 
You can use the cross-compiler that ships with EDK, however, I do not 
recommend it as it is set up for a different environment than for Linux 
and/or U-Boot and it will expect files like boot.o and libxil.a...

Other boards than the ML300 can be used, too. If you look at the 
repository layout in U-Boot there is space for other boards than the 
ML300. I'm sure Wolfgang will appreciate contributions and ports to 
different boards.

>btw Peter, I've been moaning about the weird interrupt behaviour of
>the SysACE on e.g. the Memec board for some time (see archives for
>various other people's experiences too) - and I've spoken to several
>folks at Xilinx without getting very far. If there's a fundamental
>problem then it probably makes sense for us to help get it fixed.
>
Hmm, I'm not aware of any interrupt problems with System ACE CF. For 
Linux it works for a long time unchanged as published in the 
linuxppc_2_4_devel and linuxppc-2.4 repositories. I'm operating my own 
web and mail server on a V2P based board using a 1GB MicroDrive through 
System ACE CF as the root and swap filesystems. The system is up and 
running for months now. No special tricks or hacks just a 
straight-forward EDK FPGA design with a MVL kernel.

There is now a MVL preview kit for the Memec board. You might want to 
try it out and see whether the problems you observe persist.

Looking at the postings back in April I can only say that I never saw 
any similar problems. Please let me know if you have a specific test 
case where you see problems and I'll be glad to look at it.

The implementation of System ACE CF functionality in U-Boot is written 
for polled operation. In that case Stephen Williams wrote the actual 
driver and we decided not to publish our own driver but reuse his.

- Peter

uboot and ppc405

[Peter Ryser]

Hi,

please have a look at "Getting started with U-Boot and ML300" 
http://www.xilinx.com/bvdocs/appnotes/xapp542.pdf that describes how to 
use U-Boot with Xilinx Virtex-II Pro devices.

You might also want to have a look at the README.ml300 in the u-boot 
source tree that provides a quick start.

- Peter


grave wrote:

> Hi,
>
> We re starting a disign with xilinx chip Virtex II pro and I wonder 
> the  typical size of an uboot binary. This is for our electronician 
> disigner  in order to dimension the prom and so on...
>
> Any hint welcome,
>
> Thanks in advance, xavier grave
>
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How to port ppc-linux to new custom boards? (virtexII)

[Peter Ryser]

>this means that i also have to port u-boot
>
U-Boot supports the ML300 board, again, with MLD technology (i.e. an
automatic way to setup address maps and number of peripherals directly
out of the EDK project). Read the README for the ML300 board in the
u-boot documentation directory for more information.

- Peter


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How to port ppc-linux to new custom boards? (virtexII)

[Peter Ryser]

You might want to have a look at
http://direct.xilinx.com/bvdocs/appnotes/xapp765.pdf
It explains on how to get started with Xilinx EDK and MontaVista Linux
Preview Kit on the ML300 board. The steps are pretty much the same for a
custom board.

- Peter


Patrick Huesmann wrote:

>Hi,
>
>I'm trying to port Linux to a custom board built around a virtexII-fpga
>which features a PPC-405 cpu.
>
>I've downloaded the Montavista 2_4_devel tree, which already has some
>platform and driver support for the ml300 eval board, and made a few changes
>to the xilinx specific header files to reflect our FPGA design.
>Then I changed the tophys macro in include/asm/ppc_asm.h to have a sensible
>initial mmu.
>#define MY_PHYS_RAM 0x9000
>#define tophys(rd,rs) addisrd,rs,(MY_PHYS_RAM-KERNELBASE)@h;
>#define tovirt(rd,rs) addisrd,rs,(KERNELBASE-MY_PHYS_RAM)@h;
>
>My kernel gets past the initial mmu setup, enters the C code and freezes in
>the middle of early_init in arch/ppc/kernel/setup.c when (after?) memset_io
>is called to zero the BSS region.
>
>I've some experience with porting ARM-Linux but, unfortunately, the PPC port
>seems to be significantly different (there are no mach-types and ATAG lists,
>for example).
>
>1) Is there any comprehensive documentation / tutorial on how to port the
>ppc-linux to new machines? Where does my board specific fixup stuff go (for
>example, memory and IRQ declarations and such).
>
>2) What requirements and responsibilities are imposed on the bootloader? I
>suspect that I can't use u-boot or something like that, because we have our
>own "company-specific" bootloader so that all our products use the same
>protocol for firmware updates.
>
>3) Is there a way to get a self-decompressing kernel image? ARM linux
>provides a zImage which the cpu just has to jump into (with some registers
>initialized) and then decompresses vmlinux by itself. Now I have to use a
>vmlinux file and write it to flash directly, because zImage on powerpc lacks
>decompressor code (at least with my configuration). But the 1.3meg vmlinux
>file makes for pretty long turnaround times (I can only upload at 115k at
>the moment).
>
>Any help is greatly appreciated ;)
>
>Regards,
>Patrick
>
>
>
>
>
>
>
>
>
>
>
>


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EDK 6.2 genace.tcl problem (solaris)

[Peter Ryser]

Currently, ACE file generation under Solaris is not supported. Please
use a Linux machine or a Windows machine to generate the ACE file.

- Peter


Andreas Weder wrote:

>I'm trying to build a ace file to boot linux on a ml300-board. I have
>the system.bit and the linux kernel  zImage.embedded.
>
>Documentation told me to do this:
>xmd genace.tcl -hw implementation/system.bit -elf zImage.embedded -board
>ml300 -ace out.ace
>
>This doesn't work. Genace.tcl aborted with the message  that it can't generate
>the svf-file for the kernel. (Doesn't work for smaller files like
>hello_gpio.elf ...)
>Problem is the xconnect command in genace.tcl. It does nothing (I don't
>get any return value) and generation fails. I tried to exchange
>xconnect with the (new?) ppcconnect command --> same result.
>Why do I have to use xconnect/ppcconnect to generate a svf file from elf
>file?
>Does the ML300 Board have to be connected to the computer I use to execute
>genace.tcl? (Not possible in my case ...)
>
>Board: ML300
>OS: solaris 2.8
>EDK: 6.2
>PPC-Kernel: 2.4.18
>
>cu
>Andreas Weder
>
>
>
>
>


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PCI - i *thought* the edk2 was what I was using!

[Peter Ryser]

Mike,

the ml300_edk2.zip design does not have PCI at all. Only the
ml300_edk3.zip, i.e. the design to which the link currently points has
the pcore that works with Linux.

- Peter


Mike Wellington wrote:

> Peter - I thought that the edk2 example from the link
> you gave me was the pcore I was using.  I will start
> over from scratch and try again.
>
> My machine is busy doing some big  downloads/backups
> so it will be tonite/tomorrow before I can verify
> and report back.
>
>
>
>
>
> Peter Ryser wrote:
>
>> The PCI support that is currently included in the Linux kernel tree
>> is for the V2PDK based OPB -> PCI bridge. It will not work with the
>> EDK based OPB -> PCI bridge, i.e. you will find exactly what you see.
>>
>> Please download the EDK reference design for ML300 from
>> http://www.xilinx.com/ise/embedded/edk_examples.htm (design #6). The
>> design contains the V2PDK based bridge (including the pcore therefor)
>> and, thus, the Linux kernel will work fine with that design.
>>
>> We are currently working on moving to the EDK based bridge and the
>> Linux kernel tree will be patched once this work is completed.
>>
>> - Peter
>>
>>
>


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ppc4xx_find_bridges( ) hangs kernel on Xilinx ML300 (PCI)

[Peter Ryser]

The PCI support that is currently included in the Linux kernel tree is
for the V2PDK based OPB -> PCI bridge. It will not work with the EDK
based OPB -> PCI bridge, i.e. you will find exactly what you see.

Please download the EDK reference design for ML300 from
http://www.xilinx.com/ise/embedded/edk_examples.htm (design #6). The
design contains the V2PDK based bridge (including the pcore therefor)
and, thus, the Linux kernel will work fine with that design.

We are currently working on moving to the EDK based bridge and the Linux
kernel tree will be patched once this work is completed.

- Peter


Mike Wellington wrote:

>
> Hi-
>   I am trying to port the Xilinx PCI code to
> an embedded linux kernel.  The code calls
> ppc4xx_find_bridges( ) during the kernel initialization
> and hangs the kernel.
>
>   I built the GPL 2.4 kernel from the Open Source
> archives and it hangs also.
>
>   Then I copied ppc405_pci.c from the GPL source
> to my kernel tree and copied  head_4xx.S from the
> GPL source to my kernel tree and it still
> hangs.
>
>   I'm starting to wonder if there is something
> wrong with the PCI support for the Xilinx OCP PCI
> core.
>
>   Does anybody have a working PCI device on a
> Xilinx Virtex-II Pro using the Xilinx-supplied
> PCI core?
>
> -mike wellington
>  wellington at lucent.com
>  anyplatform at bithead.com
>
>
>
>


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Xilinx ML300 u-boot question

[Peter Ryser]

Mike,

for TFTP boot normally the HW MAC address of the target device is used
for identification. On the ML300 the HW MAC address is stored inside the
IIC EEPROM. Since accessing this EEPROM is not yet supported in the
pusblished U-Boot port for ML300 the MAC address is hardcoded in
board/xilinx/xilinx_enet/emac_adapter.c.

So, to get a machine specific u-boot for every board change the MAC
address and recompile. I'm not sure that you would need the secondary
u-boot then as you could then directly load the Linux kernel in the
second step.

- Peter


Mike Wellington wrote:

>
> Does anybody know what parameters I should use to
> load u-boot, using u-boot.That's right, I want to
> build a generic u-boot that goes on the Microdrive of
> a Xilinx ML300 development board.  I have several of them
> to manage.  I want the generic u-boot to go and download
> a machine-specific u-boot that I can change on my workstation
> without having to write it to the microdrive.
>
> Or can I just have u-boot start the kernel with no parameters
> and have all the initial args for the kernel built into the
> kernel?
>
> -mike wellington
>  wellington at lucent.com
>
>
>
>


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Xilinx PLB UART

[Peter Ryser]

We are not aware of any issues with the PLB Uart. As a matter of fact,
since your posting I tried the PLB Uart both in 16450 as well as in
16550A mode on the ML300 and both ways the Linux kernel booted fine and
showed normal behavior when accessed through the serial console. For
this test I've used the kernel shipping with MontaVista Linux 3.0
(2.4.18) and used the MLD technology of EDK to generate the proper BSP
for Linux.

Send me private mail if you want to have a copy of the EDK project with
the PLB Uart.

Some things to look for in your project:
- make sure the address map of the PLB Uart does not overlap with the
address region of the PLB2OPB bridge.
- use recent tools and the most recent cores available (e.g. EDK 6.1.2
and PLB Uart v1_00_c).
- use the MLD technology in EDK to generate a BSP for your Linux kernel.
With that you will automatically avoid problems with interrupt mapping
and similar things.
- for all new designs use EDK (vs V2PDK).
- start with the EDK reference design for ML300 available from
http://www.xilinx.com/ise/embedded/edk_examples.htm (design # 6). You
can modify this design to match your board.

Cheers,
- Peter


Shamile Khan wrote:

>Hi,
>
>This question concerns Xilinx Virtex II Pro platform. We
>have been using OPB UART for Linux. We just tried to switch
>from OPB UART to PLB UART. We have interrupts enabled. So
>the kernel boots till
>
>Freeing unused kernel memory: 40k init
>
>At this point, I dont see anything on the screen. I dont
>even see the slow display of characters on the screen
>implying that the kernel has switched to polling mode. I
>didnt change anything for the kernel as I expected the OPB
>UART functionality to be identical to PLB UART from
>processor's perspective. Are you aware of any issues
>concerning PLB UART for Linux?
>
>Thanks,
>Shamile
>
>
>
>


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ml300 system init very slow

[Peter Ryser]

Lou,

make sure you don't have a mismatch between
arch/ppc/platforms/xilinx_ocp/xparameters_ml300.h and your system.mhs
especially when looking at the interrupt signals and defines. If you
made changes to xparameters_ml300.h you might want to rebuild the kernel
completely:
$ make clean dep bzImage modules.

Besides that I assume that you use a recent kernel (eg. the one in
MVL3.1) and EDK (vs. V2PDK) as a development tool kit.

- Peter


Lou Rickard wrote:

>And as the kernel boots, it loads an improved serial
>module stored on the root filesystem, which works
>fine?  Would that explain why it works fine with
>module support turned on, but doesn't work well with
>module support turned off (and hence stuck using the
>serial module that is built into the kernel)?
>
>~lr
>
>--- "VanBaren, Gerald (AGRE)"
> wrote:
>
>
>>Just in case nobody answered yet (I didn't see an
>>answer), the problem 99.% certainty is that your
>>serial interrupts are not interrupting so the kernel
>>is polling for serial I/O.  This is a fallback
>>operation with REALLY LONG timeouts.  The symptoms
>>are REALLY SLOW console interaction == your
>>symptoms.  Your follow-up message indicates the
>>problem is in your serial driver module.
>>
>>gvb
>>
>>
>
>
>
>
>
>


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Xilinx ML300 PCI

[Peter Ryser]

Shamile,

current kernels support the PCI core that shipped with V2PDK. The PCI
core that ships with EDK is slightly different and we are working on the
necessary software modifications to upgrade the kernel sources. ETA is
unknown.

- Peter


Shamile Khan wrote:

>Hi,
>
>Our custom board utilizes Xilinx's PCI Core inside the
>Virtex II chip. I looked at the kernel sources in
>linuxppc_2_4_devel tree and I see support for PCI. Is this
>support for Xilinx PCI core or an external PCI chip.
>
>Thanks,
>Shamile
>
>
>
>
>


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ml300 boot loader question

[Peter Ryser]

Lou,

there are two parts involved in booting a Linux system on the Virtex-II
Pro FPGA on the ML300:

1. a bitstream that programs the FPGA. The bitstream is created with the
EDK kit from scratch or based on the EDK reference design for ML300
available at
http://www.xilinx.com/ise/embedded/edk_examples.htm (design # 6)
2. a Linux kernel created

Then, there are two main methods on how to bring up Linux.

a. With Impact and a SW debugger (BDI2000)
b. With System ACE CF.

In both cases first the bitstream is loaded to program the FPGA and the
then Linux kernel is loaded through the processor into main memory.
If  you use method a) you first program the FPGA with Impact and then
use the BDI2000 to download the Linux kernel into main memory. The
BDI2000 will then also set the PC to the start address of the Linux
kernel and on your command start executing the code.

If you use method b) you use EDK to generate an ACE file for example in
an EDK shell type
xmd genace.tcl -jprog -board ml300 -hw implementation/download.bit -elf
 -ace top.ace
See the EDK documentation for more details.

Now, copy the resulting top.ace file onto the MicroDrive shipping with
ML300, for example, into xilinx/myace. Set the rotary dial that selects
which configuration is loaded by the System ACE chip to the correct
number. When you hit the System ACE reset button the System ACE CF chip
starts loading the ACE file and as part of the process loads the FPGA
bitstream, downloads the Linux kernel into main memory, and boots Linux.

- Peter


Lou Rickard wrote:

>I'm having a hard time figuring out how to boot our
>kernel/filesystem on the ml300.  I suspect it's a
>problem with the bootloader, but not 100% sure.
>
>We're able to generate a file to program the FPGA with
>that will allow us to use the BDI2000 to boot the
>system.  From trial and error, I've gotten the
>impression that the FPGA file includes a bootloader of
>some kind: when we didn't include some of the binary
>firmware with the FPGA file we couldn't even get the
>BDI2000 to boot the system.  When we started including
>the binary firmware stuff (which I don't quite
>understand yet), the system came up to a state where
>we could boot with the BDI2000.
>
>So, based on that, I'm guessing that the systemace
>chip fills the bram with some sort of bootloader
>sometime around when it programs the FPGA.
>
>However, I haven't been able to build a FPGA file that
>would actually boot to a linux filesystem on the flash
>card.  The FPGA programs, but then nothing happens
>(this is with the BDI2000 unplugged, I don't think any
>software can be run with the BDI2000 plugged in unless
>it's downloaded via the BDI2000, but I could very well
>be incorrect).
>
>I've looked at the Monta Vista partitions that came
>with the kit.  I don't see any kind of stand alone
>boot loader, so I'm guessing that they have included
>their bootloader with the FPGA file.  I don't know if
>this is a modification of the bootloading binaries
>that come with the Xilinx development kit.
>
>Could anyone clue me in?
>
>Thanks,
>
>~lr
>
>
>
>
>
>


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[Fwd: ppc4xx Ports]

[Peter Ryser]

The TLB errata for the Virtex-II Pro FPGA was not pushed out to the
source trees because there have basically no chips been shipped to
customers that will expose this problem. Newer mask sets of the
Virtex-II Pro FPGA have this problem fixed.

Solution record 14052 explains the problem, provides a work-around, has
a link to a Linux kernel patch, and lists the PVR values of chips for
which the problem might occur. Please note that even if you have a chip
with a matching PVR it is very unlikely that you will actually see the
problem.

- Peter


Jon Masters wrote:

>
>
> Peter Vandenabeele wrote:
>
> | On Thu, Nov 13, 2003 at 04:48:05PM -0800, Eugene Surovegin wrote:
> | [...]
> |
> |>I don't have any PTE/TLB related problems on 405GP/405GPr.
> |
> |
> | On the PowerPC 405 in the Virtex-II Pro, we needed to turn off
> | half of the TLB entries as per "Solution 12" on
> |
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14052
>
> |
> | "... Limit TLB depth to 32 entries by only using even entries in the
> TLB "
> |
> | Peter
> |
>
> Hi there,
>
> I think I mentioned before that I already fixed that for the port I am
> working on by incrementing next TLB entry by 2 if on Virtex II Pro.
> Actually if you check a post I made to comp.arch.fpga over the summer...
> I call it CONFIG_BROKEN_XILINX_TLB or something like that (other ports
> are now starting to fix that too) - several other errata too.
>
> [ Like I said before we have two similar ports now so once I can release
> the modifications then we should look at how this can help us. The stuff
> I am working on at the moment is not going out yet and for various
> commercial reasons I prefer not to disclose who it is for, etc. ]
>
> The problem I currently have was traced when using the dynamic linker
> library from my Powerbook Debian on my test NFS filesystem and then
> running up something compiled against the main normal libc with floating
> point register save restore context stuff. So this leads me on to...
>
> ...there is something wrong with the trapping and handling of stfd and
> similar operations on my port when the kernel tries to do the
> copy_to_user to actually change the saved floating point register set.
> Now that I know where the bug is I can fix it next week[0].
>
> Jon.
>
> [0] I work a 3 day week but take work home with me too much so tracked
> this down today when debugging in Starbucks without the hardware but
> with my Powerbook and various printouts...using 9600bps dialup proxied
> through my Zaurus wifi because no IR on Powerbook revision. ;-).
>
>
>
>


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mount root on the ml300 board

[Peter Ryser]

Make sure to enable device file system (/devfs) support during kernel
configuration.

- Peter

hyding wrote:

>hi,
>I am debugging MontaVista linux pro3.0(kernel 2.4.28) on the ml300
>board. I use IBM MicroDrive 1GB card to configure the FPGA and act as
>root fs. But the boot stops and displays the following:
>...
>block: 128 slots per queue, batch=32
>Partition check:
> xsysacea: xsysacea1 xsysacea2 xsysacea3
>System ACE at 0xCF00 mapped to 0xC900F000, irq=9, 1052352KB
>Kernel panic: I have no root and I want to scream
> <0>Rebooting in 180 seconds..
>There are 3 partitions in the CF card. The 1st is the fat12. The 2st
>is swap and the 3rd is the root. Kernel command line: console=ttyS0,9600
>root=/dev/sysace3 rw
>Did someone have the problem? Any hints will be appreciable.
>
>Thanks!
>
>
>
>
>


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debug Montavista on ML300

[Peter Ryser]

Hi,

you have a few options to download the Linux kernel to the board
depending on your work environment:

1. If you are using V2PDK, i.e the tool set that ships with the ML300,
then use GDB to download the kernel with the P4 cable.
a) open a V2PDK shell
b) change directories to the location where your Linux kernel resides
c) start GDB, download and start the kernel
  $ powerpc-eabi-gdb -nw -nx zImage.embedded
  (gdb) target ocd xilinx
  (gdb) set download-write-size 0
  (gdb) load
  (gdb) c

2. If you are using EDK then use XMD to download the kernel with the P4
cable.
a) open a xygwin shell
b) change directories to the location where your Linux kernel resides
c) start XMD, download and start the kernel
  $ xmd
  XMD% ppcc
  XMD% dow zImage.embedded
  XMD% run

3. If you are using a 3rd party debugger follow the instructions of the
debugger manufacturer.

4. To generate an ACE file out of the bitstream and the Linux kernel
follow the instructions in the V2PDK or EDK documentation.

- Peter


hyding wrote:

>hi,
>Maybe this is not the right place to ask questions. But i wish
>someone in this list will give me some help. Any hint will be
>appreciable.
>
>I am doing some work on ML300. After i generate the configuration
>file(top.bit), i don't know how to download the OS image to DDR SDRAM.
>Can i use the Parallel Cabel IV to download the OS image to DDR SDRAM?
>>From some docs, i see the method to combine the configuration .bit file
>and OS image into a .ace file. Put the .ace into the CF card, the FPGA
>will be configured with this .ace after power. But how to make the .ace
>file including the .bit file and OS?
>
>Thanks!
>
>---
>ding hou yong
>Nanjing Electrical Automation Institute
>Tel: 86-25-3429900-2425
>GSM: 86-(0)13814021009
>FAX: 86-25-3429900-2425
>Email: nari_dhy at nari-china.com
>Http: www.nari-china.com
>---
>
>
>
>
>


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Linux on the Virtex II Pro?

[Peter Ryser]

> Current Linux/PPC trees already
> include support for 405 as well as the Xilinx ML300 board.
> (The Linux/PPC tree I got had slightly stale libgen'ed
> code, which I simply replaced with current libgen'ed code
> from my XPS project.)  I can send you a patch file on request.

At the beginning of July the linuxppc_2_4_devel tree has been updated with the
drivers shipping with EDK 3.2 SP2. Further, all necessary changes have been
pushed to move from V2PDK to EDK (interrupt controller bit ordering, System ACE
byte/word addressing, etc.).

Unfortunately, the on-going changes to the OCP implementation (not Virtex-II
Pro related) break the kernel compilation for ML300.

- Peter



http://www.xilinx.com/ml300
http://www.xilinx.com/edk


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GPL inconsistency in arch/ppc/ocp/xlinx/

[Peter Ryser]

I'm working with our legal departement on straightening the licensing issues
out. Our intention is to distribute the source code under GPL. Most likely, we
will remove

* Xilinx products are not intended for use in life support
* appliances, devices, or systems. Use in such applications are
* expressly prohibited.

without replacement.

- Peter


Tom Rini wrote:

> On Thu, Jun 12, 2003 at 10:32:05PM +0200, Christoph Hellwig wrote:
> >
> > On Sat, May 24, 2003 at 10:12:13PM +0200, Christoph Hellwig wrote:
> > >
> > > you seem to have added the the directory in the topic to the
> > > LinuxPPC trees. Unfortunately they have a license consitency that
> > > basically makes them illegal to distribute, they claim to be under
> > > GPL but have the following notice:
> > >
> > > * Xilinx products are not intended for use in life support
> > > * appliances, devices, or systems. Use in such applications are
> > > * expressly prohibited.
> > >
> > > Could you please contact Xilinc to clarify the license and/or remove
> > > those files from the tree? Thanks.
> >
> > As there hasn't been any answer yet I think these files should be
> > remove to ensure the linuxppc tree is legally distributable.
>
> I think you should ask someone responsible first.  And on the correct
> mailing list as well.  Armin is not responsible for this code, Scott
> Anderson is.  Armin just put it into the linuxppc-2.5 tree.  Second,
> Peter Ryser (who handles the Xilinx side of things) is on the
> linuxppc-embedded list, where most of the 4xx people are.  Finally,
> Peter knows about this, and last I knew was talking to their legal
> department.  Peter, any news on this?
>
> --
> Tom Rini
> http://gate.crashing.org/~trini/
>


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bootstrap of virtex-ii pro eval board ML300

[Peter Ryser]

System ACE CF.

- Peter


NARI_DHY wrote:

> > As Scott describes correctly the preferred method of booting ML300 is 
> > through
> > System ACE CF. System ACE CF reads ACE files and programs the FPGA and the
> > PowerPC processor through the JTAG chain.
> System ACE CF reads one of the .ace files (at most 8) from the first 
> partition of FAT16/FAT12 fs.
>
> > On power-up or reset System ACE CF reads the ACE file from the MicroDrive or
> > CompactFlash card and in a first step programs the FPGA. Then, in a second
> > step, from the same ACE file, it programs the processor, i.e. similar to an
> > external debugger it loads code and data contained in the ELF file into the
> > processor memories, sets the PC to the start address, and starts executing 
> > the
> > program.
> >
> what is this "it"? Is it System ACE CF or other small executive edited by 
> developper?
>
> -hyding
>
> best regards
>


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bootstrap of virtex-ii pro eval board ML300

[Peter Ryser]

As Scott describes correctly the preferred method of booting ML300 is through
System ACE CF. System ACE CF reads ACE files and programs the FPGA and the
PowerPC processor through the JTAG chain.

The ACE file is a concatenation of zero or one bitstream with zero to n ELF
files. Typically, it is one bitstream and one ELF file.
On power-up or reset System ACE CF reads the ACE file from the MicroDrive or
CompactFlash card and in a first step programs the FPGA. Then, in a second
step, from the same ACE file, it programs the processor, i.e. similar to an
external debugger it loads code and data contained in the ELF file into the
processor memories, sets the PC to the start address, and starts executing the
program.

For Linux, you will use the Linux kernel as the ELF file.

You can generate ACE files easily by using EDK by running the command
$ xmd genace.tcl implementation/system.bit arch/ppc/boot/images/zImage.embedded
top.ace
in your hardware project directory.

- Peter

-
Some useful links:
System ACE CF: (http://www.xilinx.com/isp/systemace/systemacecf.htm
EDK: http://www.xilinx.com/edk
ML300: http://www.xilinx.com/ml300


Scott Anderson wrote:

> On Monday, June 2, 2003, at 01:48  PM, Kerl, John wrote:
> > You're saying that the entire zvmlinux.initrd file
> > (2-3 MB, say) is contained in the FPGA bitstream??
>
> I am saying that the entire zImage.embedded (without
> an initrd) is in the FPGA bitstream.  Its root partition
> is an ext2 partition on the IBM MicroDrive.
>
>Scott
>


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Virtex II Pro eval Boards

[Peter Ryser]

Bob,

V2PDK contains all necessary files for a PCI host configuration and the
example design for ML300 uses it. The design as well as the PCI host
bridge are documented in V2PDK.

- Peter


bob piatek wrote:

> Glad to hear that the OPB-PCI bridge supports host configurations!
>
> The documentation needs updating.
>
> Bob
>
> fishcamp engineering
> 105 W. Clark Ave.
> Orcutt, CA  93455
>
> http://www.fishcamp.com
> TEL: 805-937-6365
> FAX: 805-937-6252
>
> On Friday, May 16, 2003, at 05:22 PM, Peter Ryser wrote:
>
> >
> >> Xilinx has a OPB to PCI bridge that supports their PCI core but it
> >> doesn't (yet) support host applications.
> >
> > Yes, it does. Many PCI, PCMCIA, and PC cards work.
> >
> > - Peter
> >
> >
> >
> >
> >


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Virtex II Pro eval Boards

[Peter Ryser]

> Xilinx has a OPB to PCI bridge that supports their PCI core but it
> doesn't (yet) support host applications.

Yes, it does. Many PCI, PCMCIA, and PC cards work.

- Peter


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Virtex II Pro eval Boards

[Peter Ryser]

Emanuel,

Xilinx sells the ML300 board, see http://www.xilinx.com/ml300. The board has a
PMC slot, two PC Card slots and FireWire (behind a PCI bridge). All peripherals

(including the PCI host bridge) are compiled into the FPGA.
MontaVista Linux 3.0 supports the ML300 including PCI, see
http://www.mvista.com/partners/semiconductor/xilinx.html

Our distributors also sell Virtex-II Pro based boards. AFAIK, none of them have

PCI.

- Peter

emanuel stiebler wrote:

> Hi,
> I remember few people out here talking about the VirtexIIPro. What Eval
> Boards did you use ? Experiences ?
>
> Anybody used the VirtexIIPro with a PCI-Bridge ?
>
> cheers & thanks in advance
>


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advice please: virtex pro 2

[Peter Ryser]

James,

> 1.) Is it just as "easy" as an MPC860 or MPC8260 based platform ?

Once you have a board with a bitstream for the FPGA (for example ML300 as it
ships) the development environment on Virtex-II Pro doesn't look different for
a SW person than on any other microprocessor based board.

Building the board itself is the same amount of work as for other chips.

Building the bitstream for the FPGA definitely is an additional step. However,
the EDK web page has some example designs that get you started in a short
amount of time.

> 2.) Is there any big caveats I should now about for debugging bring up?

If you keep the design close to the ML300 design (schematics available) you
will be able to use the Linux kernel for ML300 and by just configuring the
kernel bring the board up in a short amount of time.

> 3.) Does anybody know about vxworks 'support' for this as well?

Not the appropriate list - I know - but VxWorks support exists as well.

> 4.) Is debugging support with BDI, vision ICE, etc there yet for this
> board? Is it just good old JTAG or something different?

Yes, it is standard JTAG. So far, any external debuggers I've used that claim
support for 405GP have worked out of the box on Virtex-II Pro (BDI2000,
RiscWatch, VisionProbe, VisionICE, Lauterbach, ...).

> 5.) Is this chip even mature yet?

It's in production. We have Virtex-II Pro based systems here at Xilinx that run
(uptime) Linux under load (web server, streaming MP3, etc.) for more than sixty
days.

- Peter

--
PS: some links for things mentioned in the text
- ML300: http://www.xilinx.com/ml300
- EDK: http://www.xilinx.com/edk
- Linux on Virtex-II Pro:
http://www.mvista.com/partners/semiconductor/xilinx.html


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Low memory on Virtex-II Pro

[Peter Ryser]

John,

please correct me if I see this wrong but it looks like you are mixing up
MicroBlaze and PowerPC. The LMB is a bus that is only available on MicroBlaze.
Linux does not have support for MicroBlaze.

However, Linux works great on the PowerPC inside the Virtex-II Pro FPGA when
you map the main memory at address zero. When using EDK to build your system
just set the BASEADDR for the SDRAM to zero.

You might also want to be aware of the fact that the interrupt controller that
ships with EDK is different from the interrupt controller that ships with the
Xilinx ML300 board. If you build your system with EDK you will have to adapt
arch/ppc/kernel/xilinx_pic.c.

Regards,
- Peter


"Kerl, John" wrote:

> Hello all,
>
> There have been some recent posts about Linux & Virtex-II Pro
> (FPGA with PPC405 hard core).  & apparently people have it working.
>
> One question before I start, though:
>
> Of course the kernel starts at *virtual* address 0xc000, regardless
> of the processor.  But my understanding is that certain processors have
> zero-based *physical* addresses for RAM, and some don't -- x86 of course
> being an example of the former, and ARM being an example of the latter.
> I believe that PPC is an example of the former.  Certainly our MPC857T
> board, and all the other boards of which I'm aware, have RAM starting at
> physical address 0x.
>
> Now, on our custom Virtex-II Pro board, with Xilinx EDK setup, there's a
> bit (the MSB) in the physical address that specifies whether a memory
> region is on the LMB bus or OPB bus.  We get to pick *which* bit, but
> there must be *a* bit set for the SDRAM.  The upshot is that our SDRAM
> starts at physical address 0xb000.  It can't be placed at address 0.
> And block RAM could be made low, but I can't see having megabytes of
> block RAM.
>
> So, I think I have to have the kernel at non-zero physical address
> with PPC405.
>
> Can anyone advise on success or failure of doing so?
>


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Virtex II Pro FPGA and Linux

[Peter Ryser]

Xilinx is and has been working very closely with MontaVista to port Linux to
Virtex-II Pro. The following peripherals are implemented and are available today
in the linuxppc_2_4_devel tree:
- Uart 16450/16550
- IIC
- TFT LCD display
- touchscreen
- 10/100 Mbit Ethernet
- GPIO
- Sytem ACE CF controller (booting and CompactFlash card/IBM MicroDrive access)
- PS/2 for mouse and keyboard

Please note that all these peripherals are implemented in soft logic as part of
the FPGA. PCI will be available in the next few weeks.
We have booted Linux on various boards: ML300, AFX Virtex-II Pro cards, and the
Insight 2VP4/7 boards. The ML300 with its TFT display also runs X11.

ppcboot has been ported before to Virtex-II Pro. The port was pretty straight
forward but has never been published. We are currently looking into whether it
makes sense to integrate support for the ML300 board into "The U-Boot".
For booting Virtex-II Pro based boards my favourite boot method is with System
ACE CF. That's a companion chip that configures FPGA(s), boots the software
(Linux kernel), and later on allows you to use the attached CompactFlash
card/MicroDrive as the root file system.

More infos is available from the locations below.

- Peter, Xilinx Systems Engineering

Some links:

Boards
-
- ML300 board: http://www.xilinx.com/ml300
- AFX boards:
http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?iLanguageID=1&iCountryID=1&title=protoboards_protoboards_page#Virtex2ProPrototype

Press Releases, Publications and Talks

- Press release: MontaVista Linux on ML300 (16 Dec):
http://www.xilinx.com/prs_rls/silicon_vir/02184ml300.htm
- Press release: MontaVista and Xilinx (7 Jul):
http://www.xilinx.com/prs_rls/partners/02103monte_vista.htm
- Linux Journal: Embedded System a la Carte (1 Aug):
http://www.linuxdevices.com/articles/AT4160697622.html
- SVLUG: Linux on Programmable Hardware (2 Oct):
http://www.svlug.org/prev/2002/Linux_on_programmable_hw.ppt (22MB!)

Other
---
- System ACE CF: http://www.xilinx.com/isp/systemace/systemacecf.htm
- MontaVista: http://www.mvista.com



Rudolf Ladyzhenskii wrote:

> Hi, all
>
> Did anyone tried to port ppcboot and/or Linux to those chips? (they containg
> up to 4 PPC cores).
>
> Also any links regarding Linux and those FPGAs are appreciated. I am looking
> on including one of those in the new design and want to hear opinions.
>
> Thanks,
>
> //
> Rudolf Ladyzhenskii
> Senior Design Engineer
> SDR Communications Technologies
> ph.  +61 3 8080 8215
> fax. +61 3 9672 8800
> Level 9, 341 Queen Street,
> Melbourne, 3000
> Australia
> e-mail: rudolf.ladyzhenskii at sdrct.com
> /***/
>


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Target CPU selection for Real time Embedded Linux

[Peter Ryser]

> - Xilinx Virtex II Pro with Linux (Linux port posted 2 months ago and on 
> ftp.mind.be)

The Xilinx Virtex-II Pro FPGA is supported and developed as part of the
linuxppc_2_4_devel tree. The drivers for the various peripherals are 
implemented by
Xilinx. Integration work into the Linux kernel is done and support is available 
from
MontaVista.

- Peter



FYI:
Virtex-II Pro:
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Virtex-II+Pro+FPGAs
Linux running on the Virtex-II Pro based ML300 board: 
http://www.xilinx.com/ml300


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[PATCH] Xilinx TFT interface driver

[Peter Ryser]

Peter,

all the devices for which you posted patches are supported in the
linuxppc_2_4_devel tree for more than a month. The tree contains device
drivers/support for the following Xilinx devices

- Interrupt Controller
- 10/100 Mbit Ethernet
- PS2 port (mouse/keyboard)
- Uart (actually, the standare Linux Uart driver)
- TFT
- GPIO
- IIC

More drivers will be added soon.

- Peter


Peter 'p2' De Schrijver wrote:

> Hi,
>
> Attached you will find a patch implementing a Linux framebuffer driver
> for the Xilinx TFT interface. It was tested on a Xilinx Virtex2Pro
> implementation.
>
> Comments welcome,
>
> Peter.
>
>   
>
>xtft-patchName: xtft-patch
>  Type: Plain Text (text/plain)


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Virtex II Pro/405GP

[Peter Ryser]

> I was just curious if you had to use any esoteric patches on the (v2.5
> I'm assuming) kernel?

There are some patches. They are not esoteric and not publicly available at this
time :-(

>  Also, did you have to worry about using a full
> featured boot loader like ppcboot?

No, just use an external debugger to load the kernel into memory or use external
ROM or use the internal BRAM or System ACE (my favorite).
We are working on PPCBoot if you really need a full-blown boot loader.

- Peter


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Virtex II Pro/405GP

[Peter Ryser]

Bob,


> 1) What sort of boot-loader did you use?

So far we did not use a boot-loader. We boot the system in one of the following
ways:
- for development by using an external debugger. In our case this is GDB. We
know that other external debuggers that support the PPC405 work, too (see
below).
- for production
- we include a minimal boot stub in the FPGA bitstream. This initial boot
stub then boots the rest of the system
- we load the program into flash
- we use System ACE. System ACE is a companion chip that reads both
bitstream and program from a CompactFlash or MicroDrive, configures the FPGA,
loads the program into memory and boots the system. System ACE acts then as an
interface to the file system on the CompactFlash/MicroDrive.
- we are working on PPCBoot


> 2) Will the GDB debugger work with the Multilinx cable or 3rd party
> emulators like the Abatron BDI-2000.

GDB currently works with the Parallel-3 and Parallel-4 cable. Multilinx is not
supported and will never be (performance). Additional external debuggers may be
added as backends for GDB.

3rd party debuggers that we know to be working are (not an exclusive list)
- VisionProbe-II from Wind River
- VisionICE from Wind River
- Abatron BDI-2000



> 3) Is Xilinx going to make the work of porting Linux to the platform
> available to the general community?

Yes.

>  Maybe you could put the source on
> your web site or sell a Linux version of the developer's kit.

Watch out for announcements.

> 4) Will Xilinx be making a reference platform or evaluation board
> available?

Yes, this work is in progress but is not yet publicly announced. You can expect
an evaluation board to be available in Q3.

> As you can see I am eager to get as much info as possible on this.  I
> have a project that I am currently working on that this would be perfect
> for.  Any info you can point me to would be helpfull.

We are willing to give as much info as we can. But, since some of this has not
been announced yet I cannot go into all the details. Please also consider
getting into contact with your closest Xilinx representative or FAE to get more
information and to tell them about your projects.

- Peter


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Virtex II Pro/405GP

[Peter Ryser]

James,

I do have some experience with this chip :-)

As you said the Virtex-II Pro FPGA from Xilinx is a chip consisting of
programmable logic, embedded PPC405 core(s) and integrated multi-gigabit
transceivers. The smallest chip (2VP2) has zero CPUs and four 3.125 Gbit IOs.
The biggest chip (2VP50) has four CPUs and sixteen 3.125 Gbit IOs. The CPU is a
PPC405 core, it is not a 405GP. The user selects the peripherals he wants to
have and synthesizes them into the FPGA fabric. This results in a very flexible
solution that allows for a wide range of system design.

The developer's kit comes - besides HW IP and HW/SW design examples - with GNU
tools. These are cross-development tools for Windows and Solaris and consist of
GCC, binutils, GDB and newlib (with backend to the Parallel-3/Parallel-4 cable
attached to the BDM port/JTAG port for non-intrusive software debugging). The
kit also has simple device drivers and stand-alone/demo applications. The kit
does currently not have any direct support for any OS.

Internally, we tested the latest Linux development kernel and found that it
works just fine on our FPGA (2VP7FF672, one CPU, eight 3.125 Gbit IOs).

Regards,
- Peter


PS: For more information about the
- Virtex-II Pro FPGA:  http://www.xilinx.com/virtex2pro/
- developer's kit:  http://www.xilinx.com/ise/vii_pro/kit.htm


James Campbell wrote:

> Hello,
>
> Does anyone have any experiance with the new Xilinx Virtex II Pro chip?
> It is a million+ gate FPGA device with embedded 405GP cores on the die.
>
> We've recently consolidated our MPC8260 and Virtex II fpgas into this
> single chip, and I'm curious about getting linux up on it.
>
> I know the dev kit comes with GNU software, but I was just curious if
> anyone had any comments on it (good or otherwise).
>
> Cheers,
>
> James Campbell
>
> --
> James Campbell  -|-   Embedded Systems Engineer
> jcampbell at omnigon.com   -|- Omnigon International
> pgp:  DA57 E174 4769 1B9D D0DF 73E6 D639 D867 A576 A5AE
> work: +1.760.804.8884 x 332   cell: +1.760.803.8476
> --
> "Computer games don't affect kids; I mean if Pac-Man
> affected us as kids, we'd all be running around darkened
> rooms, munching magic pills and listening to repetitive
> electronic music."
>  -Kristian Wilson, Nintendo, Inc. 1989
>


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Hello World and 405GP with my gcc cross compiling.

[Peter Ryser]

Try the following:

${prefix}/bin/${target}-gcc -g -c hello.c
${prefix}/bin/${target}-ld -o hello ${prefix}/${target}/lib/crt0.o hello.o -lc
-lg

- Peter


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