Re: [time-nuts] Frequency divider design critique request
[Context is filtering on inputs from switches.] Could somebody tell me why we are doing anything fancy at all? What's wrong with just a simple pullup? I can think of two cases that might be interesting. One is signal integrity. There might be enough crosstalk to cause troubles. This is a 4 layer board. Right? Unless the traces from the switch to the mux chip wrap around some high speed signal there isn't likely to be a problem. I'm not a signal integrity wizard, but the ballpark is that you only need a few trace widths of separation between agressor/source and victim/receiver. This case is slightly ugly since the pullup is not low impedance like a typical driver. So the question becomes how small a pullup do we need to maintain good signal integrity? Or how far from a nearby trace do we have to be with a given pullup? If the coupling is primarily capacitive, then we have a C-R high pass filter. I'm not sure that's valid, but it is easy to analyze. I should be smart enough to work this out, but it's late. HC is pretty slow. AC might be fast enough to make things interesting. But this only matters if the switch traces run parallel to a trace that is active for a significant length. What is the (ballpark) output impedance of a CMOS driver? What's the input capacitance on a CMOS gate? (It's in parallel with the R, making a C-C divider at high frequencies.) The other possible complication is trying to keep a clean output signal when the switch changes state. I'm assuming we don't really care what happens while the contacts are bouncing between switch settings. If we do, then we need serious switch debouncing and synchronization. I don't think anybody has mentioned this tangle. All the switch inputs I've worked with recently have been a simple pullup/down. They usually go into a small CPU using the internal pullups and software debouncing. I have heard war stories of cross talk on reset signals. They often wander all over the board and since they are slow, they often get overlooked when checking for crosstalk. -- These are my opinions, not necessarily my employer's. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Hal Murray wrote: [Context is filtering on inputs from switches.] Could somebody tell me why we are doing anything fancy at all? What's wrong with just a simple pullup? Pull down required because of thumbwheel switch encoding. I can think of two cases that might be interesting. One is signal integrity. There might be enough crosstalk to cause troubles. This is a 4 layer board. Right? Unless the traces from the switch to the mux chip wrap around some high speed signal there isn't likely to be a problem. The 10MHz clock tracks have been routed well clear of everything else. I'm not a signal integrity wizard, but the ballpark is that you only need a few trace widths of separation between agressor/source and victim/receiver. This case is slightly ugly since the pullup is not low impedance like a typical driver. So the question becomes how small a pullup do we need to maintain good signal integrity? Or how far from a nearby trace do we have to be with a given pullup? If the coupling is primarily capacitive, then we have a C-R high pass filter. I'm not sure that's valid, but it is easy to analyze. I should be smart enough to work this out, but it's late. HC is pretty slow. AC might be fast enough to make things interesting. But this only matters if the switch traces run parallel to a trace that is active for a significant length. What is the (ballpark) output impedance of a CMOS driver? What's the input capacitance on a CMOS gate? (It's in parallel with the R, making a C-C divider at high frequencies.) 10-20 ohms. 5-10pF. The other possible complication is trying to keep a clean output signal when the switch changes state. I'm assuming we don't really care what happens while the contacts are bouncing between switch settings. If we do, then we need serious switch debouncing and synchronization. I don't think anybody has mentioned this tangle. RC filter followed by a Schmitt trigger IC (74HC14) can debounce the switch contacts effectively if RC product is large enough. A shift register (clocked at 1MHz in this case)is required to synchronise each mux control input if synchronisation is required. Using a shift register is slightly simpler than using a dual FF as only need to connect clock plus input and output. All the switch inputs I've worked with recently have been a simple pullup/down. They usually go into a small CPU using the internal pullups and software debouncing. No cpu available. I have heard war stories of cross talk on reset signals. They often wander all over the board and since they are slow, they often get overlooked when checking for crosstalk. Using an emitter follower to buffer the reset circuit RC node has led to VHF oscillation problems with capacitive load on emitter (track C) with collector and base at RF ground. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Magnus is on vacation and has some (net) connectivity problems. I would expect him to be back online within a day or two. -- Björn On Wed, 2008-07-16 at 18:27 +0100, David C. Partridge wrote: I'm waiting to see what Magnus Danielson has to say, as it was he after all who suggested adding caps in parallel to the pull-downs, and also series resistors. Thinking about it retrospect, I think he may have meant the series resistors to go between the pull-downs and the chip, rather than where the schematic fragment showed them. I don't *think* switch bounce is an issue here, as it will all settle to the right answer pretty sharply. Magnus, are you there? Cheers Dave ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
David C. Partridge wrote: I'm waiting to see what Magnus Danielson has to say, as it was he after all who suggested adding caps in parallel to the pull-downs, and also series resistors. Thinking about it retrospect, I think he may have meant the series resistors to go between the pull-downs and the chip, rather than where the schematic fragment showed them. I don't *think* switch bounce is an issue here, as it will all settle to the right answer pretty sharply. Magnus, are you there? Cheers Dave Dave Switch bounce could be an issue if one wished to switch cleanly to another frequency output without incurring extraneous transitions during the changeover from one frequency to another. A hex D(74HC174) or an octal D(74HC374 74HC574) could be used to synchronise debounced multiplexer select inputs. Another issue is that all BCD switch contacts will not make or break at the same time. Also the debounce filters will not all settle simultaneously. Thus a debounced enable pushbutton may also be required. When the enable pushbutton is depressed the current state of the selector switches is latched. In this case only the enable pushbutton need be debounced. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
I don't know about sending edges that slow into a CMOS chip. Is that considered kosher for HC-series logic? -- john, KE5FX -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Behalf Of David C. Partridge Sent: Tuesday, July 15, 2008 10:16 AM To: 'Discussion of precise time and frequency measurement' Subject: Re: [time-nuts] Frequency divider design critique request Magnus, Was the attached what you had in mind? Thanks Dave ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Right; when the thumbswitches are toggled, the RC integrators will slow down the edges into pins 9-11. Sometimes CMOS parts will latch up or otherwise fail to reliably with slow edges -- it probably comes down to the complementary thing, where both halves of a totem pole can turn on erratically during a slow transition. I have seen large capacitors used on TTL MUXes for EMI suppression, but never on CMOS. I have a feeling 100 pF would be safer and still adequate. Probably no big deal, but if you want to be anal about it, it could pay to check the edge-time specs for the HC family. -- john, KE5FX -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Behalf Of David C. Partridge Sent: Tuesday, July 15, 2008 11:07 AM To: 'Discussion of precise time and frequency measurement' Subject: Re: [time-nuts] Frequency divider design critique request John, This is just DC selection of which MUX line is active. Am I missing something here? Dave -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of John Miles Sent: 15 July 2008 18:30 To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Frequency divider design critique request I don't know about sending edges that slow into a CMOS chip. Is that considered kosher for HC-series logic? -- john, KE5FX -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Behalf Of David C. Partridge Sent: Tuesday, July 15, 2008 10:16 AM To: 'Discussion of precise time and frequency measurement' Subject: Re: [time-nuts] Frequency divider design critique request Magnus, Was the attached what you had in mind? Thanks Dave ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
John Miles wrote: Right; when the thumbswitches are toggled, the RC integrators will slow down the edges into pins 9-11. Sometimes CMOS parts will latch up or otherwise fail to reliably with slow edges -- it probably comes down to the complementary thing, where both halves of a totem pole can turn on erratically during a slow transition. I have seen large capacitors used on TTL MUXes for EMI suppression, but never on CMOS. I have a feeling 100 pF would be safer and still adequate. Probably no big deal, but if you want to be anal about it, it could pay to check the edge-time specs for the HC family. -- john, KE5FX Maximum recommended transition time for most HCMOS inputs is 500ns. However this is more intended to reduce the time for which both p channel and n channel devices are simultaneously conducting. When both p and n channel devices conduct the power supply current is increased (to around 1mA for HCMOS gates with a 5V power supply), however this current is to low to cause latchup. There should not be an oscillation problem with slow input transition times when using devices that don't incorporate feedback (eg gates, multiplexers). However if there is excessive noise on the a gate input near threshold it may switch on noise spikes leading to an apparent oscillation problem. For flipflops slow clock transition times may cause oscillation problems especially if the clock inputs dont incorporate an internal Schmitt trigger circuit. In synchronous systems employing multiple flipflop or divider packages the maximum clok rise time should be about 2x the individual device clock to output propagation delay to avoid incorrect operation due to clock threshold variations from device to device. If you are concerned about the transition times at the multiplexer inputs then use a 74HC14 hex inverting Schmitt trigger after the RC filters and use pullup resistors instead of pulldown resistors. Schmitt trigger devices are recommended whenever the inpu transition times exceed 500ns. The RC filter network actually attenuates the dc mux inputs by about 10%, its better to use the alternate circuit that I posted earlier that doesnt attenuate the dc levels at the multiplexer inputs. The only major concern with large capacitors connected from the multiplexer inputs to ground is that should the power supply slew rate at turn on or turn off be too large the the multiplexer input protection diode current rating will be exceeded and the protection diodes will fail. If this is likely then use a pair of external clamp diodes connected to Vcc and ground and use a connect a small resistor between the capacitor and the CMOS input. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
John Miles wrote: Right; when the thumbswitches are toggled, the RC integrators will slow down the edges into pins 9-11. Sometimes CMOS parts will latch up or otherwise fail to reliably with slow edges -- it probably comes down to the complementary thing, where both halves of a totem pole can turn on erratically during a slow transition. I have seen large capacitors used on TTL MUXes for EMI suppression, but never on CMOS. I have a feeling 100 pF would be safer and still adequate. Probably no big deal, but if you want to be anal about it, it could pay to check the edge-time specs for the HC family. -- john, KE5FX During a transition a CMOS inverter acts as an amplifier, the gain can be high with a buffered input where 2 or more inverters are cascaded. Thus any noise riding on a slowly slewing input can be amplified considerably as the input signal passes through Vcc/2 where a CMOS inverter small signal gain is maximum. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
John Miles wrote: Right; when the thumbswitches are toggled, the RC integrators will slow down the edges into pins 9-11. Sometimes CMOS parts will latch up or otherwise fail to reliably with slow edges -- it probably comes down to the complementary thing, where both halves of a totem pole can turn on erratically during a slow transition. I have seen large capacitors used on TTL MUXes for EMI suppression, but never on CMOS. I have a feeling 100 pF would be safer and still adequate. Probably no big deal, but if you want to be anal about it, it could pay to check the edge-time specs for the HC family. -- john, KE5FX What about the common RC switch debouncer using a CMOS Schmitt trigger and an RC filter? Capacitors of 100nF or more are often used in such circuits. When using Phillips HCMOS (there is an internal 100 ohm polysilicon resistor between the input pin and the protection devices.) an external diode (anode to HCMOS input cathode to Vcc) usually suffices to protect the input during turnoff. With other brands you may have to add an external 100 ohm resistor in series with the input pin. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
From: Bruce Griffiths [EMAIL PROTECTED] Subject: Re: [time-nuts] Frequency divider design critique request Date: Sat, 12 Jul 2008 12:11:03 +1200 Message-ID: [EMAIL PROTECTED] Magnus Danielson wrote: Why not? It basically solves a problem most of us has, and only a few tweaks away and it solves it fairly generically. The only think it doesn't do well is handling 5 MHz souces rather than 10 MHz. Having that would solve many problems. While not achieving full metrological levels of stability, I am sure it could be handy for several time-nuts never the less. Only a few need that upper level anyway. A good prooven design for enought stability and decent money might be right. I would certainly not mind having a pair of those lying around and I am sure I could put a few into continous use. Now that is my lab alone... Magnus A minimalist approach for the 5MHz to 10MHz doubler could use a full wave (diode, BJT or JFET) doubler followed by a series tuned 5MHz shunt trap to minimise the 5MHz content in the output. Actually, it depends on weither you would like to get a 10 MHz or not. Another solution would be to run the first divider to /5 rather than /10 and only use the doubler for the 10 MHz output. Ah well. If the doubler components were perfectly matched (unlikely) the fundamental trap could be omitted. Agreed. If the zero of the shunt trap is made low-Q the tuning of the shunt becomes almost unnecessary. Also, temperature shifts on components would not shift phase as much. The other harmonics are of little concern as the comparator output is a square wave and the rectified sinewave waveform would produce a duty cycle of around 44% at the comparator output. Unless the duty cycle is important, the overtones help to keep the slew rate high and this avoids adding too much jitter. The diode turn on threshold will alter the duty cycle somewhat but it should still be acceptable at least for clocking the flipflops and dividers. Agreed. If desired a threshold feedback loop could be used to stabilise the comparator duty cycle at 50%. Good thought. Should be a trivial thing. However such a duty cycle stabiliser only works when the input signal waveform is sinusoidal, rectified sinewave or any other signal with a slow enough slew rate. Indeed. I was only thinking that maybe there ought to be a buffer from the input to the rectifier, or else higher frequency energy will escape out towards the source. At least some isolation should be there. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Magnus Magnus A minimalist approach for the 5MHz to 10MHz doubler could use a full wave (diode, BJT or JFET) doubler followed by a series tuned 5MHz shunt trap to minimise the 5MHz content in the output. Actually, it depends on weither you would like to get a 10 MHz or not. Another solution would be to run the first divider to /5 rather than /10 and only use the doubler for the 10 MHz output. Ah well. The other harmonics are of little concern as the comparator output is a square wave and the rectified sinewave waveform would produce a duty cycle of around 44% at the comparator output. Unless the duty cycle is important, the overtones help to keep the slew rate high and this avoids adding too much jitter. Yes, its only necessary to ensure that the odd harmonics of the 5MHz input are low the even harmonics need not be removed. Good thought. Should be a trivial thing. Except that with a Schmitt trigger device in the loop the duty stabiliser will oscillate at a low frequency in the absence of an input signal. This may or may not be a problem. In fact if one uses a comparator with a totem pole output the loop is practically guaranteed to oscillate at low frequency in the absence of an input signal. One could always disable the duty cycle stabiliser unless the input signal is large enough (requires an RF detector and another comparator). However such a duty cycle stabiliser only works when the input signal waveform is sinusoidal, rectified sinewave or any other signal with a slow enough slew rate. Indeed. I was only thinking that maybe there ought to be a buffer from the input to the rectifier, or else higher frequency energy will escape out towards the source. At least some isolation should be there. For suitable designs see: http://www.ko4bb.com/~bruce/IsolationAmplifiers.html http://www.ko4bb.com/%7Ebruce/IsolationAmplifiers.html If the phase noise performance isnt too critical a low noise wideband opamp could be used. Alternatively if 30 dB or so reverse isolation is OK use an emitter follower (if the relatively high collector current required is acceptable) or better still cascade a couple for improved isolation. Cheers, Magnus Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Bruce Griffiths wrote: I was only thinking that maybe there ought to be a buffer from the input to the rectifier, or else higher frequency energy will escape out towards the source. At least some isolation should be there. If one uses a common base stage to drive the diode frequency doubler transformer primary, then the high impedance drive minimises the effect of diode thresholds and mismatches, however it is necessary to connect a resistor in parallel with the shunt inductor in the diode doubler to provide a well defined relatively low load impedance at the 10MHz output frequency. Reverse isolation of 40dB or so is possible when using a common base stage at frequencies of around 10MHz or so. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
There are usually some BNC bulkhead connectors on eBay that terminate in SMA/SMB/SMC pigtails, which are great for panel mounting. Not directly related to this design, but it made me wonder about something. If you are building a multiple output system and channel phase to channel phase was important, would pigtails like this cause problems due to different delay times because of slight variations in length? ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Bob Paddock wrote: There are usually some BNC bulkhead connectors on eBay that terminate in SMA/SMB/SMC pigtails, which are great for panel mounting. Not directly related to this design, but it made me wonder about something. If you are building a multiple output system and channel phase to channel phase was important, would pigtails like this cause problems due to different delay times because of slight variations in length? Yes, but matching cable delays to 10ps or even 1ps or better isnt too difficult. The skew between outputs due to propagation delay mismatches between ICs and PCB track propagation delay mismatches. If all flipflops are in the same package then crosstalk between outputs will phase modulate the higher output frequencies at all the lower output frequencies. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Magnus Danielson: 1) Please could you clarify what you're proposing with the series resistors? I get the idea about 10nF in parallel with R24-R26, though I'm not sure what the benefit is? Those MUX control pins are going to sit pretty hard on 5V or pulled down to ground. 2) You said: I am sure we can come up with some arrangement for that. Several handy time-nuts around. Are you suggesting that I get more than one PCB made up, or that I get 1 prototype made up and built to confirm it works mostly as I expect, and then get a batch made up for the group to play with? Obviously if there's enough interest I could get a batch made, but it's a bit of a risk if I find problems when I build the first one! Extra features - well I guess I could have added a distribution amplifier as well, but I think that's a different project. 1pps isn't needed as the TB already provides that. Synchronising with the TB 1ppS output - hey, come on, this is my first digital design project. The impossible we do immediately, unfortunately miracles take a bit longer! All, CPLD - wassat? OK, OK I have some idea, but that's about all I know. Anyway these are probably BGA stuff which I couldn't hope to hand solder anyway - it's enough of a stretch for me to think of hand soldering this SMT board. Chris Hoover, You mean you've got something that does all that and more and you've kept quiet about it! Shame on you! Or is it really only in the early stages of gestation? Cheers Dave ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
From: David C. Partridge [EMAIL PROTECTED] Subject: Re: [time-nuts] Frequency divider design critique request Date: Fri, 11 Jul 2008 18:41:52 +0100 Message-ID: [EMAIL PROTECTED] Hej David, Magnus Danielson: 1) Please could you clarify what you're proposing with the series resistors? I get the idea about 10nF in parallel with R24-R26, though I'm not sure what the benefit is? Those MUX control pins are going to sit pretty hard on 5V or pulled down to ground. OK. I was thinking EMC here. You may think that this is a DC part of the design but infact you have DC-signals hitting a board with sharp edges, so you could very well have transmitter antennas here. Also, the succeptability of those inputs to E or H field disturbance will affect the output of the mux, so attempting to reduce the efficiency as E and H field antenna should be a benefit for the stability. Bypassing the input connection from the push- button to ground with caps just where deas leads hit the board will make the E-field susceptability low, but the low loop area over to the resistors and chip will also make the H-field susceptability low. Trying to analyze such a problem would take either a good feeling about things, luck or experience to quickly pinpoint. It is cheap enought to reduce the problem, even if I don't think the risk is imminent. Do you follow my lines of thought? 2) You said: I am sure we can come up with some arrangement for that. Several handy time-nuts around. Are you suggesting that I get more than one PCB made up, or that I get 1 prototype made up and built to confirm it works mostly as I expect, and then get a batch made up for the group to play with? Obviously if there's enough interest I could get a batch made, but it's a bit of a risk if I find problems when I build the first one! Why not? It basically solves a problem most of us has, and only a few tweaks away and it solves it fairly generically. The only think it doesn't do well is handling 5 MHz souces rather than 10 MHz. Having that would solve many problems. While not achieving full metrological levels of stability, I am sure it could be handy for several time-nuts never the less. Only a few need that upper level anyway. A good prooven design for enought stability and decent money might be right. I would certainly not mind having a pair of those lying around and I am sure I could put a few into continous use. Now that is my lab alone... Extra features - well I guess I could have added a distribution amplifier as well, but I think that's a different project. 1pps isn't needed as the TB already provides that. My point was that it was an output section away The PPS was since you do produce the signal and you can the same box to divide down to PPS and say 1 kHz as being used by other designs. Think of a separate 10 MHz source... like a Rb or so. 1 kHz for the loop comparision and PPSes for performance measurements. Synchronising with the TB 1ppS output - hey, come on, this is my first digital design project. The impossible we do immediately, unfortunately miracles take a bit longer! Oh, I seem to expect alot. But really, the extra features was really thinking out loud after asking the question What would annoy me most when using such a box that I only *almost* can do?. If using counters with loadable initial state, setting it up to come out correctly at synchronisation is not that hard. All, CPLD - wassat? OK, OK I have some idea, but that's about all I know. Anyway these are probably BGA stuff which I couldn't hope to hand solder anyway - it's enough of a stretch for me to think of hand soldering this SMT board. With CPLD you don't need to do BGA. One form of FlatPACK as I recall it. Not too hard to solder. Look at the lower end from Xilinx for instance... I agree with Bruce that resynchroniserz would be expected. The TTL/CMOS you have is however more stable in availability, but so far this has not been much of a problem with CPLDs that I have tracked. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
At 10:41 AM 7/11/2008, David C. Partridge wrote: M All, CPLD - wassat? OK, OK I have some idea, but that's about all I know. Anyway these are probably BGA stuff which I couldn't hope to hand solder anyway - it's enough of a stretch for me to think of hand soldering this SMT board. CPLD - small programmable logic device (think like a PAL, but bigger).. not BGAs, typically. Anywhere from a dozen to a couple hundred gate equivalents. Some are really, really fast (e.g. 1 ns prop delays, etc.) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Jim Lux wrote: At 10:41 AM 7/11/2008, David C. Partridge wrote: M All, CPLD - wassat? OK, OK I have some idea, but that's about all I know. Anyway these are probably BGA stuff which I couldn't hope to hand solder anyway - it's enough of a stretch for me to think of hand soldering this SMT board. CPLD - small programmable logic device (think like a PAL, but bigger).. not BGAs, typically. Anywhere from a dozen to a couple hundred gate equivalents. Some are really, really fast (e.g. 1 ns prop delays, etc.) I agree that a CPLD would be an excellent way to make a 10 MHz frequency divider board. The Coolrunner series from Xilinx is available in 44 pin quad flat packs that I have no trouble soldering into place with a regular old soldering iron and some liquid flux. It's easy to solder SMT parts if you have a microscope and the right supplies. The only problem is that the CPLD is programmable. Of course, that's also its strength, until it needs to be reprogrammed and you've lost the programming cable or the source code or the Xilinx tools fail to run on your latest PC or... ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Magnus Danielson wrote: Hej David, Magnus Danielson: 1) Please could you clarify what you're proposing with the series resistors? I get the idea about 10nF in parallel with R24-R26, though I'm not sure what the benefit is? Those MUX control pins are going to sit pretty hard on 5V or pulled down to ground. OK. I was thinking EMC here. You may think that this is a DC part of the design but infact you have DC-signals hitting a board with sharp edges, so you could very well have transmitter antennas here. Also, the succeptability of those inputs to E or H field disturbance will affect the output of the mux, so attempting to reduce the efficiency as E and H field antenna should be a benefit for the stability. Bypassing the input connection from the push- button to ground with caps just where deas leads hit the board will make the E-field susceptability low, but the low loop area over to the resistors and chip will also make the H-field susceptability low. Trying to analyze such a problem would take either a good feeling about things, luck or experience to quickly pinpoint. It is cheap enought to reduce the problem, even if I don't think the risk is imminent. Do you follow my lines of thought? Hej Magnus The attached circuit should be a little easier on the relatively delicate thumbwheel switch contacts (particularly if the capacitance of the filter caps is large) whilst still providing adequate filtering. The 74HC14 is merely indicative of logic with a low dc input current. The circuit is essentially a low pass filter which rejects any high frequency pickup in the switch wiring. Typical thumbwheel switches are have either closed or open contacts. When closed the associated wiring acts as a loop antenna picking up any hf magnetic fields. When the switch is open the wire acts as a short whip antenna terminated by the pullup (or pulldown) resistor picking up any hf electric field. Bruce inline: SwitchFiltering.gif___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Magnus A minimalist approach for the 5MHz to 10MHz doubler could use a full wave (diode, BJT or JFET) doubler followed by a series tuned 5MHz shunt trap to minimise the 5MHz content in the output. If the doubler components were perfectly matched (unlikely) the fundamental trap could be omitted. The other harmonics are of little concern as the comparator output is a square wave and the rectified sinewave waveform would produce a duty cycle of around 44% at the comparator output. The diode turn on threshold will alter the duty cycle somewhat but it should still be acceptable at least for clocking the flipflops and dividers. If desired a threshold feedback loop could be used to stabilise the comparator duty cycle at 50%. However such a duty cycle stabiliser only works when the input signal waveform is sinusoidal, rectified sinewave or any other signal with a slow enough slew rate. Bruce Attached circuit schematics illustrate the simple doubler configuration I had in mind. The series tuned shunt traps eliminate Fin and its odd harmonics due to diode mismatch and transformer imbalance. In principle the series tuned shunt traps tuned to the odd harmonics of the input frequency can all be replaced by a length of open circuited 1/4 wave (at Fin) low loss transmission line. However the 50ns of delay line (required for Fin = 5MHz) takes a lot of space. The circuit driving the 74AC14 illustrates how the doubler output may be biased with a dc level of Vcc/2. In practice either a duty cycle stabilising feedback loop or a pot may be used to adjust the output duty cycle to 50%. A similar circuit can be used to drive a comparator. Bruce inline: SimpleDoublerForHighZLoad.gifinline: SimpleFrequencyDoublerDrivingSchmitt.gif___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
David Partridge wrote: CPLD - wassat? OK, OK I have some idea, but that's about all I know. Anyway these are probably BGA stuff which I couldn't hope to hand solder anyway Many CPLD's are leaded. Only the high-pin count CPLD/FPGA's are BGA. Chris Hoover, Christopher, per favor. You mean you've got something that does all that and more and you've kept quiet about it! Shame on you! Or is it really only in the early stages of gestation? We don't have a board yet, but the code works fine on the Digilent proto board and the REFLOCK II board. The latter is Altera rather than Xilinx, but the same code works on both, but you have to tweak the pin assignments naturally. As I said, I am happy to make the VHDL available. I ought to put under revision control somewhere. -ch ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
In my best HAL 9000 voice; Hi Dave. Dave, what are you doing ? Dave we need BNC connectors. Those SMB's are hard to work with. Dave, are you intending to have those SMB's stick out through a panel ? Dave ? Dave, let me suggest that you layout the connector pattern so either one can be used and stick out a panel. Dave ? Dave ? Why are you unplugging my internet feee BillWB6BNQ David C. Partridge wrote: As I've mentioned before, I've been working on the design of a frequency divider to go with my TB. The idea is 10MHz sine in from TB, output 2.5Vp-p 50% duty cycle square wave into 50R (5V into 1M), at 10Mhz, 5MHz, 1MHz and decade selectable 100kHz down to 1Hz. All rising edges synchronised to the 10MHz clock rising edge (or as near as I can get with 74AC logic). With a considerable amount of constructive criticism from Bruce Griffiths (thank you again Bruce) I believe the design now to be complete. The aim is to have as low a level of nasties as possible (i.e. fit for time-nuts). All faults are my own - no blame attaches to Bruce! I've not yet subjected this design to the ultimate simulation tool (PCB, parts and solder) yet, and I have no means to test it for levels of jitter (phase noise) or similar nasties. I think that it's now the right time to open the design up for critique from a wider audience before I commit it to copper. I'm therefore attaching the design as a PDF file for your comments. A few comments are in order: 1) The 5Mhz and 1MHz outputs are re-clocked TWICE deliberately to delay them by one clock cycle so they line up with the 1MHz and lower outputs. 2) The selected output (at the '4051 mux) from the ripple counter chain is re-clocked to 1MHz before re-clocking to 10MHz as the worst-case delay in the chain of '4017s is large enough that the lower frquencies wouldn't reliably re-clock directly to 10MHz. I have also done a PCB layout (4-layer) and I'm happy to send a print of the top/bottom layers to anyone who feels that they want to comment on that (inner layers are ground and power). Let the brick-bats be thrown! Cheers Dave No virus found in this outgoing message. Checked by AVG - http://www.avg.com Version: 8.0.138 / Virus Database: 270.4.7/1544 - Release Date: 10/07/2008 07:37 Name: Frequency Divider 2.pdf Frequency Divider 2.pdfType: Portable Document Format (application/pdf) Encoding: base64 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
I am not a big fan of BNC connectors on the PC board itself, because I am not a big fan of attaching PC boards directly to panels in most cases. There are usually some BNC bulkhead connectors on eBay that terminate in SMA/SMB/SMC pigtails, which are great for panel mounting. http://cgi.ebay.com/eBayISAPI.dll?ViewItemitem=280222636701 fr'instance. That being said, it doesn't matter, because this board has a fault which will cause it to go a hundred percent failure within 72 hours. It is still within operational limits right now, though, and it will stay that way until it fails. :-P -- john, KE5FX In my best HAL 9000 voice; Hi Dave. Dave, what are you doing ? Dave we need BNC connectors. Those SMB's are hard to work with. Dave, are you intending to have those SMB's stick out through a panel ? Dave ? Dave, let me suggest that you layout the connector pattern so either one can be used and stick out a panel. Dave ? Dave ? Why are you unplugging my internet feee BillWB6BNQ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
From: David C. Partridge [EMAIL PROTECTED] Subject: [time-nuts] Frequency divider design critique request Date: Thu, 10 Jul 2008 21:30:56 +0100 Message-ID: [EMAIL PROTECTED] David, As I've mentioned before, I've been working on the design of a frequency divider to go with my TB. The idea is 10MHz sine in from TB, output 2.5Vp-p 50% duty cycle square wave into 50R (5V into 1M), at 10Mhz, 5MHz, 1MHz and decade selectable 100kHz down to 1Hz. All rising edges synchronised to the 10MHz clock rising edge (or as near as I can get with 74AC logic). Good initial concept. With a considerable amount of constructive criticism from Bruce Griffiths (thank you again Bruce) I believe the design now to be complete. The aim is to have as low a level of nasties as possible (i.e. fit for time-nuts). All faults are my own - no blame attaches to Bruce! The one thing I would do is to hook caps over at R24 to R26, say 10 nF, to make the thumb wheel leads less susceptible to noise and less of areal for the edges from the CMOS. The thumb-wheel either keep them floating in one end or didged hard to +5V. To avoid both E and H fields, a series-resistor should be included. I've not yet subjected this design to the ultimate simulation tool (PCB, parts and solder) yet, and I have no means to test it for levels of jitter (phase noise) or similar nasties. I am sure we can come up with some arrangement for that. Several handy time-nuts around. I think that it's now the right time to open the design up for critique from a wider audience before I commit it to copper. I'm therefore attaching the design as a PDF file for your comments. A few comments are in order: 1) The 5Mhz and 1MHz outputs are re-clocked TWICE deliberately to delay them by one clock cycle so they line up with the 1MHz and lower outputs. Neat. 2) The selected output (at the '4051 mux) from the ripple counter chain is re-clocked to 1MHz before re-clocking to 10MHz as the worst-case delay in the chain of '4017s is large enough that the lower frquencies wouldn't reliably re-clock directly to 10MHz. Good thinking! I have also done a PCB layout (4-layer) and I'm happy to send a print of the top/bottom layers to anyone who feels that they want to comment on that (inner layers are ground and power). ... and you say they are not of interest? Let the brick-bats be thrown! I have a lots of bricks around me (my summerhouse is build with old handmade bricks) but I wont toss them. So far, only the thumbwheel is the only minor flaw that I could come up with. I need to check some more... I rather have a few questions on why you did not include certain features... In my experience, having a few extra 10 MHz signals to feed Ext Ref on instruments is a good thing. That way you can keep these others at hand for various setups you need to do. I would consider a dedicated 1 PPS output. I would consider a synchronise feature with a PPS/synchronise input. It should be wise to not directly wire it to the counter resets, but provide an arm button and maybe a very simple arrangement to indicate left, on mark and right with red, gren, red LEDs. Just a tought. The arm button could also have an electrical input, but I am running into creaping featurism here. I think however that synchronisation might be a good thing. That way you can shift the phase of the signal to fit your need. Pulling and inserting the 10 MHz cable is a very crude way of doing it. Maybe it would be just too much fuzz for too little gain, what do I know, but I know I would enjoy seeing it. A pulse-add/pulse-swallow technique (with a shift in initial divide by 10) could be used to provide inc/dec functionality for a manual movement of phase. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Hej Magnus Magnus Danielson wrote: David, As I've mentioned before, I've been working on the design of a frequency divider to go with my TB. The idea is 10MHz sine in from TB, output 2.5Vp-p 50% duty cycle square wave into 50R (5V into 1M), at 10Mhz, 5MHz, 1MHz and decade selectable 100kHz down to 1Hz. All rising edges synchronised to the 10MHz clock rising edge (or as near as I can get with 74AC logic). Good initial concept. With a considerable amount of constructive criticism from Bruce Griffiths (thank you again Bruce) I believe the design now to be complete. The aim is to have as low a level of nasties as possible (i.e. fit for time-nuts). All faults are my own - no blame attaches to Bruce! The one thing I would do is to hook caps over at R24 to R26, say 10 nF, to make the thumb wheel leads less susceptible to noise and less of areal for the edges from the CMOS. The thumb-wheel either keep them floating in one end or didged hard to +5V. To avoid both E and H fields, a series-resistor should be included. You mean?: 1) Connect a 10nF capacitor from each multiplexer digital control input to ground. 2) Connect a series resistor (10k?) from multiplexer control input to the thumbwheel connector pin. 3) Connect a pullup/pulldown resistor from the thumbwheel connector pin to GND or VCC as required. I've not yet subjected this design to the ultimate simulation tool (PCB, parts and solder) yet, and I have no means to test it for levels of jitter (phase noise) or similar nasties. I am sure we can come up with some arrangement for that. Several handy time-nuts around. I think that it's now the right time to open the design up for critique from a wider audience before I commit it to copper. I'm therefore attaching the design as a PDF file for your comments. A few comments are in order: 1) The 5Mhz and 1MHz outputs are re-clocked TWICE deliberately to delay them by one clock cycle so they line up with the 1MHz and lower outputs. Neat. 2) The selected output (at the '4051 mux) from the ripple counter chain is re-clocked to 1MHz before re-clocking to 10MHz as the worst-case delay in the chain of '4017s is large enough that the lower frquencies wouldn't reliably re-clock directly to 10MHz. Good thinking! I have also done a PCB layout (4-layer) and I'm happy to send a print of the top/bottom layers to anyone who feels that they want to comment on that (inner layers are ground and power). ... and you say they are not of interest? Let the brick-bats be thrown! I have a lots of bricks around me (my summerhouse is build with old handmade bricks) but I wont toss them. So far, only the thumbwheel is the only minor flaw that I could come up with. I need to check some more... I rather have a few questions on why you did not include certain features... In my experience, having a few extra 10 MHz signals to feed Ext Ref on instruments is a good thing. That way you can keep these others at hand for various setups you need to do. I would consider a dedicated 1 PPS output. I would consider a synchronise feature with a PPS/synchronise input. It should be wise to not directly wire it to the counter resets, but provide an arm button and maybe a very simple arrangement to indicate left, on mark and right with red, gren, red LEDs. Just a tought. The arm button could also have an electrical input, but I am running into creaping featurism here. I think however that synchronisation might be a good thing. That way you can shift the phase of the signal to fit your need. Pulling and inserting the 10 MHz cable is a very crude way of doing it. Maybe it would be just too much fuzz for too little gain, what do I know, but I know I would enjoy seeing it. A pulse-add/pulse-swallow technique (with a shift in initial divide by 10) could be used to provide inc/dec functionality for a manual movement of phase. The only minor problem is that shifting phase by 1sec or so at the 1pps output will take quite a while if one were to delete 1 pulse per second (to maintain 100ns resolution via pushbutton). A variable phase adjustment rate would work but that adds considerable complication. One method is to allow phase shifting decade by decade. Another way to handle large phase adjustments is to use 2 divider chains, the master is clocked continuously without phase adjustments. The slave is adjusted by preloading it with the desired phase shift when the master divider rolls over. This is easiest to do with synchronous decade counters like the 74XX160/2, however these seem to be hard to find. However this adds considerable complexity and would be much easier to implement in a CPLD or FPGA. External resynchronising/reclocking flipflops would be required to minimise phase modulation of higher frequency outputs by lower frequency outputs. Cheers, Magnus Bruce
Re: [time-nuts] Frequency divider design critique request
Hi David, It looks like your design is pretty far along, so maybe it's too late for this suggestion, but one thing you might consider is replacing the 7400 series logic with a 5V CPLD programmable logic device. This could offer several advantages: 1) any issues (such as jitter) could be addressed by reflashing the CPLD and may let you avoid hardware PCB changes. 2) new features or applications (specially created triggers or unusual pulse outputs) that may come up in the future could possibly be added, again without PCB changes. 3) a full simulation of the design could performed prior to construction Xilinx offers a free (as in free beer, not as in free speech) complete programmable logic design simulation and synthesis tool for download from their website. It's called ISE WebPACK. There's a version for windows or linux host: http://www.xilinx.com/ise/logic_design_prod/webpack.htm This tool is quite an amazing free download. I had to go through a few gyrations to get the USB cable, as they call the downloader, to build for linux: http://wiki.archlinux.org/index.php/Xilinx_ISE_WebPACK_10.1_wUSB_cable_on_ArchLinux-2.6.24 But I'm sure it's easier on windows. The CPLD's (unlike the FPGAs) are single chip solutions. The XC9500 family is 5V logic compatible and could fit into something as small as a 44 pin package. The ISE design tool offers built in Verilog, VHDL or CUPL programming laguages, or (and this really amazed me) a built in schematic editor tool! This lets you capture the design, just as you have, in a schematic, and then synthesize the logic and perform a complete simulation of your captured schematic. You could even just download the tool, capture your existing schematic (there are logic elements for 7400 series logic devices) and use the tool as a simulation engine to test your design. Even if you ultimately plan to use the 7400 parts. No, I don't work for Xilinx 8-) but I did just finish a design using this tool and was suitably impressed. While I write quite a bit of code in my day to day work, I hadn't designed programmable logic since the old PAL days (way back in the early 80's 8-) I used the schematic capture feature of ISE to input the design and then found my way into writing the control state machines in verilog. Then simulated the functionality and when we built the hardware the whole thing just worked, right out of the box! (The design ran an A/D converter, captured the results into a static ram, and then allowed SPI access to the ram from an AVR microcontroller) I know going to programmable logic can seem like a big unknown, but perhaps it's worth just downloading the tool and checking it out. The CPLD wouldn't replace any of your signal conditioning, fusing, etc, but it could replace the core counters, muxes, etc and give you something that could continue to grow as the years go by. Very Cool Project! johnea On Thu, Jul 10, 2008 at 09:30:56PM +0100, David C. Partridge wrote: As I've mentioned before, I've been working on the design of a frequency divider to go with my TB. The idea is 10MHz sine in from TB, output 2.5Vp-p 50% duty cycle square wave into 50R (5V into 1M), at 10Mhz, 5MHz, 1MHz and decade selectable 100kHz down to 1Hz. All rising edges synchronised to the 10MHz clock rising edge (or as near as I can get with 74AC logic). With a considerable amount of constructive criticism from Bruce Griffiths (thank you again Bruce) I believe the design now to be complete. The aim is to have as low a level of nasties as possible (i.e. fit for time-nuts). All faults are my own - no blame attaches to Bruce! I've not yet subjected this design to the ultimate simulation tool (PCB, parts and solder) yet, and I have no means to test it for levels of jitter (phase noise) or similar nasties. I think that it's now the right time to open the design up for critique from a wider audience before I commit it to copper. I'm therefore attaching the design as a PDF file for your comments. A few comments are in order: 1) The 5Mhz and 1MHz outputs are re-clocked TWICE deliberately to delay them by one clock cycle so they line up with the 1MHz and lower outputs. 2) The selected output (at the '4051 mux) from the ripple counter chain is re-clocked to 1MHz before re-clocking to 10MHz as the worst-case delay in the chain of '4017s is large enough that the lower frquencies wouldn't reliably re-clock directly to 10MHz. I have also done a PCB layout (4-layer) and I'm happy to send a print of the top/bottom layers to anyone who feels that they want to comment on that (inner layers are ground and power). Let the brick-bats be thrown! Cheers Dave No virus found in this outgoing message. Checked by AVG - http://www.avg.com Version: 8.0.138 / Virus Database: 270.4.7/1544 - Release Date: 10/07/2008 07:37 ___ time-nuts mailing list -- time-nuts@febo.com To
Re: [time-nuts] Frequency divider design critique request
[EMAIL PROTECTED] wrote: Hi David, It looks like your design is pretty far along, so maybe it's too late for this suggestion, but one thing you might consider is replacing the 7400 series logic with a 5V CPLD programmable logic device. This could offer several advantages: 1) any issues (such as jitter) could be addressed by reflashing the CPLD and may let you avoid hardware PCB changes. You cannot fix modulation of the higher frequency divider outputs by lower frequency outputs by reprogramming a CPLD or FPGA. External reclocking/resynchronising flipflops (one per output frequency) are required 2) new features or applications (specially created triggers or unusual pulse outputs) that may come up in the future could possibly be added, again without PCB changes. 3) a full simulation of the design could performed prior to construction Xilinx offers a free (as in free beer, not as in free speech) complete programmable logic design simulation and synthesis tool for download from their website. It's called ISE WebPACK. There's a version for windows or linux host: http://www.xilinx.com/ise/logic_design_prod/webpack.htm This tool is quite an amazing free download. I had to go through a few gyrations to get the USB cable, as they call the downloader, to build for linux: http://wiki.archlinux.org/index.php/Xilinx_ISE_WebPACK_10.1_wUSB_cable_on_ArchLinux-2.6.24 But I'm sure it's easier on windows. The CPLD's (unlike the FPGAs) are single chip solutions. The XC9500 family is 5V logic compatible and could fit into something as small as a 44 pin package. The ISE design tool offers built in Verilog, VHDL or CUPL programming laguages, or (and this really amazed me) a built in schematic editor tool! This lets you capture the design, just as you have, in a schematic, and then synthesize the logic and perform a complete simulation of your captured schematic. You could even just download the tool, capture your existing schematic (there are logic elements for 7400 series logic devices) and use the tool as a simulation engine to test your design. Even if you ultimately plan to use the 7400 parts. Just dont use this method to implement the dividers etc in the CPLD. Its better to use a fully synchronous decade divider chain if possible as this eliminates all the realignment logic required with ripple clocked divider chains. Another issue with some (but not all) CPLDs are the power supply requirements, at least with CMOS the divider (when not driving too many outputs) has a low power supply current making battery operation feasible. No, I don't work for Xilinx 8-) but I did just finish a design using this tool and was suitably impressed. While I write quite a bit of code in my day to day work, I hadn't designed programmable logic since the old PAL days (way back in the early 80's 8-) I used the schematic capture feature of ISE to input the design and then found my way into writing the control state machines in verilog. Then simulated the functionality and when we built the hardware the whole thing just worked, right out of the box! (The design ran an A/D converter, captured the results into a static ram, and then allowed SPI access to the ram from an AVR microcontroller) I know going to programmable logic can seem like a big unknown, but perhaps it's worth just downloading the tool and checking it out. The CPLD wouldn't replace any of your signal conditioning, fusing, etc, but it could replace the core counters, muxes, etc and give you something that could continue to grow as the years go by. Very Cool Project! johnea Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
Magnus Danielson wrote: I would consider a dedicated 1 PPS output. I would consider a synchronise feature with a PPS/synchronise input. It should be wise to not directly wire it to the counter resets, but provide an arm button and maybe a very simple arrangement to indicate left, on mark and right with red, gren, red LEDs. Just a tought. The arm button could also have an electrical input, but I am running into creaping featurism here. I think however that synchronisation might be a good thing. That way you can shift the phase of the signal to fit your need. Pulling and inserting the 10 MHz cable is a very crude way of doing it. Maybe it would be just too much fuzz for too little gain, what do I know, but I know I would enjoy seeing it. A pulse-add/pulse-swallow technique (with a shift in initial divide by 10) could be used to provide inc/dec functionality for a manual movement of phase. Cheers, Magnus Hej Magnus The easiest way to add a synchronise feature is to use a shift register clocked at 10MHz (if the input PPS pulse width is sufficient 1us?) as the synchroniser. The various shift register taps can be used to generate a synchronous preload pulse for the input divider and a wider reset pulse for the 74HC4017's. If narrower sync pulses are likely then use the sync pulse to toggle a flipflop than connect the flipflop output to the shift register input and use 74XX86 XOR gates to generate the preload and REST pulses from the shift register taps. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
The CPLD's (unlike the FPGAs) are single chip solutions. There are many single chip FPGA solutions today from several different companies. If you are in the US and near a Avnet office you can pick up a Actel Igloo Icicle eval. board/programmer for $49. They are giving them out at the Actel Power seminars being held in July and August. I'll be at the one in Cleveland next week if anyone is there. Don't know if this URL will work or not: http://www.em.avnet.com/evs/home/0,4582,CID%253D47005%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32233%2526BID%253DDF2%2526CTP%253DEVS,00.html?SUL=actellowpower -- http://www.wearablesmartsensors.com/ http://www.softwaresafety.net/ http://www.designer-iii.com/ http://www.unusualresearch.com/ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
On Fri, Jul 11, 2008 at 11:33:53AM +1200, Bruce Griffiths wrote: [EMAIL PROTECTED] wrote: Hi David, It looks like your design is pretty far along, so maybe it's too late for this suggestion, but one thing you might consider is replacing the 7400 series logic with a 5V CPLD programmable logic device. This could offer several advantages: 1) any issues (such as jitter) could be addressed by reflashing the CPLD and may let you avoid hardware PCB changes. You cannot fix modulation of the higher frequency divider outputs by lower frequency outputs by reprogramming a CPLD or FPGA. External reclocking/resynchronising flipflops (one per output frequency) are required Flip flops within the CPLD can be clocked with completely asynchronous clocks and perform the exact function of devices external to the CPLD. The ISE design tool offers built in Verilog, VHDL or CUPL programming laguages, or (and this really amazed me) a built in schematic editor tool! This lets you capture the design, just as you have, in a schematic, and then synthesize the logic and perform a complete simulation of your captured schematic. You could even just download the tool, capture your existing schematic (there are logic elements for 7400 series logic devices) and use the tool as a simulation engine to test your design. Even if you ultimately plan to use the 7400 parts. Just dont use this method to implement the dividers etc in the CPLD. Its better to use a fully synchronous decade divider chain if possible as this eliminates all the realignment logic required with ripple clocked divider chains. Excellent point. While you could capture your existing design in it's exact form for simulation purposes, if you intended to use the CPLD as the final target device, a fully synchronous divider would be best. The symbol libraries contain a very nice full look ahead counter which is cascadable to arbitrary width. In fact Bruce's point of using synchronous design practices really applies equally to designs within a CPLD/FPGA or implimented using discrete components. Another issue with some (but not all) CPLDs are the power supply requirements, at least with CMOS the divider (when not driving too many outputs) has a low power supply current making battery operation feasible. I would expect that replacing the many 74HCxx logic devices with one CPLD would provide a power consumption benefit. BTW, Altera also offers a very full featured design tool for their programmable logic devices viia free download, but I haven't tried it as it's available for windows only. johnea ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
The TrueTime XL-AK Time Frequency Receiver does just what you want plus a few more outputs. Unfortunately they do not provide schematics in the manual. 73, Dick, W1KSZ -Original Message- From: David C. Partridge [EMAIL PROTECTED] Sent: Jul 10, 2008 1:30 PM To: 'Discussion of precise time and frequency measurement' time-nuts@febo.com Subject: [time-nuts] Frequency divider design critique request As I've mentioned before, I've been working on the design of a frequency divider to go with my TB. The idea is 10MHz sine in from TB, output 2.5Vp-p 50% duty cycle square wave into 50R (5V into 1M), at 10Mhz, 5MHz, 1MHz and decade selectable 100kHz down to 1Hz. All rising edges synchronised to the 10MHz clock rising edge (or as near as I can get with 74AC logic). With a considerable amount of constructive criticism from Bruce Griffiths (thank you again Bruce) I believe the design now to be complete. The aim is to have as low a level of nasties as possible (i.e. fit for time-nuts). All faults are my own - no blame attaches to Bruce! I've not yet subjected this design to the ultimate simulation tool (PCB, parts and solder) yet, and I have no means to test it for levels of jitter (phase noise) or similar nasties. I think that it's now the right time to open the design up for critique from a wider audience before I commit it to copper. I'm therefore attaching the design as a PDF file for your comments. A few comments are in order: 1) The 5Mhz and 1MHz outputs are re-clocked TWICE deliberately to delay them by one clock cycle so they line up with the 1MHz and lower outputs. 2) The selected output (at the '4051 mux) from the ripple counter chain is re-clocked to 1MHz before re-clocking to 10MHz as the worst-case delay in the chain of '4017s is large enough that the lower frquencies wouldn't reliably re-clock directly to 10MHz. I have also done a PCB layout (4-layer) and I'm happy to send a print of the top/bottom layers to anyone who feels that they want to comment on that (inner layers are ground and power). Let the brick-bats be thrown! Cheers Dave No virus found in this outgoing message. Checked by AVG - http://www.avg.com Version: 8.0.138 / Virus Database: 270.4.7/1544 - Release Date: 10/07/2008 07:37 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency divider design critique request
John Miles wrote: I am not a big fan of BNC connectors on the PC board itself, because I am not a big fan of attaching PC boards directly to panels in most cases. There are usually some BNC bulkhead connectors on eBay that terminate in SMA/SMB/SMC pigtails, which are great for panel mounting. I strongly concur. Using SMA/SMC connectors also makes the board more reusable as part of a bigger system. I like to use vertical SMA/SMC connectors on boards and right-angle connectors on any coax going to a board. With this configuration, you can cram a lot of boards in a box even at 1U height and use the remaining vertical space for cross-connections. -ch ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
