Re: [U-Boot] [PATCH] DaVinci DA8xx: fix set_cpu_clk_info()
Hi Laurence,
Thanks for the patch. I have tested this patch, below are few comments.
On Fri, Jul 27, 2012 at 4:19 PM, Laurence Withers lwith...@guralp.com wrote:
For the DA8xx family of SoCs, the set_cpu_clk_info() function was not
initialising the DSP frequency, leading to 'bdinfo' command output such as:
[...snip...]
ARM frequency = 300 MHz
DSP frequency = -536870913 MHz
DDR frequency = 300 MHz
This commit provides a separate implementation of set_cpu_clk_info() for
the DA8xx SoCs that initialises the DSP frequency to zero (since
currently the DSP is not enabled by U-Boot on any DA8xx platform). The
separate implementation is justified because there is no common code
between DA8xx and the other SoC families. It is now much easier to
understand the flow of the two separate functions.
Signed-off-by: Laurence Withers lwith...@guralp.com
Cc: Tom Rini tr...@ti.com
Cc: Hadli, Manjunath manjunath.ha...@ti.com
Cc: Heiko Schocher h...@denx.de
---
arch/arm/cpu/arm926ejs/davinci/cpu.c | 21 +
1 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c
b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 6cb857a..4bdb08b 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -117,6 +117,16 @@ int clk_get(enum davinci_clk_ids id)
out:
return pll_out;
}
+
+int set_cpu_clk_info(void)
+{
+ gd-bd-bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
+ /* DDR PHY uses an x2 input clock */
+ gd-bd-bi_ddr_freq = clk_get(0x10001) / 100;
Can you define a macro for this 0x10001 ?
With that change you can add my ACK:
Acked-by: Prabhakar Lad prabhakar@ti.com
Thx,
--Prabhakar Lad
+ gd-bd-bi_dsp_freq = 0;
+ return 0;
+}
+
#else /* CONFIG_SOC_DA8XX */
static unsigned pll_div(volatile void *pllbase, unsigned offset)
@@ -187,16 +197,9 @@ unsigned int davinci_clk_get(unsigned int div)
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 100;
}
#endif
-#endif /* !CONFIG_SOC_DA8XX */
int set_cpu_clk_info(void)
{
-#ifdef CONFIG_SOC_DA8XX
- gd-bd-bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
- /* DDR PHY uses an x2 input clock */
- gd-bd-bi_ddr_freq = clk_get(0x10001) / 100;
-#else
-
unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
#if defined(CONFIG_SOC_DM365)
pllbase = DAVINCI_PLL_CNTRL1_BASE;
@@ -215,10 +218,12 @@ int set_cpu_clk_info(void)
pllbase = DAVINCI_PLL_CNTRL0_BASE;
#endif
gd-bd-bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
-#endif
+
return 0;
}
+#endif /* !CONFIG_SOC_DA8XX */
+
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
--
1.7.2.5
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[U-Boot] [PATCH] image/FIT: Ramdisk Load, Entry address and OS tag inclusion
From: Jagannadha Sutradharudu Teki 402ja...@gmail.com The current code in image.c doesn't include the Load, Entry address and OS tag to FIT image through mkimage tool. Due to this while extracting the ramdisk from FIT blob, bootm showing an error like... Can't get ramdisk subimage load address! Ramdisk image is corrupt or invalid So, I was added Load, Entry address and also OS tag on image.c. Now mkimage is able to include these details and it's works fine. Regards, Jagan. Jagannadha Sutradharudu Teki (1): image/FIT: Add ramdisk load, entry address and OS tag inclusion common/image.c |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] image/FIT: Add ramdisk load, entry address and OS tag inclusion
From: Jagannadha Sutradharudu Teki 402ja...@gmail.com
This patch adds support to include Load, Entry address and OS tag
of ramdisk on to FIT image through mkimage tool.
Signed-off-by: Jagannadha Sutradharudu Teki 402ja...@gmail.com
---
common/image.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/common/image.c b/common/image.c
index 91954ac..70a112d 100644
--- a/common/image.c
+++ b/common/image.c
@@ -2042,13 +2042,13 @@ void fit_image_print(const void *fit, int
image_noffset, const char *p)
printf(%s Architecture: %s\n, p, genimg_get_arch_name(arch));
}
- if (type == IH_TYPE_KERNEL) {
+ if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_RAMDISK)) {
fit_image_get_os(fit, image_noffset, os);
printf(%s OS: %s\n, p, genimg_get_os_name(os));
}
if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
- (type == IH_TYPE_FIRMWARE)) {
+ (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK)) {
ret = fit_image_get_load(fit, image_noffset, load);
printf(%s Load Address: , p);
if (ret)
@@ -2057,7 +2057,8 @@ void fit_image_print(const void *fit, int image_noffset,
const char *p)
printf(0x%08lx\n, load);
}
- if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE)) {
+ if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
+ (type == IH_TYPE_RAMDISK)) {
fit_image_get_entry(fit, image_noffset, entry);
printf(%s Entry Point: , p);
if (ret)
--
1.7.0.4
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[U-Boot] V3: S3c64xx: Switch all I/O to use readl/writel functio and Clear variable
V3: 1. Replace ELFIN with S3C64XX for all the variable of cpu.h. 2. Change __S3C6400_H__ into __CPU__H__. 3. Use C language to implement memory initialization. 4. Use C language to re-write reset function. 5. Delete u-boot-nand.lds. V2: 1. Modify the type of return for s3c64xx_get_base_nand 2. Add patch 0014 to support s3c6410 board 3. Adjust patch for mix content. V1: This serial patch intent to: 1. Switch all I/O to use readl/writel function 2. Change nand_spl to use SPL framework 3. S3C64XX serial includes s3c6400 and s3c6410, Here seprate cpu and board file to support to board's of s3c6410. I test this patch on my s3c6410 development board. the log as following: U-Boot 2012.07-rc3-00016-g351ea73 (Jul 28 2012 - 16:55:32) for DMATEK6410 CPU: S3C64XX@532MHz Fclk = 532MHz, Hclk = 133MHz, Pclk = 66MHz (ASYNC Mode) Board: DMATEK6410 DRAM: 128 MiB WARNING: Caches not enabled NAND: 128 MiB *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: dm9000 Zhong Hongbo (15): smdk6400: Move smdk6400 board from Makefile to boards.cfg S3C64XX: Switch to use readl/writel to operate nand flash S3C64XX: Use readl/writel to operate uart S3C64XX: add pwm for s3c64xx support S3C64XX: reference s5p cpu time system for s3c64xx timer S3C64xx: mov cpu_init.S to the board directory S3C6400: Delete nand_spl for S3C6400 S3C6400: Adopt SPL framwork to support spl for nand flash arm1176: Fixed No relocation. S3C64XX: Change SROM init to use read/write operation S3C64XX: Switch to use read/writel to operation clock system S3c64xx: clear GPIO, Interrupt, Watchdog variable. S3C6400: clear memory init variable S3C64XX: Move s3c6400.h to cpu.h to support s3c6410 board S3C6400: Remove the unused variable for S3C6400 Makefile| 20 - arch/arm/cpu/arm1176/s3c64xx/Makefile |7 +- arch/arm/cpu/arm1176/s3c64xx/cpu_init.S | 135 arch/arm/cpu/arm1176/s3c64xx/pwm.c | 188 + arch/arm/cpu/arm1176/s3c64xx/reset.S| 34 - arch/arm/cpu/arm1176/s3c64xx/reset.c| 39 + arch/arm/cpu/arm1176/s3c64xx/speed.c| 52 +- arch/arm/cpu/arm1176/s3c64xx/srom.c | 51 ++ arch/arm/cpu/arm1176/s3c64xx/timer.c| 195 +++--- arch/arm/cpu/arm1176/start.S| 17 +- arch/arm/include/asm/arch-s3c64xx/clock.h | 163 arch/arm/include/asm/arch-s3c64xx/cpu.h | 89 +++ arch/arm/include/asm/arch-s3c64xx/dmc.h | 62 ++ arch/arm/include/asm/arch-s3c64xx/gpio.h| 38 + arch/arm/include/asm/arch-s3c64xx/interrupt.h | 31 + arch/arm/include/asm/arch-s3c64xx/nand.h| 72 ++ arch/arm/include/asm/arch-s3c64xx/pwm.h | 70 ++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 895 --- arch/arm/include/asm/arch-s3c64xx/s3c64x0.h | 90 --- arch/arm/include/asm/arch-s3c64xx/sromc.h | 49 ++ arch/arm/include/asm/arch-s3c64xx/uart.h| 54 ++ board/samsung/smdk6400/Makefile | 30 +- board/samsung/smdk6400/config.mk| 30 - board/samsung/smdk6400/dmc_init.c | 110 +++ board/samsung/smdk6400/lowlevel_init.S | 76 +- board/samsung/smdk6400/setup.h | 137 board/samsung/smdk6400/smdk6400.c | 40 +- board/samsung/smdk6400/smdk6400_nand_spl.c | 61 ++- board/samsung/smdk6400/tools/mksmdk6400_image.c | 117 +++ board/samsung/smdk6400/u-boot-nand.lds | 84 --- boards.cfg |2 + drivers/mtd/nand/s3c64xx.c | 64 +- drivers/serial/s3c64xx.c| 52 +- drivers/usb/host/s3c64xx-hcd.c | 32 +- include/configs/smdk6400.h | 40 +- nand_spl/board/samsung/smdk6400/Makefile| 117 --- nand_spl/board/samsung/smdk6400/config.mk | 40 - nand_spl/board/samsung/smdk6400/u-boot.lds | 78 -- 38 files changed, 1668 insertions(+), 1793 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/cpu_init.S create mode 100644 arch/arm/cpu/arm1176/s3c64xx/pwm.c delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/reset.S create mode 100644 arch/arm/cpu/arm1176/s3c64xx/reset.c create mode 100644 arch/arm/cpu/arm1176/s3c64xx/srom.c create mode 100644 arch/arm/include/asm/arch-s3c64xx/clock.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/cpu.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/dmc.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/gpio.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/interrupt.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/nand.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/pwm.h delete mode 100644 arch/arm/include/asm/arch-s3c64xx/s3c6400.h delete mode 100644 arch/arm/include/asm/arch-s3c64xx/s3c64x0.h create
[U-Boot] [V3 01/15] smdk6400: Move smdk6400 board from Makefile to boards.cfg
From: Zhong Hongbo bocui...@gmail.com Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V3: - None Change for V2: - None --- Makefile | 20 board/samsung/smdk6400/config.mk |4 +--- boards.cfg |2 ++ include/configs/smdk6400.h |2 +- 4 files changed, 4 insertions(+), 24 deletions(-) diff --git a/Makefile b/Makefile index d57c15e..8af1d5d 100644 --- a/Makefile +++ b/Makefile @@ -711,26 +711,6 @@ SX1_config:unconfig fi; @$(MKCONFIG) -n $@ SX1 arm arm925t sx1 -# -## ARM1176 Systems -# -smdk6400_noUSB_config \ -smdk6400_config: unconfig - @mkdir -p $(obj)include $(obj)board/samsung/smdk6400 - @mkdir -p $(obj)nand_spl/board/samsung/smdk6400 - @echo #define CONFIG_NAND_U_BOOT $(obj)include/config.h - @echo CONFIG_NAND_U_BOOT = y $(obj)include/config.mk - @if [ -z $(findstring smdk6400_noUSB_config,$@) ]; then \ - echo RAM_TEXT = 0x57e0 $(obj)board/samsung/smdk6400/config.tmp;\ - else \ - echo RAM_TEXT = 0xc7e0 $(obj)board/samsung/smdk6400/config.tmp;\ - fi - @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx - @echo CONFIG_NAND_U_BOOT = y $(obj)include/config.mk - -# -# - clean: @rm -f $(obj)examples/standalone/82559_eeprom \ $(obj)examples/standalone/atmel_df_pow2\ diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk index 6f04c2f..93a1a0d 100644 --- a/board/samsung/smdk6400/config.mk +++ b/board/samsung/smdk6400/config.mk @@ -21,10 +21,8 @@ # # download area is 0x5000c000 -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - ifndef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = $(RAM_TEXT) +CONFIG_SYS_TEXT_BASE = $(CONFIG_RAM_TEXT) else CONFIG_SYS_TEXT_BASE = 0 endif diff --git a/boards.cfg b/boards.cfg index 2d36d83..0363b41 100644 --- a/boards.cfg +++ b/boards.cfg @@ -47,6 +47,8 @@ flea3arm arm1136 - CarMedi mx35pdk arm arm1136 - freescale mx35 apollon arm arm1136 apollon - omap24xx omap2420h4 arm arm1136 - ti omap24xx +smdk6400 arm arm1176 smdk6400 samsungs3c64xx smdk6400:NAND_U_BOOT,RAM_TEXT=0xc7e0 +smdk6400_nousb arm arm1176 smdk6400 samsungs3c64xx smdk6400:NAND_U_BOOT,RAM_TEXT=0x57e0 tnetv107x_evmarm arm1176 tnetv107xevmti tnetv107x integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T integratorap_cm920t arm arm920t integrator armltd - integratorap:CM920T diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index 04caeef..47326d6 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -54,7 +54,7 @@ /* input clock of PLL: SMDK6400 has 12MHz input clock */ #define CONFIG_SYS_CLK_FREQ1200 -#if !defined(CONFIG_NAND_SPL) (CONFIG_SYS_TEXT_BASE = 0xc000) +#if !defined(CONFIG_NAND_U_BOOT) (CONFIG_SYS_TEXT_BASE = 0xc000) #define CONFIG_ENABLE_MMU #endif -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [V3 02/15] S3C64XX: Switch to use readl/writel to operate nand flash
From: Zhong Hongbo bocui...@gmail.com
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V3:
- Replace the magic numbers with variable name.
Change for V2:
- Change the type of the return value from unsinged int
to unsinged long for s3c64xx_get_base_uart function.
- Delete const for the local variable.
---
arch/arm/include/asm/arch-s3c64xx/nand.h| 72
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 79 ++-
board/samsung/smdk6400/lowlevel_init.S |1 +
drivers/mtd/nand/s3c64xx.c | 58 +---
4 files changed, 116 insertions(+), 94 deletions(-)
create mode 100644 arch/arm/include/asm/arch-s3c64xx/nand.h
diff --git a/arch/arm/include/asm/arch-s3c64xx/nand.h
b/arch/arm/include/asm/arch-s3c64xx/nand.h
new file mode 100644
index 000..a1bf3ab
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/nand.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2012
+ * Zhong Hongbo bocui...@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_NAND_H__
+#define __ASM_ARCH_NAND_H__
+
+#define NFCONF_OFFSET 0x00
+#define NFCONT_OFFSET 0x04
+
+#define NFCONF_ECC_4BIT(124)
+
+#define NFCONT_ECC_ENC (118)
+#define NFCONT_WP (116)
+#define NFCONT_MECCLOCK(17)
+#define NFCONT_SECCLOCK(16)
+#define NFCONT_INITMECC(15)
+#define NFCONT_INITSECC(14)
+#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
+#define NFCONT_CS_ALT (12)
+#define NFCONT_CS (11)
+#define NFCONT_ENABLE (10)
+
+#define NFSTAT_ECCENCDONE (17)
+#define NFSTAT_ECCDECDONE (16)
+#define NFSTAT_RnB (10)
+
+#define NFESTAT0_ECCBUSY (131)
+
+#ifndef __ASSEMBLY__
+/* NAND FLASH */
+struct s3c64xx_nand {
+ u32 nfconf;
+ u32 nfcont;
+ u32 nfcmmd;
+ u32 nfaddr;
+ u32 nfdata;
+ u32 nfmeccdata0;
+ u32 nfmeccdata1;
+ u32 nfseccdata0;
+ u32 nfsblk;
+ u32 nfeblk;
+ u32 nfstat;
+ u32 nfestat0;
+ u32 nfestat1;
+ u32 nfmecc0;
+ u32 nfmecc1;
+ u32 nfsecc;
+ u32 nfmlcbitpt;
+};
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 10b3324..d6c5dd9 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -556,80 +556,6 @@
*/
#define ELFIN_NAND_BASE0x7020
-#define NFCONF_OFFSET 0x00
-#define NFCONT_OFFSET 0x04
-#define NFCMMD_OFFSET 0x08
-#define NFADDR_OFFSET 0x0c
-#define NFDATA_OFFSET 0x10
-#define NFMECCDATA0_OFFSET 0x14
-#define NFMECCDATA1_OFFSET 0x18
-#define NFSECCDATA0_OFFSET 0x1c
-#define NFSBLK_OFFSET 0x20
-#define NFEBLK_OFFSET 0x24
-#define NFSTAT_OFFSET 0x28
-#define NFESTAT0_OFFSET0x2c
-#define NFESTAT1_OFFSET0x30
-#define NFMECC0_OFFSET 0x34
-#define NFMECC1_OFFSET 0x38
-#define NFSECC_OFFSET 0x3c
-#define NFMLCBITPT_OFFSET 0x40
-
-#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define
[U-Boot] [V3 03/15] S3C64XX: Use readl/writel to operate uart
From: Zhong Hongbo bocui...@gmail.com
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for v3:
- None.
Change for V2:
- Change the type of the return value from unsinged int
to unsinged long for s3c64xx_get_base_uart function.
- Delete const for the local variable.
---
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 65 +--
arch/arm/include/asm/arch-s3c64xx/s3c64x0.h | 31 -
arch/arm/include/asm/arch-s3c64xx/uart.h| 54 ++
board/samsung/smdk6400/lowlevel_init.S |8 ---
drivers/serial/s3c64xx.c| 50 +
5 files changed, 87 insertions(+), 121 deletions(-)
create mode 100644 arch/arm/include/asm/arch-s3c64xx/uart.h
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index d6c5dd9..77b9509 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -582,62 +582,6 @@
*/
#define ELFIN_UART_BASE0x7F005000
-#define ELFIN_UART0_OFFSET 0x
-#define ELFIN_UART1_OFFSET 0x0400
-#define ELFIN_UART2_OFFSET 0x0800
-
-#define ULCON_OFFSET 0x00
-#define UCON_OFFSET0x04
-#define UFCON_OFFSET 0x08
-#define UMCON_OFFSET 0x0C
-#define UTRSTAT_OFFSET 0x10
-#define UERSTAT_OFFSET 0x14
-#define UFSTAT_OFFSET 0x18
-#define UMSTAT_OFFSET 0x1C
-#define UTXH_OFFSET0x20
-#define URXH_OFFSET0x24
-#define UBRDIV_OFFSET 0x28
-#define UDIVSLOT_OFFSET0x2C
-#define UINTP_OFFSET 0x30
-#define UINTSP_OFFSET 0x34
-#define UINTM_OFFSET 0x38
-
-#define ULCON0_REG __REG(0x7F005000)
-#define UCON0_REG __REG(0x7F005004)
-#define UFCON0_REG __REG(0x7F005008)
-#define UMCON0_REG __REG(0x7F00500C)
-#define UTRSTAT0_REG __REG(0x7F005010)
-#define UERSTAT0_REG __REG(0x7F005014)
-#define UFSTAT0_REG__REG(0x7F005018)
-#define UMSTAT0_REG__REG(0x7F00501c)
-#define UTXH0_REG __REG(0x7F005020)
-#define URXH0_REG __REG(0x7F005024)
-#define UBRDIV0_REG__REG(0x7F005028)
-#define UDIVSLOT0_REG __REG(0x7F00502c)
-#define UINTP0_REG __REG(0x7F005030)
-#define UINTSP0_REG__REG(0x7F005034)
-#define UINTM0_REG __REG(0x7F005038)
-
-#define ULCON1_REG __REG(0x7F005400)
-#define UCON1_REG __REG(0x7F005404)
-#define UFCON1_REG __REG(0x7F005408)
-#define UMCON1_REG __REG(0x7F00540C)
-#define UTRSTAT1_REG __REG(0x7F005410)
-#define UERSTAT1_REG __REG(0x7F005414)
-#define UFSTAT1_REG__REG(0x7F005418)
-#define UMSTAT1_REG__REG(0x7F00541c)
-#define UTXH1_REG __REG(0x7F005420)
-#define URXH1_REG __REG(0x7F005424)
-#define UBRDIV1_REG__REG(0x7F005428)
-#define UDIVSLOT1_REG __REG(0x7F00542c)
-#define UINTP1_REG __REG(0x7F005430)
-#define UINTSP1_REG__REG(0x7F005434)
-#define UINTM1_REG __REG(0x7F005438)
-
-#define UTRSTAT_TX_EMPTY (1 2)
-#define UTRSTAT_RX_READY (1 0)
-#define UART_ERR_MASK 0xF
-
/*
* PWM timer
*/
@@ -804,17 +748,12 @@
#define DMC_DDR_USER_CONFIG1
#ifndef __ASSEMBLY__
-enum s3c64xx_uarts_nr {
- S3C64XX_UART0,
- S3C64XX_UART1,
- S3C64XX_UART2,
-};
#include s3c64x0.h
-static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
+static inline unsigned long s3c64xx_get_base_uart(void)
{
- return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
+ return ELFIN_UART_BASE;
}
static inline unsigned long s3c64xx_get_base_nand(void)
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
index 0bbf1d0..7add68c 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
@@ -40,37 +40,6 @@
#include asm/types.h
-/* UART (see manual chapter 11) */
-typedef struct {
- volatile u32ULCON;
- volatile u32UCON;
- volatile u32UFCON;
- volatile u32UMCON;
- volatile u32UTRSTAT;
- volatile u32UERSTAT;
- volatile u32UFSTAT;
- volatile u32UMSTAT;
-#ifdef __BIG_ENDIAN
- volatile u8 res1[3];
- volatile u8 UTXH;
- volatile u8 res2[3];
- volatile u8 URXH;
-#else /* Little Endian */
- volatile u8 UTXH;
- volatile u8 res1[3];
- volatile u8 URXH;
- volatile u8 res2[3];
-#endif
- volatile u32UBRDIV;
-#ifdef __BIG_ENDIAN
- volatile u8 res3[2];
- volatile u16UDIVSLOT;
-#else
- volatile u16UDIVSLOT;
- volatile u8
[U-Boot] [V3 04/15] S3C64XX: add pwm for s3c64xx support
From: Zhong Hongbo bocui...@gmail.com
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V3:
- None.
Change for V2:
- Change the type of the return value from unsinged int
to unsinged long for s3c64xx_get_base_nand function.
---
arch/arm/cpu/arm1176/s3c64xx/Makefile |1 +
arch/arm/cpu/arm1176/s3c64xx/pwm.c | 189 +++
arch/arm/include/asm/arch-s3c64xx/pwm.h | 70 ++
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 56 ++---
arch/arm/include/asm/arch-s3c64xx/s3c64x0.h | 59 -
include/configs/smdk6400.h |3 +
6 files changed, 272 insertions(+), 106 deletions(-)
create mode 100644 arch/arm/cpu/arm1176/s3c64xx/pwm.c
create mode 100644 arch/arm/include/asm/arch-s3c64xx/pwm.h
delete mode 100644 arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile
b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 0785b19..93f 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -32,6 +32,7 @@ SOBJS = reset.o
COBJS-$(CONFIG_S3C6400)+= cpu_init.o speed.o
COBJS-y+= timer.o
+COBJS-$(CONFIG_PWM) += pwm.o
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/arm1176/s3c64xx/pwm.c
b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
new file mode 100644
index 000..d46470a
--- /dev/null
+++ b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2012
+ *
+ * Zhong Hongbo bocui...@gmail.com
+ *
+ * based on arch/arm/cpu/armv7/s5p-common/sromc.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include errno.h
+#include pwm.h
+#include asm/io.h
+#include asm/arch/s3c6400.h
+#include asm/arch/pwm.h
+
+int pwm_enable(int pwm_id)
+{
+ const struct s3c_timer *pwm =
+ (struct s3c_timer *)s3c64xx_get_base_timer();
+ unsigned long tcon;
+
+ tcon = readl(pwm-tcon);
+ tcon |= TCON_START(pwm_id);
+
+ writel(tcon, pwm-tcon);
+
+ return 0;
+}
+
+void pwm_disable(int pwm_id)
+{
+ const struct s3c_timer *pwm =
+ (struct s3c_timer *)s3c64xx_get_base_timer();
+ unsigned long tcon;
+
+ tcon = readl(pwm-tcon);
+ tcon = ~TCON_START(pwm_id);
+
+ writel(tcon, pwm-tcon);
+}
+
+static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
+{
+ unsigned long tin_parent_rate;
+ unsigned int div;
+
+ tin_parent_rate = get_PCLK();
+
+ for (div = 2; div = 16; div *= 2) {
+ if ((tin_parent_rate / (div 16)) freq)
+ return tin_parent_rate / div;
+ }
+
+ return tin_parent_rate / 16;
+}
+
+#define NS_IN_HZ (10UL)
+
+int pwm_config(int pwm_id, int duty_ns, int period_ns)
+{
+ const struct s3c_timer *pwm =
+ (struct s3c_timer *)s3c64xx_get_base_timer();
+ unsigned int offset;
+ unsigned long tin_rate;
+ unsigned long tin_ns;
+ unsigned long period;
+ unsigned long tcon;
+ unsigned long tcnt;
+ unsigned long tcmp;
+
+ /*
+* We currently avoid using 64bit arithmetic by using the
+* fact that anything faster than 1GHz is easily representable
+* by 32bits.
+*/
+ if (period_ns NS_IN_HZ || duty_ns NS_IN_HZ)
+ return -ERANGE;
+
+ if (duty_ns period_ns)
+ return -EINVAL;
+
+ period = NS_IN_HZ / period_ns;
+
+ /* Check to see if we are changing the clock rate of the PWM */
+ tin_rate = pwm_calc_tin(pwm_id, period);
+
+ tin_ns = NS_IN_HZ / tin_rate;
+ tcnt = period_ns / tin_ns;
+
+ /* Note, counters count down */
+ tcmp = duty_ns / tin_ns;
+ tcmp = tcnt - tcmp;
+
+ /*
+* the pwm hw only checks the compare register after a decrement,
+* so the pin never toggles if tcmp = tcnt
+*/
+ if (tcmp == tcnt)
+ tcmp--;
+
+ if (tcmp 0)
+ tcmp = 0;
+
+ /* Update the PWM register block. */
+ offset = pwm_id * 3;
+ if (pwm_id 4) {
+ writel(tcnt, pwm-tcntb0 +
[U-Boot] [V3 05/15] S3C64XX: reference s5p cpu time system for s3c64xx timer
From: Zhong Hongbo bocui...@gmail.com
The old s3c64xx timer is not work normal, Adopt s5p time design,
It work perfect.
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V3:
- None.
Change for V2:
- Delete const key word for the variable of struct s3c_timer
---
arch/arm/cpu/arm1176/s3c64xx/timer.c | 193 --
1 files changed, 93 insertions(+), 100 deletions(-)
diff --git a/arch/arm/cpu/arm1176/s3c64xx/timer.c
b/arch/arm/cpu/arm1176/s3c64xx/timer.c
index f16a37b..47d7731 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/timer.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/timer.c
@@ -1,23 +1,8 @@
/*
- * (C) Copyright 2003
- * Texas Instruments www.ti.com
+ * Copyright (C) 2012
+ * Zhong Hongbo bocui...@163.com
*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH www.elinos.com
- * Marius Groeger mgroe...@sysgo.de
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH www.elinos.com
- * Alex Zuepke a...@sysgo.de
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, ga...@denx.de
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. philippe.ro...@arm.com
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+ * based on arch/arm/cpu/armv7/s5p-common/timer.c
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -39,64 +24,29 @@
*/
#include common.h
-#include asm/proc-armv/ptrace.h
+#include asm/io.h
#include asm/arch/s3c6400.h
-#include div64.h
-
-static ulong timer_load_val;
+#include asm/arch/pwm.h
+#include pwm.h
-#define PRESCALER 167
+DECLARE_GLOBAL_DATA_PTR;
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
-{
- return (s3c64xx_timers *)ELFIN_TIMER_BASE;
-}
+static unsigned long get_current_tick(void);
/* macro to read the 16 bit timer */
-static inline ulong read_timer(void)
+static inline struct s3c_timer *s3c_get_base_timer(void)
{
- s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
- return timers-TCNTO4;
+ return (struct s3c_timer *)s3c64xx_get_base_timer();
}
-/* Internal tick units */
-/* Last decremneter snapshot */
-static unsigned long lastdec;
-/* Monotonic incrementing timer */
-static unsigned long long timestamp;
-
int timer_init(void)
{
- s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
- /* use PWM Timer 4 because it has no output */
- /*
-* We use the following scheme for the timer:
-* Prescaler is hard fixed at 167, divider at 1/4.
-* This gives at PCLK frequency 66MHz approx. 10us ticks
-* The timer is set to wrap after 100s, at 66MHz this obviously
-* happens after 10,000,000 ticks. A long variable can thus
-* keep values up to 40,000s, i.e., 11 hours. This should be
-* enough for most uses:-) Possible optimizations: select a
-* binary-friendly frequency, e.g., 1ms / 128. Also calculate
-* the prescaler automatically for other PCLK frequencies.
-*/
- timers-TCFG0 = PRESCALER 8;
- if (timer_load_val == 0) {
- timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
- timers-TCFG1 = (timers-TCFG1 ~0xf) | 0x2;
- }
-
- /* load value for 10 ms timeout */
- lastdec = timers-TCNTB4 = timer_load_val;
- /* auto load, manual update of Timer 4 */
- timers-TCON = (timers-TCON ~0x0070) | TCON_4_AUTO |
- TCON_4_UPDATE;
+ /* PWM Timer 4 */
+ pwm_init(4, MUX_DIV_2, 0);
+ pwm_config(4, 0, 0);
+ pwm_enable(4);
- /* auto load, start Timer 4 */
- timers-TCON = (timers-TCON ~0x0070) | TCON_4_AUTO | COUNT_4_ON;
- timestamp = 0;
+ reset_timer_masked();
return 0;
}
@@ -104,57 +54,100 @@ int timer_init(void)
/*
* timer without interrupts
*/
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
+unsigned long get_timer(unsigned long base)
{
- ulong now = read_timer();
+ return get_timer_masked() - base;
+}
- if (lastdec = now) {
- /* normal mode */
- timestamp += lastdec - now;
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+ struct s3c_timer *timer = s3c_get_base_timer();
+ unsigned long tmo, tmp, count_value;
+
+ count_value = readl(timer-tcntb4);
+
+ if (usec = 1000) {
+ /*
+* if big number, spread normalization
+* to seconds
+* 1. start to normalize for usec to ticks per sec
+* 2. find number of ticks to wait to achieve target
+* 3. finish normalize.
+*/
+ tmo = usec / 1000;
+ tmo *= (CONFIG_SYS_HZ * count_value);
+ tmo /= 1000;
} else {
-
[U-Boot] [V3 06/15] S3C64xx: mov cpu_init.S to the board directory
From: Zhong Hongbo bocui...@gmail.com It just only do the memory init. The memory depend on the design of board. Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V3: - None. Change for V2: - None. --- arch/arm/cpu/arm1176/s3c64xx/Makefile |2 +- arch/arm/cpu/arm1176/s3c64xx/cpu_init.S | 135 --- board/samsung/smdk6400/Makefile |2 +- board/samsung/smdk6400/mem_init.S | 135 +++ 4 files changed, 137 insertions(+), 137 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/cpu_init.S create mode 100644 board/samsung/smdk6400/mem_init.S diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile index 93f..2f37431 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/Makefile +++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(SOC).o SOBJS = reset.o -COBJS-$(CONFIG_S3C6400)+= cpu_init.o speed.o +COBJS-$(CONFIG_S3C64XX)+= speed.o COBJS-y+= timer.o COBJS-$(CONFIG_PWM) += pwm.o diff --git a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S deleted file mode 100644 index df88cba..000 --- a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 - * - * Copyright (C) 2008 - * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include config.h -#include asm/arch/s3c6400.h - - .globl mem_ctrl_asm_init -mem_ctrl_asm_init: - /* DMC1 base address 0x7e001000 */ - ldr r0, =ELFIN_DMC1_BASE - - ldr r1, =0x4 - str r1, [r0, #INDEX_DMC_MEMC_CMD] - - ldr r1, =DMC_DDR_REFRESH_PRD - str r1, [r0, #INDEX_DMC_REFRESH_PRD] - - ldr r1, =DMC_DDR_CAS_LATENCY - str r1, [r0, #INDEX_DMC_CAS_LATENCY] - - ldr r1, =DMC_DDR_t_DQSS - str r1, [r0, #INDEX_DMC_T_DQSS] - - ldr r1, =DMC_DDR_t_MRD - str r1, [r0, #INDEX_DMC_T_MRD] - - ldr r1, =DMC_DDR_t_RAS - str r1, [r0, #INDEX_DMC_T_RAS] - - ldr r1, =DMC_DDR_t_RC - str r1, [r0, #INDEX_DMC_T_RC] - - ldr r1, =DMC_DDR_t_RCD - ldr r2, =DMC_DDR_schedule_RCD - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RCD] - - ldr r1, =DMC_DDR_t_RFC - ldr r2, =DMC_DDR_schedule_RFC - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RFC] - - ldr r1, =DMC_DDR_t_RP - ldr r2, =DMC_DDR_schedule_RP - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RP] - - ldr r1, =DMC_DDR_t_RRD - str r1, [r0, #INDEX_DMC_T_RRD] - - ldr r1, =DMC_DDR_t_WR - str r1, [r0, #INDEX_DMC_T_WR] - - ldr r1, =DMC_DDR_t_WTR - str r1, [r0, #INDEX_DMC_T_WTR] - - ldr r1, =DMC_DDR_t_XP - str r1, [r0, #INDEX_DMC_T_XP] - - ldr r1, =DMC_DDR_t_XSR - str r1, [r0, #INDEX_DMC_T_XSR] - - ldr r1, =DMC_DDR_t_ESR - str r1, [r0, #INDEX_DMC_T_ESR] - - ldr r1, =DMC1_MEM_CFG - str r1, [r0, #INDEX_DMC_MEMORY_CFG] - - ldr r1, =DMC1_MEM_CFG2 - str r1, [r0, #INDEX_DMC_MEMORY_CFG2] - - ldr r1, =DMC1_CHIP0_CFG - str r1, [r0, #INDEX_DMC_CHIP_0_CFG] - - ldr r1, =DMC_DDR_32_CFG - str r1, [r0, #INDEX_DMC_USER_CONFIG] - - /* DMC0 DDR Chip 0 configuration direct command reg */ - ldr r1, =DMC_NOP0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Precharge All */ - ldr r1, =DMC_PA0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Auto Refresh 2 time */ - ldr r1, =DMC_AR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* MRS */ - ldr r1, =DMC_mDDR_EMR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Mode Reg */ - ldr r1, =DMC_mDDR_MR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Enable DMC1 */ - mov r1,
[U-Boot] [V3 08/15] S3C6400: Adopt SPL framwork to support spl for nand flash
From: Zhong Hongbo bocui...@gmail.com Adopt the new SPL framework to implement the SPL booting of the nand flash for S3C6400. Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V3: - None. Change for V2: - seprate some code. --- arch/arm/cpu/arm1176/start.S| 16 +--- board/samsung/smdk6400/Makefile | 29 +- board/samsung/smdk6400/lowlevel_init.S | 22 ++-- board/samsung/smdk6400/smdk6400_nand_spl.c | 61 ++-- board/samsung/smdk6400/tools/mksmdk6400_image.c | 117 +++ drivers/mtd/nand/s3c64xx.c |4 +- include/configs/smdk6400.h | 21 +++-- 7 files changed, 221 insertions(+), 49 deletions(-) create mode 100644 board/samsung/smdk6400/tools/mksmdk6400_image.c diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index d613641..761b7fe 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -51,7 +51,7 @@ .globl _start _start: b reset -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -164,7 +164,7 @@ cpu_init_crit: * When booting from NAND - it has definitely been a reset, so, no need * to flush caches and disable the MMU */ -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* * flush v4 I/D caches */ @@ -357,21 +357,14 @@ clbss_l:cmp r0, r1 /* clear loop... */ add r0, r0, #4 b clbss_l clbss_e: -#ifndef CONFIG_NAND_SPL bl coloured_LED_init bl red_led_on #endif -#endif /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ -#ifdef CONFIG_NAND_SPL - ldr pc, _nand_boot - -_nand_boot: .word nand_boot -#else ldr r0, _board_init_r_ofs adr r1, _start add lr, r0, r1 @@ -384,7 +377,6 @@ _nand_boot: .word nand_boot _board_init_r_ofs: .word board_init_r - _start -#endif _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -398,7 +390,7 @@ _mmu_table_base: .word mmu_table #endif -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* * we assume that cache operation is done before. (eg. cleanup_before_linux()) * actually, we don't need to do anything about cache if not use d-cache in @@ -576,4 +568,4 @@ fiq: get_bad_stack bad_save_user_regs bl do_fiq -#endif /* CONFIG_NAND_SPL */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile index 645c8e2..f7fa667 100644 --- a/board/samsung/smdk6400/Makefile +++ b/board/samsung/smdk6400/Makefile @@ -28,15 +28,34 @@ include $(TOPDIR)/config.mk LIB= $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS-y:= smdk6400.o +endif + SOBJS := lowlevel_init.o mem_init.o -SRCS:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +ifdef CONFIG_SPL_BUILD +COBJS-y += smdk6400_nand_spl.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) + +ALL:= $(obj).depend $(LIB) + +ifdef CONFIG_SPL_BUILD +ALL+= $(OBJTREE)/tools/mk$(BOARD)spl +endif + +all: $(ALL) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) -$(LIB):$(obj).depend $(SOBJS) $(OBJS) - $(call cmd_link_o_target, $(SOBJS) $(OBJS)) +ifdef CONFIG_SPL_BUILD +$(OBJTREE)/tools/mk$(BOARD)spl:tools/mksmdk6400_image.c + $(HOSTCC) tools/mksmdk6400_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl +endif # diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index 45887f3..93172e7 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -84,18 +84,12 @@ lowlevel_init: str r3, [r0, #oVECTADDR] str r3, [r1, #oVECTADDR] +#ifdef CONFIG_SPL_BUILD /* init system clock */ - bl system_clock_init + bl system_clock_init -#ifndef CONFIG_NAND_SPL - /* for UART */ - bl uart_asm_init -#endif - -#ifdef CONFIG_BOOT_NAND /* simple init for NAND */ - bl nand_asm_init -#endif + bl nand_asm_init /* Memory subsystem address 0x7e00f120 */ ldr r0, =ELFIN_MEM_SYS_CFG @@ -105,6 +99,12 @@ lowlevel_init: str r1, [r0] bl mem_ctrl_asm_init +#endif + +#ifndef CONFIG_SPL_BUILD + /* for UART */ + bl uart_asm_init +#endif /* Wakeup support. Don't know if it's going to be used, untested. */ ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) @@ -244,7 +244,7 @@ wait_for_async:
[U-Boot] [V3 07/15] S3C6400: Delete nand_spl for S3C6400
From: Zhong Hongbo bocui...@gmail.com
The old spl use nand_spl directory file to support
nand flash boot. We will adopt the new SPL framework
to implement it.
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V3:
- Delete u-boot-nand.lds.
Change for V2:
- None.
---
board/samsung/smdk6400/config.mk | 28 ---
board/samsung/smdk6400/u-boot-nand.lds | 84
boards.cfg |4 +-
include/configs/smdk6400.h |2 +-
nand_spl/board/samsung/smdk6400/Makefile | 117
nand_spl/board/samsung/smdk6400/config.mk | 40 --
nand_spl/board/samsung/smdk6400/u-boot.lds | 78 --
7 files changed, 3 insertions(+), 350 deletions(-)
delete mode 100644 board/samsung/smdk6400/config.mk
delete mode 100644 board/samsung/smdk6400/u-boot-nand.lds
delete mode 100644 nand_spl/board/samsung/smdk6400/Makefile
delete mode 100644 nand_spl/board/samsung/smdk6400/config.mk
delete mode 100644 nand_spl/board/samsung/smdk6400/u-boot.lds
diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk
deleted file mode 100644
index 93a1a0d..000
--- a/board/samsung/smdk6400/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, ga...@denx.de
-# David Mueller, ELSOFT AG, d.muel...@elsoft.ch
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
-#
-# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
-#
-# see http://www.samsung.com/ for more information on SAMSUNG
-
-# On SMDK6400 we use the 64 MB SDRAM bank at
-#
-# 0x5000 to 0x5800
-#
-# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
-#
-# we load ourselves to 0x57e0 without MMU
-# with MMU, load address is changed to 0xc7e0
-#
-# download area is 0x5000c000
-
-ifndef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = $(CONFIG_RAM_TEXT)
-else
-CONFIG_SYS_TEXT_BASE = 0
-endif
diff --git a/board/samsung/smdk6400/u-boot-nand.lds
b/board/samsung/smdk6400/u-boot-nand.lds
deleted file mode 100644
index f162815..000
--- a/board/samsung/smdk6400/u-boot-nand.lds
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, ga...@denx.de
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT(elf32-littlearm, elf32-littlearm, elf32-littlearm)
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm1176/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- .mmudata : { *(.mmudata) }
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
diff --git a/boards.cfg b/boards.cfg
index 0363b41..491459a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -47,8 +47,8 @@ flea3arm arm1136 -
CarMedi
mx35pdk arm arm1136 -
freescale mx35
apollon arm arm1136 apollon
- omap24xx
omap2420h4 arm arm1136 - ti
[U-Boot] [V3 09/15] arm1176: Fixed No relocation.
From: Zhong Hongbo bocui...@gmail.com When It do not need to relocat for u-boot, the offset(r9) of relocation should be set zero. Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V3: - Replace mov with moveq. Change for V2: - Seprate some code. --- arch/arm/cpu/arm1176/start.S |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 761b7fe..dd1b73b 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -252,6 +252,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 beq clear_bss /* skip relocation */ mov r1, r6 /* r1 - scratch for copy_loop */ ldr r3, _bss_start_ofs -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [V3 10/15] S3C64XX: Change SROM init to use read/write operation
From: Zhong Hongbo bocui...@gmail.com
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V3:
- None.
Change for V2:
- Change the type of return for s3c64xx_get_base_sromc function.
---
arch/arm/cpu/arm1176/s3c64xx/Makefile |2 +-
arch/arm/cpu/arm1176/s3c64xx/srom.c | 51 +++
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 13 +++
arch/arm/include/asm/arch-s3c64xx/sromc.h | 49 +
board/samsung/smdk6400/smdk6400.c | 38 ++--
include/configs/smdk6400.h |1 +
6 files changed, 134 insertions(+), 20 deletions(-)
create mode 100644 arch/arm/cpu/arm1176/s3c64xx/srom.c
create mode 100644 arch/arm/include/asm/arch-s3c64xx/sromc.h
diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile
b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 2f37431..28786bf 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -30,7 +30,7 @@ LIB = $(obj)lib$(SOC).o
SOBJS = reset.o
-COBJS-$(CONFIG_S3C64XX)+= speed.o
+COBJS-$(CONFIG_S3C64XX)+= speed.o srom.o
COBJS-y+= timer.o
COBJS-$(CONFIG_PWM) += pwm.o
diff --git a/arch/arm/cpu/arm1176/s3c64xx/srom.c
b/arch/arm/cpu/arm1176/s3c64xx/srom.c
new file mode 100644
index 000..f1b2b34
--- /dev/null
+++ b/arch/arm/cpu/arm1176/s3c64xx/srom.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2012
+ * Zhong Hongbo bocui1...@gmail.com
+ * base on arch/arm/cpu/armv7/s5p-common/sromc.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/sromc.h
+#include asm/arch/s3c6400.h
+/*
+ * s3c64xx_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank - SROM
+ * srom_bw_conf - SMC Band witdh reg configuration value
+ * srom_bc_conf - SMC Bank Control reg configuration value
+ */
+void s3c64xx_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
+{
+ u32 tmp;
+ struct s3c64xx_sromc *srom =
+ (struct s3c64xx_sromc *)s3c64xx_get_base_sromc();
+
+ /* Configure SMC_BW register to handle proper SROMC bank */
+ tmp = srom-bw;
+ tmp = ~(0xF (srom_bank * 4));
+ tmp |= srom_bw_conf;
+
+ writel(tmp, srom-bw);
+
+ /* Configure SMC_BC register */
+ writel(srom_bc_conf, srom-bc[srom_bank]);
+}
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index b884763..d2ee9d2 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -471,14 +471,6 @@
*/
#define ELFIN_SROM_BASE0x7000
-#define SROM_BW_REG__REG(ELFIN_SROM_BASE + 0x0)
-#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4)
-#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8)
-#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC)
-#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10)
-#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14)
-#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18)
-
/*
* SDRAM Controller
*/
@@ -722,6 +714,11 @@ static inline unsigned long s3c64xx_get_base_timer(void)
{
return ELFIN_TIMER_BASE;
}
+
+static inline unsigned long s3c64xx_get_base_sromc(void)
+{
+ return ELFIN_SROM_BASE;
+}
#endif
#endif /*__S3C6400_H__*/
diff --git a/arch/arm/include/asm/arch-s3c64xx/sromc.h
b/arch/arm/include/asm/arch-s3c64xx/sromc.h
new file mode 100644
index 000..fcad635
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/sromc.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2012
+ * Zhong Hongbo bocui...@gmail.com
+ *
+ * base on arch/arm/include/asm/arch-s5pc1xx/sromc.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
[U-Boot] [V3 11/15] S3C64XX: Switch to use read/writel to operation clock system
From: Zhong Hongbo bocui...@gmail.com
Switch to use read/writel function and clear the relevant variable.
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V3:
- Use C language to re-write reset function.
- Replace the magic numbers witch variale name.
Change for V2:
- merge clock patch.
- Change the type of return for s3c64xx_get_base_clock function.
---
arch/arm/cpu/arm1176/s3c64xx/Makefile |6 +-
arch/arm/cpu/arm1176/s3c64xx/reset.S| 34
arch/arm/cpu/arm1176/s3c64xx/reset.c| 39 +
arch/arm/cpu/arm1176/s3c64xx/speed.c| 50 +--
arch/arm/include/asm/arch-s3c64xx/clock.h | 163
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 219 +--
board/samsung/smdk6400/lowlevel_init.S |3 +
board/samsung/smdk6400/setup.h | 47 ++
drivers/usb/host/s3c64xx-hcd.c | 30 -
9 files changed, 321 insertions(+), 270 deletions(-)
delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/reset.S
create mode 100644 arch/arm/cpu/arm1176/s3c64xx/reset.c
create mode 100644 arch/arm/include/asm/arch-s3c64xx/clock.h
create mode 100644 board/samsung/smdk6400/setup.h
diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile
b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 28786bf..16be887 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -28,13 +28,11 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
-SOBJS = reset.o
-
-COBJS-$(CONFIG_S3C64XX)+= speed.o srom.o
+COBJS-$(CONFIG_S3C64XX)+= speed.o srom.o reset.o
COBJS-y+= timer.o
COBJS-$(CONFIG_PWM) += pwm.o
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+OBJS := $(addprefix $(obj), $(COBJS-y))
all: $(obj).depend $(START) $(LIB)
diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.S
b/arch/arm/cpu/arm1176/s3c64xx/reset.S
deleted file mode 100644
index eae572e..000
--- a/arch/arm/cpu/arm1176/s3c64xx/reset.S
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang mk7.k...@samsung.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include asm/arch/s3c6400.h
-
-.globl reset_cpu
-reset_cpu:
- ldr r1, =ELFIN_CLOCK_POWER_BASE
- ldr r2, [r1, #SYS_ID_OFFSET]
- ldr r3, =0x
- and r2, r3, r2, lsr #12
- str r2, [r1, #SW_RST_OFFSET]
-_loop_forever:
- b _loop_forever
diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.c
b/arch/arm/cpu/arm1176/s3c64xx/reset.c
new file mode 100644
index 000..773cffa
--- /dev/null
+++ b/arch/arm/cpu/arm1176/s3c64xx/reset.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2012
+ * Zhong Hongbo bocui...@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/s3c6400.h
+#include asm/arch/clock.h
+
+void reset_cpu(ulong addr)
+{
+ unsigned long sys_id;
+ struct s3c64xx_clock *clk =
+ (struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+ sys_id = readl(clk-sys_id);
+ sys_id = 12;
+ sys_id = 0x;
+ writel(sys_id, clk-sw_rst);
+}
diff --git a/arch/arm/cpu/arm1176/s3c64xx/speed.c
b/arch/arm/cpu/arm1176/s3c64xx/speed.c
index 11962ac..05b44b9 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/speed.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/speed.c
@@ -31,12 +31,13 @@
*/
#include common.h
[U-Boot] [V3 12/15] S3c64xx: clear GPIO, Interrupt, Watchdog variable.
From: Zhong Hongbo bocui...@gmail.com Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V3: - Replace the magic numbers with the variable name. Change for V2: - None. --- arch/arm/include/asm/arch-s3c64xx/gpio.h | 38 arch/arm/include/asm/arch-s3c64xx/interrupt.h | 31 +++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 258 - board/samsung/smdk6400/lowlevel_init.S| 16 +- board/samsung/smdk6400/setup.h| 11 +- 5 files changed, 86 insertions(+), 268 deletions(-) create mode 100644 arch/arm/include/asm/arch-s3c64xx/gpio.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/interrupt.h diff --git a/arch/arm/include/asm/arch-s3c64xx/gpio.h b/arch/arm/include/asm/arch-s3c64xx/gpio.h new file mode 100644 index 000..979173c --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/gpio.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2012 + * Zhong Hongbo bocui...@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_GPIO_H_ +#define __ASM_ARM_ARCH_GPIO_H_ + +#define GPACON_OFFSET 0x00 +#define GPADAT_OFFSET 0x04 +#define GPAPUD_OFFSET 0x08 + +#define GPNCON_OFFSET 0x830 +#define GPNDAT_OFFSET 0x834 +#define GPNPUD_OFFSET 0x838 + +#define GPKCON0_OFFSET 0x800 +#define GPKCON1_OFFSET 0x804 +#define GPKDAT_OFFSET 0x808 +#define GPKPUD_OFFSET 0x80C + +#endif diff --git a/arch/arm/include/asm/arch-s3c64xx/interrupt.h b/arch/arm/include/asm/arch-s3c64xx/interrupt.h new file mode 100644 index 000..49e3ae4 --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/interrupt.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2012 + * Zhong Hongbo bocui...@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_INTERRUPT_H_ +#define __ASM_ARM_ARCH_INTERRUPT_H_ + +#define INTMOD 0x0C/* VIC INT SELECT (IRQ or FIQ) */ +#define INTUNMSK 0x10/* VIC INT EN (write 1 to unmask) */ +#define INTMSK 0x14/* VIC INT EN CLEAR (write 1 to mask) */ +#define INTSUBMSK 0x1C/* VIC SOFT INT CLEAR */ +#define VECTADDR 0xF00 /* VIC ADDRESS */ +#define EINTPEND_OFFSET0x924 +#endif diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h index b1537c1..1da327a 100644 --- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h +++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h @@ -47,172 +47,6 @@ */ #define ELFIN_GPIO_BASE0x7f008000 -#define GPACON_OFFSET 0x00 -#define GPADAT_OFFSET 0x04 -#define GPAPUD_OFFSET 0x08 -#define GPACONSLP_OFFSET 0x0C -#define GPAPUDSLP_OFFSET 0x10 -#define GPBCON_OFFSET 0x20 -#define GPBDAT_OFFSET 0x24 -#define GPBPUD_OFFSET 0x28 -#define GPBCONSLP_OFFSET 0x2C -#define GPBPUDSLP_OFFSET 0x30 -#define GPCCON_OFFSET 0x40 -#define GPCDAT_OFFSET 0x44 -#define GPCPUD_OFFSET 0x48 -#define GPCCONSLP_OFFSET 0x4C -#define GPCPUDSLP_OFFSET 0x50 -#define GPDCON_OFFSET 0x60 -#define GPDDAT_OFFSET 0x64 -#define GPDPUD_OFFSET 0x68 -#define GPDCONSLP_OFFSET 0x6C -#define GPDPUDSLP_OFFSET 0x70 -#define GPECON_OFFSET 0x80 -#define GPEDAT_OFFSET 0x84 -#define GPEPUD_OFFSET 0x88 -#define GPECONSLP_OFFSET 0x8C -#define GPEPUDSLP_OFFSET 0x90 -#define GPFCON_OFFSET 0xA0 -#define GPFDAT_OFFSET 0xA4 -#define GPFPUD_OFFSET
[U-Boot] [V3 13/15] S3C6400: clear memory init variable
From: Zhong Hongbo bocui...@gmail.com
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V3:
- Replace the magic numbers with variable name.
- Use C language to implement memory initialization.
Change for V2:
- None.
---
arch/arm/include/asm/arch-s3c64xx/dmc.h | 62 +
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 178 +--
board/samsung/smdk6400/Makefile |3 +-
board/samsung/smdk6400/dmc_init.c | 110 +
board/samsung/smdk6400/lowlevel_init.S |2 +-
board/samsung/smdk6400/mem_init.S | 135
board/samsung/smdk6400/setup.h | 85 +
7 files changed, 265 insertions(+), 310 deletions(-)
create mode 100644 arch/arm/include/asm/arch-s3c64xx/dmc.h
create mode 100644 board/samsung/smdk6400/dmc_init.c
delete mode 100644 board/samsung/smdk6400/mem_init.S
diff --git a/arch/arm/include/asm/arch-s3c64xx/dmc.h
b/arch/arm/include/asm/arch-s3c64xx/dmc.h
new file mode 100644
index 000..758e750
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/dmc.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2012
+ * Zhong Hongbo bocui...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef __ASM_ARCH_DMC_H__
+#define __ASM_ARCH_DMC_H__
+
+#ifndef __ASSEMBLY__
+
+struct s3c64xx_dmc {
+ unsigned intmemstat;
+ unsigned intmemcmd;
+ unsigned intdirectcmd;
+ unsigned intmemcfg;
+ unsigned intrefresh;
+ unsigned intcaslat;
+ unsigned intt_dqss;
+ unsigned intt_mrd;
+ unsigned intt_ras;
+ unsigned intt_rc;
+ unsigned intt_rcd;
+ unsigned intt_rfc;
+ unsigned intt_rp;
+ unsigned intt_rrd;
+ unsigned intt_wr;
+ unsigned intt_wtr;
+ unsigned intt_xp;
+ unsigned intt_xsr;
+ unsigned intt_esr;
+ unsigned intmemcfg2;
+#if defined(CONFIG_S3C6410)
+ unsigned intmemcfg3;
+ unsigned char res1[0xac];
+#else
+ unsigned char res1[0xb0];
+#endif
+ unsigned intid_0_cfg[16];
+ unsigned char res2[0xc0];
+ unsigned intchip_0_cfg;
+ unsigned intchip_1_cfg;
+ unsigned char res3[0xf8];
+ unsigned intuser_status;
+ unsigned intuser_config;
+};
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 1da327a..45a8918 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -41,191 +41,18 @@
#include asm/hardware.h
#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
-
-/*
- * GPIO
- */
#define ELFIN_GPIO_BASE0x7f008000
-
-/*
- * Bus Matrix
- */
#define ELFIN_MEM_SYS_CFG 0x7e00f120
-
-#define S3C64XX_MEM_SYS_CFG_16BIT (1 12)
-
-#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
-
-/*
- * Memory controller
- */
#define ELFIN_SROM_BASE0x7000
-
-/*
- * SDRAM Controller
- */
#define ELFIN_DMC0_BASE0x7e00
#define ELFIN_DMC1_BASE0x7e001000
-
-#define INDEX_DMC_MEMC_STATUS 0x00
-#define INDEX_DMC_MEMC_CMD 0x04
-#define INDEX_DMC_DIRECT_CMD 0x08
-#define INDEX_DMC_MEMORY_CFG 0x0C
-#define INDEX_DMC_REFRESH_PRD 0x10
-#define INDEX_DMC_CAS_LATENCY 0x14
-#define INDEX_DMC_T_DQSS 0x18
-#define INDEX_DMC_T_MRD0x1C
-#define INDEX_DMC_T_RAS0x20
-#define INDEX_DMC_T_RC 0x24
-#define INDEX_DMC_T_RCD0x28
-#define INDEX_DMC_T_RFC0x2C
-#define INDEX_DMC_T_RP 0x30
-#define INDEX_DMC_T_RRD0x34
-#define INDEX_DMC_T_WR 0x38
-#define INDEX_DMC_T_WTR0x3C
-#define INDEX_DMC_T_XP 0x40
-#define INDEX_DMC_T_XSR0x44
-#define INDEX_DMC_T_ESR0x48
-#define INDEX_DMC_MEMORY_CFG2 0x4C
-#define INDEX_DMC_CHIP_0_CFG 0x200
-#define INDEX_DMC_CHIP_1_CFG 0x204
-#define INDEX_DMC_CHIP_2_CFG 0x208
-#define INDEX_DMC_CHIP_3_CFG 0x20C
-#define INDEX_DMC_USER_STATUS 0x300
-#define INDEX_DMC_USER_CONFIG 0x304
-
-/*
- * Memory Chip direct command
- */
-#define DMC_NOP0
[U-Boot] [V3 14/15] S3C64XX: Move s3c6400.h to cpu.h to support s3c6410 board
From: Zhong Hongbo bocui...@gmail.com Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V3: - Replace ELFIN with S3C64XX for all the variable of cpu.h - Change __S3C6400_H__ into __CPU__H__ Change for V2: - New. --- arch/arm/cpu/arm1176/s3c64xx/pwm.c |2 +- arch/arm/cpu/arm1176/s3c64xx/reset.c|2 +- arch/arm/cpu/arm1176/s3c64xx/speed.c|2 +- arch/arm/cpu/arm1176/s3c64xx/srom.c |2 +- arch/arm/cpu/arm1176/s3c64xx/timer.c|2 +- arch/arm/include/asm/arch-s3c64xx/cpu.h | 89 +++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 89 --- board/samsung/smdk6400/dmc_init.c |2 +- board/samsung/smdk6400/lowlevel_init.S | 26 board/samsung/smdk6400/smdk6400.c |2 +- drivers/mtd/nand/s3c64xx.c |2 +- drivers/serial/s3c64xx.c|2 +- drivers/usb/host/s3c64xx-hcd.c |2 +- 13 files changed, 112 insertions(+), 112 deletions(-) create mode 100644 arch/arm/include/asm/arch-s3c64xx/cpu.h delete mode 100644 arch/arm/include/asm/arch-s3c64xx/s3c6400.h diff --git a/arch/arm/cpu/arm1176/s3c64xx/pwm.c b/arch/arm/cpu/arm1176/s3c64xx/pwm.c index d46470a..004dcd8 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/pwm.c +++ b/arch/arm/cpu/arm1176/s3c64xx/pwm.c @@ -28,7 +28,7 @@ #include errno.h #include pwm.h #include asm/io.h -#include asm/arch/s3c6400.h +#include asm/arch/cpu.h #include asm/arch/pwm.h int pwm_enable(int pwm_id) diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.c b/arch/arm/cpu/arm1176/s3c64xx/reset.c index 773cffa..03cb306 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/reset.c +++ b/arch/arm/cpu/arm1176/s3c64xx/reset.c @@ -23,7 +23,7 @@ #include common.h #include asm/io.h -#include asm/arch/s3c6400.h +#include asm/arch/cpu.h #include asm/arch/clock.h void reset_cpu(ulong addr) diff --git a/arch/arm/cpu/arm1176/s3c64xx/speed.c b/arch/arm/cpu/arm1176/s3c64xx/speed.c index 05b44b9..5e68090 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/speed.c +++ b/arch/arm/cpu/arm1176/s3c64xx/speed.c @@ -32,7 +32,7 @@ #include common.h #include asm/io.h -#include asm/arch/s3c6400.h +#include asm/arch/cpu.h #include asm/arch/clock.h #define APLL 0 diff --git a/arch/arm/cpu/arm1176/s3c64xx/srom.c b/arch/arm/cpu/arm1176/s3c64xx/srom.c index f1b2b34..92fb7af 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/srom.c +++ b/arch/arm/cpu/arm1176/s3c64xx/srom.c @@ -25,7 +25,7 @@ #include common.h #include asm/io.h #include asm/arch/sromc.h -#include asm/arch/s3c6400.h +#include asm/arch/cpu.h /* * s3c64xx_config_sromc() - select the proper SROMC Bank and configure the * band width control and bank control registers diff --git a/arch/arm/cpu/arm1176/s3c64xx/timer.c b/arch/arm/cpu/arm1176/s3c64xx/timer.c index 47d7731..eebd0c0 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/timer.c +++ b/arch/arm/cpu/arm1176/s3c64xx/timer.c @@ -25,7 +25,7 @@ #include common.h #include asm/io.h -#include asm/arch/s3c6400.h +#include asm/arch/cpu.h #include asm/arch/pwm.h #include pwm.h diff --git a/arch/arm/include/asm/arch-s3c64xx/cpu.h b/arch/arm/include/asm/arch-s3c64xx/cpu.h new file mode 100644 index 000..90c5328 --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/cpu.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2007 + * Byungjae Lee, Samsung Erectronics, bj...@samsung.com. + * - only support for S3C6400 + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/ + * NAME: cpu.h + * + * Based on S3C6400 User's manual Rev 0.0 + / + +#ifndef __CPU_H__ +#define __CPU_H__ + +#if defined(CONFIG_SYNC_MODE) defined(CONFIG_S3C6400) +#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! +#endif + +#define S3C64XX_UART_CHANNELS 3 +#define S3C64XX_SPI_CHANNELS 2 + +#include asm/hardware.h + +#define S3C64XX_CLOCK_POWER_BASE 0x7e00f000 +#define S3C64XX_GPIO_BASE 0x7f008000 +#define S3C64XX_MEM_SYS_CFG0x7e00f120 +#define S3C64XX_SROM_BASE 0x7000 +#define
[U-Boot] [V3 15/15] S3C6400: Remove the unused variable for S3C6400
From: Zhong Hongbo bocui...@gmail.com Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V3: - None. Change for V2: - None. --- include/configs/smdk6400.h | 15 --- 1 files changed, 0 insertions(+), 15 deletions(-) diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index fa5b1c5..2b49647 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -108,9 +108,6 @@ #define CONFIG_CMD_LOADB #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NAND -#if defined(CONFIG_BOOT_ONENAND) -#define CONFIG_CMD_ONENAND -#endif #define CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT @@ -266,13 +263,6 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63} -/* None of these are currently implemented. Left from the original Samsung - * version for reference -#define CONFIG_BOOT_NOR -#define CONFIG_BOOT_MOVINAND -#define CONFIG_BOOT_ONENAND -*/ - #define CONFIG_SPL #define CONFIG_SPL_NAND #define CONFIG_SPL_NAND_SIMPLE @@ -283,11 +273,6 @@ #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_NAND_S3C64XX -/* Unimplemented or unsupported. See comment above. -#define CONFIG_ONENAND -#define CONFIG_MOVINAND -*/ - /* Settings as above boot configuration */ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_BOOTARGSconsole=ttySAC,115200 -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [u-boot-arm/next RESEND PATCH 0/3] OMAP3: igep00x0: add nand flash and SPL support
IGEP-based boards can have two different flash memories, a OneNAND or a NAND device. Since u-boot still lacks of a device model to be the able to look at run-time which memory type is available on a the board, a built time config option is needed to choose which memory to use. This is a resend of a patch-set that adds both a config option for the nand memory type and SPL support to IGEP-based boards. The patch-set is composed of the following patches: [u-boot-arm/next RESEND PATCH 1/3] OMAP3: igep00x0: Add config [u-boot-arm/next RESEND PATCH 2/3] OMAP3: mem: Add Numonyx OneNAND [u-boot-arm/next RESEND PATCH 3/3] OMAP3: igep00x0: add SPL support Best regards, Javier ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [u-boot-arm/next RESEND PATCH 1/3] OMAP3: igep00x0: Add config option to choose flash storage memory
IGEP-based boards can have two different flash memories, a OneNAND or a
NAND device. Add a configuration option for to choose which memory to use.
Signed-off-by: Javier Martinez Canillas jav...@dowhile0.org
Acked-by: Enric Balletbo i Serra eballe...@gmail.com
---
board/isee/igep0020/igep0020.h |4
board/isee/igep0030/igep0030.h |4
boards.cfg |6 --
include/configs/igep00x0.h | 19 +++
4 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h
index 3d6e15f..3335ecc 100644
--- a/board/isee/igep0020/igep0020.h
+++ b/board/isee/igep0020/igep0020.h
@@ -26,7 +26,11 @@
const omap3_sysinfo sysinfo = {
DDR_STACKED,
IGEP v2 board,
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
ONENAND,
+#else
+ NAND,
+#endif
};
static void setup_net_chip(void);
diff --git a/board/isee/igep0030/igep0030.h b/board/isee/igep0030/igep0030.h
index b7ce5aa..a93339d 100644
--- a/board/isee/igep0030/igep0030.h
+++ b/board/isee/igep0030/igep0030.h
@@ -26,7 +26,11 @@
const omap3_sysinfo sysinfo = {
DDR_STACKED,
OMAP3 IGEP module,
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
ONENAND,
+#else
+ NAND,
+#endif
};
/*
diff --git a/boards.cfg b/boards.cfg
index 9efdc6d..7463896 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -224,8 +224,10 @@ cm_t35 arm armv7
cm_t35 -
omap3_overo arm armv7 overo -
omap3
omap3_pandoraarm armv7 pandora -
omap3
dig297 arm armv7 dig297
comelitomap3
-igep0020 arm armv7 igep0020isee
omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020
-igep0030 arm armv7 igep0030isee
omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030
+igep0020 arm armv7 igep0020isee
omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND
+igep0020_nandarm armv7 igep0020isee
omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND
+igep0030 arm armv7 igep0030isee
omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
+igep0030_nandarm armv7 igep0030isee
omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
am3517_evm arm armv7 am3517evm
logicpdomap3
mt_ventoux arm armv7 mt_ventoux
teejet omap3
omap3_zoom1 arm armv7 zoom1
logicpdomap3
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index a0a23a7..d8e87c3 100644
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -105,7 +105,12 @@
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
+#ifdef CONFIG_BOOT_ONENAND
#define CONFIG_CMD_ONENAND /* ONENAND support */
+#endif
+#ifdef CONFIG_BOOT_NAND
+#define CONFIG_CMD_NAND
+#endif
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot*/
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
@@ -244,6 +249,7 @@
* FLASH and environment organization
*/
+#ifdef CONFIG_BOOT_ONENAND
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
#define CONFIG_SYS_ONENAND_BASEONENAND_MAP
@@ -253,6 +259,19 @@
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_SIZE(512 10) /* Total Size
Environment */
#define CONFIG_ENV_ADDRONENAND_ENV_OFFSET
+#endif
+
+#ifdef CONFIG_BOOT_NAND
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_BASE NAND_BASE
+#define GPMC_NAND_ECC_LP_x16_LAYOUT1
+#define CONFIG_ENV_OFFSET 0x26 /* environment starts here */
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SIZE(512 10) /* Total Size
Environment */
+#define CONFIG_ENV_ADDRNAND_ENV_OFFSET
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#endif
/*
* Size of malloc() pool
--
1.7.7.6
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[U-Boot] [u-boot-arm/next RESEND PATCH 3/3] OMAP3: igep00x0: add SPL support for IGEP-based boards
This patch adds SPL support for IGEP-based boards.
Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory.
Signed-off-by: Javier Martinez Canillas jav...@dowhile0.org
---
board/isee/igep0020/config.mk | 33
board/isee/igep0020/igep0020.c | 42 +-
board/isee/igep0030/config.mk | 33
board/isee/igep0030/igep0030.c | 42 +-
include/configs/igep00x0.h | 65
5 files changed, 147 insertions(+), 68 deletions(-)
delete mode 100644 board/isee/igep0020/config.mk
delete mode 100644 board/isee/igep0030/config.mk
diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk
deleted file mode 100644
index 7964621..000
--- a/board/isee/igep0020/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2009
-# ISEE 2007 SL, www.iseebcn.com
-#
-# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# Physical Address:
-# 8000' (bank0)
-# A000/ (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
index 971e31b..a4d099a 100644
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep0020/igep0020.c
@@ -58,6 +58,46 @@ int board_init(void)
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: omap_rev_string
+ * Description: For SPL builds output board rev
+ */
+void omap_rev_string(void)
+{
+}
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
+ u32 *mr)
+{
+ *mr = MICRON_V_MR_165;
+#ifdef CONFIG_BOOT_NAND
+ *mcfg = MICRON_V_MCFG_200(512 20);
+ *ctrla = MICRON_V_ACTIMA_200;
+ *ctrlb = MICRON_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+#else
+ if (get_cpu_family() == CPU_OMAP34XX) {
+ *mcfg = NUMONYX_V_MCFG_165(512 20);
+ *ctrla = NUMONYX_V_ACTIMA_165;
+ *ctrlb = NUMONYX_V_ACTIMB_165;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+ } else {
+ *mcfg = NUMONYX_V_MCFG_200(512 20);
+ *ctrla = NUMONYX_V_ACTIMA_200;
+ *ctrlb = NUMONYX_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ }
+#endif
+}
+#endif
+
/*
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
@@ -91,7 +131,7 @@ static void setup_net_chip(void)
}
#endif
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0, 0, 0);
diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk
deleted file mode 100644
index 059a878..000
--- a/board/isee/igep0030/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2009
-# ISEE 2007 SL, www.iseebcn.com
-#
-# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# Physical Address:
-#
[U-Boot] [u-boot-arm/next RESEND PATCH 2/3] OMAP3: mem: Add Numonyx OneNAND 200MHz timing information
Signed-off-by: Javier Martinez Canillas jav...@dowhile0.org
---
arch/arm/include/asm/arch-omap3/mem.h | 29 +
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap3/mem.h
b/arch/arm/include/asm/arch-omap3/mem.h
index 9f6992a..12dcf4e 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -294,6 +294,35 @@ enum {
#define NUMONYX_RASWIDTH_165 15
#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
+/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
+#define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck*/
+ /* 15/5 + 15/5 = 3 + 3 - 6 */
+#define NUMONYX_TDPL_200 3 /* 15/5 = 3 - 3 (Twr) */
+#define NUMONYX_TRRD_200 2 /* 10/5 = 2 */
+#define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 - 4 */
+#define NUMONYX_TRP_2003 /* 15/5 = 3
*/
+#define NUMONYX_TRAS_200 8 /* 40/5 = 8 */
+#define NUMONYX_TRC_20011 /* 55/5 = 11
*/
+#define NUMONYX_TRFC_20028 /* 140/5 = 28 */
+
+#define NUMONYX_V_ACTIMA_200 \
+ ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \
+ NUMONYX_TRAS_200, NUMONYX_TRP_200, \
+ NUMONYX_TRCD_200, NUMONYX_TRRD_200, \
+ NUMONYX_TDPL_200, NUMONYX_TDAL_200)
+
+#define NUMONYX_TWTR_200 2
+#define NUMONYX_TCKE_200 2
+#define NUMONYX_TXP_2003
+#define NUMONYX_XSR_20040
+
+#define NUMONYX_V_ACTIMB_200 \
+ ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \
+ NUMONYX_TXP_200, NUMONYX_XSR_200)
+
+#define NUMONYX_RASWIDTH_200 15
+#define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200)
+
/*
* GPMC settings -
* Definitions is as per the following format
--
1.7.7.6
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[U-Boot] dwc_ahsata vs ahci
Hi, While working on the DM project, I found out that there are two implementations of AHCI drivers - one in block/ahci.c, one in block/dwc_ahsata.c what is the difference between them (apart from the obvious, ahci.c exposes SCSI API, dwc_ahsata exposes SATA API)? are there any problems that would prevent me from merging them? thanks Pavel Herrmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] COMMON: Add __stringify() function
This function converts static number to string in preprocessor. This is useful as it allows higher usage of puts() in favour of printf() Signed-off-by: Marek Vasut ma...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Mike Frysinger vap...@gentoo.org --- include/common.h |7 +++ 1 file changed, 7 insertions(+) diff --git a/include/common.h b/include/common.h index d1dd65a..451917d 100644 --- a/include/common.h +++ b/include/common.h @@ -268,6 +268,13 @@ typedef void (interrupt_handler_t)(void *); const typeof( ((type *)0)-member ) *__mptr = (ptr);\ (type *)( (char *)__mptr - offsetof(type,member) );}) +/** + * __stringify - preprocessor magic to return string from number + * @x: constant number + */ +#define __stringify_1(x...) #x +#define __stringify(x...) __stringify_1(x) + /* * Function Prototypes */ -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC] [PATCH 2/2] crazy: Sort u_boot_cmd at runtime
This shall eliminate the need for bubblesorting of commands at runtime.
Every command definition structure is now put into it's own subsection
of section .u_boot_cmd, that is .u_boot_cmd.name . These are then put
into .u_boot_cmd by linker and lastly, linker uses SORT() over these
subsections to make proper order on them. This shall eliminate some
runtime overhead.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Wolfgang Denk w...@denx.de
Cc: Mike Frysinger vap...@gentoo.org
---
arch/arm/cpu/u-boot.lds |2 +-
common/cmd_help.c |2 +-
include/command.h |9 ++---
3 files changed, 8 insertions(+), 5 deletions(-)
* NOTE * THIS PATCH IS CRAZY
Further notes:
- This is only compile-tested with gcc-4.7 (debian 4.7.1-5, binutils 2.22)
- This patch affects only arm926t, obviously to make it proper, every
linkerscript would have to be adjusted
- I'm not sure at all the macro logic is correct, please check
- Can this crash on *BSD or with older linker/cpp?
- Please don't rip me limb to limb ;-)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index e49ca0c..c39193b 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -50,7 +50,7 @@ SECTIONS
. = .;
__u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+ .u_boot_cmd : { *(SORT(.u_boot_cmd.*)) }
__u_boot_cmd_end = .;
. = ALIGN(4);
diff --git a/common/cmd_help.c b/common/cmd_help.c
index 8c8178e..5d778f5 100644
--- a/common/cmd_help.c
+++ b/common/cmd_help.c
@@ -41,7 +41,7 @@ U_BOOT_CMD(
);
/* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names */
-cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
+cmd_tbl_t __u_boot_cmd_question_mark Struct_Section(?) = {
?,CONFIG_SYS_MAXARGS, 1, do_help,
alias for 'help',
#ifdef CONFIG_SYS_LONGHELP
diff --git a/include/command.h b/include/command.h
index 6e1bdc2..42b4c6a 100644
--- a/include/command.h
+++ b/include/command.h
@@ -149,8 +149,11 @@ int cmd_process(int flag, int argc, char * const argv[],
#define CMD_FLAG_REPEAT0x0001 /* repeat last command
*/
#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd*/
-#define Struct_Section __attribute__((unused, section(.u_boot_cmd), \
- aligned(4)))
+#define __sectstr(__cmd,__name).__cmd.__name
+#define sectstr(type, __name) __stringify(__sectstr(type, __name))
+
+#define Struct_Section(__name) \
+ __attribute__((unused, section(sectstr(u_boot_cmd, __name)),
aligned(4)))
#ifdef CONFIG_AUTO_COMPLETE
# define _CMD_COMPLETE(x) x,
@@ -170,7 +173,7 @@ int cmd_process(int flag, int argc, char * const argv[],
U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL)
#define U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \
- cmd_tbl_t __u_boot_cmd_##name Struct_Section = \
+ cmd_tbl_t __u_boot_cmd_##name Struct_Section(name) = \
U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp)
#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
--
1.7.10.4
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[U-Boot] early_malloc() vs. enable_caches()
Hello! I am working on early_malloc() for U-Boot Driver Model (this malloc is going to serve for internal DM structures during early init and it has it's minimalistic heap in global data). My question is how to correctly switch from early allocator to full-scale malloc and when to enable caches. The current state (on ARM) is: 1) gd = id; 3) enable_caches(); 3) mem_malloc_init(); Proposed sequence for mallocator (in order no to loose any data from old and not-relocated part of GD): 1) gd_old = gd; 2) gd = id; 3) mem_malloc_init(); 4) relocation of DM structures 5) early_malloc_disab() 6) enable_caches(); Does it make sense? It actually boils down to one fundamental question: When I have not-rellocated data locked in cache-lines, do I loose them once enable_caches() is called? Thanks, Tomas -- Tomáš Hlaváček tmshl...@gmail.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] [PATCH 2/2] crazy: Sort u_boot_cmd at runtime
Dear Marek Vasut, In message 1343483279-11572-2-git-send-email-ma...@denx.de you wrote: This shall eliminate the need for bubblesorting of commands at runtime. Every command definition structure is now put into it's own subsection of section .u_boot_cmd, that is .u_boot_cmd.name . These are then put into .u_boot_cmd by linker and lastly, linker uses SORT() over these subsections to make proper order on them. This shall eliminate some runtime overhead. Signed-off-by: Marek Vasut ma...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Mike Frysinger vap...@gentoo.org --- arch/arm/cpu/u-boot.lds |2 +- common/cmd_help.c |2 +- include/command.h |9 ++--- 3 files changed, 8 insertions(+), 5 deletions(-) Seems incomplete in several aspects: 1) what about all the non-ARM architecures and the board specific linker scripts? 2) what about removing the sort code? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Men of peace usually are [brave]. -- Spock, The Savage Curtain, stardate 5906.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] [PATCH 2/2] crazy: Sort u_boot_cmd at runtime
Dear Wolfgang Denk, Dear Marek Vasut, In message 1343483279-11572-2-git-send-email-ma...@denx.de you wrote: This shall eliminate the need for bubblesorting of commands at runtime. Every command definition structure is now put into it's own subsection of section .u_boot_cmd, that is .u_boot_cmd.name . These are then put into .u_boot_cmd by linker and lastly, linker uses SORT() over these subsections to make proper order on them. This shall eliminate some runtime overhead. Signed-off-by: Marek Vasut ma...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Mike Frysinger vap...@gentoo.org --- arch/arm/cpu/u-boot.lds |2 +- common/cmd_help.c |2 +- include/command.h |9 ++--- 3 files changed, 8 insertions(+), 5 deletions(-) Seems incomplete in several aspects: Below the section: * NOTE * THIS PATCH IS CRAZY There are a few notes. I'd actually like to know if this approach is correct at all, it might break on some crazy configurations or such. 1) what about all the non-ARM architecures and the board specific linker scripts? - This patch affects only arm926t, obviously to make it proper, every linkerscript would have to be adjusted Which sucks, since there're a lot of them. But it can probably be automated. 2) what about removing the sort code? You mean in the _do_help() in common/command.c? We can do not only that, but we can do bisect search in find_cmd_tbl() now too. I'm still trying to figure out the most optimal implementation. The current one I have trimmed down the time by roughly 60%, but I don't like it. Best regards, Wolfgang Denk Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] spi: microblaze: Adds driver for Xilinx SPI controller
Hi Michal,
I'll resubmit a new patch which fixes your notes.
br,
Stephan
Am Dienstag, den 24.07.2012, 12:56 +0200 schrieb Michal Simek:
On 07/14/2012 12:30 AM, Stephan Linz wrote:
This is an improved version of the driver patch original
submitted by Graeme Smecher graeme.smec...@mail.mcgill.ca
The changes are:
- remove hard coded Xilinx BSP defines (XPAR_SPI_*) and
use CONFIG_SYS_SPI_BASE from config.h instead
- add extensive register struct definitions
- remove offset calculation for register access and
use the new register struct instead
- move default SPI controller configuration from
spi_setup_slave() to spi_claim_bus()
- add spi_set_speed()
- insert SPI controller deactivation in spi_release_bus()
- protect while loops in spi_xfer() with counter / timeouts
- support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOP
Come from:
http://patchwork.ozlabs.org/patch/71797/
Applied with:
git apply -v --whitespace=fix --reject \
U-Boot-Adds-driver-for-Xilinx-xps_spi-SPI-controller.patch
not interesting in description.
Fix manual:
drivers/spi/Makefile
this too.
Signed-off-by: Stephan Linz l...@li-pro.net
---
drivers/spi/Makefile |1 +
drivers/spi/xilinx_spi.c | 210
++
drivers/spi/xilinx_spi.h | 135 +
3 files changed, 346 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/xilinx_spi.c
create mode 100644 drivers/spi/xilinx_spi.h
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c967d87..3ae38e5 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -44,6 +44,7 @@ COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
+COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
new file mode 100644
index 000..4d83bd3
--- /dev/null
+++ b/drivers/spi/xilinx_spi.c
@@ -0,0 +1,210 @@
+/*
+ * Xilinx SPI driver
+ *
+ * supports 8 bit SPI transfers only, with or w/o FIFO
+ *
+ * based on bfin_spi.c, by way of altera_spi.c
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ * Copyright (c) 2010 Thomas Chou tho...@wytron.com.tw
+ * Copyright (c) 2010 Graeme Smecher graeme.smec...@mail.mcgill.ca
+ * Copyright (c) 2012 Stephan Linz l...@li-pro.net
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [S]:[0]/ip_documentation/xps_spi.pdf
+ * [0]/ip_documentation/axi_spi_ds742.pdf
+ */
+#include config.h
+#include common.h
+#include malloc.h
+#include spi.h
+
+#include xilinx_spi.h
+
+#ifndef CONFIG_SYS_XILINX_SPI_LIST
+#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
+#endif
+
+#ifndef CONFIG_XILINX_SPI_IDLE_VAL
+#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
+#endif
+
+#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | \
+SPICR_MASTER_MODE | \
+SPICR_SPE)
+
+#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | \
+SPICR_MANUAL_SS)
+
+#define XILSPI_MAX_XFER_BITS 8
+
+static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
+
+__attribute__((weak))
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus ARRAY_SIZE(xilinx_spi_base_list) cs 32;
+}
+
+__attribute__((weak))
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
newline
+ writel(SPISSR_ACT(slave-cs), xilspi-regs-spissr);
+}
+
+__attribute__((weak))
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
newline
+ writel(SPISSR_OFF, xilspi-regs-spissr);
+}
+
+void spi_init(void)
+{
+ /* do nothing */
+}
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ /* xilinx spi core does not support programmable speed */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct xilinx_spi_slave *xilspi;
+ struct xilinx_spi_reg *regs;
+
+ if (!spi_cs_is_valid(bus, cs)) {
+ printf(XILSPI error: %s: unsupported bus %d / cs %d\n,
+ __func__, bus, cs);
+ return NULL;
+ }
+
+ xilspi = malloc(sizeof(*xilspi));
+ if (!xilspi) {
+ printf(XILSPI error: %s: malloc of SPI structure failed\n,
+
Re: [U-Boot] [PATCH 1/2] COMMON: Add __stringify() function
Dear Marek Vasut, In message 1343483279-11572-1-git-send-email-ma...@denx.de you wrote: This function converts static number to string in preprocessor. This is useful as it allows higher usage of puts() in favour of printf() Signed-off-by: Marek Vasut ma...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Mike Frysinger vap...@gentoo.org --- include/common.h |7 +++ 1 file changed, 7 insertions(+) We have similar things already, and we don't add dead code - you add a macro without users here. If you want to unify the use of such a macro, fine - but then please replace all ocurrences of equivalent definitions all over the code. Thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Bus error -- driver executed. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] COMMON: Add __stringify() function
Dear Wolfgang Denk, Dear Marek Vasut, In message 1343483279-11572-1-git-send-email-ma...@denx.de you wrote: This function converts static number to string in preprocessor. This is useful as it allows higher usage of puts() in favour of printf() Signed-off-by: Marek Vasut ma...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Mike Frysinger vap...@gentoo.org --- include/common.h |7 +++ 1 file changed, 7 insertions(+) We have similar things already, and we don't add dead code - you add a macro without users here. It's used in 2/2 ... what macro do you have in mind ? If you want to unify the use of such a macro, fine - but then please replace all ocurrences of equivalent definitions all over the code. Thanks. Best regards, Wolfgang Denk Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] [PATCH 2/2] crazy: Sort u_boot_cmd at runtime
Dear Marek Vasut, In message 201207282039.34518.ma...@denx.de you wrote: Seems incomplete in several aspects: Below the section: * NOTE * THIS PATCH IS CRAZY Then what is actually the purpose of such a posting? Just dumping unsorted thoughts to community? You are experienced enough to know what would be needed for a semi-clean patch, even if it's just for RFC... There are a few notes. I'd actually like to know if this approach is correct at all, it might break on some crazy configurations or such. Define correct. It may be possible - but what would be the advantage? Which problem does it solve? In which way is it better than the current code? 1) what about all the non-ARM architecures and the board specific linker scripts? - This patch affects only arm926t, obviously to make it proper, every linkerscript would have to be adjusted Which sucks, since there're a lot of them. But it can probably be automated. Actually I doubt it makes sense at all. I envision a situation where some pluggable code (say, a standalone application, or some form of loadable module whatever) can add new commands - it would be nice if these would still appear in sorted order, but this cannot be done at compile-time. So please explain which actual problem you are rying to solve. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de It [being a Vulcan] means to adopt a philosophy, a way of life which is logical and beneficial. We cannot disregard that philosophy merely for personal gain, no matter how important that gain might be. -- Spock, Journey to Babel, stardate 3842.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] COMMON: Add __stringify() function
Dear Marek Vasut, In message 201207282139.05998.ma...@denx.de you wrote: include/common.h |7 +++ 1 file changed, 7 insertions(+) We have similar things already, and we don't add dead code - you add a macro without users here. It's used in 2/2 ... what macro do you have in mind ? Then add it with the patch that uses it. As for existing use, see for example arch/powerpc/include/asm/processor.h:#define stringify(s) tostring(s) drivers/mtd/ubi/build.c:#include linux/stringify.h include/configs/km/keymile-common.h:#define xstr(s) str(s) include/configs/imx27lite-common.h:#define xstr(s) str(s) include/configs/tx25.h:#define xstr(s) str(s) include/configs/mx35pdk.h:#define xstr(s) str(s) include/configs/cam_enc_4xx.h:#define xstr(s) str(s) include/configs/ea20.h:#define xstr(s) str(s) include/configs/MPC8308RDB.h:#define xstr(s)str(s) include/configs/mpc8308_p1m.h:#define xstr(s) str(s) include/configs/flea3.h:#define xstr(s) str(s) include/configs/enbw_cmc.h:#define xstr(s) str(s) include/configs/at91sam9263ek.h:#define xstr(s) str(s) include/configs/amcc-common.h:#define xstr(s) str(s) include/configs/tam3517-common.h:#define xstr(s)str(s) include/configs/manroland/common.h:#define xstr(s) str(s) include/configs/qong.h:#define xstr(s) str(s) include/configs/ima3-mx53.h:#define xstr(s) str(s) If you want to unify the use of such a macro, fine - but then please replace all ocurrences of equivalent definitions all over the code. All these above (and any I eventually didn't find) should be replaced, then. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de In the bathtub of history the truth is harder to hold than the soap, and much more difficult to find ... - Terry Pratchett, _Sourcery_ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mx28evk kernel does not boot with 2012.07-rc3
On Fri, Jul 27, 2012 at 3:14 PM, Fabio Estevam feste...@gmail.com wrote: Bytes transferred = 3343968 (330660 hex) ## Booting kernel from Legacy Image at 4200 ... Image Name: Linux-3.5.0-next-20120727+ Created: 2012-07-27 17:27:30 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size:3343904 Bytes = 3.2 MiB Load Address: 80008000 Entry Point: 80008000 My mistake: I was working with mx31 previously which has this LOADADDR. Using the correct LOADADDR for mx28 makes the kernel to boot just fine on 2012.07-rc3. Sorry for the noise. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Building u-boot for iMX28 and getting error in mkimage of missing command line parameter CONFIG_IMX_CONFIG
On Fri, Jul 27, 2012 at 3:15 PM, Fabio Estevam feste...@gmail.com wrote: On Fri, Jul 27, 2012 at 12:35 PM, Bill bsou...@techsi.com wrote: Thanks. I tried that and got the same results. Are there any debug/logging that I can use to see what's going on? I just tried it here and 2012.07-rc3 does not boot for me too. I was using the wrong LOADADDR for mx28, and that's the reason it did not boot. What is the error you are seeing? Can you post your log? Here is the log on 2012.07-rc3: ... U-Boot 2012.07-rc3 (Jul 28 2012 - 17:08:24) Freescale i.MX28 family at 454 MHz BOOT: SSP SD/MMC #0, 3V3 I2C: ready DRAM: 128 MiB MMC: MXS MMC: 0 In:serial Out: serial Err: serial Net: FEC0, FEC1 Hit any key to stop autoboot: 0 Using FEC0 device TFTP from server 192.168.1.1; our IP address is 192.168.1.2 Filename 'uImage'. Load address: 0x4200 Loading: # # # # # # # ## done Bytes transferred = 2358008 (23faf8 hex) ## Booting kernel from Legacy Image at 4200 ... Image Name: Linux-3.5.0-next-20120727-4- Created: 2012-07-28 20:06:58 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size:2357944 Bytes = 2.2 MiB Load Address: 40008000 Entry Point: 40008000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... Uncompressing Linux... done, booting the kernel. [0.00] Booting Linux on physical CPU 0 [0.00] Linux version 3.5.0-next-20120727-4-gef9b4ac (fabio@fabio-Latitude-E6410) (gcc version 4.4.4 (4.4.4_09.06.2010) ) #1309 Sat Jul 28 17:06:52 [0.00] CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177 [0.00] CPU: VIVT data cache, VIVT instruction cache [0.00] Machine: Freescale MX28 EVK [0.00] Memory policy: ECC disabled, Data cache writeback [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 [0.00] Kernel command line: console=ttyAMA0 root=/dev/nfs ip=dhcp nfsroot=192.168.1.1:/tftpboot/ltib,v3,tcp [0.00] PID hash table entries: 512 (order: -1, 2048 bytes) [0.00] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [0.00] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [0.00] Memory: 128MB = 128MB total [0.00] Memory: 119808k/119808k available, 11264k reserved, 0K highmem [0.00] Virtual kernel memory layout: ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mx28evk kernel does not boot with 2012.07-rc3
Hi Wolfgang, On Fri, Jul 27, 2012 at 4:43 PM, Wolfgang Denk w...@denx.de wrote: I understand we put the release on hold until I hear from you / see a patch / pull request ? Please go ahead with the release. It was an operator error from my side. 2012.07-rc3 boots the kernel correctly on mx28evk. Thanks, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mx28evk kernel does not boot with 2012.07-rc3
Dear Fabio, In message caomzo5cahcapwv0gmryo1fdeauwos7vyqlfvgss4u8djk88...@mail.gmail.com you wrote: I understand we put the release on hold until I hear from you / see a patch / pull request ? Please go ahead with the release. It was an operator error from my side. 2012.07-rc3 boots the kernel correctly on mx28evk. Thanks for the feedback! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de f u cn rd ths, u cn gt a gd jb n cmptr prgrmmng. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot-DM] [PATCH 1/1] early_malloc() introduced to ARM architecture
Dear Tomas Hlavacek,
I think we should still mark early patches as RFC.
early_malloc() introduced to ARM architecture (it is a proof of concept).
GD datastructure extended for holding early-heap.
mem_malloc_init() in board_init_r() has been put up by few lines.
I take it was sent by the gmail webIF ? Like WD said, not a good idea, git send-
email is really the way. it's actually simple, we can discuss that tomorrow.
Signed-off-by: Tomas Hlavacek tmshl...@gmail.com
---
arch/arm/include/asm/global_data.h |4 +-
arch/arm/lib/board.c | 32 +--
common/Makefile|1 +
common/earlymalloc.c | 102
include/common.h |1 +
include/earlymalloc.h | 84 +
lib/asm-offsets.c |2 +-
7 files changed, 220 insertions(+), 6 deletions(-)
create mode 100644 common/earlymalloc.c
create mode 100644 include/earlymalloc.h
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index c3ff789..215212a 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -30,7 +30,8 @@
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE
sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE
+ * sizeof(gd_t) + EARLY_HEAP_SIZE
*/
typedefstructglobal_data {
@@ -86,6 +87,7 @@ typedefstructglobal_data {
#endif
} gd_t;
+
Ok well ... you know, this will need cleanup. But for RFC, this is OK.
/*
* Global Data Flags
*/
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 500e216..81ee27b 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -52,6 +52,7 @@
#include fdtdec.h
#include post.h
#include logbuff.h
+#include earlymalloc.h
Do we need early_malloc.h at all? malloc.h won't cut it?
#ifdef CONFIG_BITBANGMII
#include miiphy.h
@@ -273,6 +274,9 @@ void board_init_f(ulong bootflag)
memset((void *)gd, 0, sizeof(gd_t));
+early_malloc_init();
So this basically flips a bit, do it the other way and you don't need it.
+debug(Early malloc initialized.\n);
+
gd-mon_len = _bss_end_ofs;
#ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
@@ -452,12 +469,23 @@ void board_init_r(gd_t *id, ulong dest_addr)
ulong flash_size;
#endif
+gd_t *old_gd = gd;
+
gd = id;
gd-flags |= GD_FLG_RELOC;/* tell others: relocation done */
monitor_flash_len = _end_ofs;
+/* The Malloc area is immediately below the monitor copy in DRAM */
+malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
+
+// TODO: DM Cores relocation goes here.
+
+/* Disable early mallocator (effectively switch calls to the real
malloc). */
+early_malloc_disab((gde_t *)old_gd);
+
/* Enable caches */
enable_caches();
@@ -485,10 +513,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
post_output_backlog();
#endif
-/* The Malloc area is immediately below the monitor copy in DRAM */
-malloc_start = dest_addr - TOTAL_MALLOC_LEN;
-mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
-
Can mem_malloc_init() not flip on the early_malloc bit for you here?
#if !defined(CONFIG_SYS_NO_FLASH)
puts(Flash: );
[...]
+
+#include asm/global_data.h /* for gd_t and gd */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline size_t early_malloc_align_up(phys_addr_t addr)
+{
+ if(!EARLY_MALLOC_IS_ALIGNED(addr)) {
+addr = EARLY_MALLOC_ALIGN_DOWN(addr);
+addr += EARLY_MALLOC_ALIGN_MULTIPLE;
+ }
+
+ return addr;
+}
+
+void early_malloc_init(void)
+{
+ ((gde_t *)gd)-em.flags = EARLY_MALLOC_INIT_FLAGS;
+ ((gde_t *)gd)-em.size = 0;
+}
+
+
+int early_malloc_isactive(void)
+{
+ /* The early_malloc() is inactive after relocation or when the
+ flag says so. */
+ return ((EARLY_MALLOC_IS_ACTIVE(((gde_t *)gd)-em.flags)) ||
+ (gd-flags GD_FLG_RELOC));
So ... gd-flags will be enough for the early malloc, you don't need any
further
flags
+}
+
+int early_free_isactive(void)
+{
+ /* The early free is inactive when the flag says so. */
+ return (gd-flags GD_FLG_RELOC);
+}
+
+
+void *early_malloc(size_t size)
No, we want this wrapped into malloc() call, so the drivers can be inited
indifferent of time.
+{
+ em_spc_t *em = ((gde_t *)gd)-em;
+
+ /* Check flag active. */
+ if(!EARLY_MALLOC_IS_ACTIVE(em-flags))
+return NULL;
Indent with tab please ... tools/checkpatch.pl will help here.
+ /* Choose block beginning address. */
+ phys_addr_t addr =
early_malloc_align_up(((phys_addr_t)em-heap)+em-size);
+
+ /*
Re: [U-Boot] [RFC] [PATCH 2/2] crazy: Sort u_boot_cmd at runtime
Dear Wolfgang Denk, Dear Marek Vasut, In message 201207282039.34518.ma...@denx.de you wrote: Seems incomplete in several aspects: Below the section: * NOTE * THIS PATCH IS CRAZY Then what is actually the purpose of such a posting? Just dumping unsorted thoughts to community? I'd prefer to get some feedback, you know ... You are experienced enough to know what would be needed for a semi-clean patch, even if it's just for RFC... If you mean droping the ascii art ... well, yes. But for draft patch, I'd like to actually see further ideas. There are a few notes. I'd actually like to know if this approach is correct at all, it might break on some crazy configurations or such. Define correct. If there's not some obvious flub in the code. If this kind of abuse of CPP is correct or not. It may be possible - but what would be the advantage? The list of commands will be already sorted. Which problem does it solve? Optimization, nothing else. In which way is it better than the current code? It's a bit faster. 1) what about all the non-ARM architecures and the board specific linker scripts? - This patch affects only arm926t, obviously to make it proper, every linkerscript would have to be adjusted Which sucks, since there're a lot of them. But it can probably be automated. Actually I doubt it makes sense at all. It actually does ... but not in such a plain context. I did this patch because we want the driver lists sorted. So I did this research and implemented it on the command list. I wanted to gather some feedback on if this actually can be done in such a way or if there'll be problems with toolchains maybe. Or any other issues. I envision a situation where some pluggable code (say, a standalone application, or some form of loadable module whatever) can add new commands - it would be nice if these would still appear in sorted order, but this cannot be done at compile-time. Certainly ... but we can keep a separate runtime table for these added commands. So please explain which actual problem you are rying to solve. Best regards, Wolfgang Denk Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] COMMON: Add __stringify() function
Dear Wolfgang Denk, Dear Marek Vasut, In message 201207282139.05998.ma...@denx.de you wrote: include/common.h |7 +++ 1 file changed, 7 insertions(+) We have similar things already, and we don't add dead code - you add a macro without users here. It's used in 2/2 ... what macro do you have in mind ? Then add it with the patch that uses it. I really wanted to keep this one separate, but I'll bend here. But if you mention those xstr()s below, it might be actually better to add __stringify() and then replace all those crazy xstr()s. As for existing use, see for example [...] include/configs/ima3-mx53.h:#define xstr(s) str(s) Thanks for pointing this out. If you want to unify the use of such a macro, fine - but then please replace all ocurrences of equivalent definitions all over the code. All these above (and any I eventually didn't find) should be replaced, then. Good. Best regards, Wolfgang Denk Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4] MX28: extend print_cpuinfo() to use chip information
The information now is gathered from HW_DIGCTL_CHIPID register and
includes the chip modem and revision on the output.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
Changes in v2:
- use ?? for unidentified revision and cpu type
- use numeric revisions
Changes in v3:
- drop mx23 data as it will be posted in a later patch
- fix info order (first rev, then clock)
Changes in v4:
- change short-description prefix to MX28
arch/arm/cpu/arm926ejs/mx28/mx28.c | 38 --
arch/arm/include/asm/arch-mx28/regs-digctl.h |4 +++
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c
b/arch/arm/cpu/arm926ejs/mx28/mx28.c
index ff25772..cf7a50f 100644
--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
@@ -188,13 +188,47 @@ int arch_cpu_init(void)
}
#if defined(CONFIG_DISPLAY_CPUINFO)
+static const char *get_cpu_type(void)
+{
+ struct mx28_digctl_regs *digctl_regs =
+ (struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
+
+ switch (readl(digctl_regs-hw_digctl_chipid) HW_DIGCTL_CHIPID_MASK) {
+ case HW_DIGCTL_CHIPID_MX28:
+ return 28;
+ default:
+ return ??;
+ }
+}
+
+static const char *get_cpu_rev(void)
+{
+ struct mx28_digctl_regs *digctl_regs =
+ (struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
+ uint8_t rev = readl(digctl_regs-hw_digctl_chipid) 0x00FF;
+
+ switch (readl(digctl_regs-hw_digctl_chipid) HW_DIGCTL_CHIPID_MASK) {
+ case HW_DIGCTL_CHIPID_MX28:
+ switch (rev) {
+ case 0x1:
+ return 1.2;
+ default:
+ return ??;
+ }
+ default:
+ return ??;
+ }
+}
+
int print_cpuinfo(void)
{
struct mx28_spl_data *data = (struct mx28_spl_data *)
((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) ~0xf);
- printf(Freescale i.MX28 family at %d MHz\n,
- mxc_get_clock(MXC_ARM_CLK) / 100);
+ printf(CPU: Freescale i.MX%s rev%s at %d MHz\n,
+ get_cpu_type(),
+ get_cpu_rev(),
+ mxc_get_clock(MXC_ARM_CLK) / 100);
printf(BOOT: %s\n, mx28_boot_modes[data-boot_mode_idx].mode);
return 0;
}
diff --git a/arch/arm/include/asm/arch-mx28/regs-digctl.h
b/arch/arm/include/asm/arch-mx28/regs-digctl.h
index 9a63594..247da6e 100644
--- a/arch/arm/include/asm/arch-mx28/regs-digctl.h
+++ b/arch/arm/include/asm/arch-mx28/regs-digctl.h
@@ -152,4 +152,8 @@ struct mx28_digctl_regs {
};
#endif
+/* Product code identification */
+#define HW_DIGCTL_CHIPID_MASK (0x 16)
+#define HW_DIGCTL_CHIPID_MX28 (0x2800 16)
+
#endif /* __MX28_REGS_DIGCTL_H__ */
--
1.7.10.4
___
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http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] MX28: use a clear name for DDR2 initialization
The mx28 prefix has been added to the initialization data and function
so it is clear by which SoC it is used as i.MX233 will have a specific
one. While on that, we also change it to static.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
Changes in v2:
- use static for the allocation of memory initialization matrix
Changes in v3:
- change short-description prefix
arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
index e17a4d7..cca1316 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
@@ -31,7 +31,7 @@
#include mx28_init.h
-uint32_t dram_vals[] = {
+static uint32_t mx28_dram_vals[] = {
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
@@ -88,14 +88,14 @@ void __mx28_adjust_memory_params(uint32_t *dram_vals)
void mx28_adjust_memory_params(uint32_t *dram_vals)
__attribute__((weak, alias(__mx28_adjust_memory_params)));
-void init_m28_200mhz_ddr2(void)
+void init_mx28_200mhz_ddr2(void)
{
int i;
- mx28_adjust_memory_params(dram_vals);
+ mx28_adjust_memory_params(mx28_dram_vals);
- for (i = 0; i ARRAY_SIZE(dram_vals); i++)
- writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ for (i = 0; i ARRAY_SIZE(mx28_dram_vals); i++)
+ writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
void mx28_mem_init_clock(void)
@@ -230,7 +230,7 @@ void mx28_mem_init(void)
/* Clear START bit from DRAM_CTL16 */
clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
- init_m28_200mhz_ddr2();
+ init_mx28_200mhz_ddr2();
/* Clear SREFRESH bit from DRAM_CTL17 */
clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
--
1.7.10.4
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[U-Boot] [PATCH 2/2] microblaze: Wire up SPI driver
Depending on XILINX_SPI_FLASH_BASEADDR enable SPI flash and environment in SPI flash. Expected values from xparameters.h are: - XILINX_SPI_FLASH_BASEADDR - XILINX_SPI_FLASH_MAX_FREQ - XILINX_SPI_FLASH_CS Signed-off-by: Stephan Linz l...@li-pro.net --- include/configs/microblaze-generic.h | 55 -- 1 files changed, 52 insertions(+), 3 deletions(-) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 56dcc02..87e7951 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -36,14 +36,22 @@ #define CONFIG_OF_EMBED1 #define CONFIG_DEFAULT_DEVICE_TREE microblaze -/* linear flash memory */ +/* linear and spi flash memory */ #ifdef XILINX_FLASH_START #defineFLASH +#undef SPIFLASH #undef RAMENV /* hold environment in flash */ #else +#ifdef XILINX_SPI_FLASH_BASEADDR #undef FLASH +#defineSPIFLASH +#undef RAMENV /* hold environment in flash */ +#else +#undef FLASH +#undef SPIFLASH #defineRAMENV /* hold environment in RAM */ #endif +#endif /* uart */ #ifdef XILINX_UARTLITE_BASEADDR @@ -218,20 +226,51 @@ # define CONFIG_ENV_SIZE 0x1000 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) -# else /* !RAMENV */ +# else /* FLASH !RAMENV */ # define CONFIG_ENV_IS_IN_FLASH 1 /* 128K(one sector) for env */ # define CONFIG_ENV_SECT_SIZE 0x2 # define CONFIG_ENV_ADDR \ (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) # define CONFIG_ENV_SIZE 0x2 -# endif /* !RAMBOOT */ +# endif /* FLASH !RAMBOOT */ #else /* !FLASH */ + +#ifdef SPIFLASH +# define CONFIG_SYS_NO_FLASH 1 +# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR +# define CONFIG_XILINX_SPI 1 +# define CONFIG_SPI1 +# define CONFIG_SPI_FLASH 1 +# define CONFIG_SPI_FLASH_STMICRO 1 +# define CONFIG_SF_DEFAULT_MODESPI_MODE_3 +# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ +# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS + +# ifdefRAMENV +# define CONFIG_ENV_IS_NOWHERE1 +# define CONFIG_ENV_SIZE 0x1000 +# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) + +# else /* SPIFLASH !RAMENV */ +# define CONFIG_ENV_IS_IN_SPI_FLASH 1 +# define CONFIG_ENV_SPI_MODE SPI_MODE_3 +# define CONFIG_ENV_SPI_MAX_HZCONFIG_SF_DEFAULT_SPEED +# define CONFIG_ENV_SPI_CSCONFIG_SF_DEFAULT_CS +/* 128K(two sectors) for env */ +# define CONFIG_ENV_SECT_SIZE 0x1 +# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE) +/* Warning: adjust the offset in respect of other flash content and size */ +# define CONFIG_ENV_OFFSET(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */ +# endif /* SPIFLASH !RAMBOOT */ +#else /* !SPIFLASH */ + /* ENV in RAM */ # define CONFIG_SYS_NO_FLASH 1 # define CONFIG_ENV_IS_NOWHERE 1 # define CONFIG_ENV_SIZE 0x1000 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) +#endif /* !SPIFLASH */ #endif /* !FLASH */ /* system ace */ @@ -306,6 +345,15 @@ # define CONFIG_CMD_SAVEENV # define CONFIG_CMD_SAVES # endif + +#else +#if defined(SPIFLASH) +# define CONFIG_CMD_SF + +# if !defined(RAMENV) +# define CONFIG_CMD_SAVEENV +# define CONFIG_CMD_SAVES +# endif #else # undef CONFIG_CMD_IMLS # undef CONFIG_CMD_FLASH @@ -313,6 +361,7 @@ # undef CONFIG_CMD_UBI # undef CONFIG_CMD_UBIFS #endif +#endif #if defined(CONFIG_CMD_JFFS2) # define CONFIG_MTD_PARTITIONS -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] spi: microblaze: Adds driver for Xilinx SPI controller
This is an improved version of the driver patch original
submitted by Graeme Smecher graeme.smec...@mail.mcgill.ca
The changes are:
- remove hard coded Xilinx BSP defines (XPAR_SPI_*) and
use CONFIG_SYS_SPI_BASE from config.h instead
- add extensive register struct definitions
- remove offset calculation for register access and
use the new register struct instead
- move default SPI controller configuration from
spi_setup_slave() to spi_claim_bus()
- add spi_set_speed()
- insert SPI controller deactivation in spi_release_bus()
- protect while loops in spi_xfer() with counter / timeouts
- support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOP
Come from:
http://patchwork.ozlabs.org/patch/71797/
Signed-off-by: Stephan Linz l...@li-pro.net
---
v2: Remove useles information from commit message
Add newline and split variable declaration from code
---
drivers/spi/Makefile |1 +
drivers/spi/xilinx_spi.c | 214 ++
drivers/spi/xilinx_spi.h | 135 +
3 files changed, 350 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/xilinx_spi.c
create mode 100644 drivers/spi/xilinx_spi.h
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c967d87..3ae38e5 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -44,6 +44,7 @@ COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
+COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
new file mode 100644
index 000..e563c19
--- /dev/null
+++ b/drivers/spi/xilinx_spi.c
@@ -0,0 +1,214 @@
+/*
+ * Xilinx SPI driver
+ *
+ * supports 8 bit SPI transfers only, with or w/o FIFO
+ *
+ * based on bfin_spi.c, by way of altera_spi.c
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ * Copyright (c) 2010 Thomas Chou tho...@wytron.com.tw
+ * Copyright (c) 2010 Graeme Smecher graeme.smec...@mail.mcgill.ca
+ * Copyright (c) 2012 Stephan Linz l...@li-pro.net
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ * [0]: http://www.xilinx.com/support/documentation
+ *
+ * [S]:[0]/ip_documentation/xps_spi.pdf
+ * [0]/ip_documentation/axi_spi_ds742.pdf
+ */
+#include config.h
+#include common.h
+#include malloc.h
+#include spi.h
+
+#include xilinx_spi.h
+
+#ifndef CONFIG_SYS_XILINX_SPI_LIST
+#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
+#endif
+
+#ifndef CONFIG_XILINX_SPI_IDLE_VAL
+#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
+#endif
+
+#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | \
+SPICR_MASTER_MODE | \
+SPICR_SPE)
+
+#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | \
+SPICR_MANUAL_SS)
+
+#define XILSPI_MAX_XFER_BITS 8
+
+static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
+
+__attribute__((weak))
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus ARRAY_SIZE(xilinx_spi_base_list) cs 32;
+}
+
+__attribute__((weak))
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+
+ writel(SPISSR_ACT(slave-cs), xilspi-regs-spissr);
+}
+
+__attribute__((weak))
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+
+ writel(SPISSR_OFF, xilspi-regs-spissr);
+}
+
+void spi_init(void)
+{
+ /* do nothing */
+}
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ /* xilinx spi core does not support programmable speed */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct xilinx_spi_slave *xilspi;
+ struct xilinx_spi_reg *regs;
+
+ if (!spi_cs_is_valid(bus, cs)) {
+ printf(XILSPI error: %s: unsupported bus %d / cs %d\n,
+ __func__, bus, cs);
+ return NULL;
+ }
+
+ xilspi = malloc(sizeof(*xilspi));
+ if (!xilspi) {
+ printf(XILSPI error: %s: malloc of SPI structure failed\n,
+ __func__);
+ return NULL;
+ }
+ xilspi-slave.bus = bus;
+ xilspi-slave.cs = cs;
+ xilspi-regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
+ xilspi-freq = max_hz;
+ xilspi-mode = mode;
+ debug(%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n, __func__,
+ bus, cs, xilspi-regs, xilspi-mode, xilspi-freq);
+
+ return xilspi-slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+
+
[U-Boot] [RFC PATCH 0/5] Rework for mxs SoC family support
This patchset is the basis for inclusion of i.MX233 support on U-Boot.
To accomplish it, this patchset moves code around to create the mxs
SoC family support.
The idea of posting it on the mailing list is to receive comments on
ways to improve the patchset and also try to merge it during the merge
window.
Otavio Salvador (5):
mxs: reorganize source directory for easy sharing of code in i.MXS
SoCs
mxs: prefix register acessor macros with 'mxs' prefix
mxs: prefix register structs with 'mxs' prefix
mxs: Reowork SPL to use 'mxs' prefix for methods
mxs: rename mx28.c to mxs.c as it is common to i.MX233 and i.MX28
SoCs
arch/arm/cpu/arm926ejs/{mx28 = mxs}/Makefile |2 +-
arch/arm/cpu/arm926ejs/{mx28 = mxs}/clock.c | 40 +--
arch/arm/cpu/arm926ejs/{mx28 = mxs}/iomux.c |6 +-
arch/arm/cpu/arm926ejs/{mx28/mx28.c = mxs/mxs.c} | 42 +--
.../arm926ejs/{mx28/mx28_init.h = mxs/mxs_init.h} | 14 +-
arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_boot.c| 20 +-
.../cpu/arm926ejs/{mx28 = mxs}/spl_lradc_init.c | 10 +-
.../arm/cpu/arm926ejs/{mx28 = mxs}/spl_mem_init.c | 54 ++--
.../cpu/arm926ejs/{mx28 = mxs}/spl_power_init.c | 270 ++--
arch/arm/cpu/arm926ejs/{mx28 = mxs}/start.S |0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/timer.c |8 +-
.../arm/cpu/arm926ejs/{mx28 = mxs}/u-boot-spl.lds |2 +-
.../include/asm/{arch-mx28 = arch-mxs}/clock.h|0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/dma.h |0
.../arm/include/asm/{arch-mx28 = arch-mxs}/gpio.h |0
.../include/asm/{arch-mx28 = arch-mxs}/imx-regs.h |0
.../asm/{arch-mx28 = arch-mxs}/iomux-mx28.h |0
.../include/asm/{arch-mx28 = arch-mxs}/iomux.h|0
.../asm/{arch-mx28 = arch-mxs}/regs-apbh.h| 256 +--
.../asm/{arch-mx28 = arch-mxs}/regs-base.h|0
.../include/asm/{arch-mx28 = arch-mxs}/regs-bch.h | 44 ++--
.../asm/{arch-mx28 = arch-mxs}/regs-clkctrl.h | 60 ++---
.../asm/{arch-mx28 = arch-mxs}/regs-common.h | 34 +--
.../asm/{arch-mx28 = arch-mxs}/regs-digctl.h | 52 ++--
.../asm/{arch-mx28 = arch-mxs}/regs-gpmi.h| 28 +-
.../include/asm/{arch-mx28 = arch-mxs}/regs-i2c.h | 30 +--
.../asm/{arch-mx28 = arch-mxs}/regs-lcdif.h | 66 ++---
.../asm/{arch-mx28 = arch-mxs}/regs-lradc.h | 50 ++--
.../asm/{arch-mx28 = arch-mxs}/regs-ocotp.h | 88 +++
.../asm/{arch-mx28 = arch-mxs}/regs-pinctrl.h | 170 ++--
.../asm/{arch-mx28 = arch-mxs}/regs-power.h | 30 +--
.../include/asm/{arch-mx28 = arch-mxs}/regs-rtc.h | 30 +--
.../include/asm/{arch-mx28 = arch-mxs}/regs-ssp.h | 42 +--
.../asm/{arch-mx28 = arch-mxs}/regs-timrot.h | 40 +--
.../include/asm/{arch-mx28 = arch-mxs}/regs-usb.h |2 +-
.../asm/{arch-mx28 = arch-mxs}/regs-usbphy.h | 22 +-
.../asm/{arch-mx28 = arch-mxs}/sys_proto.h| 10 +-
board/denx/m28evk/m28evk.c |4 +-
board/denx/m28evk/spl_boot.c |2 +-
board/freescale/mx28evk/iomux.c|2 +-
board/freescale/mx28evk/mx28evk.c |4 +-
boards.cfg |4 +-
doc/README.m28 |4 +-
doc/README.mx28evk |4 +-
drivers/dma/apbh_dma.c | 32 +--
drivers/gpio/mxs_gpio.c| 16 +-
drivers/i2c/mxs_i2c.c | 12 +-
drivers/mmc/mxsmmc.c | 20 +-
drivers/mtd/nand/mxs_nand.c| 12 +-
drivers/rtc/mxsrtc.c |6 +-
drivers/spi/mxs_spi.c | 19 +-
drivers/usb/host/ehci-mxs.c| 24 +-
include/configs/m28evk.h |4 +-
include/configs/mx28evk.h |4 +-
54 files changed, 847 insertions(+), 848 deletions(-)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/Makefile (97%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/clock.c (89%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/iomux.c (94%)
rename arch/arm/cpu/arm926ejs/{mx28/mx28.c = mxs/mxs.c} (86%)
rename arch/arm/cpu/arm926ejs/{mx28/mx28_init.h = mxs/mxs_init.h} (81%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_boot.c (90%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_lradc_init.c (91%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_mem_init.c (86%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_power_init.c (82%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/start.S (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/timer.c (95%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/u-boot-spl.lds (97%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/clock.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/dma.h (100%)
rename arch/arm/include/asm/{arch-mx28 =
[U-Boot] [RFC PATCH 1/5] mxs: reorganize source directory for easy sharing of code in i.MXS SoCs
Most code can be shared between i.MX23 and i.MX28 as both are from
i.MXS family; this source directory structure makes easy to share code
among them.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
arch/arm/cpu/arm926ejs/{mx28 = mxs}/Makefile |0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/clock.c|0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/iomux.c|0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/mx28.c |0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/mx28_init.h|0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_boot.c |0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_lradc_init.c |0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_mem_init.c |0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_power_init.c |0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/start.S|0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/timer.c|0
arch/arm/cpu/arm926ejs/{mx28 = mxs}/u-boot-spl.lds |2 +-
arch/arm/include/asm/{arch-mx28 = arch-mxs}/clock.h|0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/dma.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/gpio.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/imx-regs.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/iomux-mx28.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/iomux.h|0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-apbh.h|0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-base.h|0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-bch.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-clkctrl.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-common.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-digctl.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-gpmi.h|0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-i2c.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-lcdif.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-lradc.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-ocotp.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-pinctrl.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-power.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-rtc.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-ssp.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-timrot.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-usb.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-usbphy.h |0
arch/arm/include/asm/{arch-mx28 = arch-mxs}/sys_proto.h|0
boards.cfg |4 ++--
doc/README.m28 |4 ++--
doc/README.mx28evk |4 ++--
include/configs/m28evk.h|4 ++--
include/configs/mx28evk.h |4 ++--
42 files changed, 11 insertions(+), 11 deletions(-)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/Makefile (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/clock.c (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/iomux.c (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/mx28.c (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/mx28_init.h (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_boot.c (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_lradc_init.c (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_mem_init.c (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/spl_power_init.c (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/start.S (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/timer.c (100%)
rename arch/arm/cpu/arm926ejs/{mx28 = mxs}/u-boot-spl.lds (97%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/clock.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/dma.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/gpio.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/imx-regs.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/iomux-mx28.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/iomux.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-apbh.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-base.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-bch.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-clkctrl.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-common.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-digctl.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-gpmi.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-i2c.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-lcdif.h (100%)
rename arch/arm/include/asm/{arch-mx28 = arch-mxs}/regs-lradc.h (100%)
rename
[U-Boot] [RFC PATCH 2/5] mxs: prefix register acessor macros with 'mxs' prefix
As the register accessing mode is the same for all i.MXS SoCs we ought
to use 'mxs' prefix intead of 'mx28'.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
arch/arm/cpu/arm926ejs/mxs/clock.c |4 +-
arch/arm/cpu/arm926ejs/mxs/iomux.c |6 +-
arch/arm/cpu/arm926ejs/mxs/mx28.c|6 +-
arch/arm/include/asm/arch-mxs/regs-apbh.h| 254 +-
arch/arm/include/asm/arch-mxs/regs-bch.h | 42 ++---
arch/arm/include/asm/arch-mxs/regs-clkctrl.h | 58 +++---
arch/arm/include/asm/arch-mxs/regs-common.h | 34 ++--
arch/arm/include/asm/arch-mxs/regs-digctl.h | 50 ++---
arch/arm/include/asm/arch-mxs/regs-gpmi.h| 26 +--
arch/arm/include/asm/arch-mxs/regs-i2c.h | 28 +--
arch/arm/include/asm/arch-mxs/regs-lcdif.h | 64 +++
arch/arm/include/asm/arch-mxs/regs-lradc.h | 48 ++---
arch/arm/include/asm/arch-mxs/regs-ocotp.h | 86 -
arch/arm/include/asm/arch-mxs/regs-pinctrl.h | 168 -
arch/arm/include/asm/arch-mxs/regs-power.h | 28 +--
arch/arm/include/asm/arch-mxs/regs-rtc.h | 28 +--
arch/arm/include/asm/arch-mxs/regs-ssp.h | 40 ++--
arch/arm/include/asm/arch-mxs/regs-timrot.h | 38 ++--
arch/arm/include/asm/arch-mxs/regs-usbphy.h | 20 +-
arch/arm/include/asm/arch-mxs/sys_proto.h|6 +-
drivers/gpio/mxs_gpio.c | 16 +-
drivers/usb/host/ehci-mxs.c |8 +-
22 files changed, 529 insertions(+), 529 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c
b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 0439f9c..3e29c56 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -207,7 +207,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq,
int xtal)
return;
clkreg = (uint32_t)(clkctrl_regs-hw_clkctrl_ssp0) +
- (ssp * sizeof(struct mx28_register_32));
+ (ssp * sizeof(struct mxs_register_32));
clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
while (readl(clkreg) CLKCTRL_SSP_CLKGATE)
@@ -256,7 +256,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
return XTAL_FREQ_KHZ;
clkreg = (uint32_t)(clkctrl_regs-hw_clkctrl_ssp0) +
- (ssp * sizeof(struct mx28_register_32));
+ (ssp * sizeof(struct mxs_register_32));
tmp = readl(clkreg) CLKCTRL_SSP_DIV_MASK;
diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c
b/arch/arm/cpu/arm926ejs/mxs/iomux.c
index 12916b6..73f1446 100644
--- a/arch/arm/cpu/arm926ejs/mxs/iomux.c
+++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c
@@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
{
u32 reg, ofs, bp, bm;
void *iomux_base = (void *)MXS_PINCTRL_BASE;
- struct mx28_register_32 *mxs_reg;
+ struct mxs_register_32 *mxs_reg;
/* muxsel */
ofs = 0x100;
@@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
/* vol */
if (PAD_VOL_VALID(pad)) {
bp = PAD_PIN(pad) % 8 * 4 + 2;
- mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
+ mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
if (PAD_VOL(pad))
writel(1 bp, mxs_reg-reg_set);
else
@@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
ofs = PULL_OFFSET;
ofs += PAD_BANK(pad) * 0x10;
bp = PAD_PIN(pad);
- mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
+ mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
if (PAD_PULL(pad))
writel(1 bp, mxs_reg-reg_set);
else
diff --git a/arch/arm/cpu/arm926ejs/mxs/mx28.c
b/arch/arm/cpu/arm926ejs/mxs/mx28.c
index cf7a50f..65fcd75 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mx28.c
@@ -81,7 +81,7 @@ void enable_caches(void)
#endif
}
-int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int
timeout)
+int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
{
while (--timeout) {
if ((readl(reg-reg) mask) == mask)
@@ -92,7 +92,7 @@ int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t
mask, int timeout)
return !timeout;
}
-int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int
timeout)
+int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
{
while (--timeout) {
if ((readl(reg-reg) mask) == 0)
@@ -103,7 +103,7 @@ int mx28_wait_mask_clr(struct mx28_register_32 *reg,
uint32_t mask, int timeout)
return !timeout;
}
-int mx28_reset_block(struct mx28_register_32 *reg)
+int mx28_reset_block(struct mxs_register_32 *reg)
{
/* Clear SFTRST */
writel(MX28_BLOCK_SFTRST, reg-reg_clr);
[U-Boot] [RFC PATCH 3/5] mxs: prefix register structs with 'mxs' prefix
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
arch/arm/cpu/arm926ejs/mxs/clock.c | 36
arch/arm/cpu/arm926ejs/mxs/mx28.c| 28 +++---
arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c |4 +-
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c| 24 +++---
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 120 +-
arch/arm/cpu/arm926ejs/mxs/timer.c |8 +-
arch/arm/include/asm/arch-mxs/regs-apbh.h|2 +-
arch/arm/include/asm/arch-mxs/regs-bch.h |2 +-
arch/arm/include/asm/arch-mxs/regs-clkctrl.h |2 +-
arch/arm/include/asm/arch-mxs/regs-digctl.h |2 +-
arch/arm/include/asm/arch-mxs/regs-gpmi.h|2 +-
arch/arm/include/asm/arch-mxs/regs-i2c.h |2 +-
arch/arm/include/asm/arch-mxs/regs-lcdif.h |2 +-
arch/arm/include/asm/arch-mxs/regs-lradc.h |2 +-
arch/arm/include/asm/arch-mxs/regs-ocotp.h |2 +-
arch/arm/include/asm/arch-mxs/regs-pinctrl.h |2 +-
arch/arm/include/asm/arch-mxs/regs-power.h |2 +-
arch/arm/include/asm/arch-mxs/regs-rtc.h |2 +-
arch/arm/include/asm/arch-mxs/regs-ssp.h |2 +-
arch/arm/include/asm/arch-mxs/regs-timrot.h |2 +-
arch/arm/include/asm/arch-mxs/regs-usb.h |2 +-
arch/arm/include/asm/arch-mxs/regs-usbphy.h |2 +-
board/denx/m28evk/m28evk.c |4 +-
board/freescale/mx28evk/mx28evk.c|4 +-
drivers/dma/apbh_dma.c | 32 +++
drivers/i2c/mxs_i2c.c| 12 +--
drivers/mmc/mxsmmc.c | 20 ++---
drivers/mtd/nand/mxs_nand.c | 12 +--
drivers/rtc/mxsrtc.c |6 +-
drivers/spi/mxs_spi.c| 19 ++--
drivers/usb/host/ehci-mxs.c | 16 ++--
31 files changed, 188 insertions(+), 189 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c
b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 3e29c56..bfea6ab 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -43,8 +43,8 @@
static uint32_t mx28_get_pclk(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
@@ -75,8 +75,8 @@ static uint32_t mx28_get_pclk(void)
static uint32_t mx28_get_hclk(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t div;
uint32_t clkctrl;
@@ -93,8 +93,8 @@ static uint32_t mx28_get_hclk(void)
static uint32_t mx28_get_emiclk(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
@@ -118,8 +118,8 @@ static uint32_t mx28_get_emiclk(void)
static uint32_t mx28_get_gpmiclk(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
@@ -145,8 +145,8 @@ static uint32_t mx28_get_gpmiclk(void)
*/
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t div;
int io_reg;
@@ -178,8 +178,8 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
*/
static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint8_t ret;
int io_reg;
@@ -199,8 +199,8 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
*/
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clk, clkreg;
if (ssp MXC_SSPCLK3)
@@ -243,8 +243,8 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq,
int xtal)
*/
static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
{
- struct
[U-Boot] [RFC PATCH 4/5] mxs: Reowork SPL to use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
arch/arm/cpu/arm926ejs/mxs/mx28.c |8 +-
.../cpu/arm926ejs/mxs/{mx28_init.h = mxs_init.h} | 14 +-
arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 20 +--
arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c|6 +-
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 30 ++--
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c| 150 ++--
arch/arm/include/asm/arch-mxs/sys_proto.h |4 +-
board/denx/m28evk/spl_boot.c |2 +-
board/freescale/mx28evk/iomux.c|2 +-
9 files changed, 118 insertions(+), 118 deletions(-)
rename arch/arm/cpu/arm926ejs/mxs/{mx28_init.h = mxs_init.h} (81%)
diff --git a/arch/arm/cpu/arm926ejs/mxs/mx28.c
b/arch/arm/cpu/arm926ejs/mxs/mx28.c
index dc271cf..a61f75b 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mx28.c
@@ -222,8 +222,8 @@ static const char *get_cpu_rev(void)
int print_cpuinfo(void)
{
- struct mx28_spl_data *data = (struct mx28_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) ~0xf);
+ struct mxs_spl_data *data = (struct mxs_spl_data *)
+ ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) ~0xf);
printf(CPU: Freescale i.MX%s rev%s at %d MHz\n,
get_cpu_type(),
@@ -322,8 +322,8 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
int mx28_dram_init(void)
{
- struct mx28_spl_data *data = (struct mx28_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) ~0xf);
+ struct mxs_spl_data *data = (struct mxs_spl_data *)
+ ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) ~0xf);
if (data-mem_dram_size == 0) {
printf(MX28:\n
diff --git a/arch/arm/cpu/arm926ejs/mxs/mx28_init.h
b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
similarity index 81%
rename from arch/arm/cpu/arm926ejs/mxs/mx28_init.h
rename to arch/arm/cpu/arm926ejs/mxs/mxs_init.h
index e3a4493..2ddc5bc 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mx28_init.h
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
@@ -28,18 +28,18 @@
void early_delay(int delay);
-void mx28_power_init(void);
+void mxs_power_init(void);
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
-void mx28_power_wait_pswitch(void);
+void mxs_power_wait_pswitch(void);
#else
-static inline void mx28_power_wait_pswitch(void) { }
+static inline void mxs_power_wait_pswitch(void) { }
#endif
-void mx28_mem_init(void);
-uint32_t mx28_mem_get_size(void);
+void mxs_mem_init(void);
+uint32_t mxs_mem_get_size(void);
-void mx28_lradc_init(void);
-void mx28_lradc_enable_batt_measurement(void);
+void mxs_lradc_init(void);
+void mxs_lradc_enable_batt_measurement(void);
#endif /* __M28_INIT_H__ */
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index a6dfca3..46f6770 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -31,7 +31,7 @@
#include asm/arch/sys_proto.h
#include asm/gpio.h
-#include mx28_init.h
+#include mxs_init.h
/*
* This delay function is intended to be used only in early stage of boot,
where
@@ -58,7 +58,7 @@ const iomux_cfg_t iomux_boot[] = {
MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
};
-uint8_t mx28_get_bootmode_index(void)
+uint8_t mxs_get_bootmode_index(void)
{
uint8_t bootmode = 0;
int i;
@@ -92,22 +92,22 @@ uint8_t mx28_get_bootmode_index(void)
return i;
}
-void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size)
{
- struct mx28_spl_data *data = (struct mx28_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) ~0xf);
- uint8_t bootmode = mx28_get_bootmode_index();
+ struct mxs_spl_data *data = (struct mxs_spl_data *)
+ ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) ~0xf);
+ uint8_t bootmode = mxs_get_bootmode_index();
mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
- mx28_power_init();
+ mxs_power_init();
- mx28_mem_init();
- data-mem_dram_size = mx28_mem_get_size();
+ mxs_mem_init();
+ data-mem_dram_size = mxs_mem_get_size();
data-boot_mode_idx = bootmode;
- mx28_power_wait_pswitch();
+ mxs_power_wait_pswitch();
}
/* Support aparatus */
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
index c1df81d..d90f0a1 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
@@ -28,9 +28,9 @@
#include asm/io.h
#include asm/arch/imx-regs.h
-#include mx28_init.h
+#include mxs_init.h
-void mx28_lradc_init(void)
+void mxs_lradc_init(void)
{
struct
[U-Boot] [RFC PATCH 5/5] mxs: rename mx28.c to mxs.c as it is common to i.MX233 and i.MX28 SoCs
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
arch/arm/cpu/arm926ejs/mxs/Makefile |2 +-
arch/arm/cpu/arm926ejs/mxs/{mx28.c = mxs.c} |0
2 files changed, 1 insertion(+), 1 deletion(-)
rename arch/arm/cpu/arm926ejs/mxs/{mx28.c = mxs.c} (100%)
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile
b/arch/arm/cpu/arm926ejs/mxs/Makefile
index 674a3af..eeecf89 100644
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
-COBJS = clock.o mx28.o iomux.o timer.o
+COBJS = clock.o mxs.o iomux.o timer.o
ifdef CONFIG_SPL_BUILD
COBJS += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
diff --git a/arch/arm/cpu/arm926ejs/mxs/mx28.c
b/arch/arm/cpu/arm926ejs/mxs/mxs.c
similarity index 100%
rename from arch/arm/cpu/arm926ejs/mxs/mx28.c
rename to arch/arm/cpu/arm926ejs/mxs/mxs.c
--
1.7.10.4
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Re: [U-Boot] [PATCH v2 2/5] ehci-hcd: Boost transfer speed
Dear Stefan, Sorry for the delay. I'm very busy, and there is much to tell on this topic. On Tue, Jul 24, 2012 at 03:02:00 PM, Stefan Herbrechtsmeier wrote: Am 23.07.2012 19:15, schrieb Benoît Thébaudeau: On Monday 23 July 2012 15:35:25 Stefan Herbrechtsmeier wrote: Am 20.07.2012 17:35, schrieb Benoît Thébaudeau: On Friday 20 July 2012 17:15:13 Stefan Herbrechtsmeier wrote: Am 20.07.2012 17:03, schrieb Benoît Thébaudeau: On Friday 20 July 2012 16:51:33 Stefan Herbrechtsmeier wrote: Am 20.07.2012 15:56, schrieb Benoît Thébaudeau: Dear Marek Vasut, On Friday 20 July 2012 15:44:01 Marek Vasut wrote: On Friday 20 July 2012 13:37:37 Stefan Herbrechtsmeier wrote: Am 20.07.2012 13:26, schrieb Benoît Thébaudeau: + int xfr_bytes = min(left_length, + (QT_BUFFER_CNT * 4096 - + ((uint32_t)buf_ptr 4095)) + ~4095); Why you align the length to 4096? It's to guarantee that each transfer length is a multiple of the max packet length. Otherwise, early short packets are issued, which breaks the transfer and results in time-out error messages. Early short packets ? What do you mean? During a USB transfer, all packets must have a length of max packet length for the pipe/endpoint, except the final one that can be a short packet. Without the alignment I make for xfr_bytes, short packets can occur within a transfer, because the hardware starts a new packet for each new queued qTD it handles. But if I am right, the max packet length is 512 for bulk and 1024 for Interrupt transfer. There are indeed different max packet lengths for different transfer types, but it does not matter since the chosen alignment guarantees a multiple of all these possible max packet lengths. But thereby you limit the transfer to 4 qT buffers for unaligned transfers. Not exactly. The 5 qt_buffers are used for page-unaligned buffers, but that results in only 4 full pages of unaligned data, requiring 5 aligned pages. Sorry I mean 4 full pages of unaligned data. For page-aligned buffers, the 5 qt_buffers result in 5 full pages of aligned data. Sure. The unaligned case could be a little bit improved to always use as many packets as possible per qTD, but that would over-complicate things for a very negligible speed and memory gain. In my use case (fragmented file on usb storage) the gain would be nearly 20%. The reason is that the data are block aligned (512) and could be aligned to 4096 with the first transfer (5 qt_buffers). Can you explain where this gain would come from? In both cases, the data in USB transfers would be organized in the same way, and it would be accessed in memory also in the same way (regarding bursts). The only difference would be the fetch time of a little bit more qTDs, which is extremely fast and insignificant compared to the transfer time of the payload, which remains unchanged. You are right, the speed different will be minimal, only the memory usage will be lower. If your point is only the memory gain, I agree. With your suggestion, there are roughly 25% less qTDs used in the (max wMaxPacketSize)-aligned but not page-aligned case since the number of qTDs is about (total transfer size) / 5 instead of (total transfer size) / 4. But this is still small compared to usual heap sizes (at least on the kind of hardware I use). Moreover, in your use case, if you are e.g. using FAT, on the one hand, the buffers in fat.c are never aligned to more than the DMA min alignment, and on the other hand, if you can align your user buffers to 512 bytes, you can also align them directly to 4 kB. The user buffer is aligned to 4kB, but this doesn't matter as a file load from a storage device (ex. fatload) can be segmented in partial USB transfers. This can lead to any block aligned buffer for a partial transfer. What do you mean by partial USB transfers? As seen from EHCI users like the MSC driver (usb_storage.c), USB transfers either succeed or fail, but they cannot be segmented. On its side, the MSC driver will only segment the FAT layer requests if they are larger than 65535 blocks, so still not what you describe. As to the FAT stack, it will only read whole clusters while accessing file payload, and the most usual cluster sizes are by default a multiple of 4 kiB (see http://support.microsoft.com/kb/140365). So I don't see segmentation anywhere, and for usual cluster sizes, the EHCI buffer alignment is fully determined by the applicative buffer alignment and the file position corresponding to the beginning of the applicative buffer. But there are indeed some unusual use cases (e.g. smaller clusters) for which only a block-aligned buffer will reach EHCI despite a page-aligned applicative buffer. My suggestion would be to
Re: [U-Boot] [PATCH 2/5] ehci-hcd: Boost transfer speed
Dear Marek, On Fri, Jul 27, 2012 at 04:13:45 PM, Benoît Thébaudeau wrote: On Fri, Jul 27, 2012 at 04:01:11 PM, Marek Vasut wrote: [...] + token = (toggle 31) | + (xfr_bytes 16) | + ((req == NULL ? 1 : 0) 15) | + (0 12) | + (3 10) | + ((usb_pipein(pipe) ? 1 : 0) 8) | (0x80 0); If you could fix all this magic afterwards (not in these patches), that'd be great. Do you only mean #defining all those values? Yes, but let's do this in a subsequent patch. It can wait for later. OK. What would you think about merging that together with the definition of 4096 into the current patch 1/5? In the next version, this patch would thus become a general cosmetic patch for EHCI to define all used constants. Best regards, Benoît ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] usb_stor_BBB_transport 5 ms delay - performance
Dear Marek, On Fri, Jul 27, 2012 at 07:44:04 PM, Marek Vasut wrote: I did see a flags field but thought having a new one was conservative (I had no real reason to have a new field). As for the typecasts I was following the API which tests for device ready (Monkey See Monkey Do). Ouch, the API seems so broken then :-( There is already a local ss variable defined for that purpose anyway, so duplicating this typecast can be avoided. Also I have no compelling reason to need a setter function either. I have no compelling feelings towards the implementation other than the 5ms adds an unnecessary delay when the device is already known to be ready, and this delay accumulates to a very poor performance for large files. Correct! Thanks for working on this! No, thank you! I'll try to do that on Monday. That will make many changes to the patch, so I'll add my SoB after Jim's, saying what I did. Best regards, Benoît ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 2/5] mxs: prefix register acessor macros with 'mxs' prefix
Dear Otavio Salvador, As the register accessing mode is the same for all i.MXS SoCs we ought to use 'mxs' prefix intead of 'mx28'. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- arch/arm/cpu/arm926ejs/mxs/clock.c |4 +- arch/arm/cpu/arm926ejs/mxs/iomux.c |6 +- arch/arm/cpu/arm926ejs/mxs/mx28.c|6 +- arch/arm/include/asm/arch-mxs/regs-apbh.h| 254 +- arch/arm/include/asm/arch-mxs/regs-bch.h | 42 ++--- arch/arm/include/asm/arch-mxs/regs-clkctrl.h | 58 +++--- arch/arm/include/asm/arch-mxs/regs-common.h | 34 ++-- arch/arm/include/asm/arch-mxs/regs-digctl.h | 50 ++--- arch/arm/include/asm/arch-mxs/regs-gpmi.h| 26 +-- arch/arm/include/asm/arch-mxs/regs-i2c.h | 28 +-- arch/arm/include/asm/arch-mxs/regs-lcdif.h | 64 +++ arch/arm/include/asm/arch-mxs/regs-lradc.h | 48 ++--- arch/arm/include/asm/arch-mxs/regs-ocotp.h | 86 - arch/arm/include/asm/arch-mxs/regs-pinctrl.h | 168 - arch/arm/include/asm/arch-mxs/regs-power.h | 28 +-- arch/arm/include/asm/arch-mxs/regs-rtc.h | 28 +-- arch/arm/include/asm/arch-mxs/regs-ssp.h | 40 ++-- arch/arm/include/asm/arch-mxs/regs-timrot.h | 38 ++-- arch/arm/include/asm/arch-mxs/regs-usbphy.h | 20 +- arch/arm/include/asm/arch-mxs/sys_proto.h|6 +- drivers/gpio/mxs_gpio.c | 16 +- drivers/usb/host/ehci-mxs.c |8 +- 22 files changed, 529 insertions(+), 529 deletions(-) [...] Given that the PSU regs for example have completely different register map and bit maps in the registers itself, I'd be careful with the renaming. Uh oh well, I guess it has to be done like that though. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] usb_stor_BBB_transport 5 ms delay - performance
Dear Benoît Thébaudeau, Dear Marek, On Fri, Jul 27, 2012 at 07:44:04 PM, Marek Vasut wrote: I did see a flags field but thought having a new one was conservative (I had no real reason to have a new field). As for the typecasts I was following the API which tests for device ready (Monkey See Monkey Do). Ouch, the API seems so broken then :-( There is already a local ss variable defined for that purpose anyway, so duplicating this typecast can be avoided. Also I have no compelling reason to need a setter function either. I have no compelling feelings towards the implementation other than the 5ms adds an unnecessary delay when the device is already known to be ready, and this delay accumulates to a very poor performance for large files. Correct! Thanks for working on this! No, thank you! I'll try to do that on Monday. That will make many changes to the patch, so I'll add my SoB after Jim's, saying what I did. Thanks, will look forward to it. Best regards, Benoît Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/5] ehci-hcd: Boost transfer speed
Dear Benoît Thébaudeau, Dear Marek, On Fri, Jul 27, 2012 at 04:13:45 PM, Benoît Thébaudeau wrote: On Fri, Jul 27, 2012 at 04:01:11 PM, Marek Vasut wrote: [...] + token = (toggle 31) | + (xfr_bytes 16) | + ((req == NULL ? 1 : 0) 15) | + (0 12) | + (3 10) | + ((usb_pipein(pipe) ? 1 : 0) 8) | (0x80 0); If you could fix all this magic afterwards (not in these patches), that'd be great. Do you only mean #defining all those values? Yes, but let's do this in a subsequent patch. It can wait for later. OK. What would you think about merging that together with the definition of 4096 into the current patch 1/5? In the next version, this patch would thus become a general cosmetic patch for EHCI to define all used constants. That's all right with me. Best regards, Benoît Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] RFC - PatchTrack Specification (revised)
Dear Graeme Russ, A revised version of the spec (sorry, I would have used reply-to but something went amiss with gmail and I've lost the original) How does it surprise me ... superawesome google imap just crashed on me like a week ago, I finished syncing my emails today ... [...] Operation Sequence - New single stand-alone patch: - Determine which git repository the patch is intended to be applied to - Add the patch to the top of the 'patch stack' of the target repository NOTE: Patches are placed in the patch stack in the order they are received - Run the configurable set of sanity checks on the raw patch. A typical example is the checkpatch.pl script which checks the patch for correct style - Perform a dummy git-apply of the patch onto the HEAD of the target repository with all patches already on the repositories 'patch stack' applied - Record the results of the sanity checks and git-apply against the patch You might want to actually create an mbox of all these stacked patches so people can download and apply them and rebase their patches on top of them. [...] Operation Sequence - Revised version of existing patch - Remove existing patch from patch stack - Insert new patch into patch stack at same location as the removed patch - Run the configurable set of sanity checks on the raw patch. A typical example is the checkpatch.pl script which checks the patch for correct style - Perform a dummy git-apply of the patch onto the HEAD of the target repository with all patches already on the repositories 'patch stack' applied Yes? Maybe this should be applied at the place where the old patch was, rather than on top. [...] Web Interface In addition to processing inbound emails, PatchTrack includes web interface which allows a user to: - Visualise the state of the patch stack for a given repository * Passed sanity checks * Passed git-apply * Acked * Tested * Committed NOTE: The patch stack is displayed as a series of rows in a table - One row per patch. The colour of the row can be configured for each patch state. For example, 'Acked' might be blue and 'Committed' white Why not make committed like ... lavender or something /jab ? :) [...] The rest sounds quite cool. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] RFC - PatchTrack Specification (revised)
Hi Marek, For future reference, please comment against: Take a look at http://www.denx.de/wiki/U-Boot/ToolsPatchTracking On 07/29/2012 01:15 PM, Marek Vasut wrote: Dear Graeme Russ, You might want to actually create an mbox of all these stacked patches so people can download and apply them and rebase their patches on top of them. Under 'Web Interface': Download a patch set of all patches meeting a specific criteria (pass all stand-alone and inter-dependent tests and have been acked for example) This could be an mbox file or an archive (.tgz) of patches Operation Sequence - Revised version of existing patch [snip] Yes? Maybe this should be applied at the place where the old patch was, rather than on top. Revised version of existing patch - Remove existing patch from patch stack - Insert new patch into patch stack at same location as the removed patch - Run each configured static test against the patch - Run each configured dynamic test against the patch - Record the results of the static and dynamic tests against the patch So yes, in place of the existing patch Why not make committed like ... lavender or something /jab ? :) :P [...] The rest sounds quite cool. Good :) Regards, Graeme ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
