[U-Boot] [PATCH] x86: Simplify the fsp hob access functions

[Bin Meng]

Remove the troublesome union hob_pointers so that some annoying casts
are no longer needed in those hob access routines. This also improves
the readability.

Signed-off-by: Bin Meng bmeng...@gmail.com
---

 arch/x86/cpu/queensbay/fsp_support.c   | 95 --
 arch/x86/cpu/queensbay/tnc_dram.c  | 39 +
 arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h  | 46 ---
 .../include/asm/arch-queensbay/fsp/fsp_support.h   |  5 +-
 arch/x86/lib/cmd_hob.c | 16 ++--
 5 files changed, 101 insertions(+), 100 deletions(-)

diff --git a/arch/x86/cpu/queensbay/fsp_support.c 
b/arch/x86/cpu/queensbay/fsp_support.c
index ef1916b..4764e3c 100644
--- a/arch/x86/cpu/queensbay/fsp_support.c
+++ b/arch/x86/cpu/queensbay/fsp_support.c
@@ -231,26 +231,28 @@ u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase)
 
 u32 fsp_get_usable_lowmem_top(const void *hob_list)
 {
-   union hob_pointers hob;
+   const struct hob_header *hdr;
+   struct hob_res_desc *res_desc;
phys_addr_t phys_start;
u32 top;
 
/* Get the HOB list for processing */
-   hob.raw = (void *)hob_list;
+   hdr = hob_list;
 
/* * Collect memory ranges */
top = FSP_LOWMEM_BASE;
-   while (!end_of_hob(hob)) {
-   if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
-   if (hob.res_desc-type == RES_SYS_MEM) {
-   phys_start = hob.res_desc-phys_start;
+   while (!end_of_hob(hdr)) {
+   if (get_hob_type(hdr) == HOB_TYPE_RES_DESC) {
+   res_desc = (struct hob_res_desc *)hdr;
+   if (res_desc-type == RES_SYS_MEM) {
+   phys_start = res_desc-phys_start;
/* Need memory above 1MB to be collected here */
if (phys_start = FSP_LOWMEM_BASE 
phys_start  (phys_addr_t)FSP_HIGHMEM_BASE)
-   top += (u32)(hob.res_desc-len);
+   top += (u32)(res_desc-len);
}
}
-   hob.raw = get_next_hob(hob);
+   hdr = get_next_hob(hdr);
}
 
return top;
@@ -258,25 +260,27 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
 
 u64 fsp_get_usable_highmem_top(const void *hob_list)
 {
-   union hob_pointers hob;
+   const struct hob_header *hdr;
+   struct hob_res_desc *res_desc;
phys_addr_t phys_start;
u64 top;
 
/* Get the HOB list for processing */
-   hob.raw = (void *)hob_list;
+   hdr = hob_list;
 
/* Collect memory ranges */
top = FSP_HIGHMEM_BASE;
-   while (!end_of_hob(hob)) {
-   if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
-   if (hob.res_desc-type == RES_SYS_MEM) {
-   phys_start = hob.res_desc-phys_start;
+   while (!end_of_hob(hdr)) {
+   if (get_hob_type(hdr) == HOB_TYPE_RES_DESC) {
+   res_desc = (struct hob_res_desc *)hdr;
+   if (res_desc-type == RES_SYS_MEM) {
+   phys_start = res_desc-phys_start;
/* Need memory above 1MB to be collected here */
if (phys_start = (phys_addr_t)FSP_HIGHMEM_BASE)
-   top += (u32)(hob.res_desc-len);
+   top += (u32)(res_desc-len);
}
}
-   hob.raw = get_next_hob(hob);
+   hdr = get_next_hob(hdr);
}
 
return top;
@@ -285,24 +289,26 @@ u64 fsp_get_usable_highmem_top(const void *hob_list)
 u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
   struct efi_guid *guid)
 {
-   union hob_pointers hob;
+   const struct hob_header *hdr;
+   struct hob_res_desc *res_desc;
 
/* Get the HOB list for processing */
-   hob.raw = (void *)hob_list;
+   hdr = hob_list;
 
/* Collect memory ranges */
-   while (!end_of_hob(hob)) {
-   if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
-   if (hob.res_desc-type == RES_MEM_RESERVED) {
-   if (compare_guid(hob.res_desc-owner, guid)) {
+   while (!end_of_hob(hdr)) {
+   if (get_hob_type(hdr) == HOB_TYPE_RES_DESC) {
+   res_desc = (struct hob_res_desc *)hdr;
+   if (res_desc-type == RES_MEM_RESERVED) {
+   if (compare_guid(res_desc-owner, guid)) {
if (len)
-   *len = (u32)(hob.res_desc-len);
+   *len = (u32)(res_desc-len);
 
-   

Re: [U-Boot] coreboot uboot qemu x86

[Ajoy Das]

Hi Simon

Can i do a gdb on u-boot startup on the coreboot environment.
means i want to stop at _start in uboot and connect to gdb.

Thanks
Ajoy

On Tue, Dec 30, 2014 at 11:15 AM, Ajoy Das dasajo...@gmail.com wrote:

 I tried changing the boot rom size to 2MB.
 But with no effect

 coreboot.rom: 2048 kB, bootblocksize 944, romsize 2097152, offset 0x0
 alignment: 64 bytes, architecture: x86

 Name   Offset Type Size
 cmos_layout.bin0x0cmos_layout  1160
 fallback/romstage  0x4c0  stage17960
 fallback/ramstage  0x4b40 stage56190
 config 0x12700raw  2990
 revision   0x13300raw  692
 (empty)0x13600null 2016728
 HOSTCC cbfstool/rmodtool.o

 Thanks
 Ajoy



 On Tue, Dec 30, 2014 at 4:17 AM, Simon Glass s...@chromium.org wrote:

 Hi Ajoy,

  On Mon, Dec 29, 2014 at 9:28 PM, Simon Glass s...@chromium.org wrote:
 
  Hi Ajoy,
 
 
   On Mon, Dec 29, 2014 at 7:36 PM, Simon Glass s...@chromium.org
 wrote:
  
   Hi,
  
   On 28 December 2014 at 21:38, Ajoy Das dasajo...@gmail.com wrote:
Hi
   
Need Help
   
I want to run U-BOOT as coreboot payload on QEMU platform
   
I am on uboot-x86 git
   
Compiled U-BOOT with make coreboot-x86_defconfig and make all
   
Running qemu with
qemu-system-i386 -bios ../coreboot/build/coreboot.rom -hda
 disk.img
-nographic -m 1g
   
But The system crashes with the following message
   
qemu: fatal: Trying to execute code outside RAM or ROM at
 0x5e2a36c2
   
Loading Segment: addr: 0x0111 memsz:
 0x000588e8
filesz:
0x000252eb
lb: [0x0010, 0x0012b030)
Post relocation: addr: 0x0111 memsz:
 0x000588e8
filesz:
0x000252eb
using LZMA
[ 0x0111, 011688e8, 0x011688e8) - fffd2770
dest 0111, end 011688e8, bouncebuffer 3ff77000
Loaded segments
Jumping to boot code at 01110015
CPU0: stack: 00126000 - 00127000, lowest used address 00126b8c,
 stack
used:
1140 bytes
entry= 0x01110015
lb_start = 0x0010
lb_size  = 0x0002b030
buffer   = 0x3ff77000
qemu: fatal: Trying to execute code outside RAM or ROM at
 0x5e2a36c2
   
EAX=000a EBX=000186a0 ECX=01145d15 EDX=19203eb0
ESI= EDI= EBP=01145f6c ESP=01145f54
EIP=5e2a36c2 EFL=0002 [---] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0018   00cf9300 DPL=0 DS   [-WA]
CS =0010   00cf9b00 DPL=0 CS32 [-RA]
SS =0018   00cf9300 DPL=0 DS   [-WA]
DS =0018   00cf9300 DPL=0 DS   [-WA]
FS =0020 19203f5c  00cf9300 DPL=0 DS   [-WA]
GS =0018   00cf9300 DPL=0 DS   [-WA]
LDT=   8200 DPL=0 LDT
TR =   8b00 DPL=0 TSS32-busy
GDT= 19203e60 0047
IDT=  
CR0=6033 CR2= CR3= CR4=
DR0= DR1= DR2= DR3=
DR6=0ff0 DR7=0400
CCS=0218 CCD=01145f50 CCO=ADDL
EFER=
FCW=037f FSW= [ST=0] FTW=00 MXCSR=1f80
FPR0=  FPR1= 
FPR2=  FPR3= 
FPR4=  FPR5= 
FPR6=  FPR7= 
XMM00=
XMM01=
XMM02=
XMM03=
XMM04=
XMM05=
XMM06=
XMM07=
Aborted (core dumped)
   
qemu-system-i386 --version
QEMU emulator version 1.0 (qemu-kvm-1.0), Copyright (c) 2003-2008
Fabrice
Bellard
   
Is QEMU not supported for coreboot and u-boot
  
   I'm not sure it's been tried but there's no reason why it should
 work.
   It seems to be crashing in U-Boot before there is any serial output.
   Did you put u-boot-dtb.bin as the payload?

  On 29 December 2014 at 07:34, Ajoy Das dasajo...@gmail.com wrote:
   Hi Simon
  
   Thanks for your reply
  
   I have added u-boot ELF as the coreboot payload
  
   u-boot: ELF 32-bit LSB shared object, Intel 80386, version 1 (SYSV),
   statically linked, not stripped.
  
   Got this link but its a year old.
   http://lists.denx.de/pipermail/u-boot/2013-July/159140.html
  
   Thanks
   Ajoy
  
 
 [snip]
 
  I suggest using cbfstool add-flat-binary -f u-boot-dtb.bin -n
  fallback/payload -c lzma -l text_base -e entry
 
  For text_base use CONFIG_SYS_TEXT_BASE which is probably 111
 
  For entry use _start which is probably 1110015.
 
  Of course I'm not sure whether 

Re: [U-Boot] [PATCH 1/2] sun6i: Add defconfig for MSI Primo81 tablet

[Siarhei Siamashka]

On Sat, 27 Dec 2014 14:16:36 +0100
Hans de Goede hdego...@redhat.com wrote:

 Hi,
 
 Thanks, I've queued both patch up in u-boot-sunxi/next. Note I've
 changed the sync:0 to sync:3 in the LCD_MODE for the Primo73,
 because of:
 
 https://github.com/jwrdegoede/u-boot-sunxi/commit/5a6b9376f78128d00459db21da80f17ad3473d3a
 
 Before the above commit the lcd-code was ignoring the sync field,
 but now it honors it, and to get the lcd-code to behave the same as
 android you need sync:3

OK. Though now I wonder if I actually should have waited until the LCD
code lands to the sunxi 'next' branch. Just to safeguard against any
other potentially incompatible changes.

 I've updated:
 
 http://linux-sunxi.org/LCD
 
 To reflect this.

Thanks!

-- 
Best regards,
Siarhei Siamashka
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 9/9] [v3] rsa: Use checksum algorithms from struct hash_algo

[Ruchika Gupta]

Hi Simon,

 -Original Message-
 From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
 Sent: Tuesday, December 30, 2014 2:42 AM
 To: Gupta Ruchika-R66431
 Cc: U-Boot Mailing List; Sun York-R58495
 Subject: Re: [PATCH 9/9] [v3] rsa: Use checksum algorithms from struct
 hash_algo
 
 Hi Ruchika,
 
 On 29 December 2014 at 00:59, Ruchika Gupta ruchika.gu...@freescale.com
 wrote:
  Hi Simon,
 
  -Original Message-
  From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
  Sent: Wednesday, December 24, 2014 6:20 AM
  To: Gupta Ruchika-R66431
  Cc: U-Boot Mailing List; Sun York-R58495
  Subject: Re: [PATCH 9/9] [v3] rsa: Use checksum algorithms from
  struct hash_algo
 
  Hi Ruchika,
 
  On 23 December 2014 at 04:32, Ruchika Gupta
  ruchika.gu...@freescale.com
  wrote:
   Currently the hash functions used in RSA are called directly from
   the
   sha1 and sha256 libraries. Change the RSA checksum library to use
   the progressive hash API's registered with struct hash_algo. This
   will allow the checksum library to use the hardware accelerated
   progressive hash
  API's once available.
  
   Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
   CC: Simon Glass s...@chromium.org
   ---
   Changes in v3:
   Modified rsa-verify to check for return from checksum function
  
   Changes in v2:
   Added generic function hash_calculate. Pass an additional argument
   as name of algorithm.
  
common/image-sig.c|  6 ++---
include/image.h   |  5 ++--
include/u-boot/rsa-checksum.h |  7 +++---
lib/rsa/rsa-checksum.c| 53
  +++
lib/rsa/rsa-verify.c  |  7 +-
5 files changed, 64 insertions(+), 14 deletions(-)
  
   diff --git a/common/image-sig.c b/common/image-sig.c index
   8601eda..2c9f0cd 100644
   --- a/common/image-sig.c
   +++ b/common/image-sig.c
   @@ -38,7 +38,7 @@ struct checksum_algo checksum_algos[] = {  #if
   IMAGE_ENABLE_SIGN
   EVP_sha1,
#endif
   -   sha1_calculate,
   +   hash_calculate,
   padding_sha1_rsa2048,
   },
   {
   @@ -48,7 +48,7 @@ struct checksum_algo checksum_algos[] = {  #if
   IMAGE_ENABLE_SIGN
   EVP_sha256,
#endif
   -   sha256_calculate,
   +   hash_calculate,
   padding_sha256_rsa2048,
   },
   {
   @@ -58,7 +58,7 @@ struct checksum_algo checksum_algos[] = {  #if
   IMAGE_ENABLE_SIGN
   EVP_sha256,
#endif
   -   sha256_calculate,
   +   hash_calculate,
   padding_sha256_rsa4096,
   }
  
   diff --git a/include/image.h b/include/image.h index
   af30d60..ec55f23
   100644
   --- a/include/image.h
   +++ b/include/image.h
   @@ -926,8 +926,9 @@ struct checksum_algo {  #if IMAGE_ENABLE_SIGN
   const EVP_MD *(*calculate_sign)(void);  #endif
   -   void (*calculate)(const struct image_region region[],
   - int region_count, uint8_t *checksum);
   +   int (*calculate)(const char *name,
   +const struct image_region region[],
   +int region_count, uint8_t *checksum);
   const uint8_t *rsa_padding;  };
  
   diff --git a/include/u-boot/rsa-checksum.h
   b/include/u-boot/rsa-checksum.h index c996fb3..c546c80 100644
   --- a/include/u-boot/rsa-checksum.h
   +++ b/include/u-boot/rsa-checksum.h
   @@ -16,9 +16,8 @@ extern const uint8_t padding_sha256_rsa4096[];
   extern const uint8_t padding_sha256_rsa2048[];  extern const
   uint8_t padding_sha1_rsa2048[];
  
   -void sha256_calculate(const struct image_region region[], int
  region_count,
   - uint8_t *checksum);
   -void sha1_calculate(const struct image_region region[], int
 region_count,
   -   uint8_t *checksum);
   +int hash_calculate(const char *name,
   +  const struct image_region region[], int region_count,
   +  uint8_t *checksum);
  
 
  This could use a function comment.
 
#endif
   diff --git a/lib/rsa/rsa-checksum.c b/lib/rsa/rsa-checksum.c index
   8d8b59f..7f1909a 100644
   --- a/lib/rsa/rsa-checksum.c
   +++ b/lib/rsa/rsa-checksum.c
   @@ -10,12 +10,13 @@
#include asm/byteorder.h
#include asm/errno.h
#include asm/unaligned.h
   +#include hash.h
#else
#include fdt_host.h
   -#endif
   -#include u-boot/rsa.h
#include u-boot/sha1.h
#include u-boot/sha256.h
   +#endif
   +#include u-boot/rsa.h
  
/* PKCS 1.5 paddings as described in the RSA PKCS#1 v2.1 standard.
   */
  
   @@ -136,7 +137,33 @@ const uint8_t
   padding_sha256_rsa4096[RSA4096_BYTES -
  SHA256_SUM_LEN] = {
   0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20  };
  
   -void sha1_calculate(const struct image_region region[], int
   region_count,
   +#ifndef USE_HOSTCC
   +int 

Re: [U-Boot] [PATCH 04/10] x86: spi: Add device tree support

[Jagan Teki]

On 30 December 2014 at 06:42, Simon Glass s...@chromium.org wrote:
 As a temporary measure before the ICH driver moves over to driver model,
 add device tree support to the driver.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

  drivers/spi/ich.c| 7 +++
  include/configs/x86-common.h | 1 +
  2 files changed, 8 insertions(+)

 diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
 index 0379444..fdff158 100644
 --- a/drivers/spi/ich.c
 +++ b/drivers/spi/ich.c
 @@ -153,6 +153,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
 unsigned int cs,
 return ich-slave;
  }

 +struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
 + int spi_node)
 +{
 +   /* We only support a single SPI at present */
 +   return spi_setup_slave(0, 0, 2000, 0);
 +}
 +

This would call from spi_flash_probe_fdt(), who is the caller for this?

  void spi_free_slave(struct spi_slave *slave)
  {
 struct ich_spi_slave *ich = to_ich_spi(slave);
 diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
 index 4f0a3c5..ecedfc3 100644
 --- a/include/configs/x86-common.h
 +++ b/include/configs/x86-common.h
 @@ -211,6 +211,7 @@
  #define CONFIG_CMD_SF_TEST
  #define CONFIG_CMD_SPI
  #define CONFIG_SPI
 +#define CONFIG_OF_SPI_FLASH

  /*---
   * Environment configuration
 --
 2.2.0.rc0.207.ga3a616c


thanks!
-- 
Jagan.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2] Exynos: Move down common USB configuration

[Minkyu Kang]

Dear Sjoerd Simons,

On 30/12/14 06:17, Sjoerd Simons wrote:
 USB is a pretty common feature on exynos 5 board, so it seems sensible
 to configure it directly from exynos5-common. As a side-effect this
 makes USB available from u-boot on exynos 5420 based boards.
 
 While there enable support for common USB ethernet cards to make it more
 likely the default config allows booting for network and enable XHCI on
 SMDK5420 which has it defined in the dts but not in its config.
 
 Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk
 Acked-by: Simon Glass s...@chromium.org
 ---
 

applied to u-boot-samsung.

Thanks,
Minkyu Kang.

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 8/9] [v3] hash: Add function to find hash_algo struct with progressive hash

[Ruchika Gupta]

Hi Simon,

 -Original Message-
 From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
 Sent: Tuesday, December 30, 2014 2:44 AM
 To: Gupta Ruchika-R66431
 Cc: U-Boot Mailing List; Sun York-R58495; Wolfgang Denk
 Subject: Re: [PATCH 8/9] [v3] hash: Add function to find hash_algo struct
 with progressive hash
 
 +Wolfgang
 
 Hi Ruchika,
 
 On 29 December 2014 at 00:07, Ruchika Gupta ruchika.gu...@freescale.com
 wrote:
  Hi Simon,
 
  -Original Message-
  From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
  Sent: Wednesday, December 24, 2014 6:20 AM
  To: Gupta Ruchika-R66431
  Cc: U-Boot Mailing List; Sun York-R58495
  Subject: Re: [PATCH 8/9] [v3] hash: Add function to find hash_algo
  struct with progressive hash
 
  Hi Ruchika,
 
  On 23 December 2014 at 04:32, Ruchika Gupta
  ruchika.gu...@freescale.com
  wrote:
   The hash_algo structure has some implementations in which
   progressive hash API's are not defined. These are basically the
   hardware based implementations of SHA. An API is added to find the
   algo which has progressive hash API's defined. This can then be
   integrated with RSA checksum library which uses Progressive Hash API's.
  
   Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
   CC: Simon Glass s...@chromium.org
   ---
   Changes in v3 :
   Corrected ifdef for SHA1
  
   Changes in v2 :
   Added commit message
  
common/hash.c  | 33 -
   include/hash.h
   | 15 +++
2 files changed, 39 insertions(+), 9 deletions(-)
  
   diff --git a/common/hash.c b/common/hash.c index 12d6759..ea1ec60
   100644
   --- a/common/hash.c
   +++ b/common/hash.c
   @@ -20,7 +20,7 @@
#include asm/io.h
#include asm/errno.h
  
   -#ifdef CONFIG_CMD_SHA1SUM
   +#ifdef CONFIG_SHA1
 
  I'm still not sure about this. I suspect this will bloat the code for
  boards that use CONFIG_SHA1 (most) but not CONFIG_CMD_SHA1SUM. You
  could check that, but I went through some contortions to make sure
  that the hash API was not compiled in when not needed.
 
  Since we will be using this API now in RSA checksum, defining CONFIG_SHA1
 should allow the compilation of this structure. Asking user to enable
 CONFIG_CMD_SHA1SUM for using rsa-checksum doesn’t look right. Please suggest.
 
 Agreed it doesn't, it was just a code size hack. Wolfgang might be able to
 chime in with thoughts here (+Cc).
 
 But still, do you need to change it? After all, CONFIG_CMD_SHA1SUM should be
 a superest for CONFIG_SHA1.
With CONFIG_FIT_SIGNATURE, CONFIG_SHA1 and CONFIG_SHA256 get automatically 
defined in include/image.h. I need to use the structure hash_algos to find the  
functions to be used for algo SHA1. If I leave this as it is, it would mean 
that I will have to modify include/image.h to define CONFIG_CMD_SHA1SUM for FIT 
signatures. I am not sure whether that would be the right thing to do.
 
 [snip]
 
 Regards,
 Simon

Regards,
Ruchika
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] please pull u-boot-samsung master

[Minkyu Kang]

Dear Tom,

The following changes since commit d8bec60c1b0de7770f9b56ad092ab9be801d99af:

  ARM: UniPhier: enable CONFIG_CMD_DM (2014-12-18 23:34:30 +0900)

are available in the git repository at:

  http://git.denx.de/u-boot-samsung 

for you to fetch changes up to 66223787869e2059560ac583431e9968ac4cf26f:

  Exynos: Move down common USB configuration (2014-12-30 17:04:02 +0900)


Hyungwon Hwang (3):
  config: exynos5420: move non common configs to specific board files
  Odroid-XU3: Add support for Odroid-XU3
  Odroid-XU3: Add documentation for Odroid-XU3

Joonyoung Shim (1):
  arm: exynos: clock: support SPLL as mmc source clock for exynos5420

Sjoerd Simons (5):
  Exynos5800: The Peach-Pi board does not have a Parade video bridge
  exynos5420: fix compilation without parade video
  odroid-XU3: Add entry for DTS EHCI GPIO
  ARM: exynos5420: Leave VBUS GPIO configuration up to common code
  Exynos: Move down common USB configuration

 arch/arm/cpu/armv7/exynos/Kconfig |4 +++
 arch/arm/cpu/armv7/exynos/clock.c |2 ++
 arch/arm/dts/Makefile |3 +-
 arch/arm/dts/exynos5422-odroidxu3.dts |   49 +
 arch/arm/dts/exynos5800-peach-pi.dts  |5 ---
 arch/arm/include/asm/arch-exynos/system.h |3 --
 board/samsung/smdk5420/Kconfig|   13 +++
 board/samsung/smdk5420/smdk5420.c |   17 +
 configs/odroid-xu3_defconfig  |4 +++
 doc/README.odroid |   47 +++-
 include/configs/arndale.h |4 ---
 include/configs/exynos5-common.h  |   10 ++
 include/configs/exynos5250-common.h   |5 ---
 include/configs/exynos5420-common.h   |   20 ---
 include/configs/odroid_xu3.h  |   55 +
 include/configs/peach-pi.h|6 
 include/configs/peach-pit.h   |6 
 include/configs/smdk5420.h|   15 
 include/parade.h  |   18 ++
 19 files changed, 216 insertions(+), 70 deletions(-)
 create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts
 create mode 100644 configs/odroid-xu3_defconfig
 create mode 100644 include/configs/odroid_xu3.h
 create mode 100644 include/parade.h

-- 
Thanks,
Minkyu Kang.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 2/6] imx:mx6sxsabresd select SUPPORT_SPL

[Peng Fan]

select SUPPORT_SPL for mx6sxsabresd.

Signed-off-by: Peng Fan peng@freescale.com
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5eb1d03..46e708f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -637,6 +637,7 @@ config TARGET_MX6SLEVK
 config TARGET_MX6SXSABRESD
bool Support mx6sxsabresd
select CPU_V7
+   select SUPPORT_SPL
 
 config TARGET_GW_VENTANA
bool Support gw_ventana
-- 
1.8.4


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 3/6] imx:mx6sxsabresd spl support in header file

[Peng Fan]

Add SPL support in mx6sxsabresd header file.

Signed-off-by: Peng Fan peng@freescale.com
---
 include/configs/mx6sxsabresd.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 61a7a7a..19ac3dc 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -18,6 +18,12 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#include imx6_spl.h
+#endif
+
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
-- 
1.8.4


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 5/6] imx:mx6 add mx6sx in imx spl header file

[Peng Fan]

Since mx6sx's memory space is different to mx6dq, redefine the SPL
related macro for mx6sx chip.

Signed-off-by: Peng Fan peng@freescale.com
---
 include/configs/imx6_spl.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 1b9c277..21c5dce 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -61,11 +61,19 @@
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #endif
 
+#if defined(CONFIG_MX6SX)
+#define CONFIG_SPL_BSS_START_ADDR  0x8820
+#define CONFIG_SPL_BSS_MAX_SIZE0x10/* 1 MB */
+#define CONFIG_SYS_SPL_MALLOC_START0x8830
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x320   /* 50 MB */
+#define CONFIG_SYS_TEXT_BASE   0x8780
+#else
 #define CONFIG_SPL_BSS_START_ADDR  0x1820
 #define CONFIG_SPL_BSS_MAX_SIZE0x10/* 1 MB */
 #define CONFIG_SYS_SPL_MALLOC_START0x1830
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x320   /* 50 MB */
 #define CONFIG_SYS_TEXT_BASE   0x1780
 #endif
+#endif
 
 #endif
-- 
1.8.4


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 6/6] imx:mx6sxsabresd board spl support

[Peng Fan]

Add board level spl support for mx6sxsabresd board.

Signed-off-by: Peng Fan peng@freescale.com
---
 board/freescale/mx6sxsabresd/MAINTAINERS|   1 +
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 168 
 2 files changed, 169 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS 
b/board/freescale/mx6sxsabresd/MAINTAINERS
index f52f300..c0f5d9c 100644
--- a/board/freescale/mx6sxsabresd/MAINTAINERS
+++ b/board/freescale/mx6sxsabresd/MAINTAINERS
@@ -4,3 +4,4 @@ S:  Maintained
 F: board/freescale/mx6sxsabresd/
 F: include/configs/mx6sxsabresd.h
 F: configs/mx6sxsabresd_defconfig
+F: configs/mx6sxsabresd_spl_defconfig
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index fd8bc72..74f6d40 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -326,6 +326,7 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_init(bd_t *bis)
 {
+#ifndef CONFIG_SPL_BUILD
int i, ret;
 
/*
@@ -369,6 +370,47 @@ int board_mmc_init(bd_t *bis)
}
 
return 0;
+#else
+   struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+   u32 val;
+   u32 port;
+
+   val = readl(src_regs-sbmr1);
+
+   if ((val  0xc0) != 0x40) {
+   printf(Not boot from USDHC!\n);
+   return -EINVAL;
+   }
+
+   port = (val  11)  0x3;
+   printf(port %d\n, port);
+   switch (port) {
+   case 1:
+   imx_iomux_v3_setup_multiple_pads(
+   usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+   usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+   break;
+   case 2:
+   imx_iomux_v3_setup_multiple_pads(
+   usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+   gpio_direction_input(USDHC3_CD_GPIO);
+   gpio_direction_output(USDHC3_PWR_GPIO, 1);
+   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+   usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+   break;
+   case 3:
+   imx_iomux_v3_setup_multiple_pads(
+   usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+   gpio_direction_input(USDHC4_CD_GPIO);
+   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+   usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+   break;
+   }
+
+   gd-arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+   return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
+#endif
 }
 
 int board_init(void)
@@ -394,3 +436,129 @@ int checkboard(void)
 
return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+#include libfdt.h
+#include spl.h
+#include asm/arch/mx6-ddr.h
+
+const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
+   .dram_dqm0 = 0x0028,
+   .dram_dqm1 = 0x0028,
+   .dram_dqm2 = 0x0028,
+   .dram_dqm3 = 0x0028,
+   .dram_ras = 0x0020,
+   .dram_cas = 0x0020,
+   .dram_odt0 = 0x0020,
+   .dram_odt1 = 0x0020,
+   .dram_sdba2 = 0x,
+   .dram_sdcke0 = 0x3000,
+   .dram_sdcke1 = 0x3000,
+   .dram_sdclk_0 = 0x0030,
+   .dram_sdqs0 = 0x0028,
+   .dram_sdqs1 = 0x0028,
+   .dram_sdqs2 = 0x0028,
+   .dram_sdqs3 = 0x0028,
+   .dram_reset = 0x0020,
+};
+
+const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
+   .grp_addds = 0x0020,
+   .grp_ddrmode_ctl = 0x0002,
+   .grp_ddrpke = 0x,
+   .grp_ddrmode = 0x0002,
+   .grp_b0ds = 0x0028,
+   .grp_b1ds = 0x0028,
+   .grp_ctlds = 0x0020,
+   .grp_ddr_type = 0x000c,
+   .grp_b2ds = 0x0028,
+   .grp_b3ds = 0x0028,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+   .p0_mpwldectrl0 = 0x00290025,
+   .p0_mpwldectrl1 = 0x00220022,
+   .p0_mpdgctrl0 = 0x41480144,
+   .p0_mpdgctrl1 = 0x01340130,
+   .p0_mprddlctl = 0x3C3E4244,
+   .p0_mpwrdlctl = 0x34363638,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+   .mem_speed = 1600,
+   .density = 4,
+   .width = 32,
+   .banks = 8,
+   .rowaddr = 15,
+   .coladdr = 10,
+   .pagesz = 2,
+   .trcd = 1375,
+   .trcmin = 4875,
+   .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+   struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   writel(0x, ccm-CCGR0);
+   writel(0x, ccm-CCGR1);
+   writel(0x, ccm-CCGR2);
+   writel(0x, ccm-CCGR3);
+   writel(0x, ccm-CCGR4);
+   writel(0x, ccm-CCGR5);
+   writel(0x, ccm-CCGR6);
+   writel(0x, ccm-CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+   struct mx6_ddr_sysinfo sysinfo = {
+   .dsize = mem_ddr.width/32,
+   .cs_density 

[U-Boot] [PATCH 1/6] imx:mx6sxsabresd add spl config file

[Peng Fan]

Add a SPL default configuration file for mx6sxsabresd board.

Signed-off-by: Peng Fan peng@freescale.com
---
 configs/mx6sxsabresd_spl_defconfig | 4 
 1 file changed, 4 insertions(+)
 create mode 100644 configs/mx6sxsabresd_spl_defconfig

diff --git a/configs/mx6sxsabresd_spl_defconfig 
b/configs/mx6sxsabresd_spl_defconfig
new file mode 100644
index 000..6b36e06
--- /dev/null
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_MX6SXSABRESD=y
-- 
1.8.4


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/9] [v4] rsa: Split the rsa-verify to separate the modular exponentiation

[Ruchika Gupta]

Public exponentiation which is required in rsa verify functionality is
tightly integrated with verification code in rsa_verify.c. The patch
splits the file into twp separating the modular exponentiation.

1. rsa-verify.c
- The file parses device tree keys node to fill a keyprop structure.
The keyprop structure can then be converted to implementation specific
format.
(struct rsa_pub_key for sw implementation)
- The parsed device tree node is then passed to a generic rsa_mod_exp
function.

2. rsa-mod-exp.c
Move the software specific functions related to modular exponentiation
from rsa-verify.c to this file.

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass s...@chromium.org
---
Changes in v4:
Modified rsa_mod_exp_sw function to add pointer to output length

Changes in v3:
Kconfig moved to separate patch. This patch just splits the file now

Changes in v2:
Addressed few of Simon Glass's comments:
- Kconfig option added for RSA
- Comments added for new keyprop struct

 include/u-boot/rsa-mod-exp.h |  49 +++
 lib/rsa/Makefile |   2 +-
 lib/rsa/rsa-mod-exp.c| 309 ++
 lib/rsa/rsa-verify.c | 343 +--
 tools/Makefile   |   3 +-
 5 files changed, 429 insertions(+), 277 deletions(-)
 create mode 100644 include/u-boot/rsa-mod-exp.h
 create mode 100644 lib/rsa/rsa-mod-exp.c

diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h
new file mode 100644
index 000..7b74f3c
--- /dev/null
+++ b/include/u-boot/rsa-mod-exp.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2014, Ruchika Gupta.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+*/
+
+#ifndef _RSA_MOD_EXP_H
+#define _RSA_MOD_EXP_H
+
+#include errno.h
+#include image.h
+
+/**
+ * struct key_prop - holder for a public key properties
+ *
+ * The struct has pointers to modulus (Typically called N),
+ * The inverse, R^2, exponent. These can be typecasted and
+ * used as byte arrays or converted to the required format
+ * as per requirement of RSA implementation.
+ */
+struct key_prop {
+   const void *rr; /* R^2 can be treated as byte array */
+   const void *modulus;/* modulus as byte array */
+   const void *public_exponent; /* public exponent as byte array */
+   uint32_t n0inv; /* -1 / modulus[0] mod 2^32 */
+   int num_bits;   /* Key length in bits */
+   uint32_t exp_len;   /* Exponent length in number of uint8_t */
+};
+
+/**
+ * rsa_mod_exp_sw() - Perform RSA Modular Exponentiation in sw
+ *
+ * Operation: result[] = sig ^ exponent % modulus
+ *
+ * @sig:   RSA PKCS1.5 signature
+ * @sig_len:   Length of signature in number of bytes
+ * @node:  Node with RSA key elements like modulus, exponent, R^2, n0inv
+ * @outp:  Set to an allocated buffer holding the output hash
+ * @out_len:   Set to length of hash(outp) calculated after exponentiation
+ *
+ * This computes exponentiation over the signature. Resulting hash value is
+ * placed in an allocated buffer, the pointer is returned as *outp. The
+ * length of calulated hash is returned via the out_len pointer argument. The
+ * caller should free *outp
+ */
+int rsa_mod_exp_sw(const uint8_t *sig, uint32_t sig_len,
+   struct key_prop *node, uint8_t **outp, uint32_t *out_len);
+
+#endif
diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile
index a5a96cb6..cc25b3c 100644
--- a/lib/rsa/Makefile
+++ b/lib/rsa/Makefile
@@ -7,4 +7,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o
+obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o rsa-mod-exp.o
diff --git a/lib/rsa/rsa-mod-exp.c b/lib/rsa/rsa-mod-exp.c
new file mode 100644
index 000..af01b74
--- /dev/null
+++ b/lib/rsa/rsa-mod-exp.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef USE_HOSTCC
+#include common.h
+#include fdtdec.h
+#include asm/types.h
+#include asm/byteorder.h
+#include asm/errno.h
+#include asm/types.h
+#include asm/unaligned.h
+#else
+#include fdt_host.h
+#include mkimage.h
+#include fdt_support.h
+#endif
+#include malloc.h
+#include u-boot/rsa.h
+#include u-boot/rsa-mod-exp.h
+
+#define UINT64_MULT32(v, multby)  (((uint64_t)(v)) * ((uint32_t)(multby)))
+
+#define get_unaligned_be32(a) fdt32_to_cpu(*(uint32_t *)a)
+#define put_unaligned_be32(a, b) (*(uint32_t *)(b) = cpu_to_fdt32(a))
+
+/* Default public exponent for backward compatibility */
+#define RSA_DEFAULT_PUBEXP 65537
+
+/**
+ * subtract_modulus() - subtract modulus from the given value
+ *
+ * @key:   Key containing modulus to subtract
+ * @num:   Number to subtract modulus from, as little endian word array
+ */
+static void subtract_modulus(const struct rsa_public_key *key, uint32_t num[])
+{
+   int64_t acc = 0;
+   uint i;
+
+   for (i = 0; i  key-len; i++) {
+   acc += (uint64_t)num[i] - 

[U-Boot] [PATCH 2/9] [v4] FIT: Modify option FIT_SIGNATURE in Kconfig

[Ruchika Gupta]

For FIT signature based approach to work, RSA library needs to be selected. The 
FIT_SIGNATURE option in Kconfig is modified to automatically select RSA.
Selecting RSA compiles the RSA library required for image verification.

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass s...@chromium.org
---
Changes in v4:
Expanded CONFIG_RSA with documentation link

Changes in v3:
New patch created for adding Kconfig option for FIT signature

 Kconfig | 3 ++-
 lib/Kconfig | 7 +++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/Kconfig b/Kconfig
index 153ee2b..c2d7cb9 100644
--- a/Kconfig
+++ b/Kconfig
@@ -116,8 +116,9 @@ config FIT_VERBOSE
depends on FIT
 
 config FIT_SIGNATURE
-   bool Enabel signature verification of FIT uImages
+   bool Enable signature verification of FIT uImages
depends on FIT
+   select RSA
help
  This option enables signature verification of FIT uImages,
  using a hash signed and verified using RSA.
diff --git a/lib/Kconfig b/lib/Kconfig
index 8460439..2455f7a 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -27,4 +27,11 @@ config SYS_HZ
  get_timer() must operate in milliseconds and this option must be
  set to 1000.
 
+config RSA
+   bool Use RSA Library
+   help
+ RSA support.This enables the RSA algorithm used for FIT image
+ verification in U-Boot.
+ See doc/uImage.FIT/signature.txt for more details.
+
 endmenu
-- 
1.8.1.4

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 3/9] [v4] DM: crypto/rsa: Add rsa Modular Exponentiation DM driver

[Ruchika Gupta]

Add a new rsa uclass for performing modular exponentiation and implement
the software driver basing on this uclass.

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass s...@chromium.org
---
Changes in v4:
Removed Kconfig option for DM_RSA
Corrected driver name for sw rsa driver
Updated the rsa_mod_exp operation to have output length

Changes in v3:
New patch with driver model for RSA UCLASS

 drivers/crypto/Makefile |  1 +
 drivers/crypto/rsa/Makefile |  7 +++
 drivers/crypto/rsa/rsa_sw.c | 39 +++
 drivers/crypto/rsa/rsa_uclass.c | 31 +++
 include/dm/uclass-id.h  |  1 +
 include/u-boot/rsa-mod-exp.h| 37 +
 6 files changed, 116 insertions(+)
 create mode 100644 drivers/crypto/rsa/Makefile
 create mode 100644 drivers/crypto/rsa/rsa_sw.c
 create mode 100644 drivers/crypto/rsa/rsa_uclass.c

diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 7b79237..a2f30fc 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -6,4 +6,5 @@
 #
 
 obj-$(CONFIG_EXYNOS_ACE_SHA)   += ace_sha.o
+obj-y += rsa/
 obj-y += fsl/
diff --git a/drivers/crypto/rsa/Makefile b/drivers/crypto/rsa/Makefile
new file mode 100644
index 000..927c5bd
--- /dev/null
+++ b/drivers/crypto/rsa/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_RSA) += rsa_uclass.o rsa_sw.o
diff --git a/drivers/crypto/rsa/rsa_sw.c b/drivers/crypto/rsa/rsa_sw.c
new file mode 100644
index 000..3dcd512
--- /dev/null
+++ b/drivers/crypto/rsa/rsa_sw.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Ruchika Gupta ruchika.gu...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include config.h
+#include common.h
+#include dm.h
+#include u-boot/rsa-mod-exp.h
+
+int mod_exp_sw(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
+   struct key_prop *prop, uint8_t **outp, uint32_t *out_len)
+{
+   int ret = 0;
+
+   ret = rsa_mod_exp_sw(sig, sig_len, prop, outp, out_len);
+   if (ret) {
+   debug(%s: RSA failed to verify: %d\n, __func__, ret);
+   return ret;
+   }
+
+   return 0;
+}
+
+static const struct rsa_ops rsa_ops_sw = {
+   .mod_exp= mod_exp_sw,
+};
+
+U_BOOT_DRIVER(rsa_sw) = {
+   .name   = rsa_sw,
+   .id = UCLASS_RSA,
+   .ops= rsa_ops_sw,
+};
+
+U_BOOT_DEVICE(rsa_sw) = {
+   .name = rsa_sw,
+};
diff --git a/drivers/crypto/rsa/rsa_uclass.c b/drivers/crypto/rsa/rsa_uclass.c
new file mode 100644
index 000..4d52dcc
--- /dev/null
+++ b/drivers/crypto/rsa/rsa_uclass.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc
+ * Author: Ruchika Gupta ruchika.gu...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include u-boot/rsa-mod-exp.h
+#include errno.h
+#include fdtdec.h
+#include malloc.h
+#include asm/io.h
+#include linux/list.h
+
+int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
+   struct key_prop *node, uint8_t **out, uint32_t *out_len)
+{
+   const struct rsa_ops *ops = device_get_ops(dev);
+
+   if (!ops-mod_exp)
+   return -ENOSYS;
+
+   return ops-mod_exp(dev, sig, sig_len, node, out, out_len);
+}
+
+UCLASS_DRIVER(rsa) = {
+   .id = UCLASS_RSA,
+   .name   = rsa,
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index f17c3c2..823e43c 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -33,6 +33,7 @@ enum uclass_id {
UCLASS_I2C, /* I2C bus */
UCLASS_I2C_GENERIC, /* Generic I2C device */
UCLASS_I2C_EEPROM,  /* I2C EEPROM device */
+   UCLASS_RSA, /* RSA Mod Exp device */
 
UCLASS_COUNT,
UCLASS_INVALID = -1,
diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h
index 7b74f3c..417e468 100644
--- a/include/u-boot/rsa-mod-exp.h
+++ b/include/u-boot/rsa-mod-exp.h
@@ -46,4 +46,41 @@ struct key_prop {
 int rsa_mod_exp_sw(const uint8_t *sig, uint32_t sig_len,
struct key_prop *node, uint8_t **outp, uint32_t *out_len);
 
+int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
+   struct key_prop *node, uint8_t **outp, uint32_t *out_len);
+
+/**
+ * struct struct rsa_ops - Driver model for RSA operations
+ *
+ * The uclass interface is implemented by all crypto devices which use
+ * driver model.
+ */
+struct rsa_ops {
+   /**
+* Perform Modular Exponentiation
+*
+* Operation: out[] = sig ^ exponent % modulus
+*
+* @dev:RSA Device
+* @sig:RSA PKCS1.5 signature
+* @sig_len:Length of signature in number of bytes
+* @node:

[U-Boot] [PATCH 7/9] [v4] lib/rsa: Add Kconfig for devices supporting RSA Modular Exponentiation

[Ruchika Gupta]

Kconfig option added for devices which support RSA Verification.
1. RSA_SOFTWARE_EXP
Enables driver for supporting RSA Modular Exponentiation in Software
2. RSA_FREESCALE_EXP
Enables driver for supporting RSA Modular Exponentiation using Freescale 
specific
driver

The above drivers use RSA uclass

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass s...@chromium.org
---
Changes in v4:
Introduced 2 options when CONFIG_RSA is selected:
RSA_SOFTWARE_EXP
RSA_FREESCALE_EXP

Removed RSA_HW. Changes the name pf RSA_SW to RSA_SOFTWARE_EXP

Changes in v3:
New patch

 lib/Kconfig | 10 +-
 lib/rsa/Kconfig | 30 ++
 2 files changed, 31 insertions(+), 9 deletions(-)
 create mode 100644 lib/rsa/Kconfig

diff --git a/lib/Kconfig b/lib/Kconfig
index f317f81..a1f30a2 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -27,14 +27,6 @@ config SYS_HZ
  get_timer() must operate in milliseconds and this option must be
  set to 1000.
 
-config RSA
-   bool Use RSA Library
-   depends on DM
-   help
- RSA support.This enables the RSA algorithm used for FIT image
- verification in U-Boot. RSA support for Modular exponentiation
- is implemented as a driver model. Driver Model should be enabled
- to select this option.
- See doc/uImage.FIT/signature.txt for more details.
+source lib/rsa/Kconfig
 
 endmenu
diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig
new file mode 100644
index 000..14155b9
--- /dev/null
+++ b/lib/rsa/Kconfig
@@ -0,0 +1,30 @@
+config RSA
+   bool Use RSA Library
+   depends on DM
+   select RSA_FREESCALE_EXP if FSL_CAAM
+   select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP
+   help
+ RSA support.This enables the RSA algorithm used for FIT image
+ verification in U-Boot. RSA support for Modular exponentiation
+ is implemented as a driver model. Driver Model should be enabled
+ to select this option.
+ See doc/uImage.FIT/signature.txt for more details.
+
+if RSA
+config RSA_SOFTWARE_EXP
+   bool Enable driver for RSA Modular Exponentiation in software
+   depends on DM  RSA
+   help
+ Enables driver for modular exponentiation in software. This is a RSA
+ algorithm used in FIT image verification. It required RSA Key as
+ input.
+ See doc/uImage.FIT/signature.txt for more details.
+
+config RSA_FREESCALE_EXP
+   bool Enable RSA Modular Exponentiation with FSL crypto accelerator
+   depends on DM  RSA  FSL_CAAM
+   help
+   Enables driver for RSA modular exponentiation using Freescale 
cryptographic
+   accelerator - CAAM.
+
+endif
-- 
1.8.1.4

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 5/9] [v4] lib/rsa: Modify rsa to use DM driver

[Ruchika Gupta]

Modify rsa_verify to use the rsa driver of DM library .The tools
will continue to use the same RSA sw library.

CONFIG_RSA is now dependent on CONFIG_DM. All configurations which
enable FIT based signatures have been modified to enable CONFIG_DM
by default.

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass s...@chromium.org
---
Changes in v4:
Make CONFIG_RSA always depenedent on Driver Model. 
Add CONFIG_DM in defconfigs of the platforms which enable CONFIG_FIT_SIGNATURE

Changes in v3:
New patch

 README |  7 ++-
 configs/ids8313_defconfig  |  1 +
 configs/sandbox_defconfig  |  1 +
 configs/zynq_microzed_defconfig|  1 +
 configs/zynq_zc70x_defconfig   |  1 +
 configs/zynq_zc770_xm010_defconfig |  1 +
 configs/zynq_zc770_xm012_defconfig |  1 +
 configs/zynq_zc770_xm013_defconfig |  1 +
 configs/zynq_zed_defconfig |  1 +
 configs/zynq_zybo_defconfig|  1 +
 include/configs/am335x_evm.h   |  3 +++
 include/configs/sandbox.h  |  1 -
 lib/Kconfig|  5 -
 lib/rsa/rsa-verify.c   | 19 +++
 14 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/README b/README
index 4ca04d0..1d7978f 100644
--- a/README
+++ b/README
@@ -3173,8 +3173,13 @@ CBFS (Coreboot Filesystem) support
This enables the RSA algorithm used for FIT image verification
in U-Boot. See doc/uImage.FIT/signature.txt for more 
information.
 
+   The Modular Exponentiation algorithm in RSA is implemented using
+   driver model. So CONFIG_DM needs to be enabled by default for 
this
+   library to function.
+
The signing part is build into mkimage regardless of this
-   option.
+   option. The software based modular exponentiation is built into
+   mkimage irrespective of this option.
 
 - bootcount support:
CONFIG_BOOTCOUNT_LIMIT
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 8479cd4..0950ec8 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -4,3 +4,4 @@ CONFIG_MPC83xx=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_TARGET_IDS8313=y
+CONFIG_DM=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 0111f25..660063e 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -3,4 +3,5 @@ CONFIG_OF_HOSTFILE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_DM=y
 CONFIG_DEFAULT_DEVICE_TREE=sandbox
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index b9a6fe5..8b985fe 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -6,4 +6,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_DM=y
 CONFIG_DEFAULT_DEVICE_TREE=zynq-microzed
diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig
index dc8aa84..cceb321 100644
--- a/configs/zynq_zc70x_defconfig
+++ b/configs/zynq_zc70x_defconfig
@@ -7,3 +7,4 @@ CONFIG_DEFAULT_DEVICE_TREE=zynq-zc702
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_DM=y
diff --git a/configs/zynq_zc770_xm010_defconfig 
b/configs/zynq_zc770_xm010_defconfig
index 2f5fa8c..2935c0d 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -8,3 +8,4 @@ CONFIG_DEFAULT_DEVICE_TREE=zynq-zc770-xm010
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_DM=y
diff --git a/configs/zynq_zc770_xm012_defconfig 
b/configs/zynq_zc770_xm012_defconfig
index a92d495..0401739 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -8,3 +8,4 @@ CONFIG_DEFAULT_DEVICE_TREE=zynq-zc770-xm012
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_DM=y
diff --git a/configs/zynq_zc770_xm013_defconfig 
b/configs/zynq_zc770_xm013_defconfig
index 3a02f75..a95970a 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -8,3 +8,4 @@ CONFIG_DEFAULT_DEVICE_TREE=zynq-zc770-xm013
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_DM=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 1d816f6..0fbc41a 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -7,3 +7,4 @@ CONFIG_DEFAULT_DEVICE_TREE=zynq-zed
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_DM=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 9183629..4e66760 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -7,3 +7,4 @@ CONFIG_DEFAULT_DEVICE_TREE=zynq-zybo
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_DM=y
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index cc36985..1eb0ce7 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -24,6 +24,9 @@

[U-Boot] [PATCH 6/9] [v4] DM: crypto/fsl - Add Freescale rsa DM driver

[Ruchika Gupta]

Driver added for RSA Modular Exponentiation using Freescale Hardware
Accelerator CAAM. The driver used uclass rsa.

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass s...@chromium.org
---
Changes in v4:
Modified for the changes in op function of rsa class mod_exp

Changes in v3:
Moved to integrate with RSA UCLASS

 drivers/crypto/Kconfig|  1 +
 drivers/crypto/fsl/Kconfig|  6 
 drivers/crypto/fsl/Makefile   |  1 +
 drivers/crypto/fsl/fsl_rsa.c  | 69 +++
 drivers/crypto/fsl/jobdesc.c  | 28 ++
 drivers/crypto/fsl/jobdesc.h  |  5 
 drivers/crypto/fsl/rsa_caam.h | 28 ++
 7 files changed, 138 insertions(+)
 create mode 100644 drivers/crypto/fsl/Kconfig
 create mode 100644 drivers/crypto/fsl/fsl_rsa.c
 create mode 100644 drivers/crypto/fsl/rsa_caam.h

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index e69de29..bd26a2b 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -0,0 +1 @@
+source drivers/crypto/fsl/Kconfig
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
new file mode 100644
index 000..86b2f2f
--- /dev/null
+++ b/drivers/crypto/fsl/Kconfig
@@ -0,0 +1,6 @@
+config FSL_CAAM
+   bool Freescale Crypto Driver Support
+   help
+ Enables the Freescale's Cryptographic Accelerator and Assurance
+ Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
+ Job Ring as interface to communicate with CAAM.
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index cb13d2e..db3c010 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -8,3 +8,4 @@
 
 obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
 obj-$(CONFIG_CMD_BLOB) += fsl_blob.o
+obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
diff --git a/drivers/crypto/fsl/fsl_rsa.c b/drivers/crypto/fsl/fsl_rsa.c
new file mode 100644
index 000..21156b2
--- /dev/null
+++ b/drivers/crypto/fsl/fsl_rsa.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Ruchika Gupta ruchika.gu...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include config.h
+#include common.h
+#include dm.h
+#include asm/types.h
+#include malloc.h
+#include jobdesc.h
+#include desc.h
+#include jr.h
+#include rsa_caam.h
+#include u-boot/rsa-mod-exp.h
+
+int fsl_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
+   struct key_prop *prop, uint8_t **outp, uint32_t *out_len)
+{
+   uint32_t keylen;
+   struct pk_in_params pkin;
+   uint32_t desc[MAX_CAAM_DESCSIZE];
+   int ret;
+
+   /* Length in bytes */
+   keylen = prop-num_bits / 8;
+
+   *outp = malloc(sig_len);
+   if (!*outp) {
+   debug(%s: Out of malloc space\n, __func__);
+   return -EFAULT;
+   }
+
+   printf(HW\n);
+   pkin.a = sig;
+   pkin.a_siz = sig_len;
+   pkin.n = prop-modulus;
+   pkin.n_siz = keylen;
+   pkin.e = prop-public_exponent;
+   pkin.e_siz = prop-exp_len;
+
+   inline_cnstr_jobdesc_pkha_rsaexp(desc, pkin, *outp, sig_len);
+
+   ret = run_descriptor_jr(desc);
+   if (ret) {
+   debug(%s: RSA failed to verify: %d\n, __func__, ret);
+   return -EFAULT;
+   }
+
+   *out_len = sig_len;
+
+   return 0;
+}
+
+static const struct rsa_ops fsl_rsa_ops = {
+   .mod_exp= fsl_mod_exp,
+};
+
+U_BOOT_DRIVER(fsl_rsa) = {
+   .name   = fsl_rsa,
+   .id = UCLASS_RSA,
+   .ops= fsl_rsa_ops,
+};
+
+U_BOOT_DEVICE(fsl_rsa) = {
+   .name = fsl_rsa,
+};
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c
index 1386bae..cc0dced 100644
--- a/drivers/crypto/fsl/jobdesc.c
+++ b/drivers/crypto/fsl/jobdesc.c
@@ -11,6 +11,7 @@
 #include common.h
 #include desc_constr.h
 #include jobdesc.h
+#include rsa_caam.h
 
 #define KEY_BLOB_SIZE  32
 #define MAC_SIZE   16
@@ -123,3 +124,30 @@ void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc)
append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
 OP_ALG_RNG4_SK);
 }
+
+/* Change key size to bytes form bits in calling function*/
+void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
+ struct pk_in_params *pkin, uint8_t *out,
+ uint32_t out_siz)
+{
+   dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out;
+
+   dma_addr_e = virt_to_phys((void *)pkin-e);
+   dma_addr_a = virt_to_phys((void *)pkin-a);
+   dma_addr_n = virt_to_phys((void *)pkin-n);
+   dma_addr_out = virt_to_phys((void *)out);
+
+   init_job_desc(desc, 0);
+   append_key(desc, dma_addr_e, pkin-e_siz, KEY_DEST_PKHA_E | CLASS_1);
+
+   append_fifo_load(desc, dma_addr_a,
+pkin-a_siz, LDST_CLASS_1_CCB | 

[U-Boot] [PATCH 4/9] [v4] configs: Move CONFIG_FIT_SIGNATURE to defconfig

[Ruchika Gupta]

For the platforms which use,CONFIG_FIT_SIGNATURE, the required configs are
moved to the platform's defconfig file. Selecting CONFIG_FIT_SIGNATURE using
defconfig automatically resolves the dependencies for signature verification.
The RSA library gets automatically selected and user does not have to define
CONFIG_RSA manually.

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass s...@chromium.org
Acked-by: Simon Glass s...@chromium.org

---
Changes in v4:
No changes

Changes in v3:
New patch 

 configs/ids8313_defconfig  | 2 ++
 configs/sandbox_defconfig  | 3 +++
 configs/zynq_microzed_defconfig| 3 +++
 configs/zynq_zc70x_defconfig   | 3 +++
 configs/zynq_zc770_xm010_defconfig | 3 +++
 configs/zynq_zc770_xm012_defconfig | 3 +++
 configs/zynq_zc770_xm013_defconfig | 3 +++
 configs/zynq_zed_defconfig | 3 +++
 configs/zynq_zybo_defconfig| 3 +++
 include/configs/am335x_evm.h   | 4 ++--
 include/configs/ids8313.h  | 3 ---
 include/configs/sandbox.h  | 3 ---
 include/configs/zynq-common.h  | 6 --
 13 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 1c665aa..8479cd4 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -1,4 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS=SYS_TEXT_BASE=0xFFF0
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
 CONFIG_TARGET_IDS8313=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 47d8400..0111f25 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,3 +1,6 @@
 CONFIG_OF_CONTROL=y
 CONFIG_OF_HOSTFILE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
 CONFIG_DEFAULT_DEVICE_TREE=sandbox
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 9588849..b9a6fe5 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -3,4 +3,7 @@ CONFIG_SPL=y
 +S:CONFIG_ZYNQ=y
 +S:CONFIG_TARGET_ZYNQ_MICROZED=y
 CONFIG_OF_CONTROL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
 CONFIG_DEFAULT_DEVICE_TREE=zynq-microzed
diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig
index cf50730..dc8aa84 100644
--- a/configs/zynq_zc70x_defconfig
+++ b/configs/zynq_zc70x_defconfig
@@ -4,3 +4,6 @@ CONFIG_SPL=y
 +S:CONFIG_TARGET_ZYNQ_ZC70X=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE=zynq-zc702
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
diff --git a/configs/zynq_zc770_xm010_defconfig 
b/configs/zynq_zc770_xm010_defconfig
index 8bb405d..2f5fa8c 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -5,3 +5,6 @@ CONFIG_SYS_EXTRA_OPTIONS=ZC770_XM010
 +S:CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE=zynq-zc770-xm010
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
diff --git a/configs/zynq_zc770_xm012_defconfig 
b/configs/zynq_zc770_xm012_defconfig
index 0ba5da5..a92d495 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -5,3 +5,6 @@ CONFIG_SYS_EXTRA_OPTIONS=ZC770_XM012
 +S:CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE=zynq-zc770-xm012
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
diff --git a/configs/zynq_zc770_xm013_defconfig 
b/configs/zynq_zc770_xm013_defconfig
index 13f8112..3a02f75 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -5,3 +5,6 @@ CONFIG_SYS_EXTRA_OPTIONS=ZC770_XM013
 +S:CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE=zynq-zc770-xm013
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index eb057fa..1d816f6 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -4,3 +4,6 @@ CONFIG_SPL=y
 +S:CONFIG_TARGET_ZYNQ_ZED=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE=zynq-zed
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 12311cd..9183629 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -4,3 +4,6 @@ CONFIG_SPL=y
 +S:CONFIG_TARGET_ZYNQ_ZYBO=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE=zynq-zybo
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 560e3bf..cc36985 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -23,8 +23,8 @@
 # define CONFIG_TIMESTAMP
 # define CONFIG_LZO
 # ifdef CONFIG_ENABLE_VBOOT
-#  define CONFIG_FIT_SIGNATURE
-#  define CONFIG_RSA
+# define CONFIG_FIT_SIGNATURE
+# define CONFIG_RSA
 # endif
 #endif
 
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index f084834..2384864 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ 

[U-Boot] [PATCH 9/9] [v4] rsa: Use checksum algorithms from struct hash_algo

[Ruchika Gupta]

Currently the hash functions used in RSA are called directly from the sha1
and sha256 libraries. Change the RSA checksum library to use the progressive
hash API's registered with struct hash_algo. This will allow the checksum
library to use the hardware accelerated progressive hash API's once available.

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass s...@chromium.org
---
Changes in v4:
No changes in this patch. Still under discussion

Changes in v3:
Modified rsa-verify to check for return from checksum function

Changes in v2:
Added generic function hash_calculate. Pass an additional
argument as name of algorithm. 

 common/image-sig.c|  6 ++---
 include/image.h   |  5 ++--
 include/u-boot/rsa-checksum.h | 17 ++
 lib/rsa/rsa-checksum.c| 53 +++
 lib/rsa/rsa-verify.c  |  7 +-
 5 files changed, 74 insertions(+), 14 deletions(-)

diff --git a/common/image-sig.c b/common/image-sig.c
index 8601eda..2c9f0cd 100644
--- a/common/image-sig.c
+++ b/common/image-sig.c
@@ -38,7 +38,7 @@ struct checksum_algo checksum_algos[] = {
 #if IMAGE_ENABLE_SIGN
EVP_sha1,
 #endif
-   sha1_calculate,
+   hash_calculate,
padding_sha1_rsa2048,
},
{
@@ -48,7 +48,7 @@ struct checksum_algo checksum_algos[] = {
 #if IMAGE_ENABLE_SIGN
EVP_sha256,
 #endif
-   sha256_calculate,
+   hash_calculate,
padding_sha256_rsa2048,
},
{
@@ -58,7 +58,7 @@ struct checksum_algo checksum_algos[] = {
 #if IMAGE_ENABLE_SIGN
EVP_sha256,
 #endif
-   sha256_calculate,
+   hash_calculate,
padding_sha256_rsa4096,
}
 
diff --git a/include/image.h b/include/image.h
index af30d60..ec55f23 100644
--- a/include/image.h
+++ b/include/image.h
@@ -926,8 +926,9 @@ struct checksum_algo {
 #if IMAGE_ENABLE_SIGN
const EVP_MD *(*calculate_sign)(void);
 #endif
-   void (*calculate)(const struct image_region region[],
- int region_count, uint8_t *checksum);
+   int (*calculate)(const char *name,
+const struct image_region region[],
+int region_count, uint8_t *checksum);
const uint8_t *rsa_padding;
 };
 
diff --git a/include/u-boot/rsa-checksum.h b/include/u-boot/rsa-checksum.h
index c996fb3..3c69d85 100644
--- a/include/u-boot/rsa-checksum.h
+++ b/include/u-boot/rsa-checksum.h
@@ -16,9 +16,18 @@ extern const uint8_t padding_sha256_rsa4096[];
 extern const uint8_t padding_sha256_rsa2048[];
 extern const uint8_t padding_sha1_rsa2048[];
 
-void sha256_calculate(const struct image_region region[], int region_count,
- uint8_t *checksum);
-void sha1_calculate(const struct image_region region[], int region_count,
-   uint8_t *checksum);
+/**
+ * hash_calculate() - Calculate hash over the data
+ *
+ * @name:  Name of algorithm to be used for hash calculation
+ * @region: Array having info of regions over which hash needs to be calculated
+ * @region_count: Number of regions in the region array
+ * @checksum: Buffer contanining the output hash
+ *
+ * @return 0 if OK,  0 if error
+ */
+int hash_calculate(const char *name,
+  const struct image_region region[], int region_count,
+  uint8_t *checksum);
 
 #endif
diff --git a/lib/rsa/rsa-checksum.c b/lib/rsa/rsa-checksum.c
index 8d8b59f..7f1909a 100644
--- a/lib/rsa/rsa-checksum.c
+++ b/lib/rsa/rsa-checksum.c
@@ -10,12 +10,13 @@
 #include asm/byteorder.h
 #include asm/errno.h
 #include asm/unaligned.h
+#include hash.h
 #else
 #include fdt_host.h
-#endif
-#include u-boot/rsa.h
 #include u-boot/sha1.h
 #include u-boot/sha256.h
+#endif
+#include u-boot/rsa.h
 
 /* PKCS 1.5 paddings as described in the RSA PKCS#1 v2.1 standard. */
 
@@ -136,7 +137,33 @@ const uint8_t padding_sha256_rsa4096[RSA4096_BYTES - 
SHA256_SUM_LEN] = {
0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
 };
 
-void sha1_calculate(const struct image_region region[], int region_count,
+#ifndef USE_HOSTCC
+int hash_calculate(const char *name,
+   const struct image_region region[],
+   int region_count, uint8_t *checksum)
+{
+   struct hash_algo *algo;
+   int ret = 0;
+   void *ctx;
+   uint32_t i;
+   i = 0;
+
+   ret = hash_progressive_lookup_algo(name, algo);
+   if (ret)
+   return ret;
+
+   algo-hash_init(algo, ctx);
+   for (i = 0; i  region_count - 1; i++)
+   algo-hash_update(algo, ctx, region[i].data, region[i].size, 0);
+
+   algo-hash_update(algo, ctx, region[i].data, region[i].size, 1);
+   algo-hash_finish(algo, ctx, checksum, algo-digest_size);
+
+   return 0;
+}
+
+#else
+int sha1_calculate(const struct image_region region[], int region_count,

[U-Boot] [PATCH 8/9] [v4] hash: Add function to find hash_algo struct with progressive hash

[Ruchika Gupta]

The hash_algo structure has some implementations in which progressive hash
API's are not defined. These are basically the hardware based implementations
of SHA. An API is added to find the algo which has progressive hash API's
defined. This can then be integrated with RSA checksum library which uses
Progressive Hash API's.

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: Simon Glass s...@chromium.org
---
Changes in v4:
Few cosmetic changes. Currently I have not replaced CONFIG_SHA1  with 
CONFIG_CMD_SHA1SUM.
Waiting for reply from Simon and Denx for the same.

Changes in v3 :
Corrected ifdef for SHA1

Changes in v2 :
Added commit message

 common/hash.c  | 33 -
 include/hash.h | 14 ++
 2 files changed, 38 insertions(+), 9 deletions(-)

diff --git a/common/hash.c b/common/hash.c
index 12d6759..ea1ec60 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -20,7 +20,7 @@
 #include asm/io.h
 #include asm/errno.h
 
-#ifdef CONFIG_CMD_SHA1SUM
+#ifdef CONFIG_SHA1
 static int hash_init_sha1(struct hash_algo *algo, void **ctxp)
 {
sha1_context *ctx = malloc(sizeof(sha1_context));
@@ -125,12 +125,7 @@ static struct hash_algo hash_algo[] = {
CHUNKSZ_SHA256,
},
 #endif
-   /*
-* This is CONFIG_CMD_SHA1SUM instead of CONFIG_SHA1 since otherwise
-* it bloats the code for boards which use SHA1 but not the 'hash'
-* or 'sha1sum' commands.
-*/
-#ifdef CONFIG_CMD_SHA1SUM
+#ifdef CONFIG_SHA1
{
sha1,
SHA1_SUM_LEN,
@@ -140,7 +135,6 @@ static struct hash_algo hash_algo[] = {
hash_update_sha1,
hash_finish_sha1,
},
-#define MULTI_HASH
 #endif
 #ifdef CONFIG_SHA256
{
@@ -152,7 +146,6 @@ static struct hash_algo hash_algo[] = {
hash_update_sha256,
hash_finish_sha256,
},
-#define MULTI_HASH
 #endif
{
crc32,
@@ -165,6 +158,10 @@ static struct hash_algo hash_algo[] = {
},
 };
 
+#if defined(CONFIG_SHA256) || defined(CONFIG_CMD_SHA1SUM)
+#define MULTI_HASH
+#endif
+
 #if defined(CONFIG_HASH_VERIFY) || defined(CONFIG_CMD_HASH)
 #define MULTI_HASH
 #endif
@@ -311,6 +308,24 @@ int hash_lookup_algo(const char *algo_name, struct 
hash_algo **algop)
return -EPROTONOSUPPORT;
 }
 
+int hash_progressive_lookup_algo(const char *algo_name,
+struct hash_algo **algop)
+{
+   int i;
+
+   for (i = 0; i  ARRAY_SIZE(hash_algo); i++) {
+   if (!strcmp(algo_name, hash_algo[i].name)) {
+   if (hash_algo[i].hash_init) {
+   *algop = hash_algo[i];
+   return 0;
+   }
+   }
+   }
+
+   debug(Unknown hash algorithm '%s'\n, algo_name);
+   return -EPROTONOSUPPORT;
+}
+
 void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output)
 {
int i;
diff --git a/include/hash.h b/include/hash.h
index d8ec4f0..c0a7ebc 100644
--- a/include/hash.h
+++ b/include/hash.h
@@ -128,6 +128,20 @@ int hash_block(const char *algo_name, const void *data, 
unsigned int len,
 int hash_lookup_algo(const char *algo_name, struct hash_algo **algop);
 
 /**
+ * hash_progressive_lookup_algo() - Look up hash_algo for prog. hash support
+ *
+ * The function returns the pointer to the struct or -EPROTONOSUPPORT if the
+ * algorithm is not available with progressive hash support.
+ *
+ * @algo_name: Hash algorithm to look up
+ * @algop: Pointer to the hash_algo struct if found
+ *
+ * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm.
+ */
+int hash_progressive_lookup_algo(const char *algo_name,
+struct hash_algo **algop);
+
+/**
  * hash_show() - Print out a hash algorithm and value
  *
  * You will get a message like this (without a newline at the end):
-- 
1.8.1.4

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 0/6] imx:mx6 spl support for mx6sxsabresd

[Peng Fan]

This patch set is to make mx6sxsabresd spl boot capable from USDHC.
SPL image is burned to sector 2 of SD card. u-boot.img is burned to
sector 138.

Since i.MX 6SoloX chip only supports one mmdc channel, in order to reuse
mx6_dram_cfg, define a new macro MMDC1. To i.MX 6SoloX, MMDC1 does nothing;
to others, MMDC1 effects as the original mmdc1-entry = value.

Peng Fan (6):
  imx:mx6sxsabresd add spl config file
  imx:mx6sxsabresd select SUPPORT_SPL
  imx:mx6sxsabresd spl support in header file
  imx:mx6sx add dram io configure for mx6sx
  imx:mx6 add mx6sx in imx spl header file
  imx:mx6sxsabresd board spl support

 arch/arm/Kconfig|   1 +
 arch/arm/cpu/armv7/mx6/ddr.c|  96 +---
 arch/arm/include/asm/arch-mx6/mx6-ddr.h |  46 
 board/freescale/mx6sxsabresd/MAINTAINERS|   1 +
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 168 
 configs/mx6sxsabresd_spl_defconfig  |   4 +
 include/configs/imx6_spl.h  |   8 ++
 include/configs/mx6sxsabresd.h  |   6 +
 8 files changed, 316 insertions(+), 14 deletions(-)
 create mode 100644 configs/mx6sxsabresd_spl_defconfig

-- 
1.8.4


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 4/6] imx:mx6sx add dram io configure for mx6sx

[Peng Fan]

Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs.
Add a new function mx6sx_dram_iocfg to configure dram io.

Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1
to replace mmdc1-entry=value for mx6sx. And to other mx6 soc, MMDC1
effects as mmdc1-entry=value.

Signed-off-by: Peng Fan peng@freescale.com
---
 arch/arm/cpu/armv7/mx6/ddr.c| 96 -
 arch/arm/include/asm/arch-mx6/mx6-ddr.h | 46 
 2 files changed, 128 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 7a9b03a..fef2231 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -12,6 +12,65 @@
 #include asm/io.h
 #include asm/types.h
 
+#if defined(CONFIG_MX6SX)
+/* Configure MX6SX mmdc iomux */
+void mx6sx_dram_iocfg(unsigned width,
+ const struct mx6sx_iomux_ddr_regs *ddr,
+ const struct mx6sx_iomux_grp_regs *grp)
+{
+   struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
+   struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
+
+   mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
+   mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
+
+   /* DDR IO TYPE */
+   writel(grp-grp_ddr_type, mx6_grp_iomux-grp_ddr_type);
+   writel(grp-grp_ddrpke, mx6_grp_iomux-grp_ddrpke);
+
+   /* CLOCK */
+   writel(ddr-dram_sdclk_0, mx6_ddr_iomux-dram_sdclk_0);
+
+   /* ADDRESS */
+   writel(ddr-dram_cas, mx6_ddr_iomux-dram_cas);
+   writel(ddr-dram_ras, mx6_ddr_iomux-dram_ras);
+   writel(grp-grp_addds, mx6_grp_iomux-grp_addds);
+
+   /* Control */
+   writel(ddr-dram_reset, mx6_ddr_iomux-dram_reset);
+   writel(ddr-dram_sdba2, mx6_ddr_iomux-dram_sdba2);
+   writel(ddr-dram_sdcke0, mx6_ddr_iomux-dram_sdcke0);
+   writel(ddr-dram_sdcke1, mx6_ddr_iomux-dram_sdcke1);
+   writel(ddr-dram_odt0, mx6_ddr_iomux-dram_odt0);
+   writel(ddr-dram_odt1, mx6_ddr_iomux-dram_odt1);
+   writel(grp-grp_ctlds, mx6_grp_iomux-grp_ctlds);
+
+   /* Data Strobes */
+   writel(grp-grp_ddrmode_ctl, mx6_grp_iomux-grp_ddrmode_ctl);
+   writel(ddr-dram_sdqs0, mx6_ddr_iomux-dram_sdqs0);
+   writel(ddr-dram_sdqs1, mx6_ddr_iomux-dram_sdqs1);
+   if (width = 32) {
+   writel(ddr-dram_sdqs2, mx6_ddr_iomux-dram_sdqs2);
+   writel(ddr-dram_sdqs3, mx6_ddr_iomux-dram_sdqs3);
+   }
+
+   /* Data */
+   writel(grp-grp_ddrmode, mx6_grp_iomux-grp_ddrmode);
+   writel(grp-grp_b0ds, mx6_grp_iomux-grp_b0ds);
+   writel(grp-grp_b1ds, mx6_grp_iomux-grp_b1ds);
+   if (width = 32) {
+   writel(grp-grp_b2ds, mx6_grp_iomux-grp_b2ds);
+   writel(grp-grp_b3ds, mx6_grp_iomux-grp_b3ds);
+   }
+   writel(ddr-dram_dqm0, mx6_ddr_iomux-dram_dqm0);
+   writel(ddr-dram_dqm1, mx6_ddr_iomux-dram_dqm1);
+   if (width = 32) {
+   writel(ddr-dram_dqm2, mx6_ddr_iomux-dram_dqm2);
+   writel(ddr-dram_dqm3, mx6_ddr_iomux-dram_dqm3);
+   }
+}
+#endif
+
 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 /* Configure MX6DQ mmdc iomux */
 void mx6dq_dram_iocfg(unsigned width,
@@ -184,12 +243,19 @@ void mx6sdl_dram_iocfg(unsigned width,
  */
 #define MR(val, ba, cmd, cs1) \
((val  16) | (1  15) | (cmd  4) | (cs1  3) | ba)
+#ifdef CONFIG_MX6SX
+#define MMDC1(entry, value)do {} while (0)
+#else
+#define MMDC1(entry, value) do { mmdc1-entry = value; } while (0)
+#endif
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  const struct mx6_mmdc_calibration *calib,
  const struct mx6_ddr3_cfg *ddr3_cfg)
 {
volatile struct mmdc_p_regs *mmdc0;
+#ifndef CONFIG_MX6SX
volatile struct mmdc_p_regs *mmdc1;
+#endif
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -203,7 +269,9 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
int cs;
 
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+#ifndef CONFIG_MX6SX
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+#endif
 
/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
@@ -362,12 +430,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
mmdc0-mprddlctl = calib-p0_mprddlctl;
mmdc0-mpwrdlctl = calib-p0_mpwrdlctl;
if (sysinfo-dsize  1) {
-   mmdc1-mpwldectrl0 = calib-p1_mpwldectrl0;
-   mmdc1-mpwldectrl1 = calib-p1_mpwldectrl1;
-   mmdc1-mpdgctrl0 = calib-p1_mpdgctrl0;
-   mmdc1-mpdgctrl1 = calib-p1_mpdgctrl1;
-   mmdc1-mprddlctl = calib-p1_mprddlctl;
-   mmdc1-mpwrdlctl = calib-p1_mpwrdlctl;
+   MMDC1(mpwldectrl0, calib-p1_mpwldectrl0);
+   

Re: [U-Boot] Issue with uboot on imx6slevk

[Arthur Lambert]

Hi Fabio,

Thanks you :) I was able to run my linux sdcard image this morning
thanks to your input (I had modify the loadaddr value in the config on
the root directory of my buildroot project)

Arthur.

2014-12-29 21:19 GMT+01:00 Fabio Estevam feste...@gmail.com:
 Hi Arthur,

 On Mon, Dec 29, 2014 at 6:12 PM, Arthur Lambert
 lambertarthu...@gmail.com wrote:
 Hi Fabio,

 Ok I will test it tomorrow. Thanks for the reply. I did not know that
 I can use the main uboot for my build instead of the fork from
 Freescale for mx6

 I think I understand the issue you reported.

 You are booting a uImage kernel:

 ## Booting kernel from Legacy Image at 8080 ...
Image Name:   Linux-3.10.17
Image Type:   ARM Linux Kernel Image (uncompressed)
Data Size:5258504 Bytes = 5 MiB
Load Address: 10008000
Entry Point:  10008000
Verifying Checksum ... OK

 ,but the LOADADDR is incorrect: instead of 10008000 it should be 80008000

 (0x10008000 is the LOADADDR for the other mx6 SoCs, but not for solo-lite).

 So you should generate your kernel with the correct LOADADDR:

 make uImage LOADADDR=0x80008000

 Then you should be able to boot it with your current 2013.04 U-boot.

 With the latest U-boot version we use zImage by default, so there is
 no need to worry about passing the correct LOADADDR.



-- 
- Arthur LAMBERT
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 15/17] sunxi: Ippo_q8h defconfigs: Enable the LCD panel found on these tablets.

[Siarhei Siamashka]

On Thu, 25 Dec 2014 11:59:55 +0100
Hans de Goede hdego...@redhat.com wrote:

 Hi,
 
 On 25-12-14 11:00, Chen-Yu Tsai wrote:
  Hi,
 
  On Thu, Dec 25, 2014 at 3:06 AM, Hans de Goede hdego...@redhat.com wrote:
  Enable the new LCD support on Ippo_q8h tablets.
 
  Signed-off-by: Hans de Goede hdego...@redhat.com
  ---
configs/Ippo_q8h_v1_2_defconfig | 5 -
configs/Ippo_q8h_v5_defconfig   | 5 -
2 files changed, 8 insertions(+), 2 deletions(-)
 
  diff --git a/configs/Ippo_q8h_v1_2_defconfig 
  b/configs/Ippo_q8h_v1_2_defconfig
  index fefed32..c773f5f 100644
  --- a/configs/Ippo_q8h_v1_2_defconfig
  +++ b/configs/Ippo_q8h_v1_2_defconfig
  @@ -1,7 +1,10 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=5
CONFIG_FDTFILE=sun8i-a23-ippo-q8h-v1.2.dtb
  -CONFIG_VIDEO=n
  +CONFIG_VIDEO_LCD_MODE=x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
  +CONFIG_VIDEO_LCD_POWER=PH7
  +CONFIG_VIDEO_LCD_BL_EN=PH6
  +CONFIG_VIDEO_LCD_BL_PWM=PH0
CONFIG_USB_KEYBOARD=n
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
  diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig
  index b8d3afe..ce4f0b8 100644
  --- a/configs/Ippo_q8h_v5_defconfig
  +++ b/configs/Ippo_q8h_v5_defconfig
  @@ -1,7 +1,10 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=5
CONFIG_FDTFILE=sun8i-a23-ippo-q8h-v5.dtb
  -CONFIG_VIDEO=n
  +CONFIG_VIDEO_LCD_MODE=x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
 
  The display on my Q8H is a bit off to the left. With the simplefb
  bindings from your kernel sunxi-wip branch, I get a nice console.
  Though I've no way to type, at least I can tell my tablet is on. :)
 
  Could you briefly explain how to convert the values in the fex
  file to the mode line here? It could also help others with
  enabling display on their tablets.
 
 Ah yes, I used the slightly different timings from the olimex 7 lcd
 panel for olinuxino boards, and since those worked fine on my a23
 tablet I never adjusted things. Here is a translation table:
 
 
 CONFIG_VIDEO_LCD_MODE fex value(s)
 
 x lcd_x
 y lcd_y
 depth:18  lcd_frm = 1
 pclk_khz  lcd_dclk_freq * 1000
 hslcd_hv_hspw (with a minimum of 1)
 vslcd_hv_vspw (with a minimum of 1)
 lelcd_hbp - hs
 rilcd_ht - lcd_x - lcd_hbp
 uplcd_vbp - vs
 
 On sun4i/sun5i/sun7i:
 lo(lcd_vt / 2) - lcd_y - lcd_vbp
 On sun8i:
 lolcd_vt - lcd_y - lcd_vbp
 
 sync  0
 mode  0
 
 I notice that the Ippo_q8h_v5 fex uses 0 for lcd_hv_hspw and lcd_hv_vspw, 
 which
 is not a valid value as the register value contains hspw - 1, so the minimum 
 is 1,
 and looking at a register dump under android with my A23 tablet the value 
 indeed
 should be 1.

That's interesting. What would be the correct general formula for the
hs/vs values then? max(lcd_hv_hspw, 1) or maybe lcd_hv_hspw + 1?

BTW, I have done a preliminary automatic conversion for all FEX
files from sunxi-boards, which enable lcd0 in fex. The results are
now available at the all the same http://linux-sunxi.org/LCD wiki page.
If hs = lcd_hv_hspw + 1 is a better choice, then the whole table
probably needs to be re-generated.

Also additional explanations about GPIO related options (what would be
the exact rules to interpret FEX?) and more details about lcd_frm and
lcd_if would help a lot to get a better understanding about what
still needs to be done to get LCD displays supported on all devices.

If I understand it correctly, the kernel sources from the Allwinner SDK
contain the relevant code for handling the information from FEX, and
this code is the best reference. And it's more reliable to refer to
A23 SDK for interpreting the FEX files originally snatched from A23
devices, and likewise A31 SDK for A31 devices. For example, it is not
uncommon to see both 'lcd_pwm_used' and 'lcd_pwm_not_used' variables
defined in FEX. And sometimes the values of these variables even
contradict each other. So the fine details about the relative
priorities of these variables and other similar things might need
to be discovered for perfectly correct conversion.

-- 
Best regards,
Siarhei Siamashka
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 11/17] sunxi: video: Add support for VGA via external DACs connected to the LCD pins

[Hans de Goede]

Hi,

On 30-12-14 03:21, Chen-Yu Tsai wrote:

Hi Hans,

On Tue, Dec 30, 2014 at 3:25 AM, Hans de Goede hdego...@redhat.com wrote:

Hi,


On 29-12-14 14:51, Ian Campbell wrote:


On Wed, 2014-12-24 at 20:06 +0100, Hans de Goede wrote:


Add support for external DACs connected to the parallel LCD interface
driving
a VGA connector, such as found on the Olimex A13 boards.

Signed-off-by: Hans de Goede hdego...@redhat.com



Acked-by: Ian Campbell i...@hellion.org.uk


---
   board/sunxi/Kconfig   |  9 +
   drivers/video/sunxi_display.c | 14 ++
   2 files changed, 23 insertions(+)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 7a8503b..3e42866 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -253,6 +253,15 @@ config VIDEO_HDMI
 ---help---
 Say Y here to add support for outputting video over HDMI.

+config VIDEO_VGA_VIA_LCD
+   boolean VGA via LCD controller support
+   depends on VIDEO
+   default n
+   ---help---
+   Say Y here to add support for external DACs connected to the
parallel
+   LCD interface driving a VGA connector, such as found on the
+   Olimex A13 boards.



But not unique to those boards I take it?



Actually sofar it is unique to those boards, both the normal and the Micro
variant (in theory we could see something similar on other boards one day).


The Hummingbird A31 has the same setup, using an external DAC for the
RGB signals, as it doesn't have the TV encoder. See:

 http://linux-sunxi.org/Merrii_Hummingbird_A31#VGA_out


Interesting, it would be cool to see if this works with 
CONFIG_VIDEO_VGA_VIA_LCD=y
and something like setenv video-mode sunxi:1024x768-24@60,monitor=vga 
saveenv
with my sunxi-wip u-boot branch, I guess you need to add support for the enable 
gpio
for this to work, patches for this are welcome :)

Regards,

Hans
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 15/17] sunxi: Ippo_q8h defconfigs: Enable the LCD panel found on these tablets.

[Hans de Goede]

Hi,

On 30-12-14 11:18, Siarhei Siamashka wrote:

On Thu, 25 Dec 2014 11:59:55 +0100
Hans de Goede hdego...@redhat.com wrote:


Hi,

On 25-12-14 11:00, Chen-Yu Tsai wrote:

Hi,

On Thu, Dec 25, 2014 at 3:06 AM, Hans de Goede hdego...@redhat.com wrote:

Enable the new LCD support on Ippo_q8h tablets.

Signed-off-by: Hans de Goede hdego...@redhat.com
---
   configs/Ippo_q8h_v1_2_defconfig | 5 -
   configs/Ippo_q8h_v5_defconfig   | 5 -
   2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/configs/Ippo_q8h_v1_2_defconfig b/configs/Ippo_q8h_v1_2_defconfig
index fefed32..c773f5f 100644
--- a/configs/Ippo_q8h_v1_2_defconfig
+++ b/configs/Ippo_q8h_v1_2_defconfig
@@ -1,7 +1,10 @@
   CONFIG_SPL=y
   CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=5
   CONFIG_FDTFILE=sun8i-a23-ippo-q8h-v1.2.dtb
-CONFIG_VIDEO=n
+CONFIG_VIDEO_LCD_MODE=x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
+CONFIG_VIDEO_LCD_POWER=PH7
+CONFIG_VIDEO_LCD_BL_EN=PH6
+CONFIG_VIDEO_LCD_BL_PWM=PH0
   CONFIG_USB_KEYBOARD=n
   +S:CONFIG_ARM=y
   +S:CONFIG_ARCH_SUNXI=y
diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig
index b8d3afe..ce4f0b8 100644
--- a/configs/Ippo_q8h_v5_defconfig
+++ b/configs/Ippo_q8h_v5_defconfig
@@ -1,7 +1,10 @@
   CONFIG_SPL=y
   CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=5
   CONFIG_FDTFILE=sun8i-a23-ippo-q8h-v5.dtb
-CONFIG_VIDEO=n
+CONFIG_VIDEO_LCD_MODE=x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0


The display on my Q8H is a bit off to the left. With the simplefb
bindings from your kernel sunxi-wip branch, I get a nice console.
Though I've no way to type, at least I can tell my tablet is on. :)

Could you briefly explain how to convert the values in the fex
file to the mode line here? It could also help others with
enabling display on their tablets.


Ah yes, I used the slightly different timings from the olimex 7 lcd
panel for olinuxino boards, and since those worked fine on my a23
tablet I never adjusted things. Here is a translation table:


CONFIG_VIDEO_LCD_MODE   fex value(s)

x   lcd_x
y   lcd_y
depth:18lcd_frm = 1
pclk_khzlcd_dclk_freq * 1000
hs  lcd_hv_hspw (with a minimum of 1)
vs  lcd_hv_vspw (with a minimum of 1)
le  lcd_hbp - hs
ri  lcd_ht - lcd_x - lcd_hbp
up  lcd_vbp - vs

On sun4i/sun5i/sun7i:
lo  (lcd_vt / 2) - lcd_y - lcd_vbp
On sun8i:
lo  lcd_vt - lcd_y - lcd_vbp

sync0
mode0

I notice that the Ippo_q8h_v5 fex uses 0 for lcd_hv_hspw and lcd_hv_vspw, which
is not a valid value as the register value contains hspw - 1, so the minimum is 
1,
and looking at a register dump under android with my A23 tablet the value indeed
should be 1.


That's interesting. What would be the correct general formula for the
hs/vs values then? max(lcd_hv_hspw, 1) or maybe lcd_hv_hspw + 1?


Looking at the register values set by android vs the fex file, the correct
formula is max(lcd_hv_hspw, 1).


BTW, I have done a preliminary automatic conversion for all FEX
files from sunxi-boards, which enable lcd0 in fex. The results are
now available at the all the same http://linux-sunxi.org/LCD wiki page.


Cool, thanks for doing this!


If hs = lcd_hv_hspw + 1 is a better choice, then the whole table
probably needs to be re-generated.

Also additional explanations about GPIO related options (what would be
the exact rules to interpret FEX?) and more details about lcd_frm and
lcd_if would help a lot to get a better understanding about what
still needs to be done to get LCD displays supported on all devices.


Currently basically only lcd_if = 0 and lcd_frm = 1 are supported, it
should be possible to add support for other lcd_frm = x values easily,
so if you encounter those let me know, lcd_if != 0 is going to be much
harder to support and currently is not on my schedule.


If I understand it correctly, the kernel sources from the Allwinner SDK
contain the relevant code for handling the information from FEX, and
this code is the best reference. And it's more reliable to refer to
A23 SDK for interpreting the FEX files originally snatched from A23
devices, and likewise A31 SDK for A31 devices. For example, it is not
uncommon to see both 'lcd_pwm_used' and 'lcd_pwm_not_used' variables
defined in FEX. And sometimes the values of these variables even
contradict each other. So the fine details about the relative
priorities of these variables and other similar things might need
to be discovered for perfectly correct conversion.


All I can say here is that I agree with the above, I'm afraid I'm not
familiar enough with the (quite large) sunxi display code in the SDK
kernels to provide 

Re: [U-Boot] [PATCH 15/17] sunxi: Ippo_q8h defconfigs: Enable the LCD panel found on these tablets.

[Hans de Goede]

Hi,

On 30-12-14 11:26, Hans de Goede wrote:

Hi,

On 30-12-14 11:18, Siarhei Siamashka wrote:


snip


BTW, I have done a preliminary automatic conversion for all FEX
files from sunxi-boards, which enable lcd0 in fex. The results are
now available at the all the same http://linux-sunxi.org/LCD wiki page.


Cool, thanks for doing this!


I've just taken a look, looks good, as for the yellow entries with:

# warning: could not decode 'lcd_power' (port:power010default1)

Those should be translated to:

CONFIG_VIDEO_LCD_FOO=AXP0-0 for power0
CONFIG_VIDEO_LCD_FOO=AXP0-1 for power1

And I think you can also drop the:

# warning: 'lcd_pwm' gpio extracted from 'pwm0_para' section

That seems to be the right thing todo for A23 at least.

Regards,

Hans
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] v2015.01-rc4 REGRESSION: scripts: fix binutils-version.sh breaks things for non Linaro toolchains

[Hans de Goede]

Hi,

I noticed $subject while doing a MAKEALL.

It seems that this commit:
http://git.denx.de/?p=u-boot.git;a=commit;h=73c25753060c58e4c339fba306ed0ded0c335748

Breaks things with Fedora's arm toolchain:

[hans@shalem u-boot]$ scripts/binutils-version.sh arm-linux-gnu-as
scripts/binutils-version.sh: line 22: printf: GNU: invalid number
scripts/binutils-version.sh: line 22: printf: assembler: invalid number

scripts/binutils-version.sh: line 22: printf: version: invalid number
0002
2400

And:

[hans@shalem ~]$ arm-linux-gnu-as --version
GNU assembler version 2.24.0-6.fc21 20140613
Copyright 2013 Free Software Foundation, Inc.
This program is free software; you may redistribute it under the terms of
the GNU General Public License version 3 or later.
This program has absolutely no warranty.
This assembler was configured for a target of `arm-linux-gnueabi'.

Which makes $version_string: GNU assembler version 2.24.0-6.fc21 20140613
and $MAJOR: GNU assembler version 2

Regards,

Hans
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] phylib: add support for aquantia PHYs

[shh.xie]

From: Shaohui Xie shaohui@freescale.com

This patch supports AQ1202, AQ2104, AQR105 PHY.

Signed-off-by: Shaohui Xie shaohui@freescale.com
---
 drivers/net/phy/Makefile   |   1 +
 drivers/net/phy/aquantia.c | 156 +
 drivers/net/phy/phy.c  |   3 +
 include/phy.h  |   1 +
 4 files changed, 161 insertions(+)
 create mode 100644 drivers/net/phy/aquantia.c

diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 9556536..87d5c9c 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o
 
 obj-$(CONFIG_PHYLIB) += phy.o
 obj-$(CONFIG_PHYLIB_10G) += generic_10g.o
+obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o
 obj-$(CONFIG_PHY_ATHEROS) += atheros.o
 obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
 obj-$(CONFIG_PHY_DAVICOM) += davicom.o
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
new file mode 100644
index 000..ef4da4e
--- /dev/null
+++ b/drivers/net/phy/aquantia.c
@@ -0,0 +1,156 @@
+/*
+ * Aquantia PHY drivers
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+#include config.h
+#include common.h
+#include phy.h
+
+#ifndef CONFIG_PHYLIB_10G
+#error The Aquantia PHY needs 10G support
+#endif
+
+#define AQUNTIA_10G_CTL0x20
+#define AQUNTIA_VENDOR_P1  0xc400
+
+#define AQUNTIA_SPEED_LSB_MASK 0x2000
+#define AQUNTIA_SPEED_MSB_MASK 0x40
+
+int aquantia_config(struct phy_device *phydev)
+{
+   u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
+
+   if (phydev-interface == PHY_INTERFACE_MODE_SGMII) {
+   /* 1000BASE-T mode */
+   phydev-advertising = SUPPORTED_1000baseT_Full;
+   phydev-supported = phydev-advertising;
+
+   val = (val  ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
+   phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
+   } else if (phydev-interface == PHY_INTERFACE_MODE_XGMII) {
+   /* 10GBASE-T mode */
+   phydev-advertising = SUPPORTED_1baseT_Full;
+   phydev-supported = phydev-advertising;
+
+   if (!(val  AQUNTIA_SPEED_LSB_MASK) ||
+   !(val  AQUNTIA_SPEED_MSB_MASK))
+   phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
+ AQUNTIA_SPEED_LSB_MASK |
+ AQUNTIA_SPEED_MSB_MASK);
+   } else if (phydev-interface == PHY_INTERFACE_MODE_SGMII_2500) {
+   /* 2.5GBASE-T mode */
+   phydev-advertising = SUPPORTED_1000baseT_Full;
+   phydev-supported = phydev-advertising;
+
+   phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
+   phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
+   } else if (phydev-interface == PHY_INTERFACE_MODE_MII) {
+   /* 100BASE-TX mode */
+   phydev-advertising = SUPPORTED_100baseT_Full;
+   phydev-supported = phydev-advertising;
+
+   val = (val  ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
+   phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
+   }
+   return 0;
+}
+
+int aquantia_startup(struct phy_device *phydev)
+{
+   u32 reg, speed;
+   int i = 0;
+
+   phydev-duplex = DUPLEX_FULL;
+
+   /* if the AN is still in progress, wait till timeout. */
+   phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+   reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+   if (!(reg  MDIO_AN_STAT1_COMPLETE)) {
+   printf(%s Waiting for PHY auto negotiation to complete,
+  phydev-dev-name);
+   do {
+   udelay(1000);
+   reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+   if ((i++ % 500) == 0)
+   printf(.);
+   } while (!(reg  MDIO_AN_STAT1_COMPLETE) 
+i  (4 * PHY_ANEG_TIMEOUT));
+
+   if (i  PHY_ANEG_TIMEOUT)
+   printf( TIMEOUT !\n);
+   }
+
+   /* Read twice because link state is latched and a
+* read moves the current state into the register */
+   phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+   reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+   if (reg  0 || !(reg  MDIO_STAT1_LSTATUS))
+   phydev-link = 0;
+   else
+   phydev-link = 1;
+
+   speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
+   if (speed  AQUNTIA_SPEED_MSB_MASK) {
+   if (speed  AQUNTIA_SPEED_LSB_MASK)
+   phydev-speed = SPEED_1;
+   else
+   phydev-speed = SPEED_1000;
+   } else {
+   if (speed  AQUNTIA_SPEED_LSB_MASK)
+   phydev-speed = SPEED_100;
+   else
+   phydev-speed = SPEED_10;
+ 

Re: [U-Boot] [PATCH 15/17] sunxi: Ippo_q8h defconfigs: Enable the LCD panel found on these tablets.

[Siarhei Siamashka]

On Tue, 30 Dec 2014 11:36:23 +0100
Hans de Goede hdego...@redhat.com wrote:

 Hi,
 
 On 30-12-14 11:26, Hans de Goede wrote:
  Hi,
 
  On 30-12-14 11:18, Siarhei Siamashka wrote:
 
 snip
 
  BTW, I have done a preliminary automatic conversion for all FEX
  files from sunxi-boards, which enable lcd0 in fex. The results are
  now available at the all the same http://linux-sunxi.org/LCD wiki page.
 
  Cool, thanks for doing this!
 
 I've just taken a look, looks good, as for the yellow entries with:
 
 # warning: could not decode 'lcd_power' (port:power010default1)
 
 Those should be translated to:
 
 CONFIG_VIDEO_LCD_FOO=AXP0-0 for power0
 CONFIG_VIDEO_LCD_FOO=AXP0-1 for power1

Is this supported only for AXP209 so far? What about the devices with
a different PMIC?

 And I think you can also drop the:
 
 # warning: 'lcd_pwm' gpio extracted from 'pwm0_para' section
 
 That seems to be the right thing todo for A23 at least.

OK. Right now it looks up the pwmX_para section, where X is the
number from lcd_pwm_ch found in the lcd0_para section.

Thanks for your comments and clarifications.

-- 
Best regards,
Siarhei Siamashka
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 7/9] imx: woodburn: Remove reference to gdata

[Stefano Babic]

Hi Simon,

On 23/12/2014 20:04, Simon Glass wrote:
 The global_data pointer (gd) has already been set before board_init_f()
 is called. We should not assign it again. We should also not use gdata since
 it is going away.
 
 Signed-off-by: Simon Glass s...@chromium.org
 ---
 
  board/woodburn/woodburn.c | 3 ---
  1 file changed, 3 deletions(-)
 
 diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
 index 2744514..3da61a4 100644
 --- a/board/woodburn/woodburn.c
 +++ b/board/woodburn/woodburn.c
 @@ -137,9 +137,6 @@ void board_init_f(ulong dummy)
   /* Clear the BSS. */
   memset(__bss_start, 0, __bss_end - __bss_start);
  
 - /* Set global data pointer. */
 - gd = gdata;
 -
   preloader_console_init();
   timer_init();
  

Agree on this concept.

Acked-by: Stefano Babic sba...@denx.de

Best regards,
Stefano Babic



-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 15/17] sunxi: Ippo_q8h defconfigs: Enable the LCD panel found on these tablets.

[Siarhei Siamashka]

On Tue, 30 Dec 2014 11:26:51 +0100
Hans de Goede hdego...@redhat.com wrote:

 Hi,
 
 On 30-12-14 11:18, Siarhei Siamashka wrote:
  On Thu, 25 Dec 2014 11:59:55 +0100
  Hans de Goede hdego...@redhat.com wrote:
 
  Ah yes, I used the slightly different timings from the olimex 7 lcd
  panel for olinuxino boards, and since those worked fine on my a23
  tablet I never adjusted things. Here is a translation table:
 
 
  CONFIG_VIDEO_LCD_MODE  fex value(s)
 
  x  lcd_x
  y  lcd_y
  depth:18   lcd_frm = 1
  pclk_khz   lcd_dclk_freq * 1000
  hs lcd_hv_hspw (with a minimum of 1)
  vs lcd_hv_vspw (with a minimum of 1)
  le lcd_hbp - hs
  ri lcd_ht - lcd_x - lcd_hbp
  up lcd_vbp - vs
 
  On sun4i/sun5i/sun7i:
  lo (lcd_vt / 2) - lcd_y - lcd_vbp
  On sun8i:
  lo lcd_vt - lcd_y - lcd_vbp
 
  sync   0
  mode   0
 
  I notice that the Ippo_q8h_v5 fex uses 0 for lcd_hv_hspw and lcd_hv_vspw, 
  which
  is not a valid value as the register value contains hspw - 1, so the 
  minimum is 1,
  and looking at a register dump under android with my A23 tablet the value 
  indeed
  should be 1.
 
  That's interesting. What would be the correct general formula for the
  hs/vs values then? max(lcd_hv_hspw, 1) or maybe lcd_hv_hspw + 1?
 
 Looking at the register values set by android vs the fex file, the correct
 formula is max(lcd_hv_hspw, 1).

How can this be verified? Which hardware register needs to be read?

I can use Android to test this on Primo73 tablet, where the
hs/vs values are originally non-zero in fex.

  BTW, I have done a preliminary automatic conversion for all FEX
  files from sunxi-boards, which enable lcd0 in fex. The results are
  now available at the all the same http://linux-sunxi.org/LCD wiki page.
 
 Cool, thanks for doing this!
 
  If hs = lcd_hv_hspw + 1 is a better choice, then the whole table
  probably needs to be re-generated.
 
  Also additional explanations about GPIO related options (what would be
  the exact rules to interpret FEX?) and more details about lcd_frm and
  lcd_if would help a lot to get a better understanding about what
  still needs to be done to get LCD displays supported on all devices.
 
 Currently basically only lcd_if = 0 and lcd_frm = 1 are supported, it
 should be possible to add support for other lcd_frm = x values easily,
 so if you encounter those let me know, lcd_if != 0 is going to be much
 harder to support and currently is not on my schedule.

It's all in the orange part of the table at the bottom. The lcd_frm = 0
seems to be relatively common. The links to FEX files for each device
are also there in the table and can be used to confirm the details.

The http://linux-sunxi.org/Wexler_TAB_7200 tablet with its fex file
https://github.com/linux-sunxi/sunxi-boards/blob/master/sys_config/a20/wexler_tab_7200.fex
is one of the examples.

  If I understand it correctly, the kernel sources from the Allwinner SDK
  contain the relevant code for handling the information from FEX, and
  this code is the best reference. And it's more reliable to refer to
  A23 SDK for interpreting the FEX files originally snatched from A23
  devices, and likewise A31 SDK for A31 devices. For example, it is not
  uncommon to see both 'lcd_pwm_used' and 'lcd_pwm_not_used' variables
  defined in FEX. And sometimes the values of these variables even
  contradict each other. So the fine details about the relative
  priorities of these variables and other similar things might need
  to be discovered for perfectly correct conversion.
 
 All I can say here is that I agree with the above, I'm afraid I'm not
 familiar enough with the (quite large) sunxi display code in the SDK
 kernels to provide answers here.

I'm not familiar with that code either. I have just started looking at
these sources, searching for some answers. For example, that's where
I found the information about the 'pwm0_para' section and some other
things. SDK is not useful for anything other than the FEX interpretation
details. For implementing the actual code we do have the hardware
documentation.

Just right now it's a good idea to figure out some basic FEX conversion
rules and probably document them in the wiki. If you can share the
rest of the information that you know about this LCD code, it would
be surely a great help for this documentation and conversion code.

I also compared the config settings from your patches with the
automatically generated records and noticed some inconsistencies.

For example, Ippo_q8h_v1_2_defconfig :

=== A part of your patch:

+CONFIG_VIDEO_LCD_POWER=PH7
+CONFIG_VIDEO_LCD_BL_EN=PH6
+CONFIG_VIDEO_LCD_BL_PWM=PH0

=== My script:

# warning: could not decode 'lcd_power' (port:power210default1)

[U-Boot] Pull request: u-boot-uniphier

[Masahiro YAMADA]

The following changes since commit 125738e819a3b9d15210794b3dcef9f4d9bcf866:

  Prepare v2015.01-rc4 (2014-12-29 21:22:38 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-uniphier.git master

for you to fetch changes up to 7b77c9ab6fa90ada42185bcc64b7d33812fed35d:

  ARM: UniPhier: display boot swap pin status by pinmon command
(2014-12-30 17:45:40 +0900)


Masahiro Yamada (3):
  ARM: UniPhier: add DDR PHY training code
  ARM: UniPhier: add dump command of DDR PHY parameters
  ARM: UniPhier: display boot swap pin status by pinmon command

 arch/arm/cpu/armv7/uniphier/Kconfig|   7 ++
 arch/arm/cpu/armv7/uniphier/Makefile   |   2 +
 arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c   | 229

 arch/arm/cpu/armv7/uniphier/cmd_pinmon.c   |   3 +
 arch/arm/cpu/armv7/uniphier/ddrphy_training.c  | 144
+++
 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile   |   2 +-
 arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c  |  70 +
 arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c |  13 
 arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile  |   2 +-
 arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c |  70 +
 arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c|  25 +++
 arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile  |   2 +-
 arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c |  75 +++
 arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c|  13 
 arch/arm/include/asm/arch-uniphier/ddrphy-regs.h   | 172
++
 15 files changed, 826 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ddrphy_training.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c
 create mode 100644 arch/arm/include/asm/arch-uniphier/ddrphy-regs.h


-- 
Best Regards
Masahiro Yamada
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 0/3] ARM: UniPhier: add DDR PHY init code and utility command

[Masahiro YAMADA]

2014-12-19 20:20 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com:



 Masahiro Yamada (3):
   ARM: UniPhier: add DDR PHY training code
   ARM: UniPhier: add dump command of DDR PHY parameters
   ARM: UniPhier: display boot swap pin status by pinmon command


Series, applied to u-boot-uniphier/master


-- 
Best Regards
Masahiro Yamada
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] imx:mx6slevk add spi nor boot support

[Jagan Teki]

On 30 December 2014 at 08:44, Peng Fan peng@freescale.com wrote:
 Add spi nor boot support for mx6slevk board.

 Signed-off-by: Peng Fan peng@freescale.com
 ---
  board/freescale/mx6slevk/MAINTAINERS |  1 +
  configs/mx6slevk_spinor_defconfig|  3 +++
  include/configs/mx6slevk.h   | 13 -
  3 files changed, 16 insertions(+), 1 deletion(-)
  create mode 100644 configs/mx6slevk_spinor_defconfig

 diff --git a/board/freescale/mx6slevk/MAINTAINERS 
 b/board/freescale/mx6slevk/MAINTAINERS
 index 660af91..18d31a8 100644
 --- a/board/freescale/mx6slevk/MAINTAINERS
 +++ b/board/freescale/mx6slevk/MAINTAINERS
 @@ -4,3 +4,4 @@ S:  Maintained
  F: board/freescale/mx6slevk/
  F: include/configs/mx6slevk.h
  F: configs/mx6slevk_defconfig
 +F: configs/mx6slevk_spinor_defconfig
 diff --git a/configs/mx6slevk_spinor_defconfig 
 b/configs/mx6slevk_spinor_defconfig
 new file mode 100644
 index 000..93efe73
 --- /dev/null
 +++ b/configs/mx6slevk_spinor_defconfig
 @@ -0,0 +1,3 @@
 +CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR
 +CONFIG_ARM=y
 +CONFIG_TARGET_MX6SLEVK=y
 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
 index e3e7f76..e6c4130 100644
 --- a/include/configs/mx6slevk.h
 +++ b/include/configs/mx6slevk.h
 @@ -187,9 +187,20 @@
  /* FLASH and environment organization */
  #define CONFIG_SYS_NO_FLASH

 -#define CONFIG_ENV_OFFSET  (6 * SZ_64K)
  #define CONFIG_ENV_SIZESZ_8K
 +
 +#if defined CONFIG_SYS_BOOT_SPINOR
 +#define CONFIG_ENV_IS_IN_SPI_FLASH
 +#define CONFIG_ENV_OFFSET   (768 * 1024)
 +#define CONFIG_ENV_SECT_SIZE(64 * 1024)
 +#define CONFIG_ENV_SPI_BUS  CONFIG_SF_DEFAULT_BUS
 +#define CONFIG_ENV_SPI_CS   CONFIG_SF_DEFAULT_CS
 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
 +#define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED

If you need default values may be you couldn't define these so-that
common/env_sf.c
will take the defaults for undefs - please check.

 +#else
 +#define CONFIG_ENV_OFFSET  (6 * SZ_64K)
  #define CONFIG_ENV_IS_IN_MMC
 +#endif

  #define CONFIG_OF_LIBFDT
  #define CONFIG_CMD_BOOTZ
 --
 1.8.4


thanks!
-- 
Jagan.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/2] arm:mx6sx add QSPI support

[Jagan Teki]

Hi Peng/Fabio,

On 30 December 2014 at 00:14, Jagan Teki jagannadh.t...@gmail.com wrote:
 On 29 December 2014 at 23:58, Fabio Estevam feste...@gmail.com wrote:
 Hi Jagan,

 On Fri, Oct 10, 2014 at 6:58 AM, Albert ARIBAUD
 albert.u.b...@aribaud.net wrote:

 Jagan said he would review both patches. Once he gives his Acked-by,
 the patches will go in -- but note that the series is an addition, not
 a fix, and came in after the 2014.10 merge window, so it'll go in only
 after the upcoming release (that's only a few days anyway).

 Any comments about this series, please?

 I believe there is  a v3 series for this - will comment those.

These are v3 series for this patches-
https://patchwork.ozlabs.org/patch/399361/
https://patchwork.ozlabs.org/patch/399362/
https://patchwork.ozlabs.org/patch/399363/
https://patchwork.ozlabs.org/patch/399364/

Please confirm?

thanks!
-- 
Jagan.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/2] arm:mx6sx add QSPI support

[Fabio Estevam]

Hi Jagan,

On Tue, Dec 30, 2014 at 10:49 AM, Jagan Teki jagannadh.t...@gmail.com wrote:

 These are v3 series for this patches-
 https://patchwork.ozlabs.org/patch/399361/
 https://patchwork.ozlabs.org/patch/399362/
 https://patchwork.ozlabs.org/patch/399363/
 https://patchwork.ozlabs.org/patch/399364/

 Please confirm?

That's correct. Please let us know if you have comments about v3.

Thanks
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/2] arm:mx6sx add QSPI support

[Jagan Teki]

On 30 December 2014 at 18:32, Fabio Estevam feste...@gmail.com wrote:
 Hi Jagan,

 On Tue, Dec 30, 2014 at 10:49 AM, Jagan Teki jagannadh.t...@gmail.com wrote:

 These are v3 series for this patches-
 https://patchwork.ozlabs.org/patch/399361/
 https://patchwork.ozlabs.org/patch/399362/
 https://patchwork.ozlabs.org/patch/399363/
 https://patchwork.ozlabs.org/patch/399364/

 Please confirm?

 That's correct. Please let us know if you have comments about v3.

Please rebase and send the patches again, I have some issues while applying.
I will pick these on my tree.

thanks!
-- 
Jagan.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/2] arm:mx6sx add QSPI support

[Fabio Estevam]

On Tue, Dec 30, 2014 at 11:16 AM, Jagan Teki jagannadh.t...@gmail.com wrote:

 Please rebase and send the patches again, I have some issues while applying.
 I will pick these on my tree.

Peng, please rebase and resend the series. Thanks
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] imx SPL: enable boot from eMMC boot partitions.

[Stefano Babic]

On 12/12/2014 14:38, Pierre Aubert wrote:
 Signed-off-by: Pierre Aubert p.aub...@staubli.com
 ---
  arch/arm/imx-common/spl.c |4 +++-
  1 files changed, 3 insertions(+), 1 deletions(-)
 
 diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
 index 477c38c..ac6e40e 100644
 --- a/arch/arm/imx-common/spl.c
 +++ b/arch/arm/imx-common/spl.c
 @@ -68,8 +68,10 @@ u32 spl_boot_mode(void)
   /* for MMC return either RAW or FAT mode */
   case BOOT_DEVICE_MMC1:
   case BOOT_DEVICE_MMC2:
 -#ifdef CONFIG_SPL_FAT_SUPPORT
 +#if defined(CONFIG_SPL_FAT_SUPPORT)
   return MMCSD_MODE_FS;
 +#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
 + return MMCSD_MODE_EMMCBOOT;
  #else
   return MMCSD_MODE_RAW;
  #endif
 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 2/2] embestmx6boards: convert to use config_distro_bootcmd.h

[Stefano Babic]

On 14/12/2014 15:51, Iain Paton wrote:
 Since the Riot  Mars boards are dev boards it's likely people will want to
 run standard distros on them. So replace the current boot scripts with the
 standard one from config_distro_bootcmd.h
 
 Signed-off-by: Iain Paton ipat...@gmail.com
 ---


Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] embestmx6boards: convert to use config_distro_defaults.h

[Stefano Babic]

On 14/12/2014 15:51, Iain Paton wrote:
 Update to use config_distro_defaults.h and remove explicit settings
 
 Signed-off-by: Iain Paton ipat...@gmail.com
 ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/8] imx: i2c: Zap unnecessary malloc() calls

[Stefano Babic]

On 16/12/2014 14:09, Marek Vasut wrote:
 The malloc() calls are unnecessary, just allocate the stuff on stack.
 While at it, reorder the code a little, so that only one variable is
 used for the text, use snprintf() instead of sprintf() and use %01d
 as a formatting string to avoid any possible overflows.
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Igor Grinberg grinb...@compulab.co.il
 Cc: Nikita Kiryanov nik...@compulab.co.il
 Cc: Sean Cross x...@kosagi.com
 Cc: Simon Glass s...@chromium.org
 Cc: Stefano Babic sba...@denx.de
 Cc: Tim Harvey thar...@gateworks.com
 ---


Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 3/8] arm: mx6: novena: Define CONFIG_SYS_MALLOC_F_LEN

[Stefano Babic]

On 16/12/2014 14:09, Marek Vasut wrote:
 This board uses setup_i2c() in SPL. The setup_i2c() function internally
 calls gpio_request(), which in turn internally calls strdup(). The strdup()
 requires a running mallocator, so this patch makes the mallocator available.
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Igor Grinberg grinb...@compulab.co.il
 Cc: Nikita Kiryanov nik...@compulab.co.il
 Cc: Sean Cross x...@kosagi.com
 Cc: Simon Glass s...@chromium.org
 Cc: Stefano Babic sba...@denx.de
 Cc: Tim Harvey thar...@gateworks.com
 ---
  include/configs/novena.h | 1 +
  1 file changed, 1 insertion(+)
 
 diff --git a/include/configs/novena.h b/include/configs/novena.h
 index 879141a..0f3621a 100644
 --- a/include/configs/novena.h
 +++ b/include/configs/novena.h
 @@ -115,6 +115,7 @@
  #define CONFIG_SYS_MEMTEST_END   0x2000
  
  #define CONFIG_SYS_MALLOC_LEN(64 * 1024 * 1024)
 +#define CONFIG_SYS_MALLOC_F_LEN  (1  10)
  
  /* SPL */
  #define CONFIG_SPL_FAT_SUPPORT
 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic
-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 4/8] arm: mx6: novena: Minor coding style fix

[Stefano Babic]

On 16/12/2014 14:09, Marek Vasut wrote:
 Just zap multiple spaces and replace them with tabs properly.
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Igor Grinberg grinb...@compulab.co.il
 Cc: Nikita Kiryanov nik...@compulab.co.il
 Cc: Sean Cross x...@kosagi.com
 Cc: Simon Glass s...@chromium.org
 Cc: Stefano Babic sba...@denx.de
 Cc: Tim Harvey thar...@gateworks.com
 ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 5/8] arm: mx6: novena: Minor config file fix

[Stefano Babic]

On 16/12/2014 14:09, Marek Vasut wrote:
 Sequence like the following is completely useless and results from
 an errorneous ordering of the statements during development. Zap it.
  #ifdef FOO
  #define FOO
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Igor Grinberg grinb...@compulab.co.il
 Cc: Nikita Kiryanov nik...@compulab.co.il
 Cc: Sean Cross x...@kosagi.com
 Cc: Simon Glass s...@chromium.org
 Cc: Stefano Babic sba...@denx.de
 Cc: Tim Harvey thar...@gateworks.com
 ---


Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 2/8] arm: mx6: gw_ventana: Define CONFIG_SYS_MALLOC_F_LEN

[Stefano Babic]

On 16/12/2014 14:09, Marek Vasut wrote:
 This board uses setup_i2c() in SPL. The setup_i2c() function internally
 calls gpio_request(), which in turn internally calls strdup(). The strdup()
 requires a running mallocator, so this patch makes the mallocator available.
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Igor Grinberg grinb...@compulab.co.il
 Cc: Nikita Kiryanov nik...@compulab.co.il
 Cc: Sean Cross x...@kosagi.com
 Cc: Simon Glass s...@chromium.org
 Cc: Stefano Babic sba...@denx.de
 Cc: Tim Harvey thar...@gateworks.com
 ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 6/8] arm: mx6: novena: Pull GPIO definitions into header

[Stefano Babic]

On 16/12/2014 14:09, Marek Vasut wrote:
 Pull the definitions of GPIOs into a separate header file, so that
 they can be used across all source files.
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Igor Grinberg grinb...@compulab.co.il
 Cc: Nikita Kiryanov nik...@compulab.co.il
 Cc: Sean Cross x...@kosagi.com
 Cc: Simon Glass s...@chromium.org
 Cc: Stefano Babic sba...@denx.de
 Cc: Tim Harvey thar...@gateworks.com
 ---


Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 7/8] arm: mx6: novena: Pull video handling into separate file

[Stefano Babic]

On 16/12/2014 14:09, Marek Vasut wrote:
 Pull all of the video handling into a separate file, since a lot
 more code will be added and such code would polute the board file.
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Igor Grinberg grinb...@compulab.co.il
 Cc: Nikita Kiryanov nik...@compulab.co.il
 Cc: Sean Cross x...@kosagi.com
 Cc: Simon Glass s...@chromium.org
 Cc: Stefano Babic sba...@denx.de
 Cc: Tim Harvey thar...@gateworks.com
 ---


Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 8/8] arm: mx6: novena: Add proper LVDS display support

[Stefano Babic]

On 16/12/2014 14:09, Marek Vasut wrote:
 Repair the register configuration and add proper support for the
 display attached to both LVDS channels.
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Igor Grinberg grinb...@compulab.co.il
 Cc: Nikita Kiryanov nik...@compulab.co.il
 Cc: Sean Cross x...@kosagi.com
 Cc: Simon Glass s...@chromium.org
 Cc: Stefano Babic sba...@denx.de
 Cc: Tim Harvey thar...@gateworks.com
 ---

After fixing checkpatch warnings:

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] mx6slevk: Remove get_board_rev()

[Stefano Babic]

On 29/12/2014 21:05, Fabio Estevam wrote:
 From: Fabio Estevam fabio.este...@freescale.com
 
 get_board_rev() just returns the cpu revision, which does not make it really 
 useful for distinguishing between revisions of the board.
 
 Let's get rid of get_board_rev() as it is not being used with its correct 
 meaning.
 
 Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 ---
  board/freescale/mx6slevk/mx6slevk.c | 5 -
  1 file changed, 5 deletions(-)
 
 diff --git a/board/freescale/mx6slevk/mx6slevk.c 
 b/board/freescale/mx6slevk/mx6slevk.c
 index 3834eec..838ea6c 100644
 --- a/board/freescale/mx6slevk/mx6slevk.c
 +++ b/board/freescale/mx6slevk/mx6slevk.c
 @@ -308,11 +308,6 @@ int board_init(void)
   return 0;
  }
  
 -u32 get_board_rev(void)
 -{
 - return get_cpu_rev();
 -}
 -
  int checkboard(void)
  {
   puts(Board: MX6SLEVK\n);
 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic
-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] v2015.01-rc4 REGRESSION: scripts: fix binutils-version.sh breaks things for non Linaro toolchains

[Tom Rini]

On Tue, Dec 30, 2014 at 11:55:27AM +0100, Hans de Goede wrote:
 Hi,
 
 I noticed $subject while doing a MAKEALL.
 
 It seems that this commit:
 http://git.denx.de/?p=u-boot.git;a=commit;h=73c25753060c58e4c339fba306ed0ded0c335748
 
 Breaks things with Fedora's arm toolchain:
 
 [hans@shalem u-boot]$ scripts/binutils-version.sh arm-linux-gnu-as
 scripts/binutils-version.sh: line 22: printf: GNU: invalid number
 scripts/binutils-version.sh: line 22: printf: assembler: invalid number
 
 scripts/binutils-version.sh: line 22: printf: version: invalid number
 0002
 2400
 
 And:
 
 [hans@shalem ~]$ arm-linux-gnu-as --version
 GNU assembler version 2.24.0-6.fc21 20140613
 Copyright 2013 Free Software Foundation, Inc.
 This program is free software; you may redistribute it under the terms of
 the GNU General Public License version 3 or later.
 This program has absolutely no warranty.
 This assembler was configured for a target of `arm-linux-gnueabi'.
 
 Which makes $version_string: GNU assembler version 2.24.0-6.fc21 20140613
 and $MAJOR: GNU assembler version 2

FWIW it works on vanilla toolchains too so it's something in the
tweaking above that needs further tweaks to work for Fedora and Linaro:
$ 
/opt/eldk-5.5.2/armv7a/sysroots/i686-eldk-linux/usr/bin/arm-linux-gnueabi/arm-linux-gnueabi-as
--version
GNU assembler (GNU Binutils) 2.23.2

-- 
Tom


signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 4/7] fdt: Add several apis to decode pci device node

[Bin Meng]

Hi Simon,

On Sun, Dec 28, 2014 at 9:55 AM, Simon Glass s...@chromium.org wrote:
 Hi Bin,

 On 27 December 2014 at 05:10, Bin Meng bmeng...@gmail.com wrote:
 This commit adds several APIs to decode PCI device node according to
 the Open Firmware PCI bus bindings, including:
 - fdtdec_get_pci_addr() for encoded pci address
 - fdtdec_get_pci_vendev() for vendor id and device id
 - fdtdec_get_pci_bdf() for pci device bdf triplet
 - fdtdec_get_pci_bar32() for pci device register bar

 Signed-off-by: Bin Meng bmeng...@gmail.com

 Looks good - some minor comments below.


 ---

 Changes in v2:
 - New patch to add several apis to decode pci device node

  include/fdtdec.h | 108 ++
  lib/fdtdec.c | 157 
 ++-
  2 files changed, 240 insertions(+), 25 deletions(-)

 diff --git a/include/fdtdec.h b/include/fdtdec.h
 index d2b665c..2b2652f 100644
 --- a/include/fdtdec.h
 +++ b/include/fdtdec.h
 @@ -50,6 +50,49 @@ struct fdt_resource {
 fdt_addr_t end;
  };

 +enum fdt_pci_space {
 +   FDT_PCI_SPACE_CONFIG = 0,
 +   FDT_PCI_SPACE_IO = 0x0100,
 +   FDT_PCI_SPACE_MEM32 = 0x0200,
 +   FDT_PCI_SPACE_MEM64 = 0x0300,
 +   FDT_PCI_SPACE_MEM32_PREF = 0x4200,
 +   FDT_PCI_SPACE_MEM64_PREF = 0x4300,
 +};
 +
 +#define FDT_PCI_ADDR_CELLS 3
 +#define FDT_PCI_SIZE_CELLS 2
 +#define FDT_PCI_REG_SIZE   \
 +   ((FDT_PCI_ADDR_CELLS + FDT_PCI_SIZE_CELLS) * sizeof(u32))
 +
 +/*
 + * The Open Firmware spec defines PCI physical address as follows:
 + *
 + *  bits# 31  24 23  16 15  08 07  00
 + *
 + * phys.hi  cell:  npt000ss      dfff   
 + * phys.mid cell:           
 + * phys.lo  cell:           
 + *
 + * where:
 + *
 + * n:is 0 if the address is relocatable, 1 otherwise
 + * p:is 1 if addressable region is prefetchable, 0 otherwise
 + * t:is 1 if the address is aliased (for non-relocatable I/O) below 
 1MB
 + *   (for Memory), or below 64KB (for relocatable I/O)
 + * ss:   is the space code, denoting the address space
 + * : is the 8-bit Bus Number
 + * d:is the 5-bit Device Number
 + * fff:  is the 3-bit Function Number
 + * : is the 8-bit Register Number
 + * : is a 32-bit unsigned number
 + * : is a 32-bit unsigned number
 + */
 +struct fdt_pci_addr {
 +   u32 phys_hi;
 +   u32 phys_mid;
 +   u32 phys_lo;
 +};
 +
  /**
   * Compute the size of a resource.
   *
 @@ -252,6 +295,60 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int 
 node,
 const char *prop_name, fdt_size_t *sizep);

  /**
 + * Look at an address property in a node and return the pci address which
 + * corresponds to the given type in the form of fdt_pci_addr.
 + * The property must hold one fdt_pci_addr with a lengh.
 + *
 + * @param blob FDT blob
 + * @param node node to examine
 + * @param type pci address type (FDT_PCI_SPACE_xxx)
 + * @param prop_namename of property to find
 + * @param addr returns pci address in the form of fdt_pci_addr
 + * @return 0 if ok, negative on error
 + */
 +int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
 +   const char *prop_name, struct fdt_pci_addr *addr);
 +
 +/**
 + * Look at the compatible property of a device node that represents a PCI
 + * device and extract pci vendor id and device id from it.
 + *
 + * @param blob FDT blob
 + * @param node node to examine
 + * @param vendor   vendor id of the pci device
 + * @param device   device id of the pci device
 + * @return 0 if ok, negative on error
 + */
 +int fdtdec_get_pci_vendev(const void *blob, int node,
 +   u16 *vendor, u16 *device);
 +
 +/**
 + * Look at the pci address of a device node that represents a PCI device
 + * and parse the bus, device and function number from it.
 + *
 + * @param blob FDT blob
 + * @param node node to examine
 + * @param addr pci address in the form of fdt_pci_addr
 + * @param bdf  returns bus, device, function triplet
 + * @return 0 if ok, negative on error
 + */
 +int fdtdec_get_pci_bdf(const void *blob, int node,
 +   struct fdt_pci_addr *addr, pci_dev_t *bdf);
 +
 +/**
 + * Look at the pci address of a device node that represents a PCI device
 + * and return base address of the pci device's registers.
 + *
 + * @param blob FDT blob
 + * @param node node to examine
 + * @param addr pci address in the form of fdt_pci_addr
 + * @param bar  returns base address of the pci device's registers
 + * @return 0 if ok, negative on error
 + */
 +int fdtdec_get_pci_bar32(const void *blob, int node,
 +   struct fdt_pci_addr *addr, u32 *bar);
 +
 +/**
   * Look up a 32-bit 

[U-Boot] [PATCH v3 0/7] x86: Support pci based uart as the U-Boot serial console

[Bin Meng]

This series add support to the ns16550 compatible pci devices.

Newer x86 Platform Controller Hub chipset (like Topcliff, BayTrail)
starts to integrate ns16550 compatible pci uart devices. In order to
use them, we have to scan the pci bus and allocate memory/io address
in the early phase. A gd-hose is added to save the pci bus controller
hose in the early phase so that pci apis can be used.

On Intel Crown Bay board, there are 4 DB9 connectors, one of which
is from the superio legacy serial port and the other 3 are connected
to the Topcliff PCH UART devices. In order to use them as the U-Boot
serial console, we need describe those devices in the board's dts
file per Open Firmware PCI bus bindings and specify it as the console
via the 'stdout-path' in the chosen node. Several APIs are added in
fdtdec.c to provide help for decoding the pci device nodes.

Changes in v3:
- Fixed a typo: parant - parent
- Return better error code in fdtdec_get_pci_addr()
- Add some debug output in fdtdec_get_pci_addr()
- Reuse variable 'len' instead of creating a new one 'l'
- Check compatible string length and existence of '.'
- Using simple_strtol() directly on the compatible sub-string
- Change variable 'bn' to 'barnum' which is self-documenting
- Update to use 'memory-mapped' and 'i/o-mapped' in several places
- Use 'Processor Local Bus' instead of 'plb'
- Change the logic in ns16550_serial_ofdata_to_platdata() to avoid goto

Changes in v2:
- Add a commit message
- New patch to make pci apis usable before relocation
- New patch to add several apis to decode pci device node
- New patch to support ns16550 compatible pci uart devices
- New patch to use ePAPR defined properties for x86-uart
- New patch to add pci devices in crownbay.dts
- Drop v1 patch: Add an API for finding pci devices in the early phase
- Drop v1 patch: Support PCI UART in the x86_serial driver
- Drop v1 patch: Add PCI UART related defines in crownbay.h

Bin Meng (7):
  x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.c
  x86: Support pci bus scan in the early phase
  pci: Make pci apis usable before relocation
  fdt: Add several apis to decode pci device node
  serial: ns16550: Support ns16550 compatible pci uart devices
  x86: Use ePAPR defined properties for x86-uart
  x86: crownbay: Add pci devices in the dts file

 arch/x86/cpu/pci.c |  11 ++-
 arch/x86/dts/crownbay.dts  |  81 ++
 arch/x86/dts/serial.dtsi   |   5 +-
 arch/x86/include/asm/global_data.h |   1 -
 arch/x86/include/asm/pci.h |   2 +-
 drivers/pci/pci.c  |  25 --
 drivers/serial/ns16550.c   |  31 +++
 drivers/serial/serial_x86.c|   8 +-
 include/asm-generic/global_data.h  |   6 ++
 include/fdtdec.h   | 108 +---
 lib/fdtdec.c   | 166 +
 11 files changed, 401 insertions(+), 43 deletions(-)

-- 
1.8.2.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 1/7] x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.c

[Bin Meng]

arch/x86/cpu/pci.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.

Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org

---

Changes in v3: None
Changes in v2:
- Add a commit message

 arch/x86/cpu/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index f3492c3..404fbb6 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -15,6 +15,8 @@
 #include pci.h
 #include asm/pci.h
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static struct pci_controller x86_hose;
 
 int pci_early_init_hose(struct pci_controller **hosep)
-- 
1.8.2.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 2/7] x86: Support pci bus scan in the early phase

[Bin Meng]

On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.

Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index 404fbb6..1eee08b 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -29,6 +29,7 @@ int pci_early_init_hose(struct pci_controller **hosep)
 
board_pci_setup_hose(hose);
pci_setup_type1(hose);
+   hose-last_busno = pci_hose_scan(hose);
gd-arch.hose = hose;
*hosep = hose;
 
-- 
1.8.2.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 3/7] pci: Make pci apis usable before relocation

[Bin Meng]

Introduce a gd-hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd-hose in the early phase.

Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.

Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org

---

Changes in v3: None
Changes in v2:
- New patch to make pci apis usable before relocation

 arch/x86/cpu/pci.c |  8 
 arch/x86/include/asm/global_data.h |  1 -
 arch/x86/include/asm/pci.h |  2 +-
 drivers/pci/pci.c  | 25 +
 include/asm-generic/global_data.h  |  6 ++
 5 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index 1eee08b..ab1 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -30,7 +30,7 @@ int pci_early_init_hose(struct pci_controller **hosep)
board_pci_setup_hose(hose);
pci_setup_type1(hose);
hose-last_busno = pci_hose_scan(hose);
-   gd-arch.hose = hose;
+   gd-hose = hose;
*hosep = hose;
 
return 0;
@@ -51,7 +51,7 @@ void pci_init_board(void)
struct pci_controller *hose = x86_hose;
 
/* Stop using the early hose */
-   gd-arch.hose = NULL;
+   gd-hose = NULL;
 
board_pci_setup_hose(hose);
pci_setup_type1(hose);
@@ -64,8 +64,8 @@ void pci_init_board(void)
 
 static struct pci_controller *get_hose(void)
 {
-   if (gd-arch.hose)
-   return gd-arch.hose;
+   if (gd-hose)
+   return gd-hose;
 
return pci_bus_to_hose(0);
 }
diff --git a/arch/x86/include/asm/global_data.h 
b/arch/x86/include/asm/global_data.h
index 03d491a..aeab3e5 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -43,7 +43,6 @@ struct arch_global_data {
uint32_t tsc_mhz;   /* TSC frequency in MHz */
void *new_fdt;  /* Relocated FDT */
uint32_t bist;  /* Built-in self test value */
-   struct pci_controller *hose;/* PCI hose for early use */
enum pei_boot_mode_t pei_boot_mode;
const struct pch_gpio_map *gpio_map;/* board GPIO map */
struct memory_info meminfo; /* Memory information */
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index ac1a808..c30dd4c 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -29,7 +29,7 @@ void board_pci_setup_hose(struct pci_controller *hose);
  * pci_early_init_hose() - Set up PCI host before relocation
  *
  * This allocates memory for, sets up and returns the PCI hose. It can be
- * called before relocation. The hose will be stored in gd-arch.hose for
+ * called before relocation. The hose will be stored in gd-hose for
  * later use, but will become invalid one DRAM is available.
  */
 int pci_early_init_hose(struct pci_controller **hosep);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 3daf73c..83fd9a0 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -19,6 +19,8 @@
 #include asm/io.h
 #include pci.h
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PCI_HOSE_OP(rw, size, type)\
 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
  pci_dev_t dev,\
@@ -123,6 +125,14 @@ void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
 
 static struct pci_controller* hose_head;
 
+struct pci_controller *pci_get_hose_head(void)
+{
+   if (gd-hose)
+   return gd-hose;
+
+   return hose_head;
+}
+
 void pci_register_hose(struct pci_controller* hose)
 {
struct pci_controller **phose = hose_head;
@@ -139,7 +149,7 @@ struct pci_controller *pci_bus_to_hose(int bus)
 {
struct pci_controller *hose;
 
-   for (hose = hose_head; hose; hose = hose-next) {
+   for (hose = pci_get_hose_head(); hose; hose = hose-next) {
if (bus = hose-first_busno  bus = hose-last_busno)
return hose;
}
@@ -152,7 +162,7 @@ struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
 {
struct pci_controller *hose;
 
-   for (hose = hose_head; hose; hose = hose-next) {
+   for (hose = pci_get_hose_head(); hose; hose = hose-next) {
if (hose-cfg_addr == cfg_addr)
return hose;
}
@@ -162,7 +172,7 @@ struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
 
 int pci_last_busno(void)
 {
-   struct pci_controller *hose = hose_head;
+   struct pci_controller *hose = pci_get_hose_head();
 
if (!hose)
return -1;
@@ -181,7 +191,7 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, 

[U-Boot] [PATCH v3 5/7] serial: ns16550: Support ns16550 compatible pci uart devices

[Bin Meng]

There are many pci uart devices which are ns16550 compatible. We can
describe them in the board dts file and use it as the U-Boot serial
console as specified in the chosen node 'stdout-path' property.

Those pci uart devices can have their register be memory-mapped, or
i/o-mapped. The driver will try to use the memory-mapped register if
the reg property in the node has an entry to describe the memory-mapped
register, otherwise i/o-mapped register will be used.

Signed-off-by: Bin Meng bmeng...@gmail.com

---

Changes in v3:
- Update to use 'memory-mapped' and 'i/o-mapped' in several places
- Use 'Processor Local Bus' instead of 'plb'
- Change the logic in ns16550_serial_ofdata_to_platdata() to avoid goto

Changes in v2:
- New patch to support ns16550 compatible pci uart devices

 drivers/serial/ns16550.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index af5beba..70c9462 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -289,7 +289,38 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
struct ns16550_platdata *plat = dev-platdata;
fdt_addr_t addr;
 
+   /* try Processor Local Bus device first */
addr = fdtdec_get_addr(gd-fdt_blob, dev-of_offset, reg);
+#ifdef CONFIG_PCI
+   if (addr == FDT_ADDR_T_NONE) {
+   /* then try pci device */
+   struct fdt_pci_addr pci_addr;
+   u32 bar;
+   int ret;
+
+   /* we prefer to use a memory-mapped register */
+   ret = fdtdec_get_pci_addr(gd-fdt_blob, dev-of_offset,
+ FDT_PCI_SPACE_MEM32, reg,
+ pci_addr);
+   if (ret) {
+   /* try if there is any i/o-mapped register */
+   ret = fdtdec_get_pci_addr(gd-fdt_blob,
+ dev-of_offset,
+ FDT_PCI_SPACE_IO,
+ reg, pci_addr);
+   if (ret)
+   return ret;
+   }
+
+   ret = fdtdec_get_pci_bar32(gd-fdt_blob, dev-of_offset,
+  pci_addr, bar);
+   if (ret)
+   return ret;
+
+   addr = bar;
+   }
+#endif
+
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
 
-- 
1.8.2.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 6/7] x86: Use ePAPR defined properties for x86-uart

[Bin Meng]

Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat-clock of x86-uart instead of using hardcoded number.

Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org

---

Changes in v3: None
Changes in v2:
- New patch to use ePAPR defined properties for x86-uart

 arch/x86/dts/serial.dtsi| 5 ++---
 drivers/serial/serial_x86.c | 8 +++-
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
index ebdda76..9b097f4 100644
--- a/arch/x86/dts/serial.dtsi
+++ b/arch/x86/dts/serial.dtsi
@@ -3,8 +3,7 @@
compatible = x86-uart;
reg = 0x3f8 8;
reg-shift = 0;
-   io-mapped = 1;
-   multiplier = 1;
-   baudrate = 115200;
+   clock-frequency = 1843200;
+   current-speed = 115200;
};
 };
diff --git a/drivers/serial/serial_x86.c b/drivers/serial/serial_x86.c
index e81e035..4bf6062 100644
--- a/drivers/serial/serial_x86.c
+++ b/drivers/serial/serial_x86.c
@@ -6,9 +6,12 @@
 
 #include common.h
 #include dm.h
+#include fdtdec.h
 #include ns16550.h
 #include serial.h
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static const struct udevice_id x86_serial_ids[] = {
{ .compatible = x86-uart },
{ }
@@ -22,10 +25,13 @@ static int x86_serial_ofdata_to_platdata(struct udevice 
*dev)
ret = ns16550_serial_ofdata_to_platdata(dev);
if (ret)
return ret;
-   plat-clock = 1843200;
+
+   plat-clock = fdtdec_get_int(gd-fdt_blob, dev-of_offset,
+clock-frequency, 1843200);
 
return 0;
 }
+
 U_BOOT_DRIVER(serial_ns16550) = {
.name   = serial_x86,
.id = UCLASS_SERIAL,
-- 
1.8.2.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 4/7] fdt: Add several apis to decode pci device node

[Bin Meng]

This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar

Signed-off-by: Bin Meng bmeng...@gmail.com

---

Changes in v3:
- Fixed a typo: parant - parent
- Return better error code in fdtdec_get_pci_addr()
- Add some debug output in fdtdec_get_pci_addr()
- Reuse variable 'len' instead of creating a new one 'l'
- Check compatible string length and existence of '.'
- Using simple_strtol() directly on the compatible sub-string
- Change variable 'bn' to 'barnum' which is self-documenting

Changes in v2:
- New patch to add several apis to decode pci device node

 include/fdtdec.h | 108 
 lib/fdtdec.c | 166 ++-
 2 files changed, 249 insertions(+), 25 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index d2b665c..2b2652f 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -50,6 +50,49 @@ struct fdt_resource {
fdt_addr_t end;
 };
 
+enum fdt_pci_space {
+   FDT_PCI_SPACE_CONFIG = 0,
+   FDT_PCI_SPACE_IO = 0x0100,
+   FDT_PCI_SPACE_MEM32 = 0x0200,
+   FDT_PCI_SPACE_MEM64 = 0x0300,
+   FDT_PCI_SPACE_MEM32_PREF = 0x4200,
+   FDT_PCI_SPACE_MEM64_PREF = 0x4300,
+};
+
+#define FDT_PCI_ADDR_CELLS 3
+#define FDT_PCI_SIZE_CELLS 2
+#define FDT_PCI_REG_SIZE   \
+   ((FDT_PCI_ADDR_CELLS + FDT_PCI_SIZE_CELLS) * sizeof(u32))
+
+/*
+ * The Open Firmware spec defines PCI physical address as follows:
+ *
+ *  bits# 31  24 23  16 15  08 07  00
+ *
+ * phys.hi  cell:  npt000ss      dfff   
+ * phys.mid cell:           
+ * phys.lo  cell:           
+ *
+ * where:
+ *
+ * n:is 0 if the address is relocatable, 1 otherwise
+ * p:is 1 if addressable region is prefetchable, 0 otherwise
+ * t:is 1 if the address is aliased (for non-relocatable I/O) below 1MB
+ *   (for Memory), or below 64KB (for relocatable I/O)
+ * ss:   is the space code, denoting the address space
+ * : is the 8-bit Bus Number
+ * d:is the 5-bit Device Number
+ * fff:  is the 3-bit Function Number
+ * : is the 8-bit Register Number
+ * : is a 32-bit unsigned number
+ * : is a 32-bit unsigned number
+ */
+struct fdt_pci_addr {
+   u32 phys_hi;
+   u32 phys_mid;
+   u32 phys_lo;
+};
+
 /**
  * Compute the size of a resource.
  *
@@ -252,6 +295,60 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
const char *prop_name, fdt_size_t *sizep);
 
 /**
+ * Look at an address property in a node and return the pci address which
+ * corresponds to the given type in the form of fdt_pci_addr.
+ * The property must hold one fdt_pci_addr with a lengh.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param type pci address type (FDT_PCI_SPACE_xxx)
+ * @param prop_namename of property to find
+ * @param addr returns pci address in the form of fdt_pci_addr
+ * @return 0 if ok, negative on error
+ */
+int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
+   const char *prop_name, struct fdt_pci_addr *addr);
+
+/**
+ * Look at the compatible property of a device node that represents a PCI
+ * device and extract pci vendor id and device id from it.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param vendor   vendor id of the pci device
+ * @param device   device id of the pci device
+ * @return 0 if ok, negative on error
+ */
+int fdtdec_get_pci_vendev(const void *blob, int node,
+   u16 *vendor, u16 *device);
+
+/**
+ * Look at the pci address of a device node that represents a PCI device
+ * and parse the bus, device and function number from it.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param addr pci address in the form of fdt_pci_addr
+ * @param bdf  returns bus, device, function triplet
+ * @return 0 if ok, negative on error
+ */
+int fdtdec_get_pci_bdf(const void *blob, int node,
+   struct fdt_pci_addr *addr, pci_dev_t *bdf);
+
+/**
+ * Look at the pci address of a device node that represents a PCI device
+ * and return base address of the pci device's registers.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param addr pci address in the form of fdt_pci_addr
+ * @param bar  returns base address of the pci device's registers
+ * @return 0 if ok, negative on error
+ */
+int fdtdec_get_pci_bar32(const void *blob, int node,
+   struct 

[U-Boot] [PATCH v3 7/7] x86: crownbay: Add pci devices in the dts file

[Bin Meng]

The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.

Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.

Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org

---

Changes in v3: None
Changes in v2:
- New patch to add pci devices in crownbay.dts
- Drop v1 patch: Add an API for finding pci devices in the early phase
- Drop v1 patch: Support PCI UART in the x86_serial driver
- Drop v1 patch: Add PCI UART related defines in crownbay.h

 arch/x86/dts/crownbay.dts | 81 +++
 1 file changed, 81 insertions(+)

diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 97f7a52..a42e0e4 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -32,6 +32,14 @@
};
 
chosen {
+   /*
+* By default the legacy superio serial port is used as the
+* U-Boot serial console. If we want to use UART from Topcliff
+* PCH as the console, change this property to pciuart#.
+*
+* For example, stdout-path = pciuart0 will use the first
+* UART on Topcliff PCH.
+*/
stdout-path = /serial;
};
 
@@ -52,4 +60,77 @@
};
};
 
+   pci {
+   #address-cells = 3;
+   #size-cells = 2;
+   compatible = intel,pci;
+   device_type = pci;
+
+   pcie@17,0 {
+   #address-cells = 3;
+   #size-cells = 2;
+   compatible = intel,pci;
+   device_type = pci;
+
+   topcliff@0,0 {
+   #address-cells = 3;
+   #size-cells = 2;
+   compatible = intel,pci;
+   device_type = pci;
+
+   pciuart0: uart@a,1 {
+   compatible = pci8086,8811.0,
+   pci8086,8811,
+   pciclass070002,
+   pciclass0700,
+   x86-uart;
+   reg = 0x00025100 0x0 0x0 0x0 0x0
+  0x01025110 0x0 0x0 0x0 0x0;
+   reg-shift = 0;
+   clock-frequency = 1843200;
+   current-speed = 115200;
+   };
+
+   pciuart1: uart@a,2 {
+   compatible = pci8086,8812.0,
+   pci8086,8812,
+   pciclass070002,
+   pciclass0700,
+   x86-uart;
+   reg = 0x00025200 0x0 0x0 0x0 0x0
+  0x01025210 0x0 0x0 0x0 0x0;
+   reg-shift = 0;
+   clock-frequency = 1843200;
+   current-speed = 115200;
+   };
+
+   pciuart2: uart@a,3 {
+   compatible = pci8086,8813.0,
+   pci8086,8813,
+   pciclass070002,
+   pciclass0700,
+   x86-uart;
+   reg = 0x00025300 0x0 0x0 0x0 0x0
+  0x01025310 0x0 0x0 0x0 0x0;
+   reg-shift = 0;
+   clock-frequency = 1843200;
+   current-speed = 115200;
+   };
+
+   pciuart3: uart@a,4 {
+   compatible = pci8086,8814.0,
+   pci8086,8814,
+   pciclass070002,
+   pciclass0700,
+   x86-uart;
+   reg = 0x00025400 0x0 0x0 0x0 0x0
+

Re: [U-Boot] [PATCH 02/22] x86: Drop RAMTOP Kconfig

[Bin Meng]

Hi Simon,

On Sun, Dec 28, 2014 at 10:20 AM, Simon Glass s...@chromium.org wrote:
 We don't need this in U-Boot since we calculate it based on available memory.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

  arch/x86/Kconfig | 4 
  1 file changed, 4 deletions(-)

 diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
 index 7d007bb..e992e64 100644
 --- a/arch/x86/Kconfig
 +++ b/arch/x86/Kconfig
 @@ -47,10 +47,6 @@ config RAMBASE
 hex
 default 0x10

 -config RAMTOP
 -   hex
 -   default 0x20
 -
  config XIP_ROM_SIZE
 hex
 default ROM_SIZE
 --

What about mtrr.h which is still referring to CONFIG_RAMTOP?

~/work/u-boot-x86/arch/x86$ grep -nr RAMTOP *
include/asm/mtrr.h:103:#if !defined(CONFIG_RAMTOP)
include/asm/mtrr.h:104:# error CONFIG_RAMTOP not defined
include/asm/mtrr.h:117:#if (CONFIG_RAMTOP  (CONFIG_RAMTOP - 1)) != 0
include/asm/mtrr.h:118:# error CONFIG_RAMTOP must be a power of 2
Kconfig:50:config RAMTOP

Regards,
Bin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/8] imx: i2c: Zap unnecessary malloc() calls

[Marek Vasut]

On Tuesday, December 30, 2014 at 02:34:47 PM, Stefano Babic wrote:
 On 16/12/2014 14:09, Marek Vasut wrote:
  The malloc() calls are unnecessary, just allocate the stuff on stack.
  While at it, reorder the code a little, so that only one variable is
  used for the text, use snprintf() instead of sprintf() and use %01d
  as a formatting string to avoid any possible overflows.
  
  Signed-off-by: Marek Vasut ma...@denx.de
  Cc: Igor Grinberg grinb...@compulab.co.il
  Cc: Nikita Kiryanov nik...@compulab.co.il
  Cc: Sean Cross x...@kosagi.com
  Cc: Simon Glass s...@chromium.org
  Cc: Stefano Babic sba...@denx.de
  Cc: Tim Harvey thar...@gateworks.com
  ---
 
 Applied to u-boot-imx, thanks !

Hey!

hope you had a nice holiday :) You might want to apply 2/8 and 3/8 to current 
codebase and send it to Tom, since they fix real problem and the board doesn't
boot without this. I should have separated them out, sorry.

Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PULL] Please pull u-boot-imx

[Stefano Babic]

Hi Tom,

some minor fixes from i.MX side - please pull from u-boot-imx, thanks !

The following changes since commit 125738e819a3b9d15210794b3dcef9f4d9bcf866:

  Prepare v2015.01-rc4 (2014-12-29 21:22:38 -0500)

are available in the git repository at:

  git://www.denx.de/git/u-boot-imx.git master

for you to fetch changes up to 87e47e905887b91c0505495cc6bbab70ba266d51:

  mx6slevk: Remove get_board_rev() (2014-12-30 14:10:39 +0100)


Christian Gmeiner (2):
  ot1200: add fsuuid command
  ot1200: enable support for USB_STORAGE

Fabio Estevam (2):
  mx51evk: Fix MX51EVK_USB_CLK_EN_B definition
  mx6slevk: Remove get_board_rev()

Iain Paton (2):
  embestmx6boards: convert to use config_distro_defaults.h
  embestmx6boards: convert to use config_distro_bootcmd.h

Jan Luebbe (1):
  arm: mxs: olinuxino: move DRAM config tuning to SPL

Marek Vasut (8):
  imx: i2c: Zap unnecessary malloc() calls
  arm: mx6: gw_ventana: Define CONFIG_SYS_MALLOC_F_LEN
  arm: mx6: novena: Define CONFIG_SYS_MALLOC_F_LEN
  arm: mx6: novena: Minor coding style fix
  arm: mx6: novena: Minor config file fix
  arm: mx6: novena: Pull GPIO definitions into header
  arm: mx6: novena: Pull video handling into separate file
  arm: mx6: novena: Add proper LVDS display support

Peng Fan (3):
  imx:mx6 fix return value of mxc_get_clock
  imx:mx6sabresd add board level support for usb
  imx:mx6qarm2 add board level support for usb

Pierre Aubert (1):
  imx SPL: enable boot from eMMC boot partitions.

Stefan Roese (1):
  arm: mx6: gw_ventana: Change clock init to enable NAND related clocks

Stefano Babic (1):
  Merge branch 'master' of git://git.denx.de/u-boot

 arch/arm/cpu/armv7/mx6/clock.c   |   3 +-
 arch/arm/imx-common/i2c-mxv7.c   |  24 +-
 arch/arm/imx-common/spl.c|   4 +-
 board/freescale/mx51evk/mx51evk.c|   2 +-
 board/freescale/mx6qarm2/mx6qarm2.c  |  42 +++
 board/freescale/mx6sabresd/mx6sabresd.c  |  68 
 board/freescale/mx6slevk/mx6slevk.c  |   5 -
 board/gateworks/gw_ventana/gw_ventana_spl.c  |   2 +-
 board/kosagi/novena/Makefile |   1 +
 board/kosagi/novena/novena.c |  93 +-
 board/kosagi/novena/novena.h |  33 ++
 board/kosagi/novena/novena_spl.c |  17 +-
 board/kosagi/novena/video.c  | 456
+++
 board/olimex/mx23_olinuxino/mx23_olinuxino.c |  30 --
 board/olimex/mx23_olinuxino/spl_boot.c   |  30 ++
 include/configs/embestmx6boards.h| 189 +++
 include/configs/gw_ventana.h |   1 +
 include/configs/mx6qarm2.h   |  14 +
 include/configs/mx6sabresd.h |  14 +
 include/configs/novena.h |   3 +-
 include/configs/ot1200.h |   3 +
 21 files changed, 742 insertions(+), 292 deletions(-)
 create mode 100644 board/kosagi/novena/novena.h
 create mode 100644 board/kosagi/novena/video.c


-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 1/5] sunxi: Align PSCI stack calculation to comment

[Jan Kiszka]

From: Jan Kiszka jan.kis...@siemens.com

0x400 is true 1K.

Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
 arch/arm/cpu/armv7/sunxi/psci.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index b9ea78b..a84807d 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -68,7 +68,7 @@ psci_arch_init:
 
mrc p15, 0, r4, c0, c0, 5   @ MPIDR
and r4, r4, #3  @ cpu number in cluster
-   mov r5, #400@ 1kB of stack per CPU
+   mov r5, #0x400  @ 1kB of stack per CPU
mul r4, r4, r5
 
adr r5, text_end@ end of text
-- 
1.8.4.5

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 4/5] sun7i: Move psci_arch_init close to text_end

[Jan Kiszka]

From: Jan Kiszka jan.kis...@siemens.com

adr rX, text_end only works if the label is close. Adding further code
to the other functions will prevent this. So move the containing
function close to label. No functional change.

Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
 arch/arm/cpu/armv7/sunxi/psci.S | 80 -
 1 file changed, 40 insertions(+), 40 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index bba1894..a5b2b0c 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -94,46 +94,6 @@
isb
 .endm
 
-.globl psci_arch_init
-psci_arch_init:
-   movwr4, #(GICD_BASE  0x)
-   movtr4, #(GICD_BASE  16)
-
-   ldr r5, [r4, #GICD_IGROUPRn]
-   bic r5, r5, #(1  15)  @ SGI15 as Group-0
-   str r5, [r4, #GICD_IGROUPRn]
-
-   mov r5, #0  @ Set SGI15 priority to 0
-   strbr5, [r4, #(GICD_IPRIORITYRn + 15)]
-
-   add r4, r4, #0x1000 @ GICC address
-
-   mov r5, #0xff
-   str r5, [r4, #GICC_PMR] @ Be cool with non-secure
-
-   ldr r5, [r4, #GICC_CTLR]
-   orr r5, r5, #(1  3)   @ Switch FIQEn on
-   str r5, [r4, #GICC_CTLR]
-
-   mrc p15, 0, r5, c1, c1, 0   @ Read SCR
-   orr r5, r5, #4  @ Enable FIQ in monitor mode
-   bic r5, r5, #1  @ Secure mode
-   mcr p15, 0, r5, c1, c1, 0   @ Write SCR
-   isb
-
-   mrc p15, 0, r4, c0, c0, 5   @ MPIDR
-   and r4, r4, #3  @ cpu number in cluster
-   mov r5, #0x400  @ 1kB of stack per CPU
-   mul r4, r4, r5
-
-   adr r5, text_end@ end of text
-   add r5, r5, #0x2000 @ Skip two pages
-   lsr r5, r5, #12 @ Align to start of page
-   lsl r5, r5, #12
-   sub sp, r5, r4  @ here's our stack!
-
-   bx  lr
-
 .globl psci_fiq_enter
 psci_fiq_enter:
push{r0-r12}
@@ -445,5 +405,45 @@ psci_system_reset:
str r1, [r0, #WDOG_CTL]
 1: b   1b
 
+.globl psci_arch_init
+psci_arch_init:
+   movwr4, #(GICD_BASE  0x)
+   movtr4, #(GICD_BASE  16)
+
+   ldr r5, [r4, #GICD_IGROUPRn]
+   bic r5, r5, #(1  15)  @ SGI15 as Group-0
+   str r5, [r4, #GICD_IGROUPRn]
+
+   mov r5, #0  @ Set SGI15 priority to 0
+   strbr5, [r4, #(GICD_IPRIORITYRn + 15)]
+
+   add r4, r4, #0x1000 @ GICC address
+
+   mov r5, #0xff
+   str r5, [r4, #GICC_PMR] @ Be cool with non-secure
+
+   ldr r5, [r4, #GICC_CTLR]
+   orr r5, r5, #(1  3)   @ Switch FIQEn on
+   str r5, [r4, #GICC_CTLR]
+
+   mrc p15, 0, r5, c1, c1, 0   @ Read SCR
+   orr r5, r5, #4  @ Enable FIQ in monitor mode
+   bic r5, r5, #1  @ Secure mode
+   mcr p15, 0, r5, c1, c1, 0   @ Write SCR
+   isb
+
+   mrc p15, 0, r4, c0, c0, 5   @ MPIDR
+   and r4, r4, #3  @ cpu number in cluster
+   mov r5, #0x400  @ 1kB of stack per CPU
+   mul r4, r4, r5
+
+   adr r5, text_end@ end of text
+   add r5, r5, #0x2000 @ Skip two pages
+   lsr r5, r5, #12 @ Align to start of page
+   lsl r5, r5, #12
+   sub sp, r5, r4  @ here's our stack!
+
+   bx  lr
+
 text_end:
.popsection
-- 
1.8.4.5

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 2/5] sun7i: Add support for taking CPUs offline via PSCI

[Jan Kiszka]

From: Jan Kiszka jan.kis...@siemens.com

Based on the original version by Marc Zyngier. It adds a psci_cpu_off
implementation for the A20 SoC. The mechanism works by first preparing
the calling CPU to go offline (disable and flush cache, disable SMP),
then requesting CPU 0 to pull the plug. The request is sent as FIQ on
SGI15.

Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
 arch/arm/cpu/armv7/sunxi/psci.S | 170 
 1 file changed, 170 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index a84807d..0aa4007 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -18,6 +18,7 @@
  */
 
 #include config.h
+#include asm/gic.h
 #include asm/psci.h
 #include asm/arch/cpu.h
 
@@ -38,6 +39,8 @@
 
 #defineONE_MS  (CONFIG_SYS_CLK_FREQ / 1000)
 #defineTEN_MS  (10 * ONE_MS)
+#defineGICD_BASE   0x1c81000
+#defineGICC_BASE   0x1c82000
 
 .macro timer_wait  reg, ticks
@ Program CNTP_TVAL
@@ -61,7 +64,27 @@
 
 .globl psci_arch_init
 psci_arch_init:
+   movwr4, #(GICD_BASE  0x)
+   movtr4, #(GICD_BASE  16)
+
+   ldr r5, [r4, #GICD_IGROUPRn]
+   bic r5, r5, #(1  15)  @ SGI15 as Group-0
+   str r5, [r4, #GICD_IGROUPRn]
+
+   mov r5, #0  @ Set SGI15 priority to 0
+   strbr5, [r4, #(GICD_IPRIORITYRn + 15)]
+
+   add r4, r4, #0x1000 @ GICC address
+
+   mov r5, #0xff
+   str r5, [r4, #GICC_PMR] @ Be cool with non-secure
+
+   ldr r5, [r4, #GICC_CTLR]
+   orr r5, r5, #(1  3)   @ Switch FIQEn on
+   str r5, [r4, #GICC_CTLR]
+
mrc p15, 0, r5, c1, c1, 0   @ Read SCR
+   orr r5, r5, #4  @ Enable FIQ in monitor mode
bic r5, r5, #1  @ Secure mode
mcr p15, 0, r5, c1, c1, 0   @ Write SCR
isb
@@ -79,6 +102,77 @@ psci_arch_init:
 
bx  lr
 
+.globl psci_fiq_enter
+psci_fiq_enter:
+   push{r0-r12}
+
+   @ Switch to secure
+   mrc p15, 0, r7, c1, c1, 0
+   bic r8, r7, #1
+   mcr p15, 0, r8, c1, c1, 0
+   isb
+
+   movwr8, #(GICC_BASE  0x)
+   movtr8, #(GICC_BASE  16)
+   ldr r9, [r8, #GICC_IAR]
+   movwr10, #0x3ff
+   movtr10, #0
+   cmp r9, r10
+   beq out
+   movwr10, #0x3fe
+   cmp r9, r10
+   beq out
+   str r9, [r8, #GICC_EOIR]
+   dsb
+
+   @ Compute CPU number
+   lsr r9, r9, #10
+   and r9, r9, #0xf
+
+   movwr8, #(SUN7I_CPUCFG_BASE  0x)
+   movtr8, #(SUN7I_CPUCFG_BASE  16)
+
+   @ Wait for the core to enter WFI
+   lsl r11, r9, #6 @ x64
+   add r11, r11, r8
+
+1: ldr r10, [r11, #0x48]
+   tst r10, #(1  2)
+   bne 2f
+   timer_wait r10, ONE_MS
+   b   1b
+
+   @ Reset CPU
+2: mov r10, #0
+   str r10, [r11, #0x40]
+
+   @ Lock CPU
+   mov r10, #1
+   lsl r9, r10, r9 @ r9 is now CPU mask
+   ldr r10, [r8, #0x1e4]
+   bic r10, r10, r9
+   str r10, [r8, #0x1e4]
+
+   @ Set power gating
+   ldr r10, [r8, #0x1b4]
+   orr r10, r10, #1
+   str r10, [r8, #0x1b4]
+   timer_wait r10, ONE_MS
+
+   @ Activate power clamp
+   mov r10, #1
+1: str r10, [r8, #0x1b0]
+   lsl r10, r10, #1
+   orr r10, r10, #1
+   tst r10, #0x100
+   beq 1b
+
+   @ Restore security level
+out:   mcr p15, 0, r7, c1, c1, 0
+
+   pop {r0-r12}
+   subspc, lr, #4
+
@ r1 = target CPU
@ r2 = target PC
 .globl psci_cpu_on
@@ -144,6 +238,53 @@ psci_cpu_on:
 _target_pc:
.word   0
 
+/* Imported from Linux kernel */
+v7_flush_dcache_all:
+   dmb @ ensure ordering with previous 
memory accesses
+   mrc p15, 1, r0, c0, c0, 1   @ read clidr
+   andsr3, r0, #0x700  @ extract loc from clidr
+   mov r3, r3, lsr #23 @ left align loc bit field
+   beq finished@ if loc is 0, then no need to 
clean
+   mov r10, #0 @ start clean at cache level 0
+flush_levels:
+   add r2, r10, r10, lsr #1@ work out 3x current cache 
level
+   mov r1, r0, lsr r2  @ extract cache type bits from 
clidr
+   and r1, r1, #7  @ mask of the bits for current 
cache only
+   cmp r1, #2  @ see what cache we have at 
this level
+   blt skip@ skip if no cache, or just 
i-cache
+   mrs r9, cpsr@ make 

[U-Boot] [PATCH v2 5/5] sun7i: Implement PSCI v0.2 AFFINITY_INFO

[Jan Kiszka]

From: Jan Kiszka jan.kis...@siemens.com

It's mandatory according to the spec, and Linux uses it for checking if
an offlined CPU is already dead. Without this implemented, we get some
warnings on the kernel console at least.

Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
 arch/arm/cpu/armv7/sunxi/psci.S | 33 +
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index a5b2b0c..e62e295 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -159,6 +159,12 @@ psci_fiq_enter:
tst r10, #0x100
beq 1b
 
+   @ Mark CPU disabled
+   adr r2, _cpu_off
+   ldr r0, [r2]
+   orr r0, r0, r9
+   str r0, [r2]
+
@ Restore security level
 out:   mcr p15, 0, r7, c1, c1, 0
 
@@ -227,6 +233,12 @@ psci_cpu_on:
orr r6, r6, r4
str r6, [r0, #0x1e4]
 
+   @ Mark CPU enabled
+   adr r2, _cpu_off
+   ldr r0, [r2]
+   bic r0, r0, r4
+   str r0, [r2]
+
mov r0, #ARM_PSCI_RET_SUCCESS   @ Return PSCI_RET_SUCCESS
mov pc, lr
 
@@ -234,6 +246,8 @@ _target_pc:
.word   0
 _context:
.word   0
+_cpu_off:
+   .word   0x2
 
 /* Imported from Linux kernel */
 v7_flush_dcache_all:
@@ -327,6 +341,25 @@ psci_cpu_off:
 1: wfi
b   1b
 
+   @ r1 = target CPU
+   @ r2 = lowest affinity level
+.globl psci_affinity_info
+psci_affinity_info:
+   @ only support full match
+   cmp r2, #0
+   mov r0, #ARM_PSCI_RET_INVAL
+   bne 1
+
+   @ prepare CPU ID in r1, only caring about the first cluster
+   and r1, r1, #3
+
+   adr r2, _cpu_off
+   ldr r0, [r2]@ load bitmap of offlined CPUs
+   lsr r0, r0, r1  @ shift right by CPU ID
+   and r0, r0, #1  @ filter out relevant bit
+
+1: mov pc, lr
+
 /*
  * r0: TWI base address
  * r1: state to wait for
-- 
1.8.4.5

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 0/5] sun7i: PSCI enhancements

[Jan Kiszka]

This adds CPU offlining and PSCI v0.2 support. Changes since v1:
 - add AFFINITY_INFO support (mandatory for v0.2)
 - rebase over master
 - include sunxi: Align PSCI stack calculation to comment to provide
   the complete queue

See patches for further details.

Jan

Jan Kiszka (5):
  sunxi: Align PSCI stack calculation to comment
  sun7i: Add support for taking CPUs offline via PSCI
  sun7i: Add PSCI v0.2 support
  sun7i: Move psci_arch_init close to text_end
  sun7i: Implement PSCI v0.2 AFFINITY_INFO

 arch/arm/cpu/armv7/psci.S |  35 +++-
 arch/arm/cpu/armv7/sunxi/psci.S   | 350 --
 arch/arm/cpu/armv7/virt-dt.c  |   5 +-
 arch/arm/include/asm/arch-sunxi/cpu.h |   2 +
 arch/arm/include/asm/psci.h   |  24 ++-
 5 files changed, 391 insertions(+), 25 deletions(-)

-- 
1.8.4.5

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 3/5] sun7i: Add PSCI v0.2 support

[Jan Kiszka]

From: Jan Kiszka jan.kis...@siemens.com

This extends the PSCI support for the A20 to a dual v0.2 and v0.1
interface. Recent OSes will prefer v0.2, olders will still find the
original interface, just at v0.2 service IDs.

In addition to the existing services, v0.2 requires us to implement both
system off and reset. At least Linux will make use of them in favor of
its own implementations and, thus, fail if they do not work.

Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
 arch/arm/cpu/armv7/psci.S |  35 +-
 arch/arm/cpu/armv7/sunxi/psci.S   | 117 ++
 arch/arm/cpu/armv7/virt-dt.c  |   5 +-
 arch/arm/include/asm/arch-sunxi/cpu.h |   2 +
 arch/arm/include/asm/psci.h   |  24 +--
 5 files changed, 173 insertions(+), 10 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index bf11a34..e2a38ca 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -49,8 +49,18 @@ ENTRY(psci_cpu_suspend)
 ENTRY(psci_cpu_off)
 ENTRY(psci_cpu_on)
 ENTRY(psci_migrate)
+ENTRY(psci_affinity_info)
+ENTRY(psci_migrate_info_type)
+ENTRY(psci_migrate_info_up_cpu)
+ENTRY(psci_system_off)
+ENTRY(psci_system_reset)
mov r0, #ARM_PSCI_RET_NI@ Return -1 (Not Implemented)
mov pc, lr
+ENDPROC(psci_system_reset)
+ENDPROC(psci_system_off)
+ENDPROC(psci_migrate_info_up_cpu)
+ENDPROC(psci_migrate_info_type)
+ENDPROC(psci_affinity_info)
 ENDPROC(psci_migrate)
 ENDPROC(psci_cpu_on)
 ENDPROC(psci_cpu_off)
@@ -59,16 +69,33 @@ ENDPROC(psci_cpu_suspend)
 .weak psci_cpu_off
 .weak psci_cpu_on
 .weak psci_migrate
+.weak psci_affinity_info
+.weak psci_migrate_info_type
+.weak psci_migrate_info_up_cpu
+.weak psci_system_off
+.weak psci_system_reset
 
 _psci_table:
+   .word   ARM_PSCI_FN_PSCI_VERSION
+   .word   psci_version
.word   ARM_PSCI_FN_CPU_SUSPEND
.word   psci_cpu_suspend
.word   ARM_PSCI_FN_CPU_OFF
.word   psci_cpu_off
.word   ARM_PSCI_FN_CPU_ON
.word   psci_cpu_on
+   .word   ARM_PSCI_FN_AFFINITY_INFO
+   .word   psci_affinity_info
.word   ARM_PSCI_FN_MIGRATE
.word   psci_migrate
+   .word   ARM_PSCI_FN_MIGRATE_INFO_TYPE
+   .word   psci_migrate_info_type
+   .word   ARM_PSCI_FN_MIGRATE_INFO_UP_CPU
+   .word   psci_migrate_info_up_cpu
+   .word   ARM_PSCI_FN_SYSTEM_OFF
+   .word   psci_system_off
+   .word   ARM_PSCI_FN_SYSTEM_RESET
+   .word   psci_system_reset
.word   0
.word   0
 
@@ -86,7 +113,7 @@ _smc_psci:
ldr r6, [r4, #4]@ Load target PC
cmp r5, #0  @ If reach the end, bail out
moveq   r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid)
-   beq 2f
+   beq return
cmp r0, r5  @ If not matching, try next entry
addne   r4, r4, #8
bne 1b
@@ -94,9 +121,13 @@ _smc_psci:
blx r6  @ Execute PSCI function
 
@ Switch back to non-secure
-2: mcr p15, 0, r7, c1, c1, 0
+return:mcr p15, 0, r7, c1, c1, 0
 
pop {r4-r7, lr}
movspc, lr  @ Return to the kernel
 
+psci_version:
+   mov r0, #0x0002 @ Version 0.2
+   b   return
+
.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 0aa4007..bba1894 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -2,6 +2,9 @@
  * Copyright (C) 2013 - ARM Ltd
  * Author: Marc Zyngier marc.zyng...@arm.com
  *
+ * Copyright (C) Siemens AG, 2014
+ * Author: Jan Kiszka jan.kis...@siemens.com
+ *
  * Based on code by Carl van Schaik c...@ok-labs.com.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -42,6 +45,35 @@
 #defineGICD_BASE   0x1c81000
 #defineGICC_BASE   0x1c82000
 
+#defineTWI_DATA0x0008
+#defineTWI_CNTR0x000c
+#defineTWI_STAT0x0010
+#defineTWI_CCR 0x0014
+#defineTWI_SRST0x0018
+
+#defineTWI_CNTR_STOP   (1  4)
+#defineTWI_CNTR_START  (1  5)
+#defineTWI_CNTR_BUSEN  (1  6)
+
+#defineTWI_STAT_START_SENT 0x08
+#defineTWI_STAT_ADDR_ACK   0x18
+#defineTWI_STAT_DATA_ACK   0x28
+
+#defineTWI_CCR_100KHZ  ((11  3) | 2)
+
+#defineAXP209_ADDR 0x34
+#defineAXP209_REG_SHUTDOWN 0x32
+#defineAXP209_SHUTDOWN_CTRL0x80
+
+#defineWDOG_CTL0x00
+#defineWDOG_MODE   0x04
+
+#defineWDOG_CTL_RSTART (1  0)
+
+#defineWDOG_MODE_EN(1  0)
+#defineWDOG_MODE_RSTEN (1  1)
+#defineWDOG_MODE_0_5_S (0x0  3)
+
 .macro 

Re: [U-Boot] [PATCH v3 2/7] x86: Support pci bus scan in the early phase

[Simon Glass]

On 30 December 2014 at 07:53, Bin Meng bmeng...@gmail.com wrote:
 On x86, some peripherals on pci buses need to be accessed in the
 early phase (eg: pci uart) with a valid pci memory/io address,
 thus scan the pci bus and do the corresponding resource allocation.

 Signed-off-by: Bin Meng bmeng...@gmail.com
 Acked-by: Simon Glass s...@chromium.org
 ---

 Changes in v3: None
 Changes in v2: None

  arch/x86/cpu/pci.c | 1 +
  1 file changed, 1 insertion(+)

Applied to u-boot-x86/next, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v3 1/7] x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.c

[Simon Glass]

On 30 December 2014 at 07:53, Bin Meng bmeng...@gmail.com wrote:
 arch/x86/cpu/pci.c has access to the U-Boot global data thus
 DECLARE_GLOBAL_DATA_PTR is needed.

 Signed-off-by: Bin Meng bmeng...@gmail.com
 Acked-by: Simon Glass s...@chromium.org

 ---

 Changes in v3: None
 Changes in v2:
 - Add a commit message

  arch/x86/cpu/pci.c | 2 ++
  1 file changed, 2 insertions(+)


Applied to u-boot-x86/next, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v3 4/7] fdt: Add several apis to decode pci device node

[Simon Glass]

Hi Bin,

On 30 December 2014 at 07:53, Bin Meng bmeng...@gmail.com wrote:
 This commit adds several APIs to decode PCI device node according to
 the Open Firmware PCI bus bindings, including:
 - fdtdec_get_pci_addr() for encoded pci address
 - fdtdec_get_pci_vendev() for vendor id and device id
 - fdtdec_get_pci_bdf() for pci device bdf triplet
 - fdtdec_get_pci_bar32() for pci device register bar

 Signed-off-by: Bin Meng bmeng...@gmail.com

 ---

 Changes in v3:
 - Fixed a typo: parant - parent
 - Return better error code in fdtdec_get_pci_addr()
 - Add some debug output in fdtdec_get_pci_addr()
 - Reuse variable 'len' instead of creating a new one 'l'
 - Check compatible string length and existence of '.'
 - Using simple_strtol() directly on the compatible sub-string
 - Change variable 'bn' to 'barnum' which is self-documenting

 Changes in v2:
 - New patch to add several apis to decode pci device node

  include/fdtdec.h | 108 
  lib/fdtdec.c | 166 
 ++-
  2 files changed, 249 insertions(+), 25 deletions(-)

Acked-by: Simon Glass s...@chromium.org

See question below...


 diff --git a/include/fdtdec.h b/include/fdtdec.h
 index d2b665c..2b2652f 100644
 --- a/include/fdtdec.h
 +++ b/include/fdtdec.h
 @@ -50,6 +50,49 @@ struct fdt_resource {
 fdt_addr_t end;
  };

 +enum fdt_pci_space {
 +   FDT_PCI_SPACE_CONFIG = 0,
 +   FDT_PCI_SPACE_IO = 0x0100,
 +   FDT_PCI_SPACE_MEM32 = 0x0200,
 +   FDT_PCI_SPACE_MEM64 = 0x0300,
 +   FDT_PCI_SPACE_MEM32_PREF = 0x4200,
 +   FDT_PCI_SPACE_MEM64_PREF = 0x4300,
 +};
 +
 +#define FDT_PCI_ADDR_CELLS 3
 +#define FDT_PCI_SIZE_CELLS 2
 +#define FDT_PCI_REG_SIZE   \
 +   ((FDT_PCI_ADDR_CELLS + FDT_PCI_SIZE_CELLS) * sizeof(u32))
 +
 +/*
 + * The Open Firmware spec defines PCI physical address as follows:
 + *
 + *  bits# 31  24 23  16 15  08 07  00
 + *
 + * phys.hi  cell:  npt000ss      dfff   
 + * phys.mid cell:           
 + * phys.lo  cell:           
 + *
 + * where:
 + *
 + * n:is 0 if the address is relocatable, 1 otherwise
 + * p:is 1 if addressable region is prefetchable, 0 otherwise
 + * t:is 1 if the address is aliased (for non-relocatable I/O) below 
 1MB
 + *   (for Memory), or below 64KB (for relocatable I/O)
 + * ss:   is the space code, denoting the address space
 + * : is the 8-bit Bus Number
 + * d:is the 5-bit Device Number
 + * fff:  is the 3-bit Function Number
 + * : is the 8-bit Register Number
 + * : is a 32-bit unsigned number
 + * : is a 32-bit unsigned number
 + */
 +struct fdt_pci_addr {
 +   u32 phys_hi;
 +   u32 phys_mid;
 +   u32 phys_lo;
 +};
 +
  /**
   * Compute the size of a resource.
   *
 @@ -252,6 +295,60 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int 
 node,
 const char *prop_name, fdt_size_t *sizep);

  /**
 + * Look at an address property in a node and return the pci address which
 + * corresponds to the given type in the form of fdt_pci_addr.
 + * The property must hold one fdt_pci_addr with a lengh.
 + *
 + * @param blob FDT blob
 + * @param node node to examine
 + * @param type pci address type (FDT_PCI_SPACE_xxx)
 + * @param prop_namename of property to find
 + * @param addr returns pci address in the form of fdt_pci_addr
 + * @return 0 if ok, negative on error
 + */
 +int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
 +   const char *prop_name, struct fdt_pci_addr *addr);
 +
 +/**
 + * Look at the compatible property of a device node that represents a PCI
 + * device and extract pci vendor id and device id from it.
 + *
 + * @param blob FDT blob
 + * @param node node to examine
 + * @param vendor   vendor id of the pci device
 + * @param device   device id of the pci device
 + * @return 0 if ok, negative on error
 + */
 +int fdtdec_get_pci_vendev(const void *blob, int node,
 +   u16 *vendor, u16 *device);
 +
 +/**
 + * Look at the pci address of a device node that represents a PCI device
 + * and parse the bus, device and function number from it.
 + *
 + * @param blob FDT blob
 + * @param node node to examine
 + * @param addr pci address in the form of fdt_pci_addr
 + * @param bdf  returns bus, device, function triplet
 + * @return 0 if ok, negative on error
 + */
 +int fdtdec_get_pci_bdf(const void *blob, int node,
 +   struct fdt_pci_addr *addr, pci_dev_t *bdf);
 +
 +/**
 + * Look at the pci address of a device node that represents a PCI device
 + * and return base address of the pci device's registers.
 + *
 + * @param blob FDT blob
 + * @param node node to examine
 + 

Re: [U-Boot] [PATCH v3 5/7] serial: ns16550: Support ns16550 compatible pci uart devices

[Simon Glass]

On 30 December 2014 at 07:53, Bin Meng bmeng...@gmail.com wrote:
 There are many pci uart devices which are ns16550 compatible. We can
 describe them in the board dts file and use it as the U-Boot serial
 console as specified in the chosen node 'stdout-path' property.

 Those pci uart devices can have their register be memory-mapped, or
 i/o-mapped. The driver will try to use the memory-mapped register if
 the reg property in the node has an entry to describe the memory-mapped
 register, otherwise i/o-mapped register will be used.

 Signed-off-by: Bin Meng bmeng...@gmail.com

 ---

 Changes in v3:
 - Update to use 'memory-mapped' and 'i/o-mapped' in several places
 - Use 'Processor Local Bus' instead of 'plb'
 - Change the logic in ns16550_serial_ofdata_to_platdata() to avoid goto

 Changes in v2:
 - New patch to support ns16550 compatible pci uart devices

  drivers/serial/ns16550.c | 31 +++
  1 file changed, 31 insertions(+)

Acked-by: Simon Glass s...@chromium.org
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v3 3/7] pci: Make pci apis usable before relocation

[Simon Glass]

On 30 December 2014 at 07:53, Bin Meng bmeng...@gmail.com wrote:
 Introduce a gd-hose to save the pci hose in the early phase so that
 apis in drivers/pci/pci.c can be used before relocation. Architecture
 codes need assign a valid gd-hose in the early phase.

 Some variables are declared as static so change them to be either
 stack variable or global data member so that they can be used before
 relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
 just affects some print format.

 Signed-off-by: Bin Meng bmeng...@gmail.com
 Acked-by: Simon Glass s...@chromium.org

 ---

 Changes in v3: None
 Changes in v2:
 - New patch to make pci apis usable before relocation

  arch/x86/cpu/pci.c |  8 
  arch/x86/include/asm/global_data.h |  1 -
  arch/x86/include/asm/pci.h |  2 +-
  drivers/pci/pci.c  | 25 +
  include/asm-generic/global_data.h  |  6 ++
  5 files changed, 28 insertions(+), 14 deletions(-)

Applied to u-boot-x86/next, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] Fwd: coreboot uboot qemu x86

[Ajoy Das]

-- Forwarded message --
From: Ajoy Das dasajo...@gmail.com
Date: Tue, Dec 30, 2014 at 1:40 PM
Subject: Re: [U-Boot] coreboot uboot qemu x86
To: U-Boot Mailing List u-boot@lists.denx.de


Hi Simon

Can i do a gdb on u-boot startup on the coreboot environment.
means i want to stop at _start in uboot and connect to gdb.

Thanks
Ajoy

On Tue, Dec 30, 2014 at 11:15 AM, Ajoy Das dasajo...@gmail.com wrote:

 I tried changing the boot rom size to 2MB.
 But with no effect

 coreboot.rom: 2048 kB, bootblocksize 944, romsize 2097152, offset 0x0
 alignment: 64 bytes, architecture: x86

 Name   Offset Type Size
 cmos_layout.bin0x0cmos_layout  1160
 fallback/romstage  0x4c0  stage17960
 fallback/ramstage  0x4b40 stage56190
 config 0x12700raw  2990
 revision   0x13300raw  692
 (empty)0x13600null 2016728
 HOSTCC cbfstool/rmodtool.o

 Thanks
 Ajoy



 On Tue, Dec 30, 2014 at 4:17 AM, Simon Glass s...@chromium.org wrote:

 Hi Ajoy,

  On Mon, Dec 29, 2014 at 9:28 PM, Simon Glass s...@chromium.org wrote:
 
  Hi Ajoy,
 
 
   On Mon, Dec 29, 2014 at 7:36 PM, Simon Glass s...@chromium.org
 wrote:
  
   Hi,
  
   On 28 December 2014 at 21:38, Ajoy Das dasajo...@gmail.com wrote:
Hi
   
Need Help
   
I want to run U-BOOT as coreboot payload on QEMU platform
   
I am on uboot-x86 git
   
Compiled U-BOOT with make coreboot-x86_defconfig and make all
   
Running qemu with
qemu-system-i386 -bios ../coreboot/build/coreboot.rom -hda
 disk.img
-nographic -m 1g
   
But The system crashes with the following message
   
qemu: fatal: Trying to execute code outside RAM or ROM at
 0x5e2a36c2
   
Loading Segment: addr: 0x0111 memsz:
 0x000588e8
filesz:
0x000252eb
lb: [0x0010, 0x0012b030)
Post relocation: addr: 0x0111 memsz:
 0x000588e8
filesz:
0x000252eb
using LZMA
[ 0x0111, 011688e8, 0x011688e8) - fffd2770
dest 0111, end 011688e8, bouncebuffer 3ff77000
Loaded segments
Jumping to boot code at 01110015
CPU0: stack: 00126000 - 00127000, lowest used address 00126b8c,
 stack
used:
1140 bytes
entry= 0x01110015
lb_start = 0x0010
lb_size  = 0x0002b030
buffer   = 0x3ff77000
qemu: fatal: Trying to execute code outside RAM or ROM at
 0x5e2a36c2
   
EAX=000a EBX=000186a0 ECX=01145d15 EDX=19203eb0
ESI= EDI= EBP=01145f6c ESP=01145f54
EIP=5e2a36c2 EFL=0002 [---] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0018   00cf9300 DPL=0 DS   [-WA]
CS =0010   00cf9b00 DPL=0 CS32 [-RA]
SS =0018   00cf9300 DPL=0 DS   [-WA]
DS =0018   00cf9300 DPL=0 DS   [-WA]
FS =0020 19203f5c  00cf9300 DPL=0 DS   [-WA]
GS =0018   00cf9300 DPL=0 DS   [-WA]
LDT=   8200 DPL=0 LDT
TR =   8b00 DPL=0 TSS32-busy
GDT= 19203e60 0047
IDT=  
CR0=6033 CR2= CR3= CR4=
DR0= DR1= DR2= DR3=
DR6=0ff0 DR7=0400
CCS=0218 CCD=01145f50 CCO=ADDL
EFER=
FCW=037f FSW= [ST=0] FTW=00 MXCSR=1f80
FPR0=  FPR1= 
FPR2=  FPR3= 
FPR4=  FPR5= 
FPR6=  FPR7= 
XMM00=
XMM01=
XMM02=
XMM03=
XMM04=
XMM05=
XMM06=
XMM07=
Aborted (core dumped)
   
qemu-system-i386 --version
QEMU emulator version 1.0 (qemu-kvm-1.0), Copyright (c) 2003-2008
Fabrice
Bellard
   
Is QEMU not supported for coreboot and u-boot
  
   I'm not sure it's been tried but there's no reason why it should
 work.
   It seems to be crashing in U-Boot before there is any serial output.
   Did you put u-boot-dtb.bin as the payload?

  On 29 December 2014 at 07:34, Ajoy Das dasajo...@gmail.com wrote:
   Hi Simon
  
   Thanks for your reply
  
   I have added u-boot ELF as the coreboot payload
  
   u-boot: ELF 32-bit LSB shared object, Intel 80386, version 1 (SYSV),
   statically linked, not stripped.
  
   Got this link but its a year old.
   http://lists.denx.de/pipermail/u-boot/2013-July/159140.html
  
   Thanks
   Ajoy
  
 
 [snip]
 
  I suggest using cbfstool add-flat-binary -f u-boot-dtb.bin -n
  

Re: [U-Boot] coreboot uboot qemu x86

[Simon Glass]

Hi Ajoy,

On 30 December 2014 at 12:44, Ajoy Das dasajo...@gmail.com wrote:

 -- Forwarded message --
 From: Ajoy Das dasajo...@gmail.com
 Date: Tue, Dec 30, 2014 at 1:40 PM
 Subject: Re: [U-Boot] coreboot uboot qemu x86
 To: U-Boot Mailing List u-boot@lists.denx.de


 Hi Simon

 Can i do a gdb on u-boot startup on the coreboot environment.
 means i want to stop at _start in uboot and connect to gdb.

 Thanks
 Ajoy

 On Tue, Dec 30, 2014 at 11:15 AM, Ajoy Das dasajo...@gmail.com wrote:

 I tried changing the boot rom size to 2MB.
 But with no effect

 coreboot.rom: 2048 kB, bootblocksize 944, romsize 2097152, offset 0x0
 alignment: 64 bytes, architecture: x86

 Name   Offset Type Size
 cmos_layout.bin0x0cmos_layout  1160
 fallback/romstage  0x4c0  stage17960
 fallback/ramstage  0x4b40 stage56190
 config 0x12700raw  2990
 revision   0x13300raw  692
 (empty)0x13600null 2016728
 HOSTCC cbfstool/rmodtool.o

 Thanks
 Ajoy



 On Tue, Dec 30, 2014 at 4:17 AM, Simon Glass s...@chromium.org wrote:

 Hi Ajoy,

  On Mon, Dec 29, 2014 at 9:28 PM, Simon Glass s...@chromium.org wrote:
 
  Hi Ajoy,
 
 
   On Mon, Dec 29, 2014 at 7:36 PM, Simon Glass s...@chromium.org
   wrote:
  
   Hi,
  
   On 28 December 2014 at 21:38, Ajoy Das dasajo...@gmail.com wrote:
Hi
   
Need Help
   
I want to run U-BOOT as coreboot payload on QEMU platform
   
I am on uboot-x86 git
   
Compiled U-BOOT with make coreboot-x86_defconfig and make all
   
Running qemu with
qemu-system-i386 -bios ../coreboot/build/coreboot.rom -hda
disk.img
-nographic -m 1g
   
But The system crashes with the following message
   
qemu: fatal: Trying to execute code outside RAM or ROM at
0x5e2a36c2
   
Loading Segment: addr: 0x0111 memsz:
0x000588e8
filesz:
0x000252eb
lb: [0x0010, 0x0012b030)
Post relocation: addr: 0x0111 memsz:
0x000588e8
filesz:
0x000252eb
using LZMA
[ 0x0111, 011688e8, 0x011688e8) - fffd2770
dest 0111, end 011688e8, bouncebuffer 3ff77000
Loaded segments
Jumping to boot code at 01110015
CPU0: stack: 00126000 - 00127000, lowest used address 00126b8c,
stack
used:
1140 bytes
entry= 0x01110015
lb_start = 0x0010
lb_size  = 0x0002b030
buffer   = 0x3ff77000
qemu: fatal: Trying to execute code outside RAM or ROM at
0x5e2a36c2
   
EAX=000a EBX=000186a0 ECX=01145d15 EDX=19203eb0
ESI= EDI= EBP=01145f6c ESP=01145f54
EIP=5e2a36c2 EFL=0002 [---] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0018   00cf9300 DPL=0 DS   [-WA]
CS =0010   00cf9b00 DPL=0 CS32 [-RA]
SS =0018   00cf9300 DPL=0 DS   [-WA]
DS =0018   00cf9300 DPL=0 DS   [-WA]
FS =0020 19203f5c  00cf9300 DPL=0 DS   [-WA]
GS =0018   00cf9300 DPL=0 DS   [-WA]
LDT=   8200 DPL=0 LDT
TR =   8b00 DPL=0 TSS32-busy
GDT= 19203e60 0047
IDT=  
CR0=6033 CR2= CR3= CR4=
DR0= DR1= DR2= DR3=
DR6=0ff0 DR7=0400
CCS=0218 CCD=01145f50 CCO=ADDL
EFER=
FCW=037f FSW= [ST=0] FTW=00 MXCSR=1f80
FPR0=  FPR1= 
FPR2=  FPR3= 
FPR4=  FPR5= 
FPR6=  FPR7= 
XMM00=
XMM01=
XMM02=
XMM03=
XMM04=
XMM05=
XMM06=
XMM07=
Aborted (core dumped)
   
qemu-system-i386 --version
QEMU emulator version 1.0 (qemu-kvm-1.0), Copyright (c) 2003-2008
Fabrice
Bellard
   
Is QEMU not supported for coreboot and u-boot
  
   I'm not sure it's been tried but there's no reason why it should
   work.
   It seems to be crashing in U-Boot before there is any serial
   output.
   Did you put u-boot-dtb.bin as the payload?

  On 29 December 2014 at 07:34, Ajoy Das dasajo...@gmail.com wrote:
   Hi Simon
  
   Thanks for your reply
  
   I have added u-boot ELF as the coreboot payload
  
   u-boot: ELF 32-bit LSB shared object, Intel 80386, version 1 (SYSV),
   statically linked, not stripped.
  
   Got this link but its a year old.
   

[U-Boot] [PULL] u-boot-socfpga/master

[Marek Vasut]

The following changes since commit d8bec60c1b0de7770f9b56ad092ab9be801d99af:

  ARM: UniPhier: enable CONFIG_CMD_DM (2014-12-18 23:34:30 +0900)

are available in the git repository at:

  git://git.denx.de/u-boot-socfpga.git master

for you to fetch changes up to d0e932de7c8e46ade1994e03e864636db3922520:

  arm: socfpga: Change watchdog timeout (2014-12-21 14:39:04 +0100)


Stefan Roese (1):
  arm: socfpga: Change watchdog timeout

 arch/arm/cpu/armv7/socfpga/misc.c | 12 +++-
 include/configs/socfpga_common.h  |  2 +-
 2 files changed, 12 insertions(+), 2 deletions(-)
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/1] cmd, fdt: fix working_fdt is set to wrong value

[Simon Glass]

Hi,

On 29 December 2014 at 23:44, Hua Yanghao huayang...@gmail.com wrote:
 By the way, which is the current branch you guys are working on?
 u-boot/master I assume?

Yes that's right.

- Simon


 On Tue, Dec 30, 2014 at 2:44 PM, Hua Yanghao huayang...@gmail.com wrote:
 Hi Simon,
 Thank you for the suggestion. I will set up git send-email and send a
 new patch for review.
 For set_working_fdt_addr, a simple grep shows 2 other places
 (common/bootm.c common/image-fdt.c) is already using its parameter as
 void *. changing it to ulong will cause the other 2 places to use
 casting. Maybe just keep its current void * is already good enough.

 Best Regards,
 Yanghao

 On Tue, Dec 23, 2014 at 3:54 AM, Simon Glass s...@chromium.org wrote:
 Hi Hua,

 On 21 December 2014 at 13:45, Hua Yanghao huayang...@gmail.com wrote:

 Being a long time u-boot developer, this is the first time I'm trying
 to get some fix for the open source code back to mainline.
 If anything wrong during the process, please be gentle :-) Thank you.

 From 225c8f8f2af4cf6092260e5c133d90096e2f3352 Mon Sep 17 00:00:00 2001
 From: Hua Yanghao huayang...@gmail.com
 Date: Mon, 22 Dec 2014 04:32:39 +0800
 Subject: [PATCH 1/1] cmd, fdt: fix working_fdt is set to wrong value

 Instead of setting working_fdt to map_sysmem(addr) (e.g. blob), it should 
 be set
 to addr directly as inside set_working_fdt_addr it uses map_sysmem(addr) 
 again.
 To test: ./u-boot -d dts/dt.bin , then issue: fdt addr 0x100, fdt print 
 will
 then cause an segmentation fault. After this fix fdt print is functional.
 ---
  common/cmd_fdt.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c
 index 5640ded..d5eebcb 100644
 --- a/common/cmd_fdt.c
 +++ b/common/cmd_fdt.c
 @@ -123,7 +123,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int
 argc, char * const argv[])
   if (control)
   gd-fdt_blob = blob;
   else
 - set_working_fdt_addr(blob);
 + set_working_fdt_addr((void *)addr);

   if (argc = 2) {
   int  len;

 I think maybe your patch generation is a bit broken as the indentation
 has been lost. If you don't have git send-email set up you should
 probably look at that, and use patman to send patches.

 This change looks right apart from that. You could also look at
 changing the argument of set_working_fdt_addr() to ulong if you like.

 Regards,
 Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/9] arm: Add warnings about using gdata

[Simon Glass]

Hi Igor,

On 30 December 2014 at 00:39, Igor Grinberg grinb...@compulab.co.il wrote:
 Hi Simon,

 On 12/29/14 18:24, Simon Glass wrote:
 Hi Igor,

 On 23 December 2014 at 23:53, Igor Grinberg grinb...@compulab.co.il wrote:
 Hi Simon,

 On 12/23/14 21:04, Simon Glass wrote:
 We need to get rid of this SPL-specific setting of the global_data pointer.
 It is already set up in start.S immediately before board_init_f() is 
 called,
 and there may be information there that is needed (e.g. pre-reloc malloc
 info).

 Signed-off-by: Simon Glass s...@chromium.org
 ---

  arch/arm/lib/spl.c | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

 diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
 index dfcc596..c41850a 100644
 --- a/arch/arm/lib/spl.c
 +++ b/arch/arm/lib/spl.c
 @@ -15,6 +15,11 @@

  /* Pointer to as well as the global data structure for SPL */
  DECLARE_GLOBAL_DATA_PTR;
 +
 +/*
 + * WARNING: This is going away very soon. Don't use it and don't submit
 + * pafches that rely on it. The global_data area is set up in crt0.S.
 + */
  gd_t gdata __attribute__ ((section(.data)));

  /*
 @@ -28,7 +33,7 @@ void __weak board_init_f(ulong dummy)
   /* Clear the BSS. */
   memset(__bss_start, 0, __bss_end - __bss_start);

 - /* Set global data pointer. */
 + /* TODO: Remove settings of the global data pointer here */

 Why do you need this patch at all if you remove this stuff in 9/9?

 I imagine that 9/9 might take some time to be applied, since it needs
 testing, so I've put that in as a clean-up patch.

 I personally, like this patch set and think we should move forward with it.
 We'll give it a try (hopefully this week), but I don't think it should be
 merged before the next merge window.
 Is this (1/9) patch intended to go in during the rc?

There's not enough time to test/fix this, so it would be better to
apply it when the merge window opens. Then any breakage can be dealt
with. At least this time we have the patches (this series plus Tom's
patches) so the plan should work.

Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] x86: Simplify the fsp hob access functions

[Simon Glass]

Hi Bin,

On 30 December 2014 at 01:02, Bin Meng bmeng...@gmail.com wrote:
 Remove the troublesome union hob_pointers so that some annoying casts
 are no longer needed in those hob access routines. This also improves
 the readability.

 Signed-off-by: Bin Meng bmeng...@gmail.com
 ---

  arch/x86/cpu/queensbay/fsp_support.c   | 95 
 --
  arch/x86/cpu/queensbay/tnc_dram.c  | 39 +
  arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h  | 46 ---
  .../include/asm/arch-queensbay/fsp/fsp_support.h   |  5 +-
  arch/x86/lib/cmd_hob.c | 16 ++--
  5 files changed, 101 insertions(+), 100 deletions(-)


Yes a big improvement - see a few additional ideas for a follow-on patch below.

Acked-by: Simon Glass s...@chromium.org

 diff --git a/arch/x86/cpu/queensbay/fsp_support.c 
 b/arch/x86/cpu/queensbay/fsp_support.c
 index ef1916b..4764e3c 100644
 --- a/arch/x86/cpu/queensbay/fsp_support.c
 +++ b/arch/x86/cpu/queensbay/fsp_support.c
 @@ -231,26 +231,28 @@ u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase)

  u32 fsp_get_usable_lowmem_top(const void *hob_list)
  {
 -   union hob_pointers hob;
 +   const struct hob_header *hdr;
 +   struct hob_res_desc *res_desc;
 phys_addr_t phys_start;
 u32 top;

 /* Get the HOB list for processing */
 -   hob.raw = (void *)hob_list;
 +   hdr = hob_list;

 /* * Collect memory ranges */
 top = FSP_LOWMEM_BASE;
 -   while (!end_of_hob(hob)) {
 -   if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
 -   if (hob.res_desc-type == RES_SYS_MEM) {
 -   phys_start = hob.res_desc-phys_start;
 +   while (!end_of_hob(hdr)) {
 +   if (get_hob_type(hdr) == HOB_TYPE_RES_DESC) {
 +   res_desc = (struct hob_res_desc *)hdr;
 +   if (res_desc-type == RES_SYS_MEM) {
 +   phys_start = res_desc-phys_start;
 /* Need memory above 1MB to be collected here 
 */
 if (phys_start = FSP_LOWMEM_BASE 
 phys_start  
 (phys_addr_t)FSP_HIGHMEM_BASE)
 -   top += (u32)(hob.res_desc-len);
 +   top += (u32)(res_desc-len);
 }
 }
 -   hob.raw = get_next_hob(hob);
 +   hdr = get_next_hob(hdr);
 }

 return top;
 @@ -258,25 +260,27 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)

  u64 fsp_get_usable_highmem_top(const void *hob_list)
  {
 -   union hob_pointers hob;
 +   const struct hob_header *hdr;
 +   struct hob_res_desc *res_desc;
 phys_addr_t phys_start;
 u64 top;

 /* Get the HOB list for processing */
 -   hob.raw = (void *)hob_list;
 +   hdr = hob_list;

 /* Collect memory ranges */
 top = FSP_HIGHMEM_BASE;
 -   while (!end_of_hob(hob)) {
 -   if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
 -   if (hob.res_desc-type == RES_SYS_MEM) {
 -   phys_start = hob.res_desc-phys_start;
 +   while (!end_of_hob(hdr)) {
 +   if (get_hob_type(hdr) == HOB_TYPE_RES_DESC) {
 +   res_desc = (struct hob_res_desc *)hdr;
 +   if (res_desc-type == RES_SYS_MEM) {
 +   phys_start = res_desc-phys_start;
 /* Need memory above 1MB to be collected here 
 */
 if (phys_start = 
 (phys_addr_t)FSP_HIGHMEM_BASE)
 -   top += (u32)(hob.res_desc-len);
 +   top += (u32)(res_desc-len);
 }
 }
 -   hob.raw = get_next_hob(hob);
 +   hdr = get_next_hob(hdr);
 }

 return top;
 @@ -285,24 +289,26 @@ u64 fsp_get_usable_highmem_top(const void *hob_list)
  u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
struct efi_guid *guid)
  {
 -   union hob_pointers hob;
 +   const struct hob_header *hdr;
 +   struct hob_res_desc *res_desc;

 /* Get the HOB list for processing */
 -   hob.raw = (void *)hob_list;
 +   hdr = hob_list;

 /* Collect memory ranges */
 -   while (!end_of_hob(hob)) {
 -   if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
 -   if (hob.res_desc-type == RES_MEM_RESERVED) {
 -   if (compare_guid(hob.res_desc-owner, guid)) 
 {
 +   while (!end_of_hob(hdr)) {
 +   if (get_hob_type(hdr) == HOB_TYPE_RES_DESC) {
 +   res_desc = (struct hob_res_desc *)hdr;
 +   if (res_desc-type == RES_MEM_RESERVED) {
 

Re: [U-Boot] [PATCH 04/10] x86: spi: Add device tree support

[Simon Glass]

Hi Jagan,

On 30 December 2014 at 02:00, Jagan Teki jagannadh.t...@gmail.com wrote:
 On 30 December 2014 at 06:42, Simon Glass s...@chromium.org wrote:
 As a temporary measure before the ICH driver moves over to driver model,
 add device tree support to the driver.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

  drivers/spi/ich.c| 7 +++
  include/configs/x86-common.h | 1 +
  2 files changed, 8 insertions(+)

 diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
 index 0379444..fdff158 100644
 --- a/drivers/spi/ich.c
 +++ b/drivers/spi/ich.c
 @@ -153,6 +153,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
 unsigned int cs,
 return ich-slave;
  }

 +struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
 + int spi_node)
 +{
 +   /* We only support a single SPI at present */
 +   return spi_setup_slave(0, 0, 2000, 0);
 +}
 +

 This would call from spi_flash_probe_fdt(), who is the caller for this?

arch/x86/cpu/ivybridge/sdram.c: *sfp =
spi_flash_probe_fdt(blob, node, spi_node);


  void spi_free_slave(struct spi_slave *slave)
  {
 struct ich_spi_slave *ich = to_ich_spi(slave);
 diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
 index 4f0a3c5..ecedfc3 100644
 --- a/include/configs/x86-common.h
 +++ b/include/configs/x86-common.h
 @@ -211,6 +211,7 @@
  #define CONFIG_CMD_SF_TEST
  #define CONFIG_CMD_SPI
  #define CONFIG_SPI
 +#define CONFIG_OF_SPI_FLASH

  /*---
   * Environment configuration
 --
 2.2.0.rc0.207.ga3a616c

Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 03/22] x86: Correct ifdtool microcode calculation

[Bin Meng]

On Sun, Dec 28, 2014 at 10:20 AM, Simon Glass s...@chromium.org wrote:
 This currently assumes that U-Boot resides at the start of ROM. Update
 it to remove this assumption.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

  tools/ifdtool.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

 diff --git a/tools/ifdtool.c b/tools/ifdtool.c
 index fe8366b..590ccc9 100644
 --- a/tools/ifdtool.c
 +++ b/tools/ifdtool.c
 @@ -788,9 +788,9 @@ static int write_uboot(char *image, int size, struct 
 input_file *uboot,
   fdt_strerror(data_size));
 return -ENOENT;
 }
 -   offset = ucode_ptr - uboot-addr;
 +   offset = (uint32_t)(ucode_ptr + size);
 ptr = (void *)image + offset;
 -   ptr[0] = uboot-addr + (data - image);
 +   ptr[0] = (data - image) - size;
 ptr[1] = data_size;
 debug(Wrote microcode pointer at %x: addr=%x, size=%x\n,
   ucode_ptr, ptr[0], ptr[1]);
 --

Reviewed-by: Bin Meng bmeng...@gmail.com

Tested on Intel Crown Bay by adjusting ROM_SIZE to 2MB

Tested-by:  Bin Meng bmeng...@gmail.com
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v4 0/5] qspi: qspi support for mx6sxsabresd

[Peng Fan]

This patch set is to support qspi for mx6sxsabresd board.

To mx6sxsabresd Revb board, 32M flash is used, but in header file,
CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M. The LUT
initialization qspi_set_lut function uses 32BIT addr, however
CONFIG_SPI_FLASH_BAR  and 24BIT addr should be used to access
bigger than 16MB size flash, and BRRD/BRWR should also be supported.
Future patches will fix this.

Since flash opcodes are not recommended to use in driver level, use
QSPI_CMD_xx to replace OPCODE_xx. It is qspi controller's feature
to program LUT with QSPI_CMD_xx which same value with OPCODE_xx.

Since Revb board's qspi flash support 4K erase, 4K erase is added in driver.

Peng Fan (5):
  QuadSPI: use QSPI_CMD_xx instead of flash opcodes
  QuadSPI: use correct amba_base
  arm:mx6sx add QSPI support
  imx:qspi add 4K erase support
  imx:mx6sxsabresd add qspi support

 arch/arm/cpu/armv7/mx6/clock.c  |  50 ++
 arch/arm/include/asm/arch-mx6/clock.h   |   1 +
 arch/arm/include/asm/arch-mx6/imx-regs.h|  12 +--
 board/freescale/mx6sxsabresd/mx6sxsabresd.c |  40 
 drivers/spi/fsl_qspi.c  | 137 +++-
 include/configs/mx6sxsabresd.h  |  12 +++
 6 files changed, 205 insertions(+), 47 deletions(-)

-- 
1.8.4


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v4 1/5] QuadSPI: use QSPI_CMD_xx instead of flash opcodes

[Peng Fan]

Use QSPI_CMD_xx instead of flash opcodes

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v4:
  None

Changes v3:
  Use QSPI_CMD_XX instead of flash opcodes. To fsl qspi controller,
  the LUT  should be pre programmed with QSPI CMD.

Changes v2:
 None

 drivers/spi/fsl_qspi.c | 64 ++
 1 file changed, 33 insertions(+), 31 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index ba20bef..61490c9 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -29,19 +29,19 @@
 #define SEQID_PP   6
 #define SEQID_RDID 7
 
-/* Flash opcodes */
-#define OPCODE_PP  0x02/* Page program (up to 256 bytes) */
-#define OPCODE_RDSR0x05/* Read status register */
-#define OPCODE_WREN0x06/* Write enable */
-#define OPCODE_FAST_READ   0x0b/* Read data bytes (high frequency) */
-#define OPCODE_CHIP_ERASE  0xc7/* Erase whole flash chip */
-#define OPCODE_SE  0xd8/* Sector erase (usually 64KiB) */
-#define OPCODE_RDID0x9f/* Read JEDEC ID */
-
-/* 4-byte address opcodes - used on Spansion and some Macronix flashes */
-#define OPCODE_FAST_READ_4B0x0c/* Read data bytes (high frequency) */
-#define OPCODE_PP_4B   0x12/* Page program (up to 256 bytes) */
-#define OPCODE_SE_4B   0xdc/* Sector erase (usually 64KiB) */
+/* QSPI CMD */
+#define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
+#define QSPI_CMD_RDSR  0x05/* Read status register */
+#define QSPI_CMD_WREN  0x06/* Write enable */
+#define QSPI_CMD_FAST_READ 0x0b/* Read data bytes (high frequency) */
+#define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */
+#define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */
+#define QSPI_CMD_RDID  0x9f/* Read JEDEC ID */
+
+/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
+#define QSPI_CMD_FAST_READ_4B  0x0c/* Read data bytes (high frequency) */
+#define QSPI_CMD_PP_4B 0x12/* Page program (up to 256 bytes) */
+#define QSPI_CMD_SE_4B 0xdc/* Sector erase (usually 64KiB) */
 
 #ifdef CONFIG_SYS_FSL_QSPI_LE
 #define qspi_read32in_le32
@@ -94,7 +94,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
 
/* Write Enable */
lut_base = SEQID_WREN * 4;
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_WREN) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_WREN) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
qspi_write32(regs-lut[lut_base + 1], 0);
qspi_write32(regs-lut[lut_base + 2], 0);
@@ -103,13 +103,15 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
/* Fast Read */
lut_base = SEQID_FAST_READ * 4;
if (FSL_QSPI_FLASH_SIZE  = SZ_16M)
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_FAST_READ) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_FAST_READ_4B) |
-   PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
-   PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+   qspi_write32(regs-lut[lut_base],
+OPRND0(QSPI_CMD_FAST_READ_4B) |
+PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
+OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
+INSTR1(LUT_ADDR));
qspi_write32(regs-lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) |
INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
INSTR1(LUT_READ));
@@ -118,7 +120,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
 
/* Read Status */
lut_base = SEQID_RDSR * 4;
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_RDSR) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
PAD1(LUT_PAD1) | INSTR1(LUT_READ));
qspi_write32(regs-lut[lut_base + 1], 0);
@@ -128,11 +130,11 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
/* Erase a sector */
lut_base = SEQID_SE * 4;
if (FSL_QSPI_FLASH_SIZE  = SZ_16M)
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_SE) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_SE) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_SE_4B) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_SE_4B) |
PAD0(LUT_PAD1) | 

[U-Boot] [PATCH v4 2/5] QuadSPI: use correct amba_base

[Peng Fan]

According cs, use different amba_base to choose the corresponding
flash devices.  If not, `sf probe 1:0` and `sf probe 1:1` will
choose the same flash device, but not different flash devices.

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v4:
 None

Changes v3:
 None

Changes v2:
 None

 drivers/spi/fsl_qspi.c | 30 +-
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 61490c9..eae2f3a 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -194,12 +194,22 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
unsigned int cs,
if (bus = ARRAY_SIZE(spi_bases))
return NULL;
 
+   if (cs = FSL_QSPI_FLASH_NUM)
+   return NULL;
+
qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
if (!qspi)
return NULL;
 
qspi-reg_base = spi_bases[bus];
-   qspi-amba_base = amba_bases[bus];
+   /*
+* According cs, use different amba_base to choose the
+* corresponding flash devices.
+*
+* If not, only one flash device is used even if passing
+* different cs using `sf probe`
+*/
+   qspi-amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
 
qspi-slave.max_write_size = TX_BUFFER_SIZE;
 
@@ -212,10 +222,20 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
unsigned int cs,
qspi_write32(regs-mcr, QSPI_MCR_RESERVED_MASK);
 
total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
-   qspi_write32(regs-sfa1ad, FSL_QSPI_FLASH_SIZE | qspi-amba_base);
-   qspi_write32(regs-sfa2ad, FSL_QSPI_FLASH_SIZE | qspi-amba_base);
-   qspi_write32(regs-sfb1ad, total_size | qspi-amba_base);
-   qspi_write32(regs-sfb2ad, total_size | qspi-amba_base);
+   /*
+* Any read access to non-implemented addresses will provide
+* undefined results.
+*
+* In case single die flash devices, TOP_ADDR_MEMA2 and
+* TOP_ADDR_MEMB2 should be initialized/programmed to
+* TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
+* setting the size of these devices to 0.  This would ensure
+* that the complete memory map is assigned to only one flash device.
+*/
+   qspi_write32(regs-sfa1ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
+   qspi_write32(regs-sfa2ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
+   qspi_write32(regs-sfb1ad, total_size | amba_bases[bus]);
+   qspi_write32(regs-sfb2ad, total_size | amba_bases[bus]);
 
qspi_set_lut(qspi);
 
-- 
1.8.4


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v4 4/5] imx:qspi add 4K erase support

[Peng Fan]

Add 4k erase command support for qspi driver. reuse the 64k erase function,
but change the function name from qspi_op_se to qspi_op_erase, since it
supports 64k and 4k erase.

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v4:
 New patch in v4. This patch is to support 4k erase.

 drivers/spi/fsl_qspi.c | 24 +++-
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index e9c45de..d12f420 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -32,12 +32,14 @@
 #define SEQID_CHIP_ERASE   5
 #define SEQID_PP   6
 #define SEQID_RDID 7
+#define SEQID_BE_4K8
 
 /* QSPI CMD */
 #define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
 #define QSPI_CMD_RDSR  0x05/* Read status register */
 #define QSPI_CMD_WREN  0x06/* Write enable */
 #define QSPI_CMD_FAST_READ 0x0b/* Read data bytes (high frequency) */
+#define QSPI_CMD_BE_4K 0x20/* 4K erase */
 #define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */
 #define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */
 #define QSPI_CMD_RDID  0x9f/* Read JEDEC ID */
@@ -192,6 +194,12 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
qspi_write32(regs-lut[lut_base + 2], 0);
qspi_write32(regs-lut[lut_base + 3], 0);
 
+   /* SUB SECTOR 4K ERASE */
+   lut_base = SEQID_BE_4K * 4;
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
+PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+
/* Lock the LUT */
qspi_write32(regs-lutkey, LUT_KEY_VALUE);
qspi_write32(regs-lckcr, QSPI_LCKCR_LOCK);
@@ -450,7 +458,7 @@ static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf)
qspi_write32(regs-mcr, mcr_reg);
 }
 
-static void qspi_op_se(struct fsl_qspi *qspi)
+static void qspi_op_erase(struct fsl_qspi *qspi)
 {
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
u32 mcr_reg;
@@ -469,8 +477,13 @@ static void qspi_op_se(struct fsl_qspi *qspi)
while (qspi_read32(regs-sr)  QSPI_SR_BUSY_MASK)
;
 
-   qspi_write32(regs-ipcr,
-   (SEQID_SE  QSPI_IPCR_SEQID_SHIFT) | 0);
+   if (qspi-cur_seqid == QSPI_CMD_SE) {
+   qspi_write32(regs-ipcr,
+(SEQID_SE  QSPI_IPCR_SEQID_SHIFT) | 0);
+   } else if (qspi-cur_seqid == QSPI_CMD_BE_4K) {
+   qspi_write32(regs-ipcr,
+(SEQID_BE_4K  QSPI_IPCR_SEQID_SHIFT) | 0);
+   }
while (qspi_read32(regs-sr)  QSPI_SR_BUSY_MASK)
;
 
@@ -497,9 +510,10 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 
if (qspi-cur_seqid == QSPI_CMD_FAST_READ) {
qspi-sf_addr = swab32(txbuf)  OFFSET_BITS_MASK;
-   } else if (qspi-cur_seqid == QSPI_CMD_SE) {
+   } else if ((qspi-cur_seqid == QSPI_CMD_SE) ||
+  (qspi-cur_seqid == QSPI_CMD_BE_4K)) {
qspi-sf_addr = swab32(txbuf)  OFFSET_BITS_MASK;
-   qspi_op_se(qspi);
+   qspi_op_erase(qspi);
} else if (qspi-cur_seqid == QSPI_CMD_PP) {
pp_sfaddr = swab32(txbuf)  OFFSET_BITS_MASK;
}
-- 
1.8.4


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v4 3/5] arm:mx6sx add QSPI support

[Peng Fan]

Add QSPI support for mx6solox.

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v4:
 None

Changes v3:
 None

Changes v2:
 Take Fabio's suggestion, split soc code and board code into two patches.

 arch/arm/cpu/armv7/mx6/clock.c   | 50 
 arch/arm/include/asm/arch-mx6/clock.h|  1 +
 arch/arm/include/asm/arch-mx6/imx-regs.h | 12 
 drivers/spi/fsl_qspi.c   | 19 
 4 files changed, 76 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 93a02ad..a05dca3 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -434,6 +434,56 @@ static u32 get_mmdc_ch0_clk(void)
 }
 #endif
 
+#ifdef CONFIG_MX6SX
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+   u32 reg = 0;
+   /* Enable QuadSPI clock */
+   switch (qspi_num) {
+   case 0:
+   /* disable the clock gate */
+   clrbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+   /* set 50M  : (50 = 396 / 2 / 4) */
+   reg = readl(imx_ccm-cscmr1);
+   reg = ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+   reg |= ((1  MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+   (2  MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+   writel(reg, imx_ccm-cscmr1);
+
+   /* enable the clock gate */
+   setbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+   break;
+   case 1:
+   /*
+* disable the clock gate
+* QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+* disable both of them.
+*/
+   clrbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+   /* set 50M  : (50 = 396 / 2 / 4) */
+   reg = readl(imx_ccm-cs2cdr);
+   reg = ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+   reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+   MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+   writel(reg, imx_ccm-cs2cdr);
+
+   /*enable the clock gate*/
+   setbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+   break;
+   default:
+   break;
+   }
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 int enable_fec_anatop_clock(enum enet_freq freq)
 {
diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index 226a4cd..a6de5ee 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -67,5 +67,6 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
+void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 5314298..c968600 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -92,10 +92,10 @@
 #define AIPS3_END_ADDR 0x022F
 #define WEIM_ARB_BASE_ADDR  0x5000
 #define WEIM_ARB_END_ADDR   0x57FF
-#define QSPI1_ARB_BASE_ADDR 0x6000
-#define QSPI1_ARB_END_ADDR  0x6FFF
-#define QSPI2_ARB_BASE_ADDR 0x7000
-#define QSPI2_ARB_END_ADDR  0x7FFF
+#define QSPI0_AMBA_BASE0x6000
+#define QSPI0_AMBA_END 0x6FFF
+#define QSPI1_AMBA_BASE0x7000
+#define QSPI1_AMBA_END 0x7FFF
 #else
 #define SATA_ARB_BASE_ADDR  0x0220
 #define SATA_ARB_END_ADDR   0x02203FFF
@@ -262,8 +262,8 @@
 #define AUDMUX_BASE_ADDR(AIPS2_OFF_BASE_ADDR + 0x58000)
 #ifdef CONFIG_MX6SX
 #define SAI2_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x6)
-#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x6)
+#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
 #else
 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define MIPI_DSI_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x6)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index eae2f3a..e9c45de 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,7 +14,11 @@
 

[U-Boot] [PATCH v4 5/5] imx:mx6sxsabresd add qspi support

[Peng Fan]

Configure the pad setting and enable qspi clock to support qspi
flashes access.

Add QSPI related macro in configuration header file.

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v4:
 None

Changes v3:
 None

Changes v2:
 Take Fabio's suggestion, split soc code and board code into two patches.

 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +
 include/configs/mx6sxsabresd.h  | 12 +
 2 files changed, 52 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index fd8bc72..5cc58ac 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -371,6 +371,42 @@ int board_mmc_init(bd_t *bis)
return 0;
 }
 
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+   (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+   MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CLE__QSPI2_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA07__QSPI2_A_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA02__QSPI2_B_SCLK   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA05__QSPI2_B_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+   /* Set the iomux */
+   imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ARRAY_SIZE(quadspi_pads));
+
+   /* Set the clock */
+   enable_qspi_clk(1);
+
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
/* Address of boot parameters */
@@ -380,6 +416,10 @@ int board_init(void)
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info1);
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+   board_qspi_init();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 61a7a7a..469d250 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -235,6 +235,18 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
+#define CONFIG_FSL_QSPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_FSL_QSPI_LE
+#define FSL_QSPI_FLASH_SIZESZ_16M
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+
 #define CONFIG_ENV_OFFSET  (6 * SZ_64K)
 #define CONFIG_ENV_SIZESZ_8K
 #define CONFIG_ENV_IS_IN_MMC
-- 
1.8.4


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 08/22] x86: video: Add debug option to time the BIOS copy

[Bin Meng]

On Sun, Dec 28, 2014 at 10:20 AM, Simon Glass s...@chromium.org wrote:
 This can be very slow - typically 80ms even on a fast machine since it uses
 the SPI flash to read the data. Add an option to display the time taken.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

  drivers/pci/pci_rom.c | 3 +++
  1 file changed, 3 insertions(+)

 diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
 index 9808bb3..5ba315b 100644
 --- a/drivers/pci/pci_rom.c
 +++ b/drivers/pci/pci_rom.c
 @@ -156,6 +156,8 @@ int pci_rom_load(uint16_t class, struct pci_rom_header 
 *rom_header,

 target = (void *)PCI_VGA_RAM_IMAGE_START;
 if (target != rom_header) {
 +   ulong start = get_timer(0);
 +
 debug(Copying VGA ROM Image from %p to %p, 0x%x bytes\n,
   rom_header, target, rom_size);
 memcpy(target, rom_header, rom_size);
 @@ -163,6 +165,7 @@ int pci_rom_load(uint16_t class, struct pci_rom_header 
 *rom_header,
 printf(VGA ROM copy failed\n);
 return -EFAULT;
 }
 +   debug(Copy took %lums\n, get_timer(start));
 }
 *ram_headerp = target;

 --

Reviewed-by: Bin Meng bmeng...@gmail.com
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/2] arm:mx6sx add QSPI support

[Peng Fan]

Hi,

On 12/30/2014 9:19 PM, Fabio Estevam wrote:

On Tue, Dec 30, 2014 at 11:16 AM, Jagan Teki jagannadh.t...@gmail.com wrote:


Please rebase and send the patches again, I have some issues while applying.
I will pick these on my tree.


Peng, please rebase and resend the series. Thanks


After rebasing, I sent a v4 patch set. Please review.

Thanks,
Peng Fan.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 09/22] x86: ivybridge: Only run the Video BIOS when video is enabled

[Bin Meng]

Hi Simon,

On Sun, Dec 28, 2014 at 10:20 AM, Simon Glass s...@chromium.org wrote:
 This takes about about 700ms on link when running natively and 900ms when
 running using the emulator. It is a waste of time if video is not enabled,
 so don't bother running the video BIOS in that case.

 We could add a command to run the video BIOS later when needed, but this is
 not considered at present.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

  arch/x86/cpu/ivybridge/gma.c | 17 -
  1 file changed, 16 insertions(+), 1 deletion(-)

 diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
 index 3d7f740..125021b 100644
 --- a/arch/x86/cpu/ivybridge/gma.c
 +++ b/arch/x86/cpu/ivybridge/gma.c
 @@ -15,6 +15,13 @@
  #include asm/pci.h
  #include asm/arch/pch.h
  #include asm/arch/sandybridge.h
 +#include linux/kconfig.h
 +
 +#ifdef CONFIG_VIDEO
 +#define RUN_VIDEO_BIOS 1
 +#else
 +#define RUN_VIDEO_BIOS 1

Intentional? Should this be 0?

 +#endif

  struct gt_powermeter {
 u16 reg;
 @@ -745,7 +752,15 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller 
 *hose,
 if (ret)
 return ret;

 -   ret = pci_run_vga_bios(dev, int15_handler, false);
 +   /*
 +* TODO: Change to IS_ENABLED(CONFIG_VIDEO) when Kconfig supports
 +* CONFIG_VIDEO.
 +*/

Or maybe just simply do this? The if (RUN_VIDEO_BIOS) looks strange.

#ifdef CONFIG_VIDEO
   start = get_timer(0);
   ret = pci_run_vga_bios(dev, int15_handler, false);
   debug(BIOS ran in %lums\n, get_timer(start));
#endif

 +   if (RUN_VIDEO_BIOS) {
 +   start = get_timer(0);
 +   ret = pci_run_vga_bios(dev, int15_handler, false);
 +   debug(BIOS ran in %lums\n, get_timer(start));
 +   }

 /* Post VBIOS init */
 ret = gma_pm_init_post_vbios(gtt_bar, blob, node);
 --

Regards,
Bin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 12/22] x86: pci: Display vesa modes in hex

[Bin Meng]

On Sun, Dec 28, 2014 at 10:20 AM, Simon Glass s...@chromium.org wrote:
 The hex value is more commonly understood, so use that instead of decimal.
 Add a 0x prefix to avoid confusion.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

  drivers/pci/pci_rom.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

 diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
 index 5ba315b..7d25cc9 100644
 --- a/drivers/pci/pci_rom.c
 +++ b/drivers/pci/pci_rom.c
 @@ -247,7 +247,7 @@ int pci_run_vga_bios(pci_dev_t dev, int 
 (*int15_handler)(void), bool emulate)
 defined(CONFIG_FRAMEBUFFER_VESA_MODE)
 vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
  #endif
 -   debug(Selected vesa mode %d\b, vesa_mode);
 +   debug(Selected vesa mode %#x\n, vesa_mode);
 if (emulate) {
  #ifdef CONFIG_BIOSEMU
 BE_VGAInfo *info;
 @@ -275,7 +275,7 @@ int pci_run_vga_bios(pci_dev_t dev, int 
 (*int15_handler)(void), bool emulate)
 return -ENOSYS;
  #endif
 }
 -   debug(Final vesa mode %d\n, mode_info.video_mode);
 +   debug(Final vesa mode %#x\n, mode_info.video_mode);

 return 0;
  }
 --

Reviewed-by: Bin Meng bmeng...@gmail.com
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] Fwd: coreboot uboot qemu x86

[Ajoy Das]

-- Forwarded message --
From: Simon Glass s...@chromium.org
Date: Wed, Dec 31, 2014 at 2:13 AM
Subject: Re: [U-Boot] coreboot uboot qemu x86
To: Ajoy Das dasajo...@gmail.com
Cc: U-Boot Mailing List u-boot@lists.denx.de


Hi Ajoy,

On 30 December 2014 at 12:44, Ajoy Das dasajo...@gmail.com wrote:

 -- Forwarded message --
 From: Ajoy Das dasajo...@gmail.com
 Date: Tue, Dec 30, 2014 at 1:40 PM
 Subject: Re: [U-Boot] coreboot uboot qemu x86
 To: U-Boot Mailing List u-boot@lists.denx.de


 Hi Simon

 Can i do a gdb on u-boot startup on the coreboot environment.
 means i want to stop at _start in uboot and connect to gdb.

 Thanks
 Ajoy

 On Tue, Dec 30, 2014 at 11:15 AM, Ajoy Das dasajo...@gmail.com wrote:

 I tried changing the boot rom size to 2MB.
 But with no effect

 coreboot.rom: 2048 kB, bootblocksize 944, romsize 2097152, offset 0x0
 alignment: 64 bytes, architecture: x86

 Name   Offset Type Size
 cmos_layout.bin0x0cmos_layout  1160
 fallback/romstage  0x4c0  stage17960
 fallback/ramstage  0x4b40 stage56190
 config 0x12700raw  2990
 revision   0x13300raw  692
 (empty)0x13600null 2016728
 HOSTCC cbfstool/rmodtool.o

 Thanks
 Ajoy



 On Tue, Dec 30, 2014 at 4:17 AM, Simon Glass s...@chromium.org wrote:

 Hi Ajoy,

  On Mon, Dec 29, 2014 at 9:28 PM, Simon Glass s...@chromium.org wrote:
 
  Hi Ajoy,
 
 
   On Mon, Dec 29, 2014 at 7:36 PM, Simon Glass s...@chromium.org
   wrote:
  
   Hi,
  
   On 28 December 2014 at 21:38, Ajoy Das dasajo...@gmail.com
wrote:
Hi
   
Need Help
   
I want to run U-BOOT as coreboot payload on QEMU platform
   
I am on uboot-x86 git
   
Compiled U-BOOT with make coreboot-x86_defconfig and make all
   
Running qemu with
qemu-system-i386 -bios ../coreboot/build/coreboot.rom -hda
disk.img
-nographic -m 1g
   
But The system crashes with the following message
   
qemu: fatal: Trying to execute code outside RAM or ROM at
0x5e2a36c2
   
Loading Segment: addr: 0x0111 memsz:
0x000588e8
filesz:
0x000252eb
lb: [0x0010, 0x0012b030)
Post relocation: addr: 0x0111 memsz:
0x000588e8
filesz:
0x000252eb
using LZMA
[ 0x0111, 011688e8, 0x011688e8) - fffd2770
dest 0111, end 011688e8, bouncebuffer 3ff77000
Loaded segments
Jumping to boot code at 01110015
CPU0: stack: 00126000 - 00127000, lowest used address 00126b8c,
stack
used:
1140 bytes
entry= 0x01110015
lb_start = 0x0010
lb_size  = 0x0002b030
buffer   = 0x3ff77000
qemu: fatal: Trying to execute code outside RAM or ROM at
0x5e2a36c2
   
EAX=000a EBX=000186a0 ECX=01145d15 EDX=19203eb0
ESI= EDI= EBP=01145f6c ESP=01145f54
EIP=5e2a36c2 EFL=0002 [---] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0018   00cf9300 DPL=0 DS   [-WA]
CS =0010   00cf9b00 DPL=0 CS32 [-RA]
SS =0018   00cf9300 DPL=0 DS   [-WA]
DS =0018   00cf9300 DPL=0 DS   [-WA]
FS =0020 19203f5c  00cf9300 DPL=0 DS   [-WA]
GS =0018   00cf9300 DPL=0 DS   [-WA]
LDT=   8200 DPL=0 LDT
TR =   8b00 DPL=0 TSS32-busy
GDT= 19203e60 0047
IDT=  
CR0=6033 CR2= CR3= CR4=
DR0= DR1= DR2= DR3=
DR6=0ff0 DR7=0400
CCS=0218 CCD=01145f50 CCO=ADDL
EFER=
FCW=037f FSW= [ST=0] FTW=00 MXCSR=1f80
FPR0=  FPR1= 
FPR2=  FPR3= 
FPR4=  FPR5= 
FPR6=  FPR7= 
XMM00=
XMM01=
XMM02=
XMM03=
XMM04=
XMM05=
XMM06=
XMM07=
Aborted (core dumped)
   
qemu-system-i386 --version
QEMU emulator version 1.0 (qemu-kvm-1.0), Copyright (c)
2003-2008
Fabrice
Bellard
   
Is QEMU not supported for coreboot and u-boot
  
   I'm not sure it's been tried but there's no reason why it should
   work.
   It seems to be crashing in U-Boot before there is any serial
   output.
   Did you put u-boot-dtb.bin as the payload?

  On 29 December 2014 at 07:34, Ajoy Das dasajo...@gmail.com wrote:
   Hi Simon
  
   Thanks for your reply
  
   I have added 

Re: [U-Boot] [PATCH 14/22] x86: Add support for MTRRs

[Bin Meng]

Hi Simon,

On Sun, Dec 28, 2014 at 10:20 AM, Simon Glass s...@chromium.org wrote:
 Memory Type Range Registers are used to tell the CPU whether memory is
 cacheable and if so the cache write mode to use.

 Clean up the existing header file to follow style, and remove the unneeded
 code.

 These can speed up booting so should be supported. Add these to global_data
 so they can be requested while booting. We will apply the changes during
 relocation (in a later commit).

 Signed-off-by: Simon Glass s...@chromium.org
 ---

  arch/x86/cpu/Makefile  |   1 +
  arch/x86/cpu/coreboot/coreboot.c   |  22 +++--
  arch/x86/cpu/ivybridge/car.S   |  12 +--
  arch/x86/cpu/mtrr.c|  81 ++
  arch/x86/include/asm/global_data.h |  15 
  arch/x86/include/asm/mtrr.h| 163 
 +
  6 files changed, 186 insertions(+), 108 deletions(-)
  create mode 100644 arch/x86/cpu/mtrr.c

 diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
 index 5033d2b..62e43c0 100644
 --- a/arch/x86/cpu/Makefile
 +++ b/arch/x86/cpu/Makefile
 @@ -17,5 +17,6 @@ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
  obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
  obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
  obj-y += lapic.o
 +obj-y += mtrr.o
  obj-$(CONFIG_PCI) += pci.o
  obj-y += turbo.o
 diff --git a/arch/x86/cpu/coreboot/coreboot.c 
 b/arch/x86/cpu/coreboot/coreboot.c
 index cfacc05..6d06d5a 100644
 --- a/arch/x86/cpu/coreboot/coreboot.c
 +++ b/arch/x86/cpu/coreboot/coreboot.c
 @@ -15,6 +15,7 @@
  #include asm/cache.h
  #include asm/cpu.h
  #include asm/io.h
 +#include asm/mtrr.h
  #include asm/arch/tables.h
  #include asm/arch/sysinfo.h
  #include asm/arch/timestamp.h
 @@ -64,11 +65,6 @@ int board_eth_init(bd_t *bis)
 return pci_eth_init(bis);
  }

 -#define MTRR_TYPE_WP  5
 -#define MTRRcap_MSR   0xfe
 -#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 -#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 -
  void board_final_cleanup(void)
  {
 /* Un-cache the ROM so the kernel has one
 @@ -77,15 +73,17 @@ void board_final_cleanup(void)
  * Coreboot should have assigned this to the
  * top available variable MTRR.
  */
 -   u8 top_mtrr = (native_read_msr(MTRRcap_MSR)  0xff) - 1;
 -   u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr))  0xff;
 +   u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR)  0xff) - 1;
 +   u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr))  0xff;

 /* Make sure this MTRR is the correct Write-Protected type */
 -   if (top_type == MTRR_TYPE_WP) {
 -   disable_caches();
 -   wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
 -   wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
 -   enable_caches();
 +   if (top_type == MTRR_TYPE_WRPROT) {
 +   struct mtrr_state state;
 +
 +   mtrr_open(state);
 +   wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
 +   wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
 +   mtrr_close(state);
 }

 /* Issue SMI to Coreboot to lock down ME and registers */
 diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S
 index dca68e4..72b22ea 100644
 --- a/arch/x86/cpu/ivybridge/car.S
 +++ b/arch/x86/cpu/ivybridge/car.S
 @@ -61,7 +61,7 @@ clear_mtrrs:

 post_code(POST_CAR_MTRR)
 /* Configure the default memory type to uncacheable */
 -   movl$MTRRdefType_MSR, %ecx
 +   movl$MTRR_DEF_TYPE_MSR, %ecx
 rdmsr
 andl$(~0x0cff), %eax
 wrmsr
 @@ -76,16 +76,16 @@ clear_mtrrs:
 post_code(POST_CAR_BASE_ADDRESS)
 /* Set Cache-as-RAM mask */
 movl$(MTRR_PHYS_MASK_MSR(0)), %ecx
 -   movl$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
 +   movl$(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
 movl$CPU_PHYSMASK_HI, %edx
 wrmsr

 post_code(POST_CAR_MASK)

 /* Enable MTRR */
 -   movl$MTRRdefType_MSR, %ecx
 +   movl$MTRR_DEF_TYPE_MSR, %ecx
 rdmsr
 -   orl $MTRRdefTypeEn, %eax
 +   orl $MTRR_DEF_TYPE_EN, %eax
 wrmsr

 /* Enable cache (CR0.CD = 0, CR0.NW = 0) */
 @@ -130,7 +130,7 @@ clear_mtrrs:

 movl$MTRR_PHYS_MASK_MSR(1), %ecx
 movl$CPU_PHYSMASK_HI, %edx
 -   movl$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 +   movl$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
 wrmsr

 post_code(POST_CAR_ROM_CACHE)
 @@ -141,7 +141,7 @@ clear_mtrrs:
 xorl%edx, %edx
 wrmsr
 movl$MTRR_PHYS_MASK_MSR(2), %ecx
 -   movl$(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
 +   movl$(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
 movl$CPU_PHYSMASK_HI, %edx
 wrmsr
  #endif
 diff --git 

Re: [U-Boot] [PATCH] imx:mx6slevk add spi nor boot support

[Peng Fan]

Hi Jagan,

On 12/30/2014 8:38 PM, Jagan Teki wrote:

On 30 December 2014 at 08:44, Peng Fan peng@freescale.com wrote:

Add spi nor boot support for mx6slevk board.

Signed-off-by: Peng Fan peng@freescale.com
---
  board/freescale/mx6slevk/MAINTAINERS |  1 +
  configs/mx6slevk_spinor_defconfig|  3 +++
  include/configs/mx6slevk.h   | 13 -
  3 files changed, 16 insertions(+), 1 deletion(-)
  create mode 100644 configs/mx6slevk_spinor_defconfig

diff --git a/board/freescale/mx6slevk/MAINTAINERS 
b/board/freescale/mx6slevk/MAINTAINERS
index 660af91..18d31a8 100644
--- a/board/freescale/mx6slevk/MAINTAINERS
+++ b/board/freescale/mx6slevk/MAINTAINERS
@@ -4,3 +4,4 @@ S:  Maintained
  F: board/freescale/mx6slevk/
  F: include/configs/mx6slevk.h
  F: configs/mx6slevk_defconfig
+F: configs/mx6slevk_spinor_defconfig
diff --git a/configs/mx6slevk_spinor_defconfig 
b/configs/mx6slevk_spinor_defconfig
new file mode 100644
index 000..93efe73
--- /dev/null
+++ b/configs/mx6slevk_spinor_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR
+CONFIG_ARM=y
+CONFIG_TARGET_MX6SLEVK=y
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index e3e7f76..e6c4130 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -187,9 +187,20 @@
  /* FLASH and environment organization */
  #define CONFIG_SYS_NO_FLASH

-#define CONFIG_ENV_OFFSET  (6 * SZ_64K)
  #define CONFIG_ENV_SIZESZ_8K
+
+#if defined CONFIG_SYS_BOOT_SPINOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET   (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE(64 * 1024)
+#define CONFIG_ENV_SPI_BUS  CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS   CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED


If you need default values may be you couldn't define these so-that
common/env_sf.c
will take the defaults for undefs - please check.



Default values are defined in mx6slevk.h

#define CONFIG_SF_DEFAULT_BUS  0
#define CONFIG_SF_DEFAULT_CS   0
#define CONFIG_SF_DEFAULT_SPEED 2000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0

In env_sf.c
I did not see any undefs, there is only a piece of code like:
#ifndef CONFIG_ENV_SPI_BUS
#define CONFIG_ENV_SPI_BUS 0
#endif


+#else
+#define CONFIG_ENV_OFFSET  (6 * SZ_64K)
  #define CONFIG_ENV_IS_IN_MMC
+#endif

  #define CONFIG_OF_LIBFDT
  #define CONFIG_CMD_BOOTZ
--
1.8.4



thanks!


Regards,
Peng Fan
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 15/22] x86: ivybridge: Set up an MTRR for the video frame buffer

[Bin Meng]

Hi Simon,

On Sun, Dec 28, 2014 at 10:20 AM, Simon Glass s...@chromium.org wrote:
 Set the frame buffer to write-combining. This makes it faster, although for
 scrolling write-through is even faster for U-Boot.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

  arch/x86/cpu/ivybridge/gma.c | 8 
  1 file changed, 8 insertions(+)

 diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
 index 125021b..03b2ebd 100644
 --- a/arch/x86/cpu/ivybridge/gma.c
 +++ b/arch/x86/cpu/ivybridge/gma.c
 @@ -12,6 +12,7 @@
  #include fdtdec.h
  #include pci_rom.h
  #include asm/io.h
 +#include asm/mtrr.h
  #include asm/pci.h
  #include asm/arch/pch.h
  #include asm/arch/sandybridge.h
 @@ -738,6 +739,8 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller 
 *hose,
const void *blob, int node)
  {
 void *gtt_bar;
 +   ulong start;
 +   ulong base;
 u32 reg32;
 int ret;

 @@ -746,6 +749,11 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller 
 *hose,
 reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
 pci_write_config32(dev, PCI_COMMAND, reg32);

 +   /* Use write-combining for the graphics memory, 256MB */
 +   base = pci_read_bar32(hose, dev, 2);
 +   mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256  20);

To make the codes more generic, should we decode the memory size via
bar instead of hardcoded 256MB?

 +   mtrr_commit(true);
 +
 gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
 debug(GT bar %p\n, gtt_bar);
 ret = gma_pm_init_pre_vbios(gtt_bar);
 --

Regards,
Bin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] Fwd: coreboot uboot qemu x86

[Ajoy Das]

-- Forwarded message --
From: Ajoy Das dasajo...@gmail.com
Date: Wed, Dec 31, 2014 at 8:51 AM
Subject: Fwd: [U-Boot] coreboot uboot qemu x86
To: U-Boot Mailing List u-boot@lists.denx.de, Simon Glass 
s...@chromium.org



-- Forwarded message --
From: Simon Glass s...@chromium.org
Date: Wed, Dec 31, 2014 at 2:13 AM
Subject: Re: [U-Boot] coreboot uboot qemu x86
To: Ajoy Das dasajo...@gmail.com
Cc: U-Boot Mailing List u-boot@lists.denx.de


Hi Ajoy,

On 30 December 2014 at 12:44, Ajoy Das dasajo...@gmail.com wrote:

 -- Forwarded message --
 From: Ajoy Das dasajo...@gmail.com
 Date: Tue, Dec 30, 2014 at 1:40 PM
 Subject: Re: [U-Boot] coreboot uboot qemu x86
 To: U-Boot Mailing List u-boot@lists.denx.de


 Hi Simon

 Can i do a gdb on u-boot startup on the coreboot environment.
 means i want to stop at _start in uboot and connect to gdb.

 Thanks
 Ajoy

 On Tue, Dec 30, 2014 at 11:15 AM, Ajoy Das dasajo...@gmail.com wrote:

 I tried changing the boot rom size to 2MB.
 But with no effect

 coreboot.rom: 2048 kB, bootblocksize 944, romsize 2097152, offset 0x0
 alignment: 64 bytes, architecture: x86

 Name   Offset Type Size
 cmos_layout.bin0x0cmos_layout  1160
 fallback/romstage  0x4c0  stage17960
 fallback/ramstage  0x4b40 stage56190
 config 0x12700raw  2990
 revision   0x13300raw  692
 (empty)0x13600null 2016728
 HOSTCC cbfstool/rmodtool.o

 Thanks
 Ajoy



 On Tue, Dec 30, 2014 at 4:17 AM, Simon Glass s...@chromium.org wrote:

 Hi Ajoy,

  On Mon, Dec 29, 2014 at 9:28 PM, Simon Glass s...@chromium.org wrote:
 
  Hi Ajoy,
 
 
   On Mon, Dec 29, 2014 at 7:36 PM, Simon Glass s...@chromium.org
   wrote:
  
   Hi,
  
   On 28 December 2014 at 21:38, Ajoy Das dasajo...@gmail.com
wrote:
Hi
   
Need Help
   
I want to run U-BOOT as coreboot payload on QEMU platform
   
I am on uboot-x86 git
   
Compiled U-BOOT with make coreboot-x86_defconfig and make all
   
Running qemu with
qemu-system-i386 -bios ../coreboot/build/coreboot.rom -hda
disk.img
-nographic -m 1g
   
But The system crashes with the following message
   
qemu: fatal: Trying to execute code outside RAM or ROM at
0x5e2a36c2
   
Loading Segment: addr: 0x0111 memsz:
0x000588e8
filesz:
0x000252eb
lb: [0x0010, 0x0012b030)
Post relocation: addr: 0x0111 memsz:
0x000588e8
filesz:
0x000252eb
using LZMA
[ 0x0111, 011688e8, 0x011688e8) - fffd2770
dest 0111, end 011688e8, bouncebuffer 3ff77000
Loaded segments
Jumping to boot code at 01110015
CPU0: stack: 00126000 - 00127000, lowest used address 00126b8c,
stack
used:
1140 bytes
entry= 0x01110015
lb_start = 0x0010
lb_size  = 0x0002b030
buffer   = 0x3ff77000
qemu: fatal: Trying to execute code outside RAM or ROM at
0x5e2a36c2
   
EAX=000a EBX=000186a0 ECX=01145d15 EDX=19203eb0
ESI= EDI= EBP=01145f6c ESP=01145f54
EIP=5e2a36c2 EFL=0002 [---] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0018   00cf9300 DPL=0 DS   [-WA]
CS =0010   00cf9b00 DPL=0 CS32 [-RA]
SS =0018   00cf9300 DPL=0 DS   [-WA]
DS =0018   00cf9300 DPL=0 DS   [-WA]
FS =0020 19203f5c  00cf9300 DPL=0 DS   [-WA]
GS =0018   00cf9300 DPL=0 DS   [-WA]
LDT=   8200 DPL=0 LDT
TR =   8b00 DPL=0 TSS32-busy
GDT= 19203e60 0047
IDT=  
CR0=6033 CR2= CR3= CR4=
DR0= DR1= DR2= DR3=
DR6=0ff0 DR7=0400
CCS=0218 CCD=01145f50 CCO=ADDL
EFER=
FCW=037f FSW= [ST=0] FTW=00 MXCSR=1f80
FPR0=  FPR1= 
FPR2=  FPR3= 
FPR4=  FPR5= 
FPR6=  FPR7= 
XMM00=
XMM01=
XMM02=
XMM03=
XMM04=
XMM05=
XMM06=
XMM07=
Aborted (core dumped)
   
qemu-system-i386 --version
QEMU emulator version 1.0 (qemu-kvm-1.0), Copyright (c)
2003-2008
Fabrice
Bellard
   
Is QEMU not supported for coreboot and u-boot
  
   I'm not sure it's been tried but there's no reason why it should
   work.
   It seems to