https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/76901
>From ff9b72bdb5442a037d4325619de66e25ad211586 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 1 Jan 2024 15:13:38 +0800
Subject: [PATCH] [X86][BF16][WIP] Try to use `f16` for lowering
---
phoebewang wrote:
Ping @RKSimon
https://github.com/llvm/llvm-project/pull/75156
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phoebewang wrote:
> Making avx512f the only case where avx512vl can be disabled doesn't seem like
> too much of a stretch to me - we'd be merely making all avx512 extension
> features depend on avx512vl.
Agreed.
https://github.com/llvm/llvm-project/pull/75580
phoebewang wrote:
> I also think we need a policy regarding what test coverage we need for
> various avx512 features (when should we assume avx512vl etc.)
Considering the new evolution in AVX10, we should switch testing model from
`avx512xxx ± avx512vl` to `avx512xxx + avx512vl ±
evex512`.
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm -target-feature +sse2 < %s
| FileCheck %s --check-prefixes=CHECK
phoebewang wrote:
Yes, e.g, `llvm/test/CodeGen/X86/{soft-fp,x87}.ll`, though I doubt if they can
work in reality since they
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm -target-feature +sse2 < %s
| FileCheck %s --check-prefixes=CHECK
phoebewang wrote:
I decided not to report error for `-sse` after investigating the current
diagnosis machinism.
We didn't
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/75156
>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/2] [X86] Add ABI handling for fp128
Fixes #74601
---
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/75992
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phoebewang wrote:
Thanks @MaxEW707 ! I don't have other comments now. Do you need help to merge
it for you?
https://github.com/llvm/llvm-project/pull/75992
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@@ -580,8 +580,7 @@ _storebe_i64(void * __P, long long __D) {
#include
#endif
-/* Some intrinsics inside adxintrin.h are available only on processors with
ADX,
- * whereas others are also available at all times. */
phoebewang wrote:
I think comment is
@@ -580,8 +580,7 @@ _storebe_i64(void * __P, long long __D) {
#include
#endif
-/* Some intrinsics inside adxintrin.h are available only on processors with
ADX,
- * whereas others are also available at all times. */
phoebewang wrote:
Sorry, just noticed
@@ -92,136 +92,11 @@ __INLINE unsigned char
}
#endif
-/* Intrinsics that are also available if __ADX__ is undefined. */
-
-/// Adds unsigned 32-bit integers \a __x and \a __y, plus 0 or 1 as indicated
-///by the carry flag \a __cf. Stores the unsigned 32-bit sum in the
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/75992
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@@ -0,0 +1,160 @@
+/*=== adxintrin.h - ADX intrinsics -===
phoebewang wrote:
adx -> adc
https://github.com/llvm/llvm-project/pull/75992
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@@ -0,0 +1,160 @@
+/*=== adxintrin.h - ADX intrinsics -===
phoebewang wrote:
adx -> adc
https://github.com/llvm/llvm-project/pull/75711
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phoebewang wrote:
> Can you give me a better idea of the stages you intend to follow with this.
> The patch title suggests removing all KNL/KNM handling but the patch itself
> looks to be just about the KNL/KNM specific features.
>
> Removing the (incomplete) KNL/KNM specific features
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/75571
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phoebewang wrote:
One more reason I can think of is with KNL/KNM removal, we can simplify
supporting widen 128/256-bit vector to 512-bit without AVX512VL feature since
all reset targets support AVX512VL. The test cases can be simplified too.
https://github.com/llvm/llvm-project/pull/75580
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/75571
>From 2e31cbd1a0b5b9c1689f664c6c261cabbc656f2a Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Fri, 15 Dec 2023 16:11:02 +0800
Subject: [PATCH 1/2] [X86][AVX10] Allow 64-bit mask register used without
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm -target-feature +sse2 < %s
| FileCheck %s --check-prefixes=CHECK
phoebewang wrote:
This patch only changes for 64-bit ABI, non-SSE is not a valid case for 64-bit.
OTOH, -sse just generate
phoebewang wrote:
Can this solve https://github.com/llvm/llvm-project/issues/68566 too?
https://github.com/llvm/llvm-project/pull/75448
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@@ -8251,6 +8251,25 @@ static void HandleVectorSizeAttr(QualType ,
const ParsedAttr ,
return;
}
+ // check -mgeneral-regs-only is specified
+ const TargetInfo = S.getASTContext().getTargetInfo();
+ llvm::Triple::ArchType arch = targetInfo.getTriple().getArch();
+
@@ -717,8 +717,15 @@ bool TargetInfo::validateOutputConstraint(ConstraintInfo
) const {
if (*Name != '=' && *Name != '+')
return false;
- if (*Name == '+')
+ if (*Name == '+') {
Info.setIsReadWrite();
+// To align with GCC asm: "=f" is not allowed, the
+
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/75156
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/75156
Fixes #74601
>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH] [X86] Add ABI handling for fp128
Fixes #74601
Author: Phoebe Wang
Date: 2023-12-05T15:58:55+08:00
New Revision: 0ca80eb5e814a6d061556888c9c9fbd04f054a80
URL:
https://github.com/llvm/llvm-project/commit/0ca80eb5e814a6d061556888c9c9fbd04f054a80
DIFF:
https://github.com/llvm/llvm-project/commit/0ca80eb5e814a6d061556888c9c9fbd04f054a80.diff
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/68618
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/74199
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@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable
@@ -422,3 +422,28 @@
// RUN: touch %t.o
// RUN: %clang -fdriver-only -Werror --target=x86_64-pc-linux-gnu
-mharden-sls=all %t.o -o /dev/null 2>&1 | count 0
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf %s -### -o %t.o 2>&1 |
FileCheck -check-prefix=APXF %s
@@ -422,3 +422,28 @@
// RUN: touch %t.o
// RUN: %clang -fdriver-only -Werror --target=x86_64-pc-linux-gnu
-mharden-sls=all %t.o -o /dev/null 2>&1 | count 0
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf %s -### -o %t.o 2>&1 |
FileCheck -check-prefix=APXF %s
+//
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable
Author: Phoebe Wang
Date: 2023-11-19T10:14:34+08:00
New Revision: 5237193b87721134541f228e28edfd544a9c8ac8
URL:
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8
DIFF:
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8.diff
@@ -7254,6 +7255,10 @@ static SDValue
lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp,
EVT CVT = Ld.getValueType();
assert(!CVT.isVector() && "Must not broadcast a vector type");
+// 512 bit vpbroadcastw is only available with AVX512BW
+if (ScalarSize ==
Author: Phoebe Wang
Date: 2023-11-22T21:59:30+08:00
New Revision: e5cc3da6a9077548f613eee3aacc5e7b017c81f3
URL:
https://github.com/llvm/llvm-project/commit/e5cc3da6a9077548f613eee3aacc5e7b017c81f3
DIFF:
https://github.com/llvm/llvm-project/commit/e5cc3da6a9077548f613eee3aacc5e7b017c81f3.diff
Author: Phoebe Wang
Date: 2023-11-19T10:14:34+08:00
New Revision: 5237193b87721134541f228e28edfd544a9c8ac8
URL:
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8
DIFF:
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8.diff
Author: Phoebe Wang
Date: 2023-11-14T15:39:30+08:00
New Revision: e96eddec5e8ecc0fdab377571aabe85a2ee7617e
URL:
https://github.com/llvm/llvm-project/commit/e96eddec5e8ecc0fdab377571aabe85a2ee7617e
DIFF:
https://github.com/llvm/llvm-project/commit/e96eddec5e8ecc0fdab377571aabe85a2ee7617e.diff
Author: Phoebe Wang
Date: 2023-11-14T15:34:38+08:00
New Revision: 17dd0c70c8c3183c62d184de2e91a859c36880e9
URL:
https://github.com/llvm/llvm-project/commit/17dd0c70c8c3183c62d184de2e91a859c36880e9
DIFF:
https://github.com/llvm/llvm-project/commit/17dd0c70c8c3183c62d184de2e91a859c36880e9.diff
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/72126
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/8] [X86][AVX10] Fix a bug when using -march with no-evex512
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/7] [X86][AVX10] Fix a bug when using -march with no-evex512
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/6] [X86][AVX10] Fix a bug when using -march with no-evex512
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/4] [X86][AVX10] Fix a bug when using -march with no-evex512
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/3] [X86][AVX10] Fix a bug when using -march with no-evex512
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/2] [X86][AVX10] Fix a bug when using -march with no-evex512
phoebewang wrote:
Thanks @ronlieb and @mstorsjo. Created #72126 for it.
https://github.com/llvm/llvm-project/pull/71318
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https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/72126
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/72126
failed to clear EVEX512 feature for intended intrinsics.
Fixes #72106
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject:
phoebewang wrote:
@ronlieb The reproducer can compile successfully in trunk:
https://godbolt.org/z/hvKhGq9bq
Are you using a downstream compiler? You can check if the "emmintrin.h" has the
same change as main trunk.
You can also check it through pre-compile the code:
```
$ clang++ -E
phoebewang wrote:
@ronlieb Do you have a reproducer for this problem? I just checked the
definition of both intrinsics have `no-evex512` already, so shouldn't have such
problem.
You can use -mno-evex512 as workaround for the problem anyway.
https://github.com/llvm/llvm-project/pull/71318
phoebewang wrote:
Thanks @KanRobert @e-kud
https://github.com/llvm/llvm-project/pull/71318
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/71318
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https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/71318
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phoebewang wrote:
> I'm a little bit confused, What's the expected behavior of `+avx10.1-512
> -avx10.1-256` in codegen aspect? Should we generate only instructions in the
> difference of sets? Or do we consider `avx10.1-256` as a base of
> `avx10.1-512` and if it is disabled `avx10.1-512`
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (Feature.substr(0, 7) == "+avx10.") {
- HasAVX10 = true;
- HasAVX512F = true;
- if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
- }
@@ -50,11 +50,11 @@ typedef __bf16 __m128bh __attribute__((__vector_size__(16),
__aligned__(16)));
/* Define the default attributes for the functions in this file. */
#define __DEFAULT_FN_ATTRS
\
-
@@ -15,8 +15,12 @@
#define __AVX2INTRIN_H
/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS256 __attribute__((__always_inline__, __nodebug__,
__target__("avx2"), __min_vector_width__(256)))
-#define __DEFAULT_FN_ATTRS128
@@ -119,9 +119,13 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabled(Features, F, true);
std::vector UpdatedFeaturesVec;
- bool HasEVEX512 = true;
+ std::vector UpdatedAVX10FeaturesVec;
+ int HasEVEX512 = -1;
phoebewang wrote:
I think it's
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/71318
>From d9ee6309924e7f248695cbd488afe98273432e84 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Sun, 5 Nov 2023 21:15:53 +0800
Subject: [PATCH 1/3] [X86][AVX10] Permit AVX512 options/features used together
phoebewang wrote:
Ping~
https://github.com/llvm/llvm-project/pull/71318
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/68618
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/71317
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/71318
>From d9ee6309924e7f248695cbd488afe98273432e84 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Sun, 5 Nov 2023 21:15:53 +0800
Subject: [PATCH 1/2] [X86][AVX10] Permit AVX512 options/features used together
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/71318
This patch relaxes the driver logic to permit combinations between AVX512 and
AVX10 options and makes sure we have a unified behavior between options and
features combination.
Here are rules we are
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/71317
None
>From 50fb9c29b16c26e82bbc07ae8a092f572caa73a5 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Sun, 5 Nov 2023 21:50:44 +0800
Subject: [PATCH] [X86] Add a EVEX256 macro to match with GCC and MSVC
---
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/67278
>From eaf36c8cac3fe6d9bb3dcb1387b0b4f1febf5ef7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 25 Sep 2023 10:31:37 +0800
Subject: [PATCH 1/2] [X86][RFC] Support AVX10 options
AVX10 Architecture
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/67278
>From eaf36c8cac3fe6d9bb3dcb1387b0b4f1febf5ef7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 25 Sep 2023 10:31:37 +0800
Subject: [PATCH 1/2] [X86][RFC] Support AVX10 options
AVX10 Architecture
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/67278
>From eaf36c8cac3fe6d9bb3dcb1387b0b4f1febf5ef7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 25 Sep 2023 10:31:37 +0800
Subject: [PATCH 1/2] [X86][RFC] Support AVX10 options
AVX10 Architecture
@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (!HasAVX512F && Feature.substr(0, 7) == "+avx512")
+if (Feature.substr(0, 7) == "+avx10.") {
+ HasAVX10 = true;
HasAVX512F = true;
-if (HasAVX512F && Feature ==
@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (!HasAVX512F && Feature.substr(0, 7) == "+avx512")
+if (Feature.substr(0, 7) == "+avx10.") {
+ HasAVX10 = true;
HasAVX512F = true;
-if (HasAVX512F && Feature ==
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/69277
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phoebewang wrote:
Ping~
https://github.com/llvm/llvm-project/pull/67278
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phoebewang wrote:
Ping~
https://github.com/llvm/llvm-project/pull/67278
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/67278
>From eaf36c8cac3fe6d9bb3dcb1387b0b4f1febf5ef7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 25 Sep 2023 10:31:37 +0800
Subject: [PATCH 1/2] [X86][RFC] Support AVX10 options
AVX10 Architecture
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/67278
>From eaf36c8cac3fe6d9bb3dcb1387b0b4f1febf5ef7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 25 Sep 2023 10:31:37 +0800
Subject: [PATCH 1/2] [X86][RFC] Support AVX10 options
AVX10 Architecture
https://github.com/phoebewang approved this pull request.
https://github.com/llvm/llvm-project/pull/68944
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@@ -325,6 +325,8 @@ def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk",
"HasTSXLDTRK", "true",
"Support TSXLDTRK instructions">;
def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true",
"Has
@@ -0,0 +1,26 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s
--check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 |
FileCheck %s --check-prefixes=INTEL
+
+# ATT: urdmsr $123, %r9
+# INTEL: urdmsr r9, 123
@@ -241,6 +241,7 @@ X86_FEATURE (SM3, "sm3")
X86_FEATURE (SM4, "sm4")
X86_FEATURE (AVXVNNIINT16,"avxvnniint16")
X86_FEATURE (EVEX512, "evex512")
+X86_FEATURE (USERMSR,"usermsr")
@@ -922,8 +922,6 @@ endif()
include(HandleLLVMOptions)
-##
-
phoebewang wrote:
Unrelated change
https://github.com/llvm/llvm-project/pull/68944
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@@ -20,6 +20,11 @@
#include
#endif
+#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||
\
+defined(__UINTR__)
phoebewang wrote:
__USERMSR__
https://github.com/llvm/llvm-project/pull/68944
https://github.com/phoebewang approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/68517
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phoebewang wrote:
I think it's ok to merge.
https://github.com/llvm/llvm-project/pull/68419
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https://github.com/phoebewang approved this pull request.
Good catch, thanks!
https://github.com/llvm/llvm-project/pull/68419
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/67278
>From eaf36c8cac3fe6d9bb3dcb1387b0b4f1febf5ef7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 25 Sep 2023 10:31:37 +0800
Subject: [PATCH 1/2] [X86][RFC] Support AVX10 options
AVX10 Architecture
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/67410
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@@ -4742,6 +4742,125 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_castsi128_pd(__m128i __a) {
return (__m128d)__a;
}
+/// Compares each of the corresponding double-precision values of two
+///128-bit vectors of [2 x double], using the operation specified by the
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/67400
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/67400
None
>From 08a386acd5e14a7af905ae3ea819e5d29d84e4c1 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 26 Sep 2023 16:07:17 +0800
Subject: [PATCH] [X86][FP16] Add missing handling for FP16 constrained cmp
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/67278
>From eaf36c8cac3fe6d9bb3dcb1387b0b4f1febf5ef7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 25 Sep 2023 10:31:37 +0800
Subject: [PATCH 1/2] [X86][RFC] Support AVX10 options
AVX10 Architecture
https://github.com/phoebewang reopened
https://github.com/llvm/llvm-project/pull/67278
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https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/67278
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https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/67278
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/67278
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/67278
- Reapply "[AArch64] Merge LDRSWpre-LD[U]RSW pair into LDPSWpre"
- Revert "[ORC][LLJIT] Move enable-debugger-support utility out of
LLJITBuilder."
- [gn build] Port e5f169f91a86
- [ConstraintElimination]
https://github.com/phoebewang approved this pull request.
LGTM. I didn't review Clang document before, but I'll give approval since I
don't find anything blocking it.
https://github.com/llvm/llvm-project/pull/65662
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@@ -358,6 +358,12 @@ __m128i test_mm_stream_load_si128(__m128i const *a) {
return _mm_stream_load_si128(a);
}
+__m128i test_mm_stream_load_si128_void(void const *a) {
phoebewang wrote:
`const void`?
https://github.com/llvm/llvm-project/pull/66310
@@ -2979,7 +2979,7 @@ _mm256_xor_si256(__m256i __a, __m256i __b)
///A pointer to the 32-byte aligned memory containing the vector to load.
/// \returns A 256-bit integer vector loaded from memory.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -645,7 +645,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS
_mm_mul_epi32(__m128i __V1,
/// \returns A 128-bit integer vector containing the data stored at the
///specified memory location.
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_stream_load_si128(__m128i
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