答复: [PATCH] drm/amdgpu/gmc7: simplify logic in firmware message

Reviewed-by: Jim Qu Thanks JimQu 发件人: amd-gfx 代表 Alex Deucher 发送时间: 2018年7月6日 4:46:33 收件人: amd-gfx@lists.freedesktop.org 抄送: Deucher, Alexander 主题: [PATCH] drm/amdgpu/gmc7: simplify logic in firmware message Switching the firmware paths for CIK parts

答复: [PATCH v3 2/2] drm/admgpu: Present amdgpu_task_info in VM_FAULTS.

Look good to me. there is a small typo error about title admgpu->amdgpu Acked-by: Jim Qu Thanks JimQu 发件人: amd-gfx 代表 Andrey Grodzovsky 发送时间: 2018年7月6日 3:27:00 收件人: amd-gfx@lists.freedesktop.org 抄送: Grodzovsky, Andrey; Zhou, David(ChunMing); Koenig, C

[pull] amdgpu, radeon, scheduler drm-next-4.19

Hi Dave, More features for 4.19: - Use core pcie functionality rather than duplicating our own for pcie gens and lanes - Scheduler function naming cleanups - More documentation - Reworked DC/Powerplay interfaces to improve power savings - Initial stutter mode support for RV (power feature) - Veg

[PATCH] drm/amdgpu/gmc7: simplify logic in firmware message

Switching the firmware paths for CIK parts resulted in no need for this anymore. Fixes: "drm/amdgpu: switch firmware path for CIK parts" Noticed-by: Julia Lawall Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff

Re: BUG: *ERROR* No EDID read

[0.00] Command line: BOOT_IMAGE=/vmlinuz-linuxtest root=UUID=27247597-a354-42f3-8040-caff9592a297 drm.debug=0x4 rw quiet [0.00] Kernel command line: BOOT_IMAGE=/vmlinuz-linuxtest root=UUID=27247597-a354-42f3-8040-caff9592a297 drm.debug=0x4 rw quiet [5.674793] [drm:bios_parser_ge

[PATCH v3 1/2] drm/amdgpu: Add support for logging process info in amdgpu_vm.

Add process and thread names and pids and a function to extract this info from relevant amdgpu_vm. v2: Add documentation and fix identation. v3: Add getter and setter functions for amdgpu_task_info. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 39 ++

[PATCH v3 2/2] drm/admgpu: Present amdgpu_task_info in VM_FAULTS.

Extract and present the reposnsible process and thread when VM_FAULT happens. v2: Use getter and setter functions. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

Re: [PATCH v5] drm/amdgpu: update documentation for amdgpu_drv.c

On Thu, Jul 5, 2018 at 2:30 PM, Sonny Jiang wrote: > Signed-off-by: Sonny Jiang > Acked-by: Junwei Zhang > Acked-by: Christian König A few more nits below. WIth those fixed: Reviewed-by: Alex Deucher > --- > Documentation/gpu/amdgpu.rst| 7 + > drivers/gpu/drm/amd/amdgpu/amdg

Re: Raven Ridge Ryzen 2500U hang reproduced

Suspend/resume are working fine now. There is big chance idle=nomwait fixed all hangs (from https://community.amd.com/thread/224000). Couldn't reproduce a hang since using it. CPU max. frequency is limited to 2000mhz, by firmware or linux 4.17, maybe due to overheating? It goes beyond 3hz on wind

[PATCH v2] drm/amdgpu: Verify root PD is mapped into kernel address space.

Problem: When PD/PT update made by CPU root PD was not yet mapped causing page fault. Fix: Verify root PD is mapped into CPU address space. v2: Make sure that we add the root PD to the relocated list since then it's get mapped into CPU address space bt default in amdgpu_vm_update_directories. Li

[PATCH v5] drm/amdgpu: update documentation for amdgpu_drv.c

Signed-off-by: Sonny Jiang Acked-by: Junwei Zhang Acked-by: Christian König --- Documentation/gpu/amdgpu.rst| 7 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 230 +++- 2 files changed, 230 insertions(+), 7 deletions(-) diff --git a/Documentation/gpu/amd

Re: BUG: *ERROR* No EDID read

On 2018-07-05 01:43 PM, Daniel Andersson wrote: > Well, this workaround: > > diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c > b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c > index 10a5807a7e8b..d0f5910c906c 100644 > --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c >

Re: BUG: *ERROR* No EDID read

Well, this workaround: diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 10a5807a7e8b..d0f5910c906c 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -

Re: BUG: *ERROR* No EDID read

So your vbios has table v3.1 so it should not be affected by that patch. Does reverting that patch actually fix the issue? Alex From: amd-gfx on behalf of Daniel Andersson Sent: Thursday, July 5, 2018 12:22:17 PM To: Alex Deucher Cc: amd-gfx@lists.freedeskto

Re: [PATCH] drm/amdgpu/acp: Fix slab-out-of-bounds in mfd_add_device in acp_hw_init

On Wed, Jul 4, 2018 at 4:48 AM, Mukunda,Vijendar wrote: > > > On Tuesday 03 July 2018 09:50 PM, Alex Deucher wrote: >> >> On Mon, Jul 2, 2018 at 5:48 PM, Daniel Kurtz wrote: >>> >>> Hi Alex, >>> >>> On Sun, Apr 15, 2018 at 9:48 PM Agrawal, Akshu >>> wrote: On 4/13/2018 9

Re: BUG: *ERROR* No EDID read

I have not flashed any GPU BIOS. It's not a reference Vega though, Sapphire something. Maybe they made changes? vbios is attached. // Daniel On 5 July 2018 at 15:38, Alex Deucher wrote: > On Mon, Jul 2, 2018 at 5:39 PM, Daniel Andersson wrote: >> Sure, bisecting gets me 6e65fb862064663ad3a08f9

Re: [PATCH] drm/amd/display: Use 2-factor allocator calls

On Thu, Jul 5, 2018 at 6:37 AM, Michel Dänzer wrote: > On 2018-07-04 07:27 PM, Kees Cook wrote: >> As already done treewide, switch from open-coded multiplication to >> 2-factor allocation helper. >> >> Signed-off-by: Kees Cook >> --- >> drivers/gpu/drm/amd/display/modules/color/color_gamma.c |

[pull] amdgpu drm-fixes-4.18

Hi Dave, Fixes for 4.18. Highlights: - Fix an HDMI 2.0 4k@60 regression - Hotplug fixes for PX/HG laptops - Fixes for vbios changes in vega12 - Fix a race in the user fence code - Fix a couple of misc typos The following changes since commit 4de9f38bb2cce3a4821ffb8a83d6b08f6e37d905: drm/amd/d

Re: [PATCH] drm/amd/pp: Implement get_performance_level for legacy dgpu

On Thu, Jul 5, 2018 at 10:00 AM, Rex Zhu wrote: > display can get clock info through this function. > implement this function for vega10 and old asics. > from vega12, there is no power state management. so need other > interface to notify display the clock info > > Signed-off-by: Rex Zhu Reviewe

Re: [PATCH] drm/amd/pp: Convert 10KHz to KHz as variable name

On Thu, Jul 5, 2018 at 9:59 AM, Rex Zhu wrote: > The default clock unit in powerplay is 10KHz. > > Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +- > drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 3 +-- > 2 files change

Re: [PATCH 05/10] drm/amdgpu: drop mmRLC_PG_CNTL clear

On Thu, Jul 5, 2018 at 5:09 AM, Evan Quan wrote: > This may break gfxoff support since this register will > be set by smc fw(for vega12, that's the case). > It took me a second to understand what you meant here. Might be worthwhile to clarify with something like: SMU owns this register so the dr

Re: [PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init

On Thu, Jul 5, 2018 at 11:25 AM, Huang Rui wrote: > On Thu, Jul 05, 2018 at 05:09:26PM +0800, Evan Quan wrote: >> Without this pin, the csb buffer will be filled with inconsistent >> data after S3 resume. And that will causes gfx hang on gfxoff >> exit since this csb will be executed then. >> >> C

Re: [PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init

On Thu, Jul 05, 2018 at 05:09:26PM +0800, Evan Quan wrote: > Without this pin, the csb buffer will be filled with inconsistent > data after S3 resume. And that will causes gfx hang on gfxoff > exit since this csb will be executed then. > > Change-Id: I1ae1f2eed096eaba5f601cf2a3e2650c8e583dc9 > Sig

Re: [PATCH v4] drm/amdgpu: update documentation for amdgpu_drv.c

On Thu, Jul 5, 2018 at 10:45 AM, Sonny Jiang wrote: > Signed-off-by: Sonny Jiang > Acked-by: Junwei Zhang > Acked-by: Christian König > --- > Documentation/gpu/amdgpu.rst| 7 + > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 371 > +++- > 2 files changed,

Re: [PATCH 09/10] drm/amd/powerplay: add vega12 SMU gfxoff support

On Thu, Jul 05, 2018 at 05:09:34PM +0800, Evan Quan wrote: > Export apis for enabling/disabling SMU gfxoff support. > > Change-Id: Idcea1db9f3dbe15edda1b76e1ff05435865af2a1 > Signed-off-by: Evan Quan Reviewed-by: Huang Rui > --- > .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 19 +++

Re: [PATCH 03/10] drm/amdgpu: init rlc save restore as long as the lists exist

On Thu, Jul 05, 2018 at 05:09:28PM +0800, Evan Quan wrote: > It does not have to be rlc v2_1 and pg enabled. For rlc v2_0, rlc > save restore is also needed. And pg support is definitely not a > must for rlc save restore. > > Change-Id: I85c0e3525ca7fb385c3d0b9e5abc13708c91e795 > Signed-off-by: Ev

Re: [PATCH v2] drm/amd/display: adding ycbcr420 pixel encoding for hdmi

On 2018-07-04 05:26 PM, mikita.lip...@amd.com wrote: > From: Mikita Lipski > > [why] > HDMI EDID's VSDB contains spectial timings for specifically > YCbCr 4:2:0 colour space. In those cases we need to verify > if the mode provided is one of the special ones has to use > YCbCr 4:2:0 pixel encoding

Re: [PATCH v2] drm/amd/display: add a check for display depth validity

On 2018-07-04 05:27 PM, mikita.lip...@amd.com wrote: > From: Mikita Lipski > > [why] > HDMI 2.0 fails to validate 4K@60 timing with 10 bpc > [how] > Adding a helper function that would verify if the display depth > assigned would pass a bandwidth validation. > Drop the display depth by one level

Re: [PATCH 05/10] drm/amdgpu: drop mmRLC_PG_CNTL clear

On Thu, Jul 05, 2018 at 05:09:30PM +0800, Evan Quan wrote: > This may break gfxoff support since this register will > be set by smc fw(for vega12, that's the case). > > Change-Id: Id3108c63634a2f941289021bfbd78588c0f6c4d6 > Signed-off-by: Evan Quan Reviewed-by: Huang Rui > --- > drivers/gpu/d

Re: [PATCH v3] drm/amdgpu: update documentation for amdgpu_drv.c

Mhm, double checking that I now knew why my memory fooled me: We use 0 as infinite timeout in radeon. Maybe we should change amdgpu to do the same and reject negative values. Christian. Am 05.07.2018 um 16:54 schrieb Christian König: Sounds like my memory fooled me, but we should document tha

Re: [PATCH 04/10] drm/amdgpu: correct direct reg list length for v2_0 rlc

On Thu, Jul 05, 2018 at 05:09:29PM +0800, Evan Quan wrote: > For v2_0 rlc, rlc save restore list also needs to be initialized. > However, there is no reg_list_format_direct_reg_list_length > member(v2_1 spefic) for it. > > Change-Id: I29bfe441c4f4b4726a7dd61b315347fea057163b > Signed-off-by: Evan

Re: [PATCH v2] drm/amdgpu: update documentation for amdgpu_drv.c

On Wed, Jul 4, 2018 at 12:12 PM, Jiang, Sonny wrote: > Hi Alex, > > > IP blocks indexes are not fixed. What's your idea to list them? By asic > family? > > > enum amd_ip_block_type { > AMD_IP_BLOCK_TYPE_COMMON, > AMD_IP_BLOCK_TYPE_GMC, > AMD_IP_BLOCK_TYPE_IH, > AMD_

Re: [PATCH v3] drm/amdgpu: update documentation for amdgpu_drv.c

Sounds like my memory fooled me, but we should document that as well. Christian. Am 05.07.2018 um 16:47 schrieb Jiang, Sonny: Change it to, Value 0 is invalidated, will be adjusted to 1. Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). Thanks, Sonny --

Re: [PATCH v3] drm/amdgpu: update documentation for amdgpu_drv.c

Change it to, Value 0 is invalidated, will be adjusted to 1. Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). Thanks, Sonny From: Christian König Sent: Thursday, July 5, 2018 3:30:28 AM To: Jiang, Sonny; amd-gfx@lists.freedesktop.org Subject:

[PATCH v4] drm/amdgpu: update documentation for amdgpu_drv.c

Signed-off-by: Sonny Jiang Acked-by: Junwei Zhang Acked-by: Christian König --- Documentation/gpu/amdgpu.rst| 7 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 371 +++- 2 files changed, 371 insertions(+), 7 deletions(-) diff --git a/Documentation/gpu/amd

[PATCH] drm/amd/pp: Implement get_performance_level for legacy dgpu

display can get clock info through this function. implement this function for vega10 and old asics. from vega12, there is no power state management. so need other interface to notify display the clock info Signed-off-by: Rex Zhu --- .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 2 +- dri

[PATCH] drm/amd/pp: Convert 10KHz to KHz as variable name

The default clock unit in powerplay is 10KHz. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega1

Re: Proposal to merge KFD into amdgpu

On 2018-07-04 11:36 PM, Felix Kuehling wrote: > Since KFD is only supported by a single GPU driver now (amdgpu), it > makes sense to merge the two. This has been raised on the amd-gfx list > before and I've been putting it off to avoid more churn while I was > working on upstreaming KFD. Now seems

Re: BUG: *ERROR* No EDID read

On Mon, Jul 2, 2018 at 5:39 PM, Daniel Andersson wrote: > Sure, bisecting gets me 6e65fb862064663ad3a08f964af1e8f3f2abf688 . > > In drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c, > get_firmware_info_v3_1() works but get_firmware_info_v3_2() does not > do the right thing for my Vega. > > Could

Re: [PATCH] drm/amd/display: Use 2-factor allocator calls

On 2018-07-04 07:27 PM, Kees Cook wrote: > As already done treewide, switch from open-coded multiplication to > 2-factor allocation helper. > > Signed-off-by: Kees Cook > --- > drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-)

[PATCH] drm/amd/display: Use 2-factor allocator calls

As already done treewide, switch from open-coded multiplication to 2-factor allocation helper. Signed-off-by: Kees Cook --- drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/colo

Re: [PATCH] drm/amd/display/dc/dce: Fix multiple potential integer overflows

On 07/04/2018 12:51 PM, Harry Wentland wrote: [..] >>> >>> @@ -145,8 +145,8 @@ static bool calculate_fb_and_fractional_fb_divider( >>> * of fractional feedback decimal point and the fractional FB Divider >>> precision >>> * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / >>>

Re: [PATCH] drm/amd/display/dc/dce: Fix multiple potential integer overflows

Hi Michel, On 07/04/2018 02:38 AM, Michel Dänzer wrote: > On 2018-07-04 03:13 AM, Gustavo A. R. Silva wrote: >> Add suffix ULL to constant 5 and cast variables target_pix_clk_khz and >> feedback_divider to uint64_t in order to avoid multiple potential integer >> overflows and give the compiler com

[PATCH v2] drm/amd/display/dc/dce: Fix multiple potential integer overflows

Add suffix ULL to constant 5 and cast variables target_pix_clk_khz and feedback_divider to uint64_t in order to avoid multiple potential integer overflows and give the compiler complete information about the proper arithmetic to use. Notice that such constant and variables are used in contexts tha

[PATCH xf86-video-ati 09/10] Add struct radeon_buffer

From: Michel Dänzer Inspired by amdgpu, preparation for the following change. For now, this is mostly a wrapper around struct radeon_bo, no functional change intended. Signed-off-by: Michel Dänzer --- src/drmmode_display.c | 123 ++-- src/drmmode_display.h

[PATCH xf86-video-ati 01/10] Drop unused drmmode_create_bo_pixmap surface parameter

From: Michel Dänzer Signed-off-by: Michel Dänzer --- src/drmmode_display.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/drmmode_display.c b/src/drmmode_display.c index f056bf3b4..958532fb6 100644 --- a/src/drmmode_display.c +++ b/src/drmmode_display.c @@ -1

[PATCH xf86-video-ati 04/10] glamor: Don't store radeon_surfaces in pixmaps

From: Michel Dänzer Only EXA needs them. Signed-off-by: Michel Dänzer --- src/drmmode_display.c | 77 +- src/radeon.h | 19 ++- src/radeon_bo_helper.c | 22 +--- src/radeon_glamor.c| 8 ++--- src/radeon_kms.c | 11 ++

[PATCH xf86-video-ati 08/10] Refactor radeon_finish helper

From: Michel Dänzer Signed-off-by: Michel Dänzer --- src/drmmode_display.c| 16 +++- src/radeon.h | 1 + src/radeon_bo_helper.c | 10 ++ src/radeon_bo_helper.h | 3 +++ src/radeon_glamor_wrappers.c | 21 ++--- src/radeon_

[PATCH xf86-video-ati 10/10] glamor: Use GBM for BO allocation when possible

From: Michel Dänzer Inspired by amdgpu. This avoids various issues due to a GEM handle lifetime conflict between us and Mesa with current glamor. Bugzilla: https://bugs.freedesktop.org/105381 Signed-off-by: Michel Dänzer --- configure.ac | 10 src/Makefile.am| 4 +- s

[PATCH xf86-video-ati 05/10] Factor out radeon_surface_initialize helper

From: Michel Dänzer Signed-off-by: Michel Dänzer --- src/drmmode_display.c | 66 +--- src/radeon.h | 5 + src/radeon_bo_helper.c | 231 + src/radeon_kms.c | 35 +-- 4 files changed, 131 insertions(+), 206 deletions(-) dif

[PATCH xf86-video-ati 02/10] EXA: Remove old RADEONEXACreatePixmap hook

From: Michel Dänzer Not used by any supported version of xserver. Signed-off-by: Michel Dänzer --- src/evergreen_exa.c| 1 - src/evergreen_state.h | 1 - src/r600_exa.c | 1 - src/r600_state.h | 1 - src/radeon_exa.c | 29 - src/radeon_e

[PATCH xf86-video-ati 07/10] Remove throttling from radeon_dri2_copy_region2

From: Jammy Zhou Throttling should be handled by the client-side drivers. Signed-off-by: Jammy Zhou (Ported from amdgpu commit 8a34a8149860ac15e83ccdbd8d9a527d8d3e5997) Signed-off-by: Michel Dänzer --- src/radeon_dri2.c | 22 -- 1 file changed, 22 deletions(-) diff --git

[PATCH xf86-video-ati 00/10] glamor: Use GBM for BO allocation when possible

From: Michel Dänzer This series addresses https://bugs.freedesktop.org/105381 and is mostly inspired by the amdgpu driver. Patches 1 & 2 clean up things I noticed being unused while working on this series. Patches 3-5 are struct radeon_surface related cleanups. Patches 6-8 are flush/finish rel

[PATCH xf86-video-ati 06/10] Move flush from radeon_scanout_do_update to its callers

From: Michel Dänzer No functional change intended. Signed-off-by: Michel Dänzer --- src/drmmode_display.c | 2 ++ src/radeon_kms.c | 8 +--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/drmmode_display.c b/src/drmmode_display.c index c7bec59c8..54b09730d 100644 -

[PATCH xf86-video-ati 03/10] Only initialize libdrm_radeon surface manager for >= R600

From: Michel Dänzer Not used with older GPUs. Signed-off-by: Michel Dänzer --- src/drmmode_display.c | 5 +++-- src/radeon_bo_helper.c | 7 --- src/radeon_kms.c | 18 +++--- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/src/drmmode_display.c b/src/dr

Re: [PATCH] drm/amdgpu: Add CLK IP base offset

Reviewed-by: Evan Quan From: amd-gfx on behalf of Rex Zhu Sent: Thursday, July 5, 2018 4:39:44 PM To: amd-gfx@lists.freedesktop.org Cc: Zhu, Rex Subject: [PATCH] drm/amdgpu: Add CLK IP base offset so we can read/write the registers in CLK domain through RREG32

[PATCH 10/10] drm/amd/powerplay: no need to mask workable gfxoff feature for vega12

Gfxoff feature for vega12 is workable. So, there is no need to mask it any more. Change-Id: I7e4d05c5c0acc2aa2b077eaaaf6f13589c87114b Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/p

[PATCH 09/10] drm/amd/powerplay: add vega12 SMU gfxoff support

Export apis for enabling/disabling SMU gfxoff support. Change-Id: Idcea1db9f3dbe15edda1b76e1ff05435865af2a1 Signed-off-by: Evan Quan --- .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 19 +++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega

[PATCH 08/10] drm/amdgpu: use the accessible target rlc safe mode Apis directly

No need to do double dereference to reach the Apis. They are accessible directly. Change-Id: I4b810c5e1981e0810df36a701b20edaf1f6af207 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/am

[PATCH 07/10] drm/amdgpu: reduce the idle period that RLC has to wait before request CGCG

Gfxoff feature may depends on the CGCG(on vega12, that's the case). This change will help to enable gfxoff feature more frequently. Change-Id: I021577e331b7beb19796bd6f5465b867f6038974 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++ 1 file changed, 7 insertio

[PATCH 05/10] drm/amdgpu: drop mmRLC_PG_CNTL clear

This may break gfxoff support since this register will be set by smc fw(for vega12, that's the case). Change-Id: Id3108c63634a2f941289021bfbd78588c0f6c4d6 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/

[PATCH 06/10] drm/amdgpu: no touch for the reserved bit of RLC_CGTT_MGCG_OVERRIDE

On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved. Change-Id: I9042a8c89db16f220da5a589264937b51870c187 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v

[PATCH 04/10] drm/amdgpu: correct direct reg list length for v2_0 rlc

For v2_0 rlc, rlc save restore list also needs to be initialized. However, there is no reg_list_format_direct_reg_list_length member(v2_1 spefic) for it. Change-Id: I29bfe441c4f4b4726a7dd61b315347fea057163b Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++-- 1 file chan

[PATCH 02/10] drm/amdgpu: init CSIB regardless of rlc version and pg status

CSIB init has no relation with rlc version and pg status. It should be needed regardless of them. Change-Id: Iccd12e1015f41c7e2bc3fe02472dc979015514d4 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/

[PATCH 03/10] drm/amdgpu: init rlc save restore as long as the lists exist

It does not have to be rlc v2_1 and pg enabled. For rlc v2_0, rlc save restore is also needed. And pg support is definitely not a must for rlc save restore. Change-Id: I85c0e3525ca7fb385c3d0b9e5abc13708c91e795 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++-

[PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init

Without this pin, the csb buffer will be filled with inconsistent data after S3 resume. And that will causes gfx hang on gfxoff exit since this csb will be executed then. Change-Id: I1ae1f2eed096eaba5f601cf2a3e2650c8e583dc9 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40

[PATCH] drm/amdgpu: Add CLK IP base offset

so we can read/write the registers in CLK domain through RREG32/WREG32_SOC15 Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/dr

Re: [PATCH v3] drm/amdgpu: update documentation for amdgpu_drv.c

Am 04.07.2018 um 20:20 schrieb Sonny Jiang: [SNIP] +/** + * DOC: lockup_timeout (int) + * Set GPU scheduler timeout value in ms. It must be > 0. The default is 1. + */ MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 1)"); module_param_named(lockup_timeou

Re: [PATCH v2 1/2] drm/amdgpu: Add support for logging process info in amdgpu_vm.

Am 04.07.2018 um 17:04 schrieb Andrey Grodzovsky: Add process and thread names and pids and a function to extract this info from relevant amdgpu_vm. v2: Add documentation and fix identation. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21

Re: [PATCH 1/2] drm/amdgpu: Add support for logging process info in amdgpu_vm.

Am 04.07.2018 um 16:22 schrieb Andrey Grodzovsky: On 07/04/2018 10:17 AM, Christian König wrote: Am 04.07.2018 um 16:10 schrieb Andrey Grodzovsky: Add process and thread names and pids and a function to extract this info from relevant amdgpu_vm. Signed-off-by: Andrey Grodzovsky ---   driver

Re: [PATCH] drm/amdgpu: Verify root PD is mapped into kernel address space.

Am 05.07.2018 um 04:09 schrieb zhoucm1: On 2018年07月05日 03:49, Andrey Grodzovsky wrote: Problem: When PD/PT update made by CPU root PD was not yet mapped causing page fault. Fix: Move amdgpu_bo_kmap into amdgpu_vm_bo_base_init to cover all cases and avoid code duplication with amdgpu_vm_alloc