From: Aurabindo Pillai
[Why & How]
Fix the instatiation sequence for MPC registers and add a few other
missing register definitions that were ommited erroneously when copying
them over to enable runtime initialization of reigster offsets for
DCN32/321
Reviewed-by: Rodrigo Siqueira
Signed-off-by
compilation for dcn314
Acked-by: Pavle Kotarac
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index e8e8e031b9d7..53b13beff0b2 100644
l come in a following patch to make this transition easier to
bisect.
Reviewed-by: Jun Lei
Acked-by: Pavle Kotarac
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 2 +-
.../gpu/drm/amd/display/dc/dml/display_mode_lib.c| 12
.../gp
From: "Lee, Alvin"
[Description]
Regkey option for forcing num ways for
subvp for debug purposes
Reviewed-by: Jun Lei
Acked-by: Pavle Kotarac
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../drm/amd/display/dc/dcn32/dcn32_resource_help
; 1, just like
what we do in translate_from_linear_space for other
re-gamma build paths.
Reviewed-by: Krunoslav Kovac
Reviewed-by: Krunoslav Kovac
Reviewed-by: Aric Cyr
Acked-by: Pavle Kotarac
Signed-off-by: Yao Wang1
---
drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 4
1 f
From: JeromeHong
[why]
Call commit_minimal_transition_state wrongly in case of surface_count equal to
0.
[how]
Add a condition to filter case of surface_count equal to 0.
Reviewed-by: Aric Cyr
Acked-by: Pavle Kotarac
Signed-off-by: JeromeHong
---
drivers/gpu/drm/amd/display/dc/core/dc.c
From: "Lee, Alvin"
[Description]
In some cases the viewport position of the
main pipes can change without triggering a full update.
In this case the subvp phantom viewports must be updated accordingly.
Reviewed-by: Jun Lei
Acked-by: Pavle Kotarac
Signed-off-by: Alvin Lee
---
.
From: Alvin Lee
Refactor calculation to remove floating point operations from dmub_srv.
To ensure that 32-bit compilation works well, we use the div64 family of
macros to do integer division for SubVP-related timing parameters.
Cc: MaĆra Canal
Cc: Alex Deucher
Cc: Isabella Basso
Cc: Magali Le
From: "Chen, Leo"
[Why & How]
Enable logging for spread_spectrum_percentage in spread_spectrum_info
to facilitate debugging for audio compliance issues
Co-authored-by: Leo Chen
Reviewed-by: Charlene Liu
Acked-by: Pavle Kotarac
Signed-off-by: Leo Chen
---
.../drm/amd/d
remove it.
Similarly, the stream update for VRR is done after dc_commit and should
not update its adjust field until after the update is completed. The
adjust field is managed by dc_stream_adjust_vmin_vmax and should not be
manually updated in amdgpu_dm.
Reviewed-by: Anthony Koo
Acked-by: Pavle Kotar
d-by: Aurabindo Pillai
Acked-by: Pavle Kotarac
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 5 +
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
drivers/gpu/drm/amd/di
From: Rodrigo Siqueira
We were not using the VBA and DLG files for DCN314, but the next
sequence of changes for DCN314 will require those files. This commit
adds the necessary files to the Makefile.
Cc: Roman Li
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/Makefile |
ound could be removed after
cursor caching is fixed while a subviewport config is active.
Reviewed-by: Alvin Lee
Acked-by: Pavle Kotarac
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
From: Nicholas Kazlauskas
[Why]
HW can support the display swizzle modes for video, and those are
preferable over standard or linear for decode use.
[How]
Remove the check for DCN314.
Reviewed-by: Jun Lei
Acked-by: Pavle Kotarac
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd
From: Rodrigo Siqueira
We have some compilation errors in some DML files from DCN314 that we
never noticed because we were not compiling some of the DML files. This
commit fixes those syntax errors before we enable the compilation.
Cc: Roman Li
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/
From: Duncan Ma
[Why]
The interpretation of the number of memory channels
differ by memory type, and this affects channel width
for the DML input.
[How]
Set dram channel width according to memory type for
dcn314.
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Jun Lei
Acked-by: Pavle Kotarac
From: Taimur Hassan
[Why & How]
When calculating cursor size for MALL allocation, the cursor width should
be the actual width rounded up to 64 alignment. Additionally, the bit
depth should vary depending on color format.
Reviewed-by: Alvin Lee
Acked-by: Pavle Kotarac
Signed-off-by: Ta
From: Leo Chen
[Why & How]
DIG_FIFO_READ_START_LEVEL should only be set to default value (7) by software.
Removed all instances of resetting the register to 0
Reviewed-by: Nicholas Kazlauskas
Acked-by: Pavle Kotarac
Signed-off-by: Leo Chen
---
.../gpu/drm/amd/display/dc/dc
From: Aric Cyr
[why]
Incorrectly using MicroTileWidth instead of MacroTileWidth for
calculations.
[how]
Remove all unused references to MicroTile and change them to MacroTile.
Reviewed-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Pavle Kotarac
Signed-off-by: Aric Cyr
---
.../dc/dml/dcn32
From: Iswara Nagulendran
[HOW&WHY]
Revert a previous commit by moving DSC programming
back to before link enablement.
Reviewed-by: Jayendran Ramani
Acked-by: Pavle Kotarac
Signed-off-by: Iswara Nagulendran
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 13 +
...
From: "Xu, Jinze"
[Why]
link type is not assigned before check dpia_mst_dsc_always_on conditions.
Reviewed-by: Wenjing Liu
Acked-by: Pavle Kotarac
Signed-off-by: JinZe.Xu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
di
From: Aurabindo Pillai
This reverts commit 8dbf225893cb07f98f8edc2d775b6a68fc1eab3b since
returning false in case of SubVP results in no cursor being visible on
desktop as there is no sw cursor fallback path on all platforms.
Reviewed-by: Alvin Lee
Acked-by: Pavle Kotarac
Signed-off-by
From: "Lee, Alvin"
[Description]
pipe_ctx[i] exists even if the pipe
is not in use. If the pipe is not in
use it will always have a null stream,
so don't return false in this case.
Reviewed-by: Ethan Wellenreiter
Acked-by: Pavle Kotarac
Signed-off-by: Alvin Lee
---
driv
From: "Lee, Alvin"
[Description]
Update MBLK calculation according to hardware doc.
For DCC case we were not allocation enough MALL
due to an inaccurate MBLK calculation.
Reviewed-by: Jun Lei
Acked-by: Pavle Kotarac
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn32/dcn32_
From: Hansen Dsouza
[why]
update header files, and remove not used register access marco
Reviewed-by: Hansen Dsouza
Acked-by: Pavle Kotarac
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
.
Reviewed-by: Charlene Liu
Acked-by: Pavle Kotarac
Signed-off-by: Chris Park
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 9 -
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 17 +
.../drm/amd/display/dc/dcn321/dcn321_resource.c | 9 -
3 files changed
granularity.
Reviewed-by: Nevenko Stupar
Acked-by: Pavle Kotarac
Signed-off-by: Aric Cyr
---
.../amd/display/dc/dml/calcs/dcn_calc_auto.c | 22 ++---
.../amd/display/dc/dml/calcs/dcn_calc_math.c | 16 +-
.../dc/dml/dcn20/display_mode_vba_20v2.c | 10 +++---
.../dc/dml/dcn21
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
*Fixed register definitions for DCN32/321
*Adding log for spread_spectrum_info
*Reverted DSC programming sequence change
*Correct I2C register offset
*Updated DCN30 header files, viewport position for phantom pipes
new helper from linux DM (amdgpu_dm_psr)
Acked-by: Pavle Kotarac
Acked-by: Tom Chung
Signed-off-by: David Zhang
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 9 -
.../amd/display/modules/power/power_helpers.c | 38 +++
.../amd/display/modules/power/power_helpers.h | 1
From: Dillon Varone
[WHY&HOW]
Change criteria for setting DTO source value, and always set it regardless of
the signal type.
Reviewed-by: Ariel Bernstein
Acked-by: Pavle Kotarac
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 +-
1 file change
connected
*Disable FEC if DSC not supported for EDP
*Add odm seamless boot support
*Select correct DTO source
*Power down hardware if timer not trigger
Acked-by: Pavle Kotarac
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
causes the 32bit build to fail to
compile.
[How]
Change the / operator to div_u64 instead.
Reviewed-by: Aric Cyr
Acked-by: Pavle Kotarac
Signed-off-by: Hayden Goodfellow
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
From: hersen wu
[Why] within dc link detecion, dp link training will be
executed for external sst dp. for debug purpose, we may
need skip dp link training.
[How] expose dc debug option to skip_detection_link_training
to debugfs
Reviewed-by: Roman Li
Acked-by: Pavle Kotarac
Signed-off-by
timestamp in the unit we want.
Reviewed-by: Aric Cyr
Acked-by: Pavle Kotarac
Signed-off-by: Angus Wang
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b
From: Jingwen Zhu
[Why]
FEC init used on DCN30.
[How]
Check fec active when HW init.
Co-authored-by: Jingwen Zhu
Reviewed-by: Wenjing Liu
Acked-by: Pavle Kotarac
Signed-off-by: Jingwen Zhu
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 +-
1 file changed, 5 insertions
From: Dillon Varone
Reviewed-by: Ariel Bernstein
Acked-by: Pavle Kotarac
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 863d90bec61b
From: Oliver Logush
[why]
Make sure smu is not busy before sending another request, this is to
prevent stress failures from MS.
[how]
Check to make sure the SMU fw busy signal is cleared before sending
another request
Reviewed-by: Charlene Liu
Reviewed-by: Nicholas Kazlauskas
Acked-by: Pavle
From: Oliver Logush
[why]
Need to update the update_clock sequence to a fully tested sequence for
dcn30
[how]
Removed the check to see if clock is lowered
Reviewed-by: Charlene Liu
Acked-by: Pavle Kotarac
Signed-off-by: Oliver Logush
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201
Pre-OS odm to Post-OS non-odm to avoid corruption.
Apply logic to set odm accordingly upon commit.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Pavle Kotarac
Signed-off-by: "Duncan Ma"
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 13 +++
.../gpu/drm/amd/display/dc/core/dc_resou
SetPowerState to D3, power down hardware.
2. Update HDMI hang w/a to apply to all TMDS signals on
headless system
Reviewed-by: Martin Leung
Acked-by: Pavle Kotarac
Signed-off-by: Paul Hsieh
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 17 +---
.../display/dc/clk_mgr/dcn31
From: Charlene Liu
[why]
dcn316's dtbclk is from non_ss clock source.
no compensation required here.
Reviewed-by: Chris Park
Acked-by: Pavle Kotarac
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 2 +-
.../gpu/drm/amd/display/dc/cl
From: Evgenii Krasnikov
[HOW&WHY]
Make sure psr_force_static() can always be called regardless of
psr_allow_active value.
Reviewed-by: Harry Vanzylldejong
Reviewed-by: Evgenii Krasnikov
Reviewed-by: Nicholas Choi
Acked-by: Pavle Kotarac
Signed-off-by: Evgenii Krasnikov
---
drivers/gpu
support in DC caps
or if DSC should be disabled for EDP
before enabling FEC for EDP.
Reviewed-by: Harry Vanzylldejong
Reviewed-by: Evgenii Krasnikov
Reviewed-by: Nicholas Choi
Acked-by: Pavle Kotarac
Signed-off-by: Iswara Nagulendran
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 --
1
enii Krasnikov
Reviewed-by: Nicholas Choi
Acked-by: Pavle Kotarac
Signed-off-by: Harry VanZyllDeJong
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c| 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.
: Pavle Kotarac
Signed-off-by: Max Erenberg
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 47b67fd1e84c..22f2d88fab99 100644
--- a/drivers/gpu
From: "AMD\\syerizvi"
[WHY]
Z10 is should not be enabled by default on DCN31.
[HOW]
Using DC debug flags to disable Z10 by default on DCN31.
Reviewed-by: Eric Yang
Acked-by: Pavle Kotarac
Signed-off-by: AMD\syerizvi
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 1
never happens and
the wait times out. This can add hundreds of milliseconds to the boot
time.
[How]
Do not wait for mpc idle if tg is disabled
Reviewed-by: Jun Lei
Acked-by: Pavle Kotarac
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
1
From: Eric Yang
[Why]
Z10 and S0i3 have some shared path. Previous code clean up ,
incorrectly removed these pointers, which breaks s0i3 restore
[How]
Do not clear the function pointers based on Z10 disable.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Pavle Kotarac
Signed-off-by: Eric Yang
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
*Disabling Z10 on DCN31
*Fix issue breaking 32bit Linux build
*Fix inconsistent timestamp type
*Add DCN30 support FEC init
*Fix crash on setting VRR with no display connected
*Disable FEC
From: Aric Cyr
Acked-by: Pavle Kotarac
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 963b58803ae5..18e59d635ca2 100644
--- a
ed-by: Aurabindo Jayamohanan Pillai
Acked-by: Pavle Kotarac
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdg
clock change to override underflow
added logic to change clk based on pstatesupport and softmax
added logic in prepare/optimize_bw to conform while changing
clocks
Reviewed-by: Aric Cyr
Acked-by: Pavle Kotarac
Signed-off-by: Martin Leung
---
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 44
+ windows MPO, where MPO window is
on right half, left half, and both halves or ODM.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Pavle Kotarac
Signed-off-by: Eric Bernstein
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 81 ++-
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 11
From: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Pavle Kotarac
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd
From: Michael Strauss
[WHY]
This workaround resolves underflow caused by incorrect DST_Y_PREFETCH.
Overriding to 192KB DET buf size until the DST_Y_PREFETCH calc is fixed.
Reviewed-by: Eric Yang
Acked-by: Pavle Kotarac
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dcn31
function to check if PSR SU is supported by sink
and the driver
Reviewed-by: Roman Li
Reviewed-by: Rodrigo Siqueira
Acked-by: Pavle Kotarac
Signed-off-by: Mikita Lipski
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 101 +++---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 9
From: Wayne Lin
[Why & How]
In order to know the intermediate link rates supported by the eDP
panel and test to select the optimized link rate to save power,
create a new debugfs entry "ilr_setting" for
setting ILR.
Reviewed-by: Aurabindo Jayamohanan Pillai
Acked-by: Pavle Kotar
From: Solomon Chiu
[Why]
Current error log of dummy irq service doesn't have
src/ext ID info in the log.
[How]
Add src/ext ID in ack/set of dummy irq service.
Reviewed-by: Wayne Lin
Acked-by: Pavle Kotarac
Signed-off-by: Solomon Chiu
---
.../drm/amd/display/dc/irq/dce110/irq_service_d
with exit_optimized_pwr_state
but this is only set on DCN21 and DCN301. Set it for dcn31 as well.
This fixes DMCUB timeouts in the PHY.
Fixes: 64b1d0e8d500 ("drm/amd/display: Add DCN3.1 HWSEQ")
Reviewed-by: Eric Yang
Acked-by: Pavle Kotarac
Signed-off-by: Nicholas Kazlauskas
---
driv
This new DC version brings improvements in the following areas:
- FW promotion to 0.0.97
- DSC fixes for supported Docks
- Fixes eDP display issue
- Vendor LTTR workarounds
- Fixes Tiled display audio issue
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.97
Aric Cyr (1):
drm
From: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Pavle Kotarac
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index a43c008bd0f2
From: Aric Cyr
Reduce stack usage by moving an unnecessary structure copy to a pointer.
Reviewed-by: Joshua Aberback
Acked-by: Pavle Kotarac
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a
ed-by: Hansen Dsouza
Acked-by: Pavle Kotarac
Signed-off-by: Nicholas Kazlauskas
---
.../display/dc/dcn31/dcn31_dio_link_encoder.c | 97 +++
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 29 ++
2 files changed, 88 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/dr
From: Wenjing Liu
[why]
A debug option is needed to temporarily force dp2 new link training
fallback method for debugging purpose.
Reviewed-by: George Shen
Acked-by: Pavle Kotarac
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 ++---
drivers/gpu/drm
From: Anthony Koo
Acked-by: Pavle Kotarac
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Oliver Logush
[why]
Need to fix the code so it does not use reserved keywords
[how]
Change the total_length member of the cea struct
Reviewed-by: Anthony Koo
Acked-by: Pavle Kotarac
Signed-off-by: Oliver Logush
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu
From: Meenakshikumar Somasundaram
[Why]
Need to have dpia debug bits for configuring hpd delay.
[How]
Added hpd_delay_in_ms variable in dpia_debug_options.
Reviewed-by: Jimmy Kizito
Acked-by: Pavle Kotarac
Signed-off-by: meenakshikumar somasundaram
---
drivers/gpu/drm/amd/display/dc/dc.h
From: Jude Shih
[Why]
We shouldn't be accessing res_pool funcs from DM level,
therefore, we should create API and let the flow
be done in DC level.
[How]
We create new interface dp_get_link_enc to access and get the correct link_enc
Reviewed-by: Nicholas Kazlauskas
Acked-by: Pavle Ko
: Dan Carpenter
Fixes: 9a65df193108 ("drm/amd/display: Use PSP TA to read out crc")
Reviewed-by: Rodrigo Siqueira
Acked-by: Pavle Kotarac
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
From: Mikita Lipski
[why/how]
The function can be called on boot or after suspend when
links are not initialized, to prevent it guard it with
NULL pointer check
Reviewed-by: Nicholas Kazlauskas
Acked-by: Pavle Kotarac
Signed-off-by: Mikita Lipski
---
drivers/gpu/drm/amd/display/dc/dc_link.h
From: Jarif Aftab
[WHY]
-To ensure dc->res_pool has been initialized
[HOW]
-Check if dc->res_pool is true in
the if statement
Reviewed-by: Martin Leung
Acked-by: Pavle Kotarac
Signed-off-by: Jarif Aftab
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion
FW.
Theoretically PSR can be enabled during hw programming
sequences or any other situation where we must disable PSR.
[How]
Check if PSR is enabled before doing PSR disable/reenable.
Reviewed-by: Anthony Koo
Acked-by: Pavle Kotarac
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dc
er
DC interrupts.
Guard both instances of the outbox interrupt enable or we'll hang
during restore on ASIC that don't support it.
Fixes: 19fde255f248 ("drm/amd/display: Fix DPIA outbox timeout after GPU reset")
Reviewed-by: Jude Shih
Acked-by: Pavle Kotarac
Signed-of
From: George Shen
[Why]
Certain LTTPR require output VS/PE to be explicitly
set during PHY test automation.
[How]
Add vendor-specific sequence to set LTTPR
output VS/PE.
Reviewed-by: Jun Lei
Acked-by: Pavle Kotarac
Signed-off-by: George Shen
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c
From: George Shen
[Why]
Some of the vendor-specific workarounds added for transparent mode
also need to be applied to non-transparent mode in order to succeed
link training consistently.
[How]
Remove transparent mode check for the required workarounds.
Reviewed-by: Jun Lei
Acked-by: Pavle
This new DC version brings improvements in the following areas:
- Improvements for USB4;
- Isolate FPU code for DCN20, DCN301, and DSC;
- Fixes on Linking training;
- Refactoring some parts of the code, such as PSR;
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