had a quick look at Dove and Orion5x. It looks like there are none
> with PCIe support. So only Kirkwood is broken.
There are some Dove and Orion5x with PCIe support, but none of them are
using the new PCIe driver yet.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drive
Dear Jonathan Cameron,
On Tue, 16 Jul 2013 20:03:38 +0100, Jonathan Cameron wrote:
> On 07/16/2013 12:30 PM, Thomas Petazzoni wrote:
> > I've asked exactly this question last week at Linaro Connect during the
> > ARM SoC consolidation panel/discussion, where Grant Likely, Arn
something we did say
when we submitted at91-adc and during the reviews, but the maintainer
wasn't listening to our comments...
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting,
l follow.
But Ezequiel will confirm all that, we had a discussion together about
this yesterday, so I guess what I said should be the plan, but it's
better if Ezequiel confirms, obviously :)
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
deve
Following the introduction of of_phy_register_fixed_link(), this patch
introduces fixed link support in the mvneta driver, for Marvell Armada
370/XP SOCs.
Signed-off-by: Thomas Petazzoni
---
.../bindings/net/marvell-armada-370-neta.txt | 24 +++---
drivers/net/ethernet
Signed-off-by: Thomas Petazzoni
---
drivers/net/phy/fixed.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
index ba55adf..bd1e67a 100644
--- a/drivers/net/phy/fixed.c
+++ b/drivers/net/phy/fixed.c
@@ -195,6 +195,8 @@ int fixed_phy_add(unsigned
says
new drivers should not use it, since Grant Likely indicated that
this "fixed-link" property is indeed the way to go.
Signed-off-by: Thomas Petazzoni
---
.../devicetree/bindings/net/fixed-link.txt | 26
drivers/of/of_mdio.c
welcome. Thanks!
Thomas
[1] http://www.spinics.net/lists/netdev/msg242766.html
http://www.spinics.net/lists/netdev/msg243192.html
Thomas Petazzoni (3):
of: provide a binding for the 'fixed-link' property
net: phy: call mdiobus_scan() after adding a fixed PHY
net: mvneta: add support
a temporary stop-gap and will be removed soon. It is
* only to support the fs_enet, ucc_geth and gianfar Ethernet drivers. Do
* not call this function from new drivers.
Also, it would probably be good to have a few more helpers to make
parsing the "phy" and "fixed-link" p
gt;;
> duplex = <1>;
> pause;
> asym-pause;
> };
Yeah, that's fine, I have no problem with the internal properties of
the PHY nodes themselves. My question is really the one described above.
Thomas
--
Thomas
HY properties ...
};
};
soc {
ethernet@0 {
compatible = "...";
...
phy = <&phy0>;
};
ethernet@1 {
compa
ing else? Or a
specific compatible string?
> What do you think? I suspect someone might rightfully say that the
> "fixed-mdio" is not a real piece of hardware and is just a software
> concept. A PHY in the real world may very well have a fixed link
> speed/duplex/pause
ndle ...
};
phy1: ethernet-phy@1 {
... all the properties you listed ...
... maybe the "id" property is not needed
because of the phandle ...
};
};
soc {
-mmp/time.c| 15 ++-
> 3 files changed, 5 insertions(+), 18 deletions(-)
Maybe it would be good to take this opportunity to move
arch/arm/mach-mmp/time.c into drivers/clocksource/.
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulti
window
base address allocation for now. This makes sense, as mvebu-mbus
is the "gake keeper" of what gets mapped in terms of mbus windows.
(2) The ranges property of the main pcie-controller {} node is changed
to use 0x8200 and 0x8100 for all PCIe in
a fake MBUS_ID(0xf0, 0x02). Those
are global to all PCIe interfaces.
*) The target and attribute values for MEM and I/O windows, that are
per-PCIe interface.
As long as we can get those two informations from the DT, I believe
we're open to all your suggestions on how to encode them.
jorn ACK, of course), so that Arnd/Olof can
make sure the ordering is correct with regard to the of/pci changes and
the mvebu/pci driver.
I'll let you discuss that with Jason Cooper.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
developme
11), regardless of
what happens for the rest of your PCIe patches.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
___
devicetree-d
Dear Jingoo Han,
On Thu, 20 Jun 2013 16:12:24 +0900, Jingoo Han wrote:
> - pinctrl {
> + pin_ctrl: pinctrl {
> compatible = "samsung,exynos5440-pinctrl";
I know I'm nitpicking, but isn't this change completely unrelated to
PCIe support?
Thom
for PCIe devices will not work?
>
> Where did I suggest static windows for PCIe devices?
Where does your new proposal buys us anything useful compared to the
existing PCIe DT binding that has been discussed at length with you?
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel,
indows for PCIe devices, which
lead us to have the emulated PCI-to-PCI bridge stuff. I'm starting to
be fed up to re-explain this to you over-and-over again.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-tim
Linux PCI core, which then dynamically assigns sub-ranges for each
PCIe device into those two global ranges.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
looking for right now is a Acked-by from both
the Marvell maintainers, Arnd Bergmann and Jason Gunthorpe. Once we get
those Acked-by, we can figure out the merge strategy for this patch
set.
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-t
uot; tells you... Which by itself is a very good indicator that
you're probably not the best interlocutor for Allwinner as far as
mainline development is concerned.
Best regards,
Thomas Petazzoni
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development
Dear Ezequiel Garcia,
On Fri, 7 Jun 2013 13:47:49 -0300, Ezequiel Garcia wrote:
> These properties are not needed so it's safe to remove them.
>
> Signed-off-by: Ezequiel Garcia
Acked-by: Thomas Petazzoni
I believe this one should be applied now, regardless of what happens
rcia
Acked-by: Thomas Petazzoni
I believe this one could be applied regardless of what happens to the
rest of the patch series.
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://fre
ntrol the access to the shared TIMER_CTRL
register.
(3) Something else.
And this still does not solve the access to BRIDGE_CAUSE and
RSTOUTn_MASK.
Ideas?
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support
ere is already a pinctrl driver for sunxi platforms (i.e Allwinner
SoCs), it's at drivers/pinctrl/pinctrl-sunxi.c, and it's DT-based and
allows to describe the pin muxing in the Device Tree.
Cc'ing Maxime Ripard, who is the mach-sunxi maintainer in the mainline
kernel.
Best regards,
2C is
working.
All in mainline, completely Device Tree based.
So isn't this entire discussion completely moot? The mainline support
for sunxi has already started since 6 months or so, and has been Device
Tree based from day one.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Ker
e Ripard, since I see that mach-sunxi does have a
Makefile.boot, even though I believe it is not needed.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and sup
d-off-by: Wei Yongjun
Acked-by: Thomas Petazzoni
Jason, this needs to be in the mvebu/pcie branch, so I'll guess you
would have to rebase mvebu/pcie_bridge on top of it.
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consul
x27;t decided to do a 'git gc' right
> > after my rebase. It's been gc-ing for quite some time now...
>
> Dear boss,
>
> I am in desperate need of a 500GB SSD on which to do my kernel work.
>
> Thanks,
>
> Kranky Kernel Developer
>
> hehehe...
The Armada 370 has two gatable clocks for each PCIe interface, and we
want both of them to be enabled. We therefore make one of the two
clocks a child of the other, as we did for the sataX and sataXlnk
clocks on Armada XP.
Signed-off-by: Thomas Petazzoni
Cc: Mike Turquette
---
drivers/clk
From: Thierry Reding
This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.
Signed-off-by: Thierry Reding
---
drivers/of/of_pci.c| 25 +
include/linux/of_pci.h |1 +
2 files changed, 26 insertions(+)
dif
: Thomas Petazzoni
---
arch/arm/configs/mvebu_defconfig |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index f3e8ae0..966281e 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -13,6
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni
Acked
those PCIe interfaces.
It also changes the name of the previously existing PCIe gatable
clocks, in order to match the naming using the datasheets.
Signed-off-by: Thomas Petazzoni
Cc: Mike Turquette
---
drivers/clk/mvebu/clk-gating-ctrl.c | 14 ++
1 file changed, 10 insertions(+), 4
Now that the PCIe driver for mvebu has been integrated and all its
relevant dependencies, we can mark the ARCH_MVEBU platform has
MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.
Signed-off-by: Thomas Petazzoni
---
arch/arm/mach-mvebu/Kconfig |2 ++
1 file changed, 2
From: Thierry Reding
This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.
Signed-off-by: Thierry Reding
Signed-off-by: Thomas
es and merges them
into a single range (as was the case with powerpc and microblaze).
Signed-off-by: Andrew Murray
Signed-off-by: Liviu Dudau
Signed-off-by: Thomas Petazzoni
Reviewed-by: Rob Herring
Tested-by: Thomas Petazzoni
Tested-by: Linus Walleij
Tested-by: Jingoo Han
Acked-by: Gran
ernal register space.
However, beyond just the register areas, there are also PCIe I/O and
memory regions, whose addresses should be properly translated. This
patch fixes the Armada 370 and XP ranges property to take PCIe into
account properly.
Signed-off-by: Thomas Petazzoni
---
Since
Stephen Warren.
* Fix the ->resource_align() to only apply on bus 0 (the one on which
the emulated PCI-to-PCI bridges sit), and to request an alignment
on the size of the window (and not only 64 KB for I/O windows and 1
MB for memory windows).
* Clarified the commit log of "clk
is
__init (and this explains what I wasn't seeing the warning, since I'm
building CONFIG_MODULES=y). The two other functions are more cosmetic,
but good to have as well.
It would already been sent if git hadn't decided to do a 'git gc' right
after my rebase. It's
Dear Mike Turquette,
On Wed, 15 May 2013 14:41:54 -0700, Mike Turquette wrote:
> Quoting Thomas Petazzoni (2013-05-15 06:25:19)
> > The Armada 370 has two gatable clocks for each PCIe interface, and we
> > want both of them to be enabled. We therefore make one of the two
> >
: Thomas Petazzoni
---
arch/arm/configs/mvebu_defconfig |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index f3e8ae0..966281e 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -13,6
Now that the PCIe driver for mvebu has been integrated and all its
relevant dependencies, we can mark the ARCH_MVEBU platform has
MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.
Signed-off-by: Thomas Petazzoni
---
arch/arm/mach-mvebu/Kconfig |2 ++
1 file changed, 2
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni
Acked
those PCIe interfaces.
It also changes the name of the previously existing PCIe gatable
clocks, in order to match the naming using the datasheets.
Signed-off-by: Thomas Petazzoni
Cc: Mike Turquette
---
drivers/clk/mvebu/clk-gating-ctrl.c | 14 ++
1 file changed, 10 insertions(+), 4
The Armada 370 has two gatable clocks for each PCIe interface, and we
want both of them to be enabled. We therefore make one of the two
clocks a child of the other, as we did for the sataX and sataXlnk
clocks on Armada XP.
Signed-off-by: Thomas Petazzoni
Cc: Mike Turquette
---
drivers/clk
From: Thierry Reding
This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.
Signed-off-by: Thierry Reding
---
drivers/of/of_pci.c| 25 +
include/linux/of_pci.h |1 +
2 files changed, 26 insertions(+)
dif
From: Thierry Reding
This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.
Signed-off-by: Thierry Reding
Signed-off-by: Thomas
ly 64 KB for I/O windows and 1
MB for memory windows).
* Clarified the commit log of "clk: mvebu: create parent-child
relation for PCIe clocks on Armada 370"
Thanks,
Thomas
Andrew Murray (1):
of/pci: Provide support for parsing PCI DT ranges property
Thierry Reding (2):
of/pci:
es and merges them
into a single range (as was the case with powerpc and microblaze).
Signed-off-by: Andrew Murray
Signed-off-by: Liviu Dudau
Signed-off-by: Thomas Petazzoni
Reviewed-by: Rob Herring
Tested-by: Thomas Petazzoni
Tested-by: Linus Walleij
Tested-by: Jingoo Han
Acked-by: Gran
ernal register space.
However, beyond just the register areas, there are also PCIe I/O and
memory regions, whose addresses should be properly translated. This
patch fixes the Armada 370 and XP ranges property to take PCIe into
account properly.
Signed-off-by: Thomas Petazzoni
---
Since
ation of the Ethernet devices. Shouldn't such files be
removed in this patch?
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
_
ght (thanks
to automated build tests), and Andrew Murray has just sent a new
version v7 of the patch set addressing those issues, as well as the
missing include.
Also, please note that Andrew's patch set contains three patches, but
the Marvell PCIe driver only requires PATCH 1/3 and PATCH
m Andrew series to
> > replace PATCH 1,2,3 from my series. Andrew v6 has quite a number of
> > changes compared to v5, so I really recommend using those ones.
>
> No need to mess with v9, I'll pull AndrewM's v6.
Excellent, thanks.
Thomas
--
Thomas Petazzoni, Free Ele
nally used as a base for
my PCIe v8. I can resend a v9 of my PCIe patch set based on the v6 of
Andrew, or you can directly use PATCH 1,2,3 from Andrew series to
replace PATCH 1,2,3 from my series. Andrew v6 has quite a number of
changes compared to v5, so I really recommend using those ones.
ot;
> property of a PCI host device, is found in both Microblaze and PowerPC
> architectures. These implementations are nearly identical. This patch
> moves this common code to a common place.
>
> Signed-off-by: Andrew Murray
> Signed-off-by: Liviu Dudau
> Reviewed-by: Rob Herr
ly interested. But I
believe in most cases, converting them to DT should be quite easy.
Best regards,
Thomas
--
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Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
__
ons, it will be a
clean platform, and we can merge it into mach-mvebu without any
problem.
So let's continue the cleanup work, conversion to DT, usage of drivers
in drivers/, improvement of pinmux to support orion5x/mv78xx0, and do
the move per-platform, once they are ready.
What do you thi
' rather than above of_irq_map_pci to be
> consistent with the rest of the file.
Right, sounds good.
Do we have some news from the PowerPC and Microblaze maintainers about
their acceptance of PATCH 1/3 ? This of/pci thing is the only last
remaining patch for which I need a Ack to get the
uct pci_controller *hose,
+ struct device_node *dev, int primary);
+
#endif
But otherwise, for PATCH 1/3 and 2/3,
Tested-by: Thomas Petazzoni
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, con
the Marvell
PCIe driver I'm hoping to get merged in 3.10.
Thanks a lot for your feedback,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
__
Dear Bjorn Helgaas,
On Tue, 9 Apr 2013 15:12:58 -0600, Bjorn Helgaas wrote:
> On Tue, Apr 9, 2013 at 3:06 PM, Thomas Petazzoni
> wrote:
> > This driver implements the support for the PCIe interfaces on the
> > Marvell Armada 370/XP ARM SoCs. In the future, it might be ext
: Thomas Petazzoni
---
arch/arm/configs/mvebu_defconfig |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2ec8119..071a5b1 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -13,6
The Marvell Armada XP GP board has 3 physical full-size PCIe slots, so
we enable the corresponding PCIe interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-xp-gp.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm
The Marvell evaluation board (DB) for the Armada 370 SoC has 2
physical full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-370-db.dts | 17 +
1 file changed, 17 insertions
The Globalscale Mirabox platform uses one PCIe interface for an
available mini-PCIe slot, and the other PCIe interface for an internal
USB 3.0 controller. We add the necessary Device Tree informations to
enable those two interfaces.
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada
The Marvell evaluation board (DB) for the Armada XP SoC has 6
physicals full-size PCIe slots, so we enable the corresponding PCIe
interfaces in the Device Tree.
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-xp-db.dts | 33 +
1 file changed, 33
The PlatHome OpenBlocks AX3-4 has an internal mini-PCIe slot that can
be used to plug mini-PCIe devices. We therefore enable the PCIe
interface that corresponds to this slot.
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts |9 +
1 file changed, 9
informations to make those PCIe interfaces
usable.
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 104 +
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 122 +++
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 188 ++
3
The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the
necessary Device Tree informations to make these interfaces availabel.
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/armada-370.dtsi | 51 +
1 file changed, 51 insertions(+)
diff
Now that the PCIe driver for mvebu has been integrated and all its
relevant dependencies, we can mark the ARCH_MVEBU platform has
MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.
Signed-off-by: Thomas Petazzoni
---
arch/arm/mach-mvebu/Kconfig |2 ++
1 file changed, 2
-mvebu/addr-map.c.
Signed-off-by: Thomas Petazzoni
Acked-by: Bjorn Helgaas
---
.../devicetree/bindings/pci/mvebu-pci.txt | 220 +
drivers/pci/host/Kconfig |4 +
drivers/pci/host/Makefile |2 +-
drivers/pci/host/pci-mvebu.c
those PCIe interfaces.
It also changes the name of the previously existing PCIe gatable
clocks, in order to match the naming using the datasheets.
Signed-off-by: Thomas Petazzoni
Cc: Mike Turquette
---
drivers/clk/mvebu/clk-gating-ctrl.c | 14 ++
1 file changed, 10 insertions(+), 4
The Armada 370 has two gatable clocks for each PCIe interface, and we
want both of them to be enabled. We therefore make one of the two
clocks a child of the other, as we did for the sataX and sataXlnk
clocks on Armada XP.
Signed-off-by: Thomas Petazzoni
Cc: Mike Turquette
---
drivers/clk
egister a align_resource() hook, and do
its own specific alignement, depending on the specific constraints of
the underlying hardware.
Signed-off-by: Thomas Petazzoni
Cc: Russell King
---
arch/arm/include/asm/mach/pci.h | 11 +++
arch/arm/kernel/bios32.c|6 ++
2 files ch
As agreed by the community, PCI host drivers will now be stored in
drivers/pci/host. This commit adds this directory and the related
Kconfig/Makefile changes to allow new drivers to be added in this
directory.
Signed-off-by: Thomas Petazzoni
Acked-by: Bjorn Helgaas
---
drivers/pci/Kconfig
From: Thierry Reding
This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.
Signed-off-by: Thierry Reding
---
drivers/of/of_pci.c| 25 +
include/linux/of_pci.h |1 +
2 files changed, 26 insertions(+)
dif
From: Thierry Reding
This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.
Signed-off-by: Thierry Reding
Signed-off-by: Thomas
From: Andrew Murray
This patch converts the pci_load_of_ranges function to use the new
common of_pci_range_parser.
Signed-off-by: Andrew Murray
Signed-off-by: Liviu Dudau
Signed-off-by: Thomas Petazzoni
Cc: mon...@monstr.eu
Cc: b...@kernel.crashing.org
Cc: pau...@samba.org
Cc: Ralf Baechle
merges them into a single range (as was the case with powerpc and
microblaze).
Signed-off-by: Andrew Murray
Signed-off-by: Liviu Dudau
Signed-off-by: Thomas Petazzoni
Cc: mon...@monstr.eu
Cc: b...@kernel.crashing.org
Cc: pau...@samba.org
Cc: Ralf Baechle
---
drivers/
by: Andrew Murray
Signed-off-by: Liviu Dudau
Signed-off-by: Thomas Petazzoni
Cc: mon...@monstr.eu
Cc: b...@kernel.crashing.org
Cc: pau...@samba.org
Cc: Ralf Baechle
---
arch/microblaze/include/asm/pci-bridge.h |5 +-
arch/microblaze/pci/pci-common.c | 192
t only 64 KB for I/O windows and 1
MB for memory windows).
* Clarified the commit log of "clk: mvebu: create parent-child
relation for PCIe clocks on Armada 370"
Thanks,
Thomas
Andrew Murray (3):
of/pci: Unify pci_process_bridge_OF_ranges from Microblaze and
PowerPC
o
Shouldn't this last line be using "min()" so that we guarantee we don't
have an I/O region that goes beyond IO_SPACE_LIMIT?
Thanks,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting,
rst port should get ports 0x1000 to 0x, later
> ones can used the entire 65536 ports e.g. 0x1 to 0x1.
Then I guess it should work with the code I'm proposing here, no?
Note: this pcie->realio region is global: it will be shared by all PCIe
interfaces.
Thomas
--
Thomas Pet
ial
cflags.
For sure, I'll send a v8 that has those cflags removed, they are
unneeded.
Sorry for this.
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
__
Dear Bjorn Helgaas,
On Mon, 8 Apr 2013 14:29:59 -0600, Bjorn Helgaas wrote:
> > Signed-off-by: Thomas Petazzoni
> >
>
> Acked-by: Bjorn Helgaas
>
> A few trivial comments below; it's up to you whether you do anything
> with them or not. It's OK with m
Mike,
Could we have your opinion on the below patch, and possibly an Acked-by
to carry it through the arm-soc tree?
Thanks,
Thomas
On Wed, 27 Mar 2013 15:40:24 +0100, Thomas Petazzoni wrote:
> The current revision of the datasheet only mentions the gatable clocks
> for the PCIe 0.0, 0.
Mike,
Could we have your opinion on this patch, and possibly a Acked-by to
pass it through arm-soc?
Thanks!
Thomas
On Wed, 27 Mar 2013 15:40:23 +0100, Thomas Petazzoni wrote:
> The Armada 370 has two gatable clocks for each PCIe interface, and we
> want both of them to be enabled. We the
ounds like a good idea. I'll cook a patch set later today and I'll
send it.
Thanks for the suggestion!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
_
not
hesitate to request for additional ones as needed.
Thanks a lot for your support,
Thomas
On Wed, 27 Mar 2013 15:40:17 +0100, Thomas Petazzoni wrote:
> Hello,
>
> This series of patches introduces PCIe support for the Marvell Armada
> 370 and Armada XP. In the future, we plan to e
l finalize the cleanup of the kirkwood PCIe branch in
order to be able to submit a version that hopefully should be
acceptable.
Thanks,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and suppo
19:05:01 +0100, Thomas Petazzoni wrote:
> The target and attributes for the PCIe address decoding windows were
> not correct on Kirkwood for the second PCIe interface.
>
> Signed-off-by: Thomas Petazzoni
> ---
> Note: this patch should be merged with the existing
Dear Neil Greatorex,
On Thu, 28 Mar 2013 00:28:02 +, Neil Greatorex wrote:
> Surely this patch should include the drivers/pci/host/Makefile or it will
> not build?
Ah, correct. I'll fix that up in the v8. Thank you for noticing!
Best regards,
Thomas
--
Thomas Petazzoni, Fre
Dear Jason Gunthorpe,
On Wed, 27 Mar 2013 12:35:34 -0600, Jason Gunthorpe wrote:
> On Wed, Mar 27, 2013 at 07:05:02PM +0100, Thomas Petazzoni wrote:
>
> This all looks really great to me, I hope to try it as well when I get
> time. But just one small suggestion:
>
> > diff
Arnd,
On Wed, 27 Mar 2013 19:11:14 +0100, Thomas Petazzoni wrote:
> > I assume it works with PIO, but does the SATA card use the I/O
> > space registers, or just memory space?
>
> Both cards only use memory space. I have a quick and dirty patch for
> the e1000e driver tha
, this patch set is for now just to show that it works, there
are some adjustments to be made here and there before those patches are
ready to be merged.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and
interfaces (because that's the board
I have in my hands). We'll probably have to create two separate Device
Trees to distinguish between those two boards.
Signed-off-by: Thomas Petazzoni
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/kirkwood-db-88f6281.dt
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