> So then you need to produce a changelog entry by hand.
I had this problem on some old Ubuntu 18.04. Anyway, here's new ChangeLog:
libstdc++-v3/ChangeLog:
* include/std/variant: Fix -Wignored-qualifiers
in system headers.
>That doesn't test this header at all.
It do
On 8/28/20 1:29 AM, Martin Sebor wrote:
With --enable-valgrind-annotations the change to the member function
signature in this patch triggers compilation errors during bootstrap:
I must confirm I didn't tested the configuration. Feel free to install
the patch, it's obvious.
Thank you,
Martin
On Thu, Aug 27, 2020 at 3:20 PM Jakub Jelinek wrote:
>
> On Thu, Aug 27, 2020 at 03:07:59PM +0200, Richard Biener wrote:
> > > Also, isn't the pass also useful for TARGET_AVX and above (but in that
> > > case
> > > only if it is a simple memory load)? Or are avx/avx2 broadcast slower
> > > than
>Test suite confirmation:
>All tests pass. Tested on both Manjaro and some Ubuntu 18.04 with gcc10
and gcc8 respectively.
Jonathan, one more thing. I hope it's what you asked for cause all I did
was:
make bootstrap
make check
On Fri, 28 Aug 2020 at 08:32, Krystian Kuźniarek <
krystian.kuznia...@g
Ok, so here it is.
New diff:
diff --git a/libstdc++-v3/include/bits/atomic_base.h
b/libstdc++-v3/include/bits/atomic_base.h
index 015acef83c4..c4a763aae5c 100644
--- a/libstdc++-v3/include/bits/atomic_base.h
+++ b/libstdc++-v3/include/bits/atomic_base.h
@@ -231,7 +231,8 @@ _GLIBCXX_BEGIN_NAMESPACE
gcc/ChangeLog:
* config.gcc (C-SKY): Add compatibility of elf target name.
libgcc/ChangeLog:
* config.host (C-SKY): Add compatibility of elf target name.
---
gcc/config.gcc | 2 +-
libgcc/config.host | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc
On Fri, Aug 28, 2020 at 10:48:43AM +0930, Alan Modra wrote:
> On Thu, Aug 27, 2020 at 03:17:45PM -0500, Segher Boessenkool wrote:
> > On Thu, Aug 27, 2020 at 01:51:25PM -0500, Bill Schmidt wrote:
> > It not the copy that is unnecessary: the preventing it *here*, manually,
> > is what is unnecessary
On Mon, Aug 24, 2020 at 6:12 PM Jeff Law wrote:
> On Thu, 2020-08-06 at 12:42 +, Pip Cet via Gcc-patches wrote:
> > I've bootstrapped and run the test suite with the patch, without
> > differences.
> So it looks like Richard has given you some feedback and you've got some
> further
> work to
On Thu, Aug 27, 2020 at 03:47:19PM -0500, will schmidt wrote:
> > (Fm): New mode attribute for floating point scalars.
>
> Mixed feels on mixed case, but I defer. :-)
It is similar to other mode attributes (Ff, Fv) used for setting constraints
based on the mode.
--
Michael Meissner, IBM
IB
Hi Iain
Iain Sandoe wrote:
>Richard Sandiford wrote:
>> "Qian, Jianhua" writes:
>>> Hi Richard
>>>
>>> I found that some instructions are using '#' before immediate value，
>>> and others are not. For example
>>> (define_insn "insv_imm"
>>> [(set (zero_extract:GPI (match_operand:GPI 0 "registe
#pragma region is a feature introduced by Microsoft in order to allow
manual grouping and folding of code within Visual Studio. It is
entirely ignored by the compiler. Clang has supported this feature
since 2012 when in MSVC compatibility mode, and enabled it across the
board 3 months ago.
As it
On Thu, Aug 27, 2020 at 03:17:45PM -0500, Segher Boessenkool wrote:
> On Thu, Aug 27, 2020 at 01:51:25PM -0500, Bill Schmidt wrote:
> It not the copy that is unnecessary: the preventing it *here*, manually,
> is what is unnecessary.
Blame me for the original !rtx_equal_p in rs6000_call_aix that Bi
With --enable-valgrind-annotations the change to the member function
signature in this patch triggers compilation errors during bootstrap:
/src/gcc/trunk/gcc/ggc-common.c: In function ‘void gt_pch_save(FILE*)’:
/src/gcc/trunk/gcc/ggc-common.c:509:33: error: no matching function for
call to ‘vec:
This libgo patch by Maciej W. Rozycki removes a middle dot from the
gotest shell script. There was a U+00B7 middle dot character, placed
after "mips64p32le" in the target lists, which is now changed to a
space. The U+00B7 character may not be considered whitespace by
Bourne shell and any non-ASCI
Hi,
this patch adds two static methods to ipa_call_context which construct
and return the object in the two scenarios where we use them (what if
an edge was inlined, what if a node wascloned) which saves callers a
bit work and are more intuitive.
The next step is to make ipa_call_context::estimat
Hi, Honza.
Again, thank you for your detailed review!
On 08/27, Jan Hubicka wrote:
> > When using the LTO infrastructure to compile files in parallel, we
> > can't simply use any of the LTO partitioner, once extra dependency
> > analysis is required to ensure that some nodes are correctly
> > par
This implements the changes from P0548 "common_type and duration". That
was a change for C++17, but as it corrects some issues introduced by DRs
I'm also treating it as a DR and changing it for all modes from C++11
up.
The main change is that duration::period no longer denotes P, but
rather P::typ
Hi,
this large patch is a semi-mechanical change which aims to replace
uses of separate vectors about known scalar values (usually called
known_vals or known_csts), known aggregate values (known_aggs), known
virtual call contexts (known_contexts) and known value
ranges (known_value_ranges) with us
On Thu, 27 Aug 2020, Martin Sebor via Gcc-patches wrote:
> The attached change has match_builtin_function_types() fail
> for erroneous argument types to prevent an ICE due to assuming
> they are necessarily valid.
OK.
--
Joseph S. Myers
jos...@codesourcery.com
On Wed, 2020-08-26 at 22:46 -0400, Michael Meissner via Gcc-patches wrote:
> PowerPC: Add power10 xscmp{eq,gt,ge}qp support.
>
> This patch adds the conditional move support. In adding the conditional move
> support, the optimizers will be able to convert things like:
>
> a = (b > c) ? b :
On Wed, 2020-08-26 at 22:45 -0400, Michael Meissner via Gcc-patches wrote:
> PowerPC: Add power10 xsmaxcqp/xsmincqp support.
>
> This patch adds support for the ISA 3.1 (power10) IEEE 128-bit "C" minimum and
> maximum functions. Because of the NaN differences, the built-in functions
> will
> onl
On Wed, 2020-08-26 at 22:44 -0400, Michael Meissner via Gcc-patches wrote:
> PowerPC: Rename functions for min, max, cmove.
>
> This patch renames the functions that generate the ISA 3.0 C minimum, C
> maximum, and conditional move instructions to use a better name than just
> using
> a _p9 suffi
On Wed, 2020-08-26 at 22:43 -0400, Michael Meissner via Gcc-patches wrote:
> PowerPC: Change cmove function return to bool.
>
> In doing the other work for adding ISA 3.1 128-bit minimum, maximum, and
> conditional move support, I noticed the two functions that process conditional
> moves return '
Excerpts from Jakub Jelinek's message of August 27, 2020 12:06 pm:
> On Fri, Jul 31, 2020 at 04:28:05PM -0400, Jason Merrill via Gcc-patches wrote:
>> On 7/31/20 6:06 AM, Jakub Jelinek wrote:
>> > On Fri, Jul 31, 2020 at 10:54:46AM +0100, Jonathan Wakely wrote:
>> > > > Does the standard require th
Hi!
On Thu, Aug 27, 2020 at 08:47:19PM +0800, Jojo R wrote:
> +insn-emit-split-c = $(foreach o, $(shell for i in
> {1..$(insn-generated-split-num)}; do echo $$i; done), insn-emit$(o).c)
If you use a variable for the result of that "seq", this will be more
readable / maintainable / etc.
(Should
On Thu, Aug 27, 2020 at 01:51:25PM -0500, Bill Schmidt wrote:
> >>+ /* For ELFv2, r12 and CTR need to hold the function address
> >>+ for an indirect call. */
> >>+ if (GET_CODE (func_desc) != SYMBOL_REF && DEFAULT_ABI == ABI_ELFv2)
> >>+{
> >>+ r12 = gen_rtx_REG (Pmode, 12);
> >>+
Due to revisions to hppa_rtx_costs by Roger Sayle, we now have shift add
instructions in
the shadd-2.c test. Committed to trunk and gcc-10 branch.
Dave
Fix shadd-2.c scan assembler count.
2020-08-27 John David Anglin
gcc/testsuite/
* gcc.target/hppa/shadd-2.c: Adjust times to 4.
d
Hi Roger,
On 2020-08-27 12:42 p.m., Roger Sayle wrote:
> I was wondering whether you could please "put this in the queue", and
> reconfirm that PR middle-end/87256 remains resolved?
>
>
> 2020-08-27 Roger Sayle
>
> gcc/ChangeLog
> * config/pa/pa.c (hppa_rtx_costs) [ASHIFT, ASHIFTRT, LSHIF
Hi!
On 8/27/20 1:41 PM, Segher Boessenkool wrote:
Hi!
On Thu, Aug 27, 2020 at 08:21:34AM -0500, Bill Schmidt wrote:
+ /* For ELFv2, r12 and CTR need to hold the function address
+ for an indirect call. */
+ if (GET_CODE (func_desc) != SYMBOL_REF && DEFAULT_ABI == ABI_ELFv2)
+{
+
Hi!
On Thu, Aug 27, 2020 at 08:21:34AM -0500, Bill Schmidt wrote:
> + /* For ELFv2, r12 and CTR need to hold the function address
> + for an indirect call. */
> + if (GET_CODE (func_desc) != SYMBOL_REF && DEFAULT_ABI == ABI_ELFv2)
> +{
> + r12 = gen_rtx_REG (Pmode, 12);
> + if
On Thu, Aug 27, 2020 at 08:43:40AM -0700, Carl Love wrote:
> 2020-08-26 Carl Love
> * config/rs6000/rs6000-builtin.def: (BU_P10V_VSX_1) New builtin macro
> expansion.
> (XVCVBF16SPN, XVCVSPBF16): Replace macro expansion BU_VSX_1 with
> BU_P10V_VSX_1.
> * config/rs6000/rs6000-
Hi, Honza.
Thank you for your detailed review!
On 08/27, Jan Hubicka wrote:
> > diff --git a/gcc/cgraph.c b/gcc/cgraph.c
> > index c0b45795059..22405098dc5 100644
> > --- a/gcc/cgraph.c
> > +++ b/gcc/cgraph.c
> > @@ -226,6 +226,22 @@ cgraph_node::delete_function_version_by_decl (tree
> > decl)
>
On Thu, 2020-08-27 at 17:42 +0100, Roger Sayle wrote:
> Hi Dave (and Jeff),
> For your consideration, here's a patch that should fix the recent regression
> of gcc.dg/tree-ssa/slrt-13.c on hppa targets.
>
> This patch provides more accurate rtx_costs estimates for shifts by
> integer constants (wh
On 8/14/20 11:04 AM, Jeff Chapman wrote:
Hello!
Attached is a patch that fixes an ICE on the devel/c++-modules branch caused
by a slot invalidation edge case in push_namespace.
I just fell over this myself, reducing a testcase. your fix wasn;t
quite right -- we were creating an empty slot in
The attached change has match_builtin_function_types() fail
for erroneous argument types to prevent an ICE due to assuming
they are necessarily valid.
Martin
PR c/96596 - ICE in match_builtin_function_types on a declaration of a built-in with invalid array argument
gcc/c/ChangeLog:
PR c/96596
Hello,
Following on from the earlier patch to fix up the syntax for
add/sub/adds/subs and friends with a sign/zero-extended operand [0],
this patch removes the "mult" variants of these patterns which are
all redundant.
This patch removes the following patterns from the AArch64 backend:
*adds_mu
On Thu, Aug 27, 2020 at 4:45 PM H.J. Lu wrote:
> > > > > > How about target("baseline-isas-only")? All CPUID functions are
> > > > > > inlined.
> > > > >
> > > > > No, I don't think this is a good idea. Now consider the situation that
> > > > > caller functions are compiled with e.g. -mgeneral-re
"Kewen.Lin" writes:
> Hi Richard,
>
>>> Yeah, the comments were confusing, its intent is to check which targets
>>> support partial vectors and which usage to be used.
>>>
>>> How about to update them like:
>>>
>>> "Return true if loops using partial vectors are supported and usage kind is
>>> 1/2
On 27/08/20 12:37 -0400, Patrick Palka wrote:
On Thu, 27 Aug 2020, Jonathan Wakely wrote:
On 27/08/20 11:29 -0400, Patrick Palka via Libstdc++ wrote:
> This fixes the months-based addition for year_month when the
> year_month's month component is zero.
>
> Successfully tested on x86_64-pc-linux
Hi Dave (and Jeff),
For your consideration, here's a patch that should fix the recent regression
of gcc.dg/tree-ssa/slrt-13.c on hppa targets.
This patch provides more accurate rtx_costs estimates for shifts by
integer constants (which are cheaper than by a register amount).
Fine tuning these is
On Thu, 27 Aug 2020, Jonathan Wakely wrote:
> On 27/08/20 11:29 -0400, Patrick Palka via Libstdc++ wrote:
> > This fixes the months-based addition for year_month when the
> > year_month's month component is zero.
> >
> > Successfully tested on x86_64-pc-linux-gnu, on the 'date' library's
> > cale
On 25/08/20 15:47 -0400, Patrick Palka via Libstdc++ wrote:
My original patch that implemented the calendar type operations failed
to enforce a constraint on some of the addition/subtraction operator
overloads that take a 'months' argument:
Constraints: If the argument supplied by the caller fo
On 27/08/20 11:29 -0400, Patrick Palka via Libstdc++ wrote:
This fixes the months-based addition for year_month when the
year_month's month component is zero.
Successfully tested on x86_64-pc-linux-gnu, on the 'date' library's
calendar and (now) on libcxx's calendar tests. Does this look OK to
GCC maintainers:
The following patch has been updated based on the comments from Will
and Segher.
The patch is a subset of the mainline commit:
commit
07d456bb80a16405723c98c2ab74ccc2a5a23898
Author: Carl Love
> On Thu, 20 Aug 2020, Giuliano Belinassi via Gcc-patches wrote:
>
> > libbacktrace/Makefile.in | 2 +-
> > zlib/Makefile.in | 64 ++--
>
> These directories use makefiles generated by automake. Rather than
> modifying the generated files, you need to modify the sources (whet
> diff --git a/gcc/cgraph.c b/gcc/cgraph.c
> index c0b45795059..22405098dc5 100644
> --- a/gcc/cgraph.c
> +++ b/gcc/cgraph.c
> @@ -226,6 +226,22 @@ cgraph_node::delete_function_version_by_decl (tree decl)
>decl_node->remove ();
> }
>
> +/* Release function dominator info if present. */
> +
This fixes the months-based addition for year_month when the
year_month's month component is zero.
Successfully tested on x86_64-pc-linux-gnu, on the 'date' library's
calendar and (now) on libcxx's calendar tests. Does this look OK to
commit?
libstdc++-v3/ChangeLog:
* include/std/chrono
> We also implemented a GNU Make Jobserver integration to this mechanism,
> as implemented in jobserver.cc. This works as follows:
> diff --git a/gcc/jobserver.cc b/gcc/jobserver.cc
> new file mode 100644
> index 000..8cb374de86e
> --- /dev/null
> +++ b/gcc/jobserver.cc
I wonder if this ca
> When using the LTO infrastructure to compile files in parallel, we
> can't simply use any of the LTO partitioner, once extra dependency
> analysis is required to ensure that some nodes are correctly
> partitioned together.
>
> Therefore, here we implement a new partitioner called
> "lto_merge_co
On Thu, Aug 27, 2020 at 5:20 AM Uros Bizjak wrote:
>
> On Thu, Aug 27, 2020 at 10:35 AM Jakub Jelinek wrote:
> >
> > Hi!
> >
> > For _Atomic fields, lowering the alignment of long long or double etc.
> > fields on ia32 is undesirable, because then one really can't perform atomic
> > operations on
On Tue, Aug 25, 2020 at 5:27 AM Uros Bizjak wrote:
>
> On Tue, Aug 25, 2020 at 2:13 PM H.J. Lu wrote:
> >
> > On Mon, Aug 24, 2020 at 12:40 PM H.J. Lu wrote:
> > >
> > > On Mon, Aug 24, 2020 at 12:25 PM Uros Bizjak wrote:
> > > >
> > > > On Mon, Aug 24, 2020 at 6:17 PM H.J. Lu wrote:
> > > > >
On Thu, Aug 27, 2020 at 9:21 AM Bill Schmidt wrote:
>
> Prior to P10, ELFv2 hasn't implemented nonlocal sibcalls. Now that we do,
> we need to be sure that r12 is set up prior to such a call.
>
> Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
> regressions. Is this okay for tru
On Thu, Aug 27, 2020 at 08:21:34AM -0500, Bill Schmidt wrote:
> Prior to P10, ELFv2 hasn't implemented nonlocal sibcalls. Now that we do,
> we need to be sure that r12 is set up prior to such a call.
>
> Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
> regressions. Is this okay
In comment 14 from PR94538, it was suggested to switch off jump tables
on thumb-1 cores when using -mpure-code, like we already do for thumb-2.
This is what this patch does, and also restores the previous value of
CASE_VECTOR_PC_RELATIVE since it was not the right way of handling
this.
It also ad
Prior to P10, ELFv2 hasn't implemented nonlocal sibcalls. Now that we do,
we need to be sure that r12 is set up prior to such a call.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for trunk?
Thanks,
Bill
2020-08-27 Bill Schmidt
gcc/
PR
On Thu, Aug 27, 2020 at 03:07:59PM +0200, Richard Biener wrote:
> > Also, isn't the pass also useful for TARGET_AVX and above (but in that case
> > only if it is a simple memory load)? Or are avx/avx2 broadcast slower than
> > full vector loads?
> >
> > As Jeff wrote, I wonder if when successfully
This simple patch rewords a comment in cfgloop.h to improve the
grammar and readability.
OK for master?
Thanks,
Alex
---
gcc/ChangeLog:
* cfgloop.h (nb_iter_bound): Reword comment describing is_exit.
diff --git a/gcc/cfgloop.h b/gcc/cfgloop.h
index 18b404e292f..be978288aab 100644
---
On Thu, Aug 27, 2020 at 2:25 PM Jakub Jelinek via Gcc-patches
wrote:
>
> On Thu, Jul 09, 2020 at 04:33:46PM +0800, Hongtao Liu via Gcc-patches wrote:
> > +static void
> > +replace_constant_pool_with_broadcast (rtx_insn* insn)
> > +{
> > + subrtx_ptr_iterator::array_type array;
> > + FOR_EACH_SUB
Hi,
Ok & thanks, I will reroll this :)
Jojo
在 2020年8月26日 +0800 AM4:22，Jeff Law ，写道：
> On Fri, 2020-08-21 at 14:18 +0800, Jojo R wrote:
> > gcc/ChangeLog:
> >
> > * config/csky/csky.opt (TARGET_BACKTRACE): New.
> > * doc/invoke.texi (C-SKY Options): Document -mbacktrace.
> ISTM you need an
gcc/ChangeLog:
* genemit.c (main): Print 'split line'.
* Makefile.in (insn-emit.c): Define split count and file
---
gcc/Makefile.in | 15 +
gcc/genemit.c | 87 -
2 files changed, 64 insertions(+), 38 deletions(-)
diff --g
Jojo
在 2020年8月2日 +0800 AM8:09，Segher Boessenkool ，写道：
> On Sat, Aug 01, 2020 at 07:02:07PM +0800, Jojo R wrote:
> > +insn-generated-split-num = $(shell nproc)
>
> nproc isn't portable, is not the same on every system, and can lead to
> a number of processes quadratic in the number of processors b
This carries over the PR87609 fix also to RTL loop unrolling. The
gcc.dg/torture/pr90328.c testcase otherwise is miscompiled with
the tree-ssa-address.c hunk (or alternatively with -fno-ivopts
on master). I've tried to find the correct abstraction and
adjusted two other duplicate_insn_chain users
This removes the bogus tranfer of flow-sensitive info in copy_ref_info
plus fixes one oversight in FRE when flow-sensitive non-NULLness was added to
points-to info.
Bootstrapped / tested on x86_64-unknown-linux-gnu, pushed.
2020-08-27 Richard Biener
PR tree-optimization/96522
On Thu, Jul 09, 2020 at 04:33:46PM +0800, Hongtao Liu via Gcc-patches wrote:
> +static void
> +replace_constant_pool_with_broadcast (rtx_insn* insn)
> +{
> + subrtx_ptr_iterator::array_type array;
> + FOR_EACH_SUBRTX_PTR (iter, array, &PATTERN (insn), ALL)
> +{
> + rtx *loc = *iter;
> +
On Thu, Aug 27, 2020 at 10:35 AM Jakub Jelinek wrote:
>
> Hi!
>
> For _Atomic fields, lowering the alignment of long long or double etc.
> fields on ia32 is undesirable, because then one really can't perform atomic
> operations on those using cmpxchg8b.
>
> The following patch stops lowering the a
On Thu, Aug 27, 2020 at 11:13:50AM +, Hu, Jiangping wrote:
> I'm not sure about if the case should fail.
> So, I add Jakub who committed this testcase.
>
> I thought the case should success, but for changes of gcc of
> years, now it failed. So I think that may be some optimization
> are unnece
On 27/08/20 13:17 +0200, Jakub Jelinek wrote:
On Thu, Aug 27, 2020 at 12:06:59PM +0100, Jonathan Wakely wrote:
On 27/08/20 12:46 +0200, Jakub Jelinek wrote:
> On Thu, Aug 27, 2020 at 12:06:13PM +0200, Jakub Jelinek via Gcc-patches wrote:
>
> Oops, rewrote the testcase from __builtin_bit_cast to
On Thu, 27 Aug 2020 at 11:02, Ramana Radhakrishnan
wrote:
>
> On Mon, Aug 24, 2020 at 4:35 PM Christophe Lyon
> wrote:
> >
> > On Mon, 24 Aug 2020 at 11:09, Christophe Lyon
> > wrote:
> > >
> > > On Sat, 22 Aug 2020 at 00:44, Ramana Radhakrishnan
> > > wrote:
> > > >
> > > > On Wed, Aug 19, 202
On Thu, Aug 27, 2020 at 12:06:59PM +0100, Jonathan Wakely wrote:
> On 27/08/20 12:46 +0200, Jakub Jelinek wrote:
> > On Thu, Aug 27, 2020 at 12:06:13PM +0200, Jakub Jelinek via Gcc-patches
> > wrote:
> >
> > Oops, rewrote the testcase from __builtin_bit_cast to std::bit_cast without
> > adjusting
Hi, Richard, Jakub
Thanks for reply.
I'm not sure about if the case should fail.
So, I add Jakub who committed this testcase.
I thought the case should success, but for changes of gcc of
years, now it failed. So I think that may be some optimization
are unnecessary for this testcase, and I foun
> Under what circumstances are we seeing a SEQUENCE in the x86 backend? I'm
> surprised we need to handle that case.
>
> So your pass modifies the insn in place, which is fine. But do we actually
> remove the original constant pool entry if it's no longer used? If not, does
> this patch actuall
The following streamlines TARGET_MEM_REF dumping building
on what we do for MEM_REF and thus dumping things like
access type, TBAA type and base/clique. I've changed it
to do semantic dumping aka base + offset + step * index
rather than the odd base: A, step: way.
Bootstrapped and tested on x86_6
On 27/08/20 12:46 +0200, Jakub Jelinek wrote:
On Thu, Aug 27, 2020 at 12:06:13PM +0200, Jakub Jelinek via Gcc-patches wrote:
Oops, rewrote the testcase from __builtin_bit_cast to std::bit_cast without
adjusting the syntax properly.
Also, let's not use bitfields in there, as clang doesn't support
On 27/08/20 12:06 +0200, Jakub Jelinek wrote:
On Fri, Jul 31, 2020 at 04:28:05PM -0400, Jason Merrill via Gcc-patches wrote:
On 7/31/20 6:06 AM, Jakub Jelinek wrote:
> On Fri, Jul 31, 2020 at 10:54:46AM +0100, Jonathan Wakely wrote:
> > > Does the standard require that somewhere? Because that i
On Thu, Aug 27, 2020 at 12:06:13PM +0200, Jakub Jelinek via Gcc-patches wrote:
Oops, rewrote the testcase from __builtin_bit_cast to std::bit_cast without
adjusting the syntax properly.
Also, let's not use bitfields in there, as clang doesn't support those.
So, adjusted testcase below. clang++ re
On Thu, Aug 27, 2020 at 1:47 AM Richard Biener
wrote:
>
> On Wed, Aug 26, 2020 at 9:40 PM H.J. Lu via Gcc-patches
> wrote:
> >
> > Reject target("no-general-regs-only") pragma and attribute.
>
> mgeneral-regs-only
> Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags)
> Sa
On Thu, Aug 27, 2020 at 9:17 AM Roger Sayle wrote:
>
>
> >On 2020-08-26 5:23 p.m., Roger Sayle wrote:
> >> These more accurate target rtx_costs are used by the
> >> gimple-ssa-strength-reduction.c (via a call to mult_by_coeff_cost) to
> >> decide whether applying strength reduction would be profit
On Thu, 27 Aug 2020, Jakub Jelinek wrote:
> On Fri, Jul 31, 2020 at 04:28:05PM -0400, Jason Merrill via Gcc-patches wrote:
> > On 7/31/20 6:06 AM, Jakub Jelinek wrote:
> > > On Fri, Jul 31, 2020 at 10:54:46AM +0100, Jonathan Wakely wrote:
> > > > > Does the standard require that somewhere? Becaus
On Fri, Jul 31, 2020 at 04:28:05PM -0400, Jason Merrill via Gcc-patches wrote:
> On 7/31/20 6:06 AM, Jakub Jelinek wrote:
> > On Fri, Jul 31, 2020 at 10:54:46AM +0100, Jonathan Wakely wrote:
> > > > Does the standard require that somewhere? Because that is not what the
> > > > compiler implements
From: gengq
gcc/ChangeLog:
* config/csky/constraints.md (W): New constriant for mem operand with
a base reg with a index register.
(Q): Renamed and modified "csky_valid_fpuv2_mem_operand" to
"csky_valid_mem_constraint_operand" to deal with both "Q" and "W"
On Thu, Aug 27, 2020 at 3:38 AM Hu Jiangping wrote:
>
> This patch add -fno-tree-fre to dg-options in gcc.dg/guality/sra-1.c,
> to make the following testcases passed.
>
> FAIL: gcc.dg/guality/sra-1.c -Og -DPREVENT_OPTIMIZATION line 43 a.i == 4
> FAIL: gcc.dg/guality/sra-1.c -Og -DPREVENT_OPTIM
On Mon, Aug 24, 2020 at 4:35 PM Christophe Lyon
wrote:
>
> On Mon, 24 Aug 2020 at 11:09, Christophe Lyon
> wrote:
> >
> > On Sat, 22 Aug 2020 at 00:44, Ramana Radhakrishnan
> > wrote:
> > >
> > > On Wed, Aug 19, 2020 at 10:32 AM Christophe Lyon via Gcc-patches
> > > wrote:
> > > >
> > > > armv8
On Wed, Aug 26, 2020 at 11:02 PM Jeff Law wrote:
>
> On Tue, 2020-08-11 at 13:37 +0200, Martin Liška wrote:
> > From cc1d41a469d76f2f8e4f44bed788ace77a1c6d62 Mon Sep 17 00:00:00 2001
> > From: Martin Liska
> > Date: Mon, 10 Aug 2020 12:09:19 +0200
> > Subject: [PATCH 3/3] vec: use inexact growth
On Wed, Aug 26, 2020 at 9:40 PM H.J. Lu via Gcc-patches
wrote:
>
> Reject target("no-general-regs-only") pragma and attribute.
mgeneral-regs-only
Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save
Generate code which uses only the general registers.
it has already R
Richard Sandiford wrote:
"Qian, Jianhua" writes:
Hi Richard
I found that some instructions are using '#' before immediate value，
and others are not. For example
(define_insn "insv_imm"
[(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r")
(const_int
Hi,
This patch fix a typo in rtl.texi.
Regards!
Weiwt
---
gcc/doc/rtl.texi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi
index 501fa1a31da..f8e1f950823 100644
--- a/gcc/doc/rtl.texi
+++ b/gcc/doc/rtl.texi
@@ -3954,7 +3954,7 @@ variable.
Hi!
For _Atomic fields, lowering the alignment of long long or double etc.
fields on ia32 is undesirable, because then one really can't perform atomic
operations on those using cmpxchg8b.
The following patch stops lowering the alignment in fields for _Atomic
types (the x86_field_alignment change)
xiezhiheng writes:
> I made two separate patches for these two groups for review purposes.
>
> Note: Patch for min/max intrinsics should be applied before the patch for
> rounding intrinsics
>
> Bootstrapped and tested on aarch64 Linux platform.
Thanks, LGTM. Pushed to master.
Richard
This makes sure to put special-ops expanded rhs left where
expression rewrite expects it.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
2020-08-27 Richard Biener
PR tree-optimization/96579
* tree-ssa-reassoc.c (linearize_expr_tree): If we expand
rhs via
"Qian, Jianhua" writes:
> Hi Richard
>
> I found that some instructions are using '#' before immediate value，
> and others are not. For example
> (define_insn "insv_imm"
> [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r")
> (const_int 16)
>
Hi,
This patch add 'cd' command before 'make check-gcc' command
when run the testsuite on selected tests.
I think the implicit meaning of the original text is to
execute the cd command to move to the gcc subdirectory of
the object directory before executing the make command.
However, due to the f
Looks good to me.
Thanks for the patch!
Tobias
On 8/27/20 8:17 AM, Paul Richard Thomas via Fortran wrote:
Hi All,
Here is another of Steve Kargl's patches.
Before the patch is applied, the following code is generated:
atmp.0.span = 4;
atmp.0.data = 0B;
atmp.0.offset = 0;
>On 2020-08-26 5:23 p.m., Roger Sayle wrote:
>> These more accurate target rtx_costs are used by the
>> gimple-ssa-strength-reduction.c (via a call to mult_by_coeff_cost) to
>> decide whether applying strength reduction would be profitable. This test
>> case, slsr-13.c, assumes that two multi
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