Documents operand modifiers which are available in asm stmt but
missing in document.
| Modifier | Description | Available in asm stmt | Existed in documentation |
| --- | --- | --- | - |
| L,W,B,Q,S,T | print the opcode suffix for specified size of
operand. | Available | Not |
| C | pr
Hi:
Test is ok for funcspec-5.c, funcspec-6.c.
gcc/testuite/ChangeLog
* gcc.target/i386/funcspec-56.inc: Add enqcmd, avx512bf16,
avx512vp2intersect.
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 6 ++
1 file changed, 6 insertions(+)
diff --git a/gcc/testsuite/gcc.target/
On Mon, May 4, 2020 at 1:17 AM Uros Bizjak wrote:
>
> On Wed, Apr 1, 2020 at 9:23 AM Hongtao Liu wrote:
> >
> > Hi:
> > This patch is about to enable GCC support for SERIALIZE which would
> > be in GLC. There's only 1 instruction: SERIALIZE, more det
On Mon, May 4, 2020 at 12:58 AM Uros Bizjak wrote:
>
> The part above is OK, but you are missing support for
> __attribute__((__target__("..."))). Please see how for example -msgx
> is handled in isa2_opts in i386-options.c and in
> gcc.target/i386/funcspec-56.h test source.
>
> Please repost the
On Wed, Apr 1, 2020 at 3:32 PM Hongtao Liu wrote:
>
> Hi:
> This patch is about to enable GCC support for TSXLDTRK which would
> be in GLC. There's only 2 instructions: XRESLDTRK, XSUSLDTRK, more
> details please
> refer to
> https://software.intel.com/sites/d
Hi:
This patch is about to enable GCC support for TSXLDTRK which would
be in GLC. There's only 2 instructions: XRESLDTRK, XSUSLDTRK, more
details please
refer to
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
I kno
2001
From: liuhongt
Date: Wed, 4 Mar 2020 14:08:40 +0800
Subject: [PATCH] Enable GCC support for SERIALIZE
2020-03-04 Hongtao Liu
2020-03-04 Wei Xiao
gcc/Changelog:
* gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,
OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.
(ix86_ha
On Tue, Feb 18, 2020 at 7:00 PM Hongtao Liu wrote:
>
> On Tue, Feb 18, 2020 at 4:24 PM Uros Bizjak wrote:
> >
> >
> >
> > On Thu, Feb 13, 2020 at 9:39 AM Uros Bizjak wrote:
> >>
> >> > Changelog
> >> > gcc/
> >> >
On Tue, Feb 18, 2020 at 4:24 PM Uros Bizjak wrote:
>
>
>
> On Thu, Feb 13, 2020 at 9:39 AM Uros Bizjak wrote:
>>
>> > Changelog
>> > gcc/
>> >* config/i386/avx512vbmi2intrin.h
>> >(_mm512_[,mask_,maskz_]shrdi_epi16,
>> >_mm512_[,mask_,maskz_]shrdi_epi32,
>> >_m512_
Done.
On Fri, Feb 14, 2020 at 7:16 PM Uros Bizjak wrote:
>
> On Fri, Feb 14, 2020 at 8:06 AM Uros Bizjak wrote:
> >
> > On Fri, Feb 14, 2020 at 7:03 AM Hongtao Liu wrote:
> > >
> > > On Thu, Feb 13, 2020 at 5:31 PM Hongtao Liu wrote:
> > > >
>
On Thu, Feb 13, 2020 at 5:31 PM Hongtao Liu wrote:
>
> On Thu, Feb 13, 2020 at 5:12 PM Uros Bizjak wrote:
> >
> > On Thu, Feb 13, 2020 at 9:53 AM Jakub Jelinek wrote:
> > >
> > > On Thu, Feb 13, 2020 at 09:39:05AM +0100, Uros Bizjak wrot
On Thu, Feb 13, 2020 at 5:12 PM Uros Bizjak wrote:
>
> On Thu, Feb 13, 2020 at 9:53 AM Jakub Jelinek wrote:
> >
> > On Thu, Feb 13, 2020 at 09:39:05AM +0100, Uros Bizjak wrote:
> > > > Changelog
> > > > gcc/
> > > >* config/i386/avx512vbmi2intrin.h
> > > >(_mm512_[,mask_,maskz_]sh
Hi
As mentioned in PR93724, several intrinsic macros lack a closing
parenthesis. These macros are only used with -O0 option, and currently
unit tests use -O2, so not covered.
Bootstrap ok, regression tests on i386/x86_64 is ok.
Ok for trunk?
Changelog
gcc/
* config/i386/avx512vbmi2in
On Wed, Dec 18, 2019 at 4:26 PM Segher Boessenkool
wrote:
>
> On Wed, Dec 18, 2019 at 10:37:11AM +0800, Hongtao Liu wrote:
> > Hi:
> > This patch is to simplify A * C + (-D) -> (A - D/C) * C when C is a
> > power of 2 and D mod C == 0.
> > bootstrap and make c
On Wed, Dec 18, 2019 at 10:50 AM Andrew Pinski wrote:
>
> On Tue, Dec 17, 2019 at 6:33 PM Hongtao Liu wrote:
> >
> > Hi:
> > This patch is to simplify A * C + (-D) -> (A - D/C) * C when C is a
> > power of 2 and D mod C == 0.
> > bootstrap and make ch
Hi:
This patch is to simplify A * C + (-D) -> (A - D/C) * C when C is a
power of 2 and D mod C == 0.
bootstrap and make check is ok.
changelog
gcc/
* gcc/match.pd (A * C + (-D) = (A - D/C) * C. when C is a
power of 2 and D mod C == 0): Add new simplification.
gcc/testsuite
Hi:
This patch is about to add tune option for integer mask cmov, for
some targets has both integer mask register and sse mask register,
this tune indicates to use integer one. Currently it's default on for
m_CORE_AVX512.
Bootstrap is ok, regression test on i386/x86_64 backends is ok.
ok for
On Wed, Dec 11, 2019 at 3:54 PM Jakub Jelinek wrote:
>
> On Wed, Dec 11, 2019 at 09:55:24AM +0800, Hongtao Liu wrote:
> > Changelog
> > gcc/
> > PR target/92865
> > * config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Enable
> > integer mask cmov
On Tue, Dec 10, 2019 at 4:11 PM Jakub Jelinek wrote:
>
> On Tue, Dec 10, 2019 at 01:47:50PM +0800, Hongtao Liu wrote:
> > This patch is to enable integer mask cmp/cmov under AVX512F even
> > with TARGET_XOP .
> > Bootstrap and regression test on i386/x86_64 backend
Hi jakub:
This patch is to enable integer mask cmp/cmov under AVX512F even
with TARGET_XOP .
Bootstrap and regression test on i386/x86_64 backend is ok.
Changelog:
PR target/92865
* gcc/config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Enable
integer mask cmov when available ev
Hi uros:
This patch is about to rename OPTION_MASK_ISA_$target_[SET,UNSET, ]
to OPTION_MASK_ISA2_$target_[SET,UNSET, ] for those targets setting
x_ix86_isa_flags2.
target list as bellow:
-
188static struct ix86_target_opts isa2_opts[] =
189{
190 { "-mcx16", OPTION_MASK_ISA2_CX
On Thu, Dec 5, 2019 at 4:03 PM Jakub Jelinek wrote:
>
> On Thu, Dec 05, 2019 at 09:56:46AM +0800, Hongtao Liu wrote:
> > --- a/gcc/config/i386/i386-expand.c
> > +++ b/gcc/config/i386/i386-expand.c
> > + /* Using vector move with mask register. */
> > +
On Wed, Dec 4, 2019 at 4:22 PM Jakub Jelinek wrote:
>
> On Wed, Dec 04, 2019 at 10:07:05AM +0800, Hongtao Liu wrote:
> > Changelog
> > gcc/
> > PR target/92686
> > * config/i386/sse.md
> > (*_cmp3,
> > *_cmp3,
> > *_uc
Hi:
Currently for VCOND_EXPR, integer mask operation is only available
for 512-bit vector, but since mask register is related to isa not
vector size, under avx512f we can also have 128/256-bit vector
condition move. My local tests show there's no boost frequency penalty
for using integer mask reg
hi jakub:
VF is used for differentiating AVX512F/AVX/SSE, but there's
condition TARGET_AVX512F in avx512f_maskcmp3, it must be a TYPO
and should be VF_AVX512VL instead.
Bootstrap and regression test on i386/x86_64 backend is ok.
OK for trunk?
diff --git a/gcc/config/i386/sse.md b/gcc/config/i3
On Sat, Nov 16, 2019 at 7:27 AM Jeff Law wrote:
>
> On 11/14/19 5:21 AM, Richard Biener wrote:
> > On Tue, Nov 12, 2019 at 11:35 AM Hongtao Liu wrote:
> >>
> >> Hi:
> >> As mentioned in https://gcc.gnu.org/ml/gcc-patches/2019-11/msg00832.html
> >
On Tue, Nov 12, 2019 at 4:41 PM Richard Biener
wrote:
>
> On Tue, Nov 12, 2019 at 9:29 AM Hongtao Liu wrote:
> >
> > On Tue, Nov 12, 2019 at 4:19 PM Richard Biener
> > wrote:
> > >
> > > On Tue, Nov 12, 2019 at 8:36 AM Hongtao Liu wrote:
> > >
Hi:
As mentioned in https://gcc.gnu.org/ml/gcc-patches/2019-11/msg00832.html
> So yes, it's poorly named. A preparatory patch to clean this up
> (and maybe split it into TARGET_AVX256_SPLIT_REGS and TARGET_AVX128_OPTIMAL)
> would be nice.
Bootstrap and regression test for i386 backend is ok.
On Tue, Nov 12, 2019 at 4:29 PM Richard Biener
wrote:
>
> On Tue, Nov 12, 2019 at 9:19 AM Richard Biener
> wrote:
> >
> > On Tue, Nov 12, 2019 at 8:36 AM Hongtao Liu wrote:
> > >
> > > Hi:
> > > This patch is about to set X86_TUNE_AVX128_OPTIMA
On Tue, Nov 12, 2019 at 4:19 PM Richard Biener
wrote:
>
> On Tue, Nov 12, 2019 at 8:36 AM Hongtao Liu wrote:
> >
> > Hi:
> > This patch is about to set X86_TUNE_AVX128_OPTIMAL as default for
> > all AVX target because we found there's still perfo
Hi:
This patch is about to set X86_TUNE_AVX128_OPTIMAL as default for
all AVX target because we found there's still performance gap between
128-bit auto-vectorization and 256-bit auto-vectorization even with
epilog vectorized.
The performance influence of setting avx128_optimal as default on
SP
Ping!
On Sat, Nov 2, 2019 at 9:38 PM Hongtao Liu wrote:
>
> Hi Jakub:
> Could you help reviewing this patch.
>
> PS: Since this patch is related to vectors(avx512f), and Uros
> mentioned before that he has no intension to maintain avx512f.
>
> On Fri, Nov 1, 2019 at 9:
Hi Jakub:
Could you help reviewing this patch.
PS: Since this patch is related to vectors(avx512f), and Uros
mentioned before that he has no intension to maintain avx512f.
On Fri, Nov 1, 2019 at 9:12 AM Hongtao Liu wrote:
>
> Hi uros:
> This patch is about to fix inefficie
Hi uros:
This patch is about to fix inefficient vector constructor.
Currently in ix86_expand_vector_init_concat, vector are initialized
per 2 elements which can miss some optimization opportunity like
pr92295.
Bootstrap and i386 regression test is ok.
Ok for trunk?
Changelog
gcc/
> BTW: Please also note that there is no need to use or operand
> mode override in scalar insn templates for intel asm dialect when
> operand already has a scalar mode.
https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01868.html
This patch is to remove redundant when operand already has a scalar mo
> Looking into sse.md, there is a lot of inconsistencies in existing *vm
> patterns w.r.t. operand constraints. Unfortunately, these were copied
> into proposed patterns. One example is existing
>
> (define_insn "_vmsqrt2"
> [(set (match_operand:VF_128 0 "register_operand" "=x,v")
> (vec_merg
Update patch.
On Fri, Oct 25, 2019 at 4:01 PM Uros Bizjak wrote:
>
> On Fri, Oct 25, 2019 at 7:55 AM Hongtao Liu wrote:
> >
> > On Fri, Oct 25, 2019 at 1:23 PM Hongtao Liu wrote:
> > >
> > > On Fri, Oct 25, 2019 at 2:39 AM Uros Bizjak wrote:
> > &
On Fri, Oct 25, 2019 at 1:23 PM Hongtao Liu wrote:
>
> On Fri, Oct 25, 2019 at 2:39 AM Uros Bizjak wrote:
> >
> > On Wed, Oct 23, 2019 at 7:48 AM Hongtao Liu wrote:
> > >
> > > Update patch:
> > > Add m constraint to define_insn (sse_1_round > &g
On Fri, Oct 25, 2019 at 2:39 AM Uros Bizjak wrote:
>
> On Wed, Oct 23, 2019 at 7:48 AM Hongtao Liu wrote:
> >
> > Update patch:
> > Add m constraint to define_insn (sse_1_round > *sse_1_round > when under sse4 but not avx512f.
>
> It looks to me that the origi
Update patch:
Add m constraint to define_insn (sse_1_round):
Change constraint x to xm
since vround support memory operand.
* (*sse4_1_round): Ditto.
Bootstrap and regression test ok.
On Wed, Oct 23, 2019 at 9:56 AM Hongtao Liu wrote:
>
> Hi uros:
> This patch fi
Hi uros:
This patch fixes false dependence of scalar operations
vrcp/vsqrt/vrsqrt/vrndscale.
Bootstrap ok, regression test on i386/x86 ok.
It does something like this:
-
For scalar instructions with both xmm operands:
op %xmmN,%xmmQ,%xmmQ > op %xmmN, %xmmN, %xmmQ
for scalar instruc
On Mon, Oct 21, 2019 at 1:15 AM Gerald Pfeifer wrote:
>
> On Fri, 11 Oct 2019, liuho...@gcc.gnu.org wrote:
> > commit 63fbcfeaf27d9dd2083ccbd34bdff8fccb63949c
> > Author: liuhongt
> > Date: Fri Oct 11 14:27:47 2019 +0800
> >
> > Update gcc10 changes with new intel ISA.
>
> I just applied th
On Sat, Oct 12, 2019 at 4:15 PM Jakub Jelinek wrote:
>
> Hi!
>
> > gcc/
> > * config/i386/avx512fintrin.h (_mm_mask_roundscale_ss,
> > _mm_maskz_roundscale_ss, _mm_maskz_roundscale_round_ss,
> > _mm_maskz_roundscale_round_ss, _mm_mask_roundscale_sd,
> > _mm_maskz_roundscale
Hi:
This patch is enabling missing avx512f intrinsics listed as
_mm_mask_roundscale_sd
_mm_mask_roundscale_round_sd
_mm_maskz_roundscale_sd
_mm_maskz_roundscale_round_sd
_mm_mask_roundscale_ss
_mm_mask_roundscale_round_ss
_mm_maskz_roundscale_ss
_mm_maskz_roundscale_round_ss
Bootstrap ok, reg
Hi Uros:
This patch extend pass rpad to handle AVX512F vcvtusi2ss/vcvtusi2sd.
538.image_r would be improved by 4% with single copy run on skylake
workstation.
Bootstrap ok. regression test for i386/x86 backend ok.
Ok for trunk?
Changelog
gcc/
* config/i386/i386.md
(*floatuns2_avx512)
On Wed, Sep 4, 2019 at 9:44 AM Hongtao Liu wrote:
>
> On Wed, Sep 4, 2019 at 12:50 AM Uros Bizjak wrote:
> >
> > On Tue, Sep 3, 2019 at 1:33 PM Richard Biener
> > wrote:
> >
> > > > > Note:
> > > > > Removing limit of cost would in
On Wed, Sep 4, 2019 at 12:50 AM Uros Bizjak wrote:
>
> On Tue, Sep 3, 2019 at 1:33 PM Richard Biener
> wrote:
>
> > > > Note:
> > > > Removing limit of cost would introduce lots of regressions in SPEC2017
> > > > as follow
> > > >
> > > > 531.deepsjeng_r -7.18%
On Mon, Sep 2, 2019 at 4:41 PM Uros Bizjak wrote:
>
> On Mon, Sep 2, 2019 at 10:13 AM Hongtao Liu wrote:
> >
> > > which is not the case with core_cost (and similar with skylake_cost):
> > >
> > > 2, 2, 4,/* cost of moving XMM,YMM,
On Mon, Sep 2, 2019 at 6:23 PM Richard Biener
wrote:
>
> On Mon, Sep 2, 2019 at 10:13 AM Hongtao Liu wrote:
> >
> > > which is not the case with core_cost (and similar with skylake_cost):
> > >
> > > 2, 2, 4,/* cost of moving XMM,YMM,
> which is not the case with core_cost (and similar with skylake_cost):
>
> 2, 2, 4,/* cost of moving XMM,YMM,ZMM register */
> {6, 6, 6, 6, 12},/* cost of loading SSE registers
>in 32,64,128,256 and 512-bit */
> {6, 6, 6, 6, 12},
On Fri, Aug 30, 2019 at 2:18 PM Uros Bizjak wrote:
>
> On Fri, Aug 30, 2019 at 2:08 AM Hongtao Liu wrote:
> >
> > On Fri, Aug 30, 2019 at 2:09 AM Uros Bizjak wrote:
> > >
> > > 2019-08-28 Uroš Bizjak
> > >
> > > * config/i386/i386.c
On Fri, Aug 30, 2019 at 8:10 AM Hongtao Liu wrote:
>
> On Fri, Aug 30, 2019 at 2:09 AM Uros Bizjak wrote:
> >
> > 2019-08-28 Uroš Bizjak
> >
> > * config/i386/i386.c (ix86_register_move_cost): Do not
> > limit the cost of moves to/from XMM registe
On Fri, Aug 30, 2019 at 2:09 AM Uros Bizjak wrote:
>
> 2019-08-28 Uroš Bizjak
>
> * config/i386/i386.c (ix86_register_move_cost): Do not
> limit the cost of moves to/from XMM register to minimum 8.
>
> Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
>
> Actually committe
his or attach the patch instead.
> > >> >>
> > >> >> > Index: ChangeLog
> > >> >> > ===
> > >> >> > --- ChangeLog (revision 272668)
> > >> >>
gt; > =======
> >> > --- ChangeLog (revision 272668)
> >> > +++ ChangeLog (working copy)
> >> > @@ -1,3 +1,8 @@
> >> > +2019-06-27 Hongtao Liu
> >> > +
> >> >
; single space. Please fix this or attach the patch instead.
>
> > Index: ChangeLog
> > ===
> > --- ChangeLog (revision 272668)
> > +++ ChangeLog (working copy)
> > @@ -1,3 +1,8 @@
> > +2019-06-27
_avx512ifma { } {
> > return [check_no_compiler_messages avx512ifma object {
>
> as usual, the new effective-target keyword needs documenting in
> sourcebuild.texi.
Like this?
Index: ChangeLog
===
--- ChangeLog (revis
On Wed, Jun 26, 2019 at 5:21 PM Martin Liška wrote:
>
> Hi.
>
> Started from r272668 I see:
>
> /tmp/ccqxwVjt.s: Assembler messages:
>
> /tmp/ccqxwVjt.s:22: Error: no such instruction: `vp2intersectq
> .LC1(%rip),%zmm0,%k0'
>
> /tmp/ccqxwVjt.s:33: Error: no such instruction: `vp2intersectd
> .LC
On Wed, Jun 26, 2019 at 1:13 AM Uros Bizjak wrote:
>
> On Tue, Jun 25, 2019 at 4:44 AM Hongtao Liu wrote:
> >
> > On Sat, Jun 22, 2019 at 3:38 PM Uros Bizjak wrote:
> > >
> > > On Fri, Jun 21, 2019 at 8:38 PM H.J. Lu wrote:
> > >
>
to invent something like SPECIAL_INT_MODE, which would
> avoid mode promotion functionality (basically, it should not be listed
> in mode_wider and similar arrays). This would prevent mode promotion
> issues, while it would still allow to have mode, having the same width
> as existing mode, but with special properties.
>
> I'
On Fri, Jun 21, 2019 at 1:56 PM Uros Bizjak wrote:
>
> On Fri, Jun 21, 2019 at 4:21 AM Hongtao Liu wrote:
> >
> > On Thu, Jun 20, 2019 at 10:58 PM H.J. Lu wrote:
> > >
> > > On Thu, Jun 20, 2019 at 3:54 AM Hongtao Liu wrote:
> > > >
> >
On Thu, Jun 20, 2019 at 7:37 PM Uros Bizjak wrote:
>
> On Thu, Jun 20, 2019 at 12:54 PM Hongtao Liu wrote:
> >
> > On Thu, Jun 20, 2019 at 2:13 PM Uros Bizjak wrote:
> > >
> > > On Thu, Jun 20, 2019 at 7:36 AM Hongtao Liu wrote:
> > > >
> >
On Thu, Jun 20, 2019 at 10:58 PM H.J. Lu wrote:
>
> On Thu, Jun 20, 2019 at 3:54 AM Hongtao Liu wrote:
> >
> > On Thu, Jun 20, 2019 at 2:13 PM Uros Bizjak wrote:
> > >
> > > On Thu, Jun 20, 2019 at 7:36 AM Hongtao Liu wrote:
> > > >
> >
On Thu, Jun 20, 2019 at 2:13 PM Uros Bizjak wrote:
>
> On Thu, Jun 20, 2019 at 7:36 AM Hongtao Liu wrote:
> >
> > On Sat, Jun 8, 2019 at 4:12 AM Uros Bizjak wrote:
> > >
> > > On 6/7/19, H.J. Lu wrote:
> > >
> > > >> > > +/* Re
On Sat, Jun 8, 2019 at 4:12 AM Uros Bizjak wrote:
>
> On 6/7/19, H.J. Lu wrote:
>
> >> > > +/* Register pair. */
> >> > > +VECTOR_MODES_WITH_PREFIX (P, INT, 2); /* P2QI */
> >> > > +VECTOR_MODES_WITH_PREFIX (P, INT, 4); /* P2HI P4QI */
> >> > >
> >> > > I think
> >> > >
> >> > > INT_MODE (P2QI,
-instruction-set-extensions-programming-reference.pdf
Bootstrap is ok, and no regressions for i386/x86-64 testsuite.
Changelog:
gcc/
+2019-06-06 Hongtao Liu
+ H.J. Lu
+ Olga Makhotina
+
+ * common/config/i386/i386-common.c
+ (OPTION_MASK_ISA_AVX512VP2INTERSECT_SET
On Thu, Jun 6, 2019 at 6:18 AM Jeff Law wrote:
>
> On 6/5/19 1:39 AM, Hongtao Liu wrote:
> > Hi Jeff and Jakub:
> > When adding new intrinsics(PR target/89803), i found vfpclassp[sd],
> > vfpclasss[sd] patterns didn't support memory operand which is
> > suppo
ed on x86_64-linux and i686-linux (on skylake-avx512),
ok for trunk?
Changelog
gcc/
2019-06-05 Hongtao Liu
* config/i386/sse.md (define_mode_suffix vecmemsuffix): New.
(define_insn "avx512dq_fpclass"):
Enable memory operand for it.
(define_insn "avx512dq_vmfpclass"): Ditto.
On Tue, Jun 4, 2019 at 5:56 PM Hongtao Liu wrote:
>
> On Tue, Jun 4, 2019 at 5:21 PM Jakub Jelinek wrote:
> >
> > On Tue, Jun 04, 2019 at 05:00:05PM +0800, Hongtao Liu wrote:
> > > Thanks for reminding, Here is updated:
> >
> > You've missed some not
On Tue, Jun 4, 2019 at 5:21 PM Jakub Jelinek wrote:
>
> On Tue, Jun 04, 2019 at 05:00:05PM +0800, Hongtao Liu wrote:
> > Thanks for reminding, Here is updated:
>
> You've missed some notes. Ok for trunk with:
> 1) the following patch applied on top of your patch
> 2
On Tue, Jun 4, 2019 at 3:59 PM Jakub Jelinek wrote:
>
> On Tue, Jun 04, 2019 at 03:38:08PM +0800, Hongtao Liu wrote:
> > --- gcc/ChangeLog (revision 271853)
> > +++ gcc/ChangeLog (working copy)
> > @@ -4706,6 +4706,26 @@
> > reprocessing. Always ca
On Mon, Jun 3, 2019 at 7:06 PM Jakub Jelinek wrote:
>
> On Mon, Jun 03, 2019 at 06:01:40PM +0800, Hongtao Liu wrote:
> > The following patch adds forgotten avx512f fpclass instrinsics for
> > masked scalar operations.
> >
> > Bootstrapped/regtested on x86_64-li
Hi Jeff:
The following patch adds forgotten avx512f fpclass instrinsics for
masked scalar operations.
Bootstrapped/regtested on x86_64-linux and i686-linux (on skylake-avx512),
ok for trunk?
Changelog:
gcc/
+2019-03-24 Hongtao Liu
+
+ PR target/89803
+ * config/i386/avx512dqintrin.h
On Sat, Jun 1, 2019 at 6:08 AM Jeff Law wrote:
>
> On 5/30/19 2:53 AM, Hongtao Liu wrote:
> > On Thu, May 30, 2019 at 3:23 AM Jeff Law wrote:
> >> On 5/9/19 10:54 PM, Hongtao Liu wrote:
> >>> On Fri, May 10, 2019 at 3:55 AM Jeff Law wrote:
> >&g
On Thu, May 30, 2019 at 3:23 AM Jeff Law wrote:
>
> On 5/9/19 10:54 PM, Hongtao Liu wrote:
> > On Fri, May 10, 2019 at 3:55 AM Jeff Law wrote:
> >>
> >> On 5/6/19 11:38 PM, Hongtao Liu wrote:
> >>> Hi Uros and GCC:
> >>> This patch is
On Fri, May 24, 2019 at 3:51 PM Uros Bizjak wrote:
>
> On Fri, May 24, 2019 at 9:43 AM Uros Bizjak wrote:
> >
> > On Fri, May 24, 2019 at 7:16 AM Hongtao Liu wrote:
> > >
> > > Hi Uros and all:
> > > This patch is about to enable support for E
Hi Uros and all:
This patch is about to enable support for ENQCMD(Enqueue Command)
which will be in Willow Cove.
There are two instructions for ENQCMD: ENQCMD and ENQCMDS. More
details please refer to
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-exte
On Fri, May 10, 2019 at 12:54 PM Hongtao Liu wrote:
>
> On Fri, May 10, 2019 at 3:55 AM Jeff Law wrote:
> >
> > On 5/6/19 11:38 PM, Hongtao Liu wrote:
> > > Hi Uros and GCC:
> > > This patch is to fix ix86_expand_sse_comi_round whose implementatio
On Fri, May 10, 2019 at 3:55 AM Jeff Law wrote:
>
> On 5/6/19 11:38 PM, Hongtao Liu wrote:
> > Hi Uros and GCC:
> > This patch is to fix ix86_expand_sse_comi_round whose implementation
> > was not correct.
> > New implentation aligns with _mm_cmp_round_s[s
Sorry for the indentation issue, and thanks for your reminder.
On Wed, May 8, 2019 at 3:39 PM Uros Bizjak wrote:
>
> On Wed, May 8, 2019 at 5:06 AM Hongtao Liu wrote:
> >
> > On Wed, May 8, 2019 at 2:33 AM Uros Bizjak wrote:
> > >
> > > On Tue, May 7
Any other comments, i'll merge to trunk?
On Tue, May 7, 2019 at 3:31 PM Hongtao Liu wrote:
>
> On Tue, May 7, 2019 at 3:03 PM Jakub Jelinek wrote:
> >
> > On Tue, May 07, 2019 at 01:38:49PM +0800, Hongtao Liu wrote:
> > > +2019-05-06 H.J.
On Wed, May 8, 2019 at 2:33 AM Uros Bizjak wrote:
>
> On Tue, May 7, 2019 at 8:49 AM Hongtao Liu wrote:
>
> > > > > > > > > > This patch is about to enable support for bfloat16
> > > > > > > > > > which will
On Tue, May 7, 2019 at 3:03 PM Jakub Jelinek wrote:
>
> On Tue, May 07, 2019 at 01:38:49PM +0800, Hongtao Liu wrote:
> > +2019-05-06 H.J. Lu
> > + Hongtao Liu
> > +
> > + PR Target/89750
> > + PR Target/86444
>
> target, not Targe
On Wed, Apr 17, 2019 at 7:14 PM Uros Bizjak wrote:
>
> On Wed, Apr 17, 2019 at 1:03 PM Uros Bizjak wrote:
> >
> > On Wed, Apr 17, 2019 at 12:29 PM Hongtao Liu wrote:
> > >
> > > On Fri, Apr 12, 2019 at 11:18 PM H.J. Lu wrote:
> > > >
> >
- gcc/ChangeLog (revision 270933)
+++ gcc/ChangeLog (working copy)
@@ -1,3 +1,11 @@
+2019-05-06 H.J. Lu
+ Hongtao Liu
+
+ PR Target/89750
+ PR Target/86444
+ * config/i386/i386-expand.c (ix86_expand_sse_comi_round):
+ Modified, original implementation isn't correct.
+
2019-05-
Since GCC 9.1 released [2019-05-03].
I'll merge this to trunk?
On Wed, Apr 17, 2019 at 7:14 PM Uros Bizjak wrote:
>
> On Wed, Apr 17, 2019 at 1:03 PM Uros Bizjak wrote:
> >
> > On Wed, Apr 17, 2019 at 12:29 PM Hongtao Liu wrote:
> > >
> > > On Fri
On Fri, Apr 12, 2019 at 11:18 PM H.J. Lu wrote:
>
> On Fri, Apr 12, 2019 at 3:19 AM Uros Bizjak wrote:
> >
> > On Fri, Apr 12, 2019 at 11:03 AM Hongtao Liu wrote:
> > >
> > > On Fri, Apr 12, 2019 at 3:30 PM Uros Bizjak wrote:
> > > >
>
On Wed, Apr 17, 2019 at 4:48 PM Martin Liška wrote:
>
> On 4/17/19 10:14 AM, Hongtao Liu wrote:
> > Any other comments, I'll merge this to trunk?
>
> Hi.
>
> I don't understand you. The patch in its original version will no be
> installed to trunk
>
On Tue, Apr 16, 2019 at 11:41 PM H.J. Lu wrote:
>
> On Tue, Apr 16, 2019 at 8:36 AM Martin Liška wrote:
> >
> > On 4/16/19 4:50 PM, H.J. Lu wrote:
> > > On Tue, Apr 16, 2019 at 1:28 AM Martin Liška wrote:
> > >>
> > >> On 4/15/19 5:09 PM, H.J. Lu wrote:
> > >>> On Mon, Apr 15, 2019 at 12:26 AM M
On Fri, Apr 12, 2019 at 3:30 PM Uros Bizjak wrote:
>
> On Fri, Apr 12, 2019 at 9:09 AM Liu, Hongtao wrote:
> >
> > Hi :
> > This patch is about to enable support for bfloat16 which will be in
> > Future Cooper Lake, Please refer to
> > https://software.intel.com/en-us/download/intel-archite
On Sat, Mar 30, 2019 at 5:34 AM Jeff Law wrote:
>
> On 3/28/19 1:38 AM, Uros Bizjak wrote:
> > On Thu, Mar 28, 2019 at 7:47 AM Hongtao Liu wrote:
> >>
> >> Hi Uros:
> >> would you help to review this patch?
> >
> > This is AVX512F patch, you w
Hi Uros:
would you help to review this patch?
Regards,
Hongtao.
On Sun, Mar 24, 2019 at 8:13 PM Hongtao Liu wrote:
>
> Hi:
> The following patch adds forgotten avx512f fpclass instrinsics for
> masked scalar operations.
>
> Bootstrapped/regtested on x86_64-linux and i686
269894)
+++ ChangeLog (working copy)
@@ -1,3 +1,16 @@
+2019-03-24 Hongtao Liu
+
+ PR target/89803
+ * config/i386/avx512dqintrin.h
+ (_mm_mask_fpclass_ss_mask,_mm_mask_fpclass_sd_mask):
+ New intrinsics.
+ * config/i386/i386-builtin.def
+ (__builtin_ia32_fpcla_mask
2,
buitins with both flags can't be handled easily.
This patch intends to handle this issue.
Tested with bootstrap and regression test on x86, no problem found.
Is it ok for trunk?
Thanks,
Hongtao
---
gcc/
2019-01-21 Hongtao Liu
H.J. Lu
PR target/88909
* config/i386/i386-builtin.def:
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