On Sat, Apr 11, 2020 at 02:48:22PM -0700, H.J. Lu via Gcc-patches wrote:
> Even though ix86_hard_regno_mode_ok doesn't allow xmm16-xmm31 nor
> ymm16-ymm31 in 128/256 bit modes when AVX512VL is disabled, reload
> can still generate reg to reg moves with xmm16-xmm31 and ymm16-ymm31
> in 128/256 bit m
Even though ix86_hard_regno_mode_ok doesn't allow xmm16-xmm31 nor
ymm16-ymm31 in 128/256 bit modes when AVX512VL is disabled, reload
can still generate reg to reg moves with xmm16-xmm31 and ymm16-ymm31
in 128/256 bit modes. Remove mode size check in ix86_get_ssemov.
gcc/
PR target/94561