Hi
I have been looking at the mmu source code in gem5, and I am curious about how
gem5 handles page table fault. It seems that instruction will be labled Fault
everytime a TLB miss happens in both SE and FullSystem mode, but I could not
see how that page fault is dealt with afterwards. So my
Hi
I was trying to add a new CPU inherit from BaseCPU:
class MY_CPU: public BaseCPU
{
public:
MY_CPU(const MY_CPUParams p);
~MY_CPU(){}
...
private:
...
}
but incurs the following running error: fatal: Process system.cpu.workload is
not associated with any HW contexts!
...
Hi
What is the interface between L1 and L2 cache in Ruby cache coherence model? Is
there a clear defined interface, similar to the icachePort and dcachePort
between CPU and memory, between different levels of caches in Ruby?
Thanks in advance
Fengze
Hi
Building GEM5 using scons generates an executable file gem5.opt. What if
I want to generate a static or dynamic library, which is either a .a or .so
file, instead of an executable?
I have noticed that inSConscript under gem5/src, there is a
process to make all the object into an library,