This patch depends on patch "drm/i915:merge ring_put/get_irq into
bsd_ring_put/get_irq"
On g4x, user interrupt in bsd ring is missed.
g4x and ironlake share the same bsd_ring, but their interrupt control
interfaces are different, g4x use I915 while ironlake use GT.
The interrupt mask reg address
This patch is a clean-up, since ring_put_irq/ring_get_irq are only used
by bsd_ring_put_irq and bsd_ring_get_irq.
This patch also serve the further fix about irq miss in bsd ring on g4x.
Interrupt control interfaces are different between g4x and ironlake,
they use different interrupt control reg a
On Wed, Apr 27, 2011 at 7:00 PM, Chris Wilson wrote:
> The unusual sequence appears to be:
>
> [ 30.081906] [drm:intel_dp_i2c_init], i2c_init DPDDC-B
> [ 30.082413] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003e
> [ 30.082415] [drm:intel_dp_i2c_aux_ch], aux_ch failed -110
> [
I got it!
Thanks for reminding me. :)
-Original Message-
From: Keith Packard [mailto:kei...@keithp.com]
Sent: Thursday, April 28, 2011 10:41 AM
To: Feng, Boqun; intel-gfx@lists.freedesktop.org
Subject: RE: [Intel-gfx] [PATCH 1/2] drm/i915:merge ring_put/get_irq into
bsd_ring_put/get_irq
On Thu, 28 Apr 2011 10:06:51 +0800, "Feng, Boqun" wrote:
> I have discussed this with Chris in my earlier patch.
>
> This change is a clean-up, since ring_put_irq and ring_get_irq are only used
> by
> bsd_ring_put_irq and bsd_ring_get_irq.
>
> And once this change is made, it is more clear to
I have discussed this with Chris in my earlier patch.
This change is a clean-up, since ring_put_irq and ring_get_irq are only used by
bsd_ring_put_irq and bsd_ring_get_irq.
And once this change is made, it is more clear to see the difference between
g4x and ironlake BSD interrupt control interfa
On Wed, 27 Apr 2011 22:46:06 +0200, Daniel Vetter
wrote:
> Pipecontrol is also required to implement gfdt flushing on gen6+.
> And if we ever switch to pipecontrol based cache management in the
> kernel, also required on gen4. I don't see the point in saving that
> little bit of storge.
>
> In t
On Wed, 27 Apr 2011 23:03:14 +0100
Chris Wilson wrote:
> > We should probably just enable fbc on the pipe connected to the
> > internal panel (if any) and keep it disabled otherwise.
>
> On Arrandale, fbc is potentially a bigger win than rc6 - but is also a
> potential loss - right?
No, I think
On Wed, 27 Apr 2011 14:20:09 -0700, Jesse Barnes
wrote:
> On Wed, 27 Apr 2011 08:49:28 +0100
> Chris Wilson wrote:
>
> > On Fri, 18 Mar 2011 16:12:48 -0700, Ben Widawsky wrote:
> > > The previous patches should fix enough of the known issues to try
> > > re-enabling rc6 for general consumption
On Wed, 27 Apr 2011 14:01:50 -0700, Jesse Barnes
wrote:
> On Wed, 27 Apr 2011 07:59:17 +0100
> Chris Wilson wrote:
> > So I think we just want IS_GEN7() for IVB code.
>
> I'd rather keep them separate since we know we'll have gen7 chips with
> different display engines in the future. I've been
On Wed, 27 Apr 2011 08:49:28 +0100
Chris Wilson wrote:
> On Fri, 18 Mar 2011 16:12:48 -0700, Ben Widawsky wrote:
> > The previous patches should fix enough of the known issues to try
> > re-enabling rc6 for general consumption
>
> Yay, and they bring back the old bugs! :)
>
> So upon enabling
On Wed, 27 Apr 2011 08:10:29 -0700
Keith Packard wrote:
> On Tue, 26 Apr 2011 16:38:49 -0700, Jesse Barnes
> wrote:
> > A0 stepping chips need to use manual training, but the bits have all
> > moved. So fix things up so we can at least train FDI for VGA links.
>
> This patch should be before
On Wed, 27 Apr 2011 08:05:37 -0700
Keith Packard wrote:
> On Tue, 26 Apr 2011 16:38:45 -0700, Jesse Barnes
> wrote:
>
> > We can treat PantherPoint as CougarPoint as far as display goes.
>
> I'll note in passing that pch_type is never set to PCH_IBX explicitly,
> which only works because PCH_
On Wed, 27 Apr 2011 08:19:21 +0100
Chris Wilson wrote:
> On Tue, 26 Apr 2011 16:38:46 -0700, Jesse Barnes
> wrote:
> > Ivy Bridge has a similar split display controller to Sandy Bridge, so
> > use HAS_PCH_SPLIT. And gen7 also has the pipe control instruction, so
> > use HAS_PIPE_CONTROL as wel
On Wed, 27 Apr 2011 08:23:33 +0100
Chris Wilson wrote:
> On Tue, 26 Apr 2011 16:38:42 -0700, Jesse Barnes
> wrote:
> > Check for IVB desktop, mobile and other SKUs and set flags
> > appropriately.
> >
> > Signed-off-by: Jesse Barnes
> > ---
> > static const struct pci_device_id pciidlist[] =
On Wed, 27 Apr 2011 07:59:17 +0100
Chris Wilson wrote:
> On Tue, 26 Apr 2011 16:38:42 -0700, Jesse Barnes
> wrote:
> > Check for IVB desktop, mobile and other SKUs and set flags
> > appropriately.
> >
> > Signed-off-by: Jesse Barnes
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/
On 4/26/2011 11:19 PM, Chris Wilson wrote:
> On Tue, 26 Apr 2011 17:06:01 -0700, Jesse Barnes
> wrote:
> > You can ignore this set; I only sent it because I thought the
> > others wouldn't come through.
>
> Before I find the others... Do they treat IS_IVYBRIDGE() vs IS_GEN7
> consistently? Do
On Wed, 27 Apr 2011 08:58:38 -0700
Ben Widawsky wrote:
> On Tue, Apr 26, 2011 at 04:38:39PM -0700, Jesse Barnes wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 0296967..c10d7e9 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/driv
Pipecontrol is also required to implement gfdt flushing on gen6+.
And if we ever switch to pipecontrol based cache management in the
kernel, also required on gen4. I don't see the point in saving that
little bit of storge.
In the process make cleanup_pipe_control more robust and call it
unconditio
With the snb blt workaround gone, gen5 pipe_control is the only user of
ring->private. It's already tiny, but make it even smaller to prepare for
embedding. The added indirection will be killed in the next patch.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c |8 +++
This was just to facilitate product enablement with pre-production hw.
Allows us to kill quite a bit of cruft.
Cc: Eric Anholt
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 83 +--
1 files changed, 2 insertions(+), 81 deletions(-)
diff
Hi all,
While mucking around with gfdt to check whether the llc api feels good (it
does!) I've once again noticed a few things in intel_ringbuffer.c
These patches weed them out. Please review and consider merging for -next.
Thanks, Daniel
Daniel Vetter (3):
drm/i915/ringbuffer: kill snb blt w
On Wed, Apr 27, 2011 at 08:19:21AM +0100, Chris Wilson wrote:
> On Tue, 26 Apr 2011 16:38:46 -0700, Jesse Barnes
> wrote:
> > Ivy Bridge has a similar split display controller to Sandy Bridge, so
> > use HAS_PCH_SPLIT. And gen7 also has the pipe control instruction, so
> > use HAS_PIPE_CONTROL a
On Wed, 27 Apr 2011 15:41:18 +0800, "Feng, Boqun" wrote:
> Remove ring_put_irq/ring_get_irq:drivers/gpu/drm/i915/intel_ringbuffer.c
> , they are only used by bsd_ring_put_irq/bsd_ring_get_irq.
> Expand the code in bsd_ring_put_irq/bsd_ring_get_irq.
Why is this change useful?
--
keith.pack...@in
On Wed, Apr 27, 2011 at 01:07:24PM +0200, Daniel Vetter wrote:
> On Wed, Apr 27, 2011 at 11:15 AM, Chris Wilson
> wrote:
> > At the moment, I'm more concerned about making sure our functions are
> > consistently named and prefixed with the chipset they first work with.
> >
> > So we have:
> > ?in
On Tue, Apr 26, 2011 at 04:38:39PM -0700, Jesse Barnes wrote:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0296967..c10d7e9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -209,7 +209,7 @@ struct drm_i915_displa
On Tue, 26 Apr 2011 16:38:49 -0700, Jesse Barnes
wrote:
> A0 stepping chips need to use manual training, but the bits have all
> moved. So fix things up so we can at least train FDI for VGA links.
This patch should be before the auto-train patch so that we don't have
a broken driver between the
On Tue, 26 Apr 2011 16:38:45 -0700, Jesse Barnes
wrote:
> We can treat PantherPoint as CougarPoint as far as display goes.
I'll note in passing that pch_type is never set to PCH_IBX explicitly,
which only works because PCH_IBX is zero.
--
keith.pack...@intel.com
pgpz4oSyZkoyH.pgp
Descriptio
On Wed, Apr 27, 2011 at 11:15 AM, Chris Wilson wrote:
> At the moment, I'm more concerned about making sure our functions are
> consistently named and prefixed with the chipset they first work with.
>
> So we have:
> intel_ -> general functions, used by all
> i8xx_ -> gen2
> i915_ -> gen3 (915/
On Wed, 27 Apr 2011 16:23:00 +0800, "Feng, Boqun" wrote:
> Err...I just send another two patches before read this letter. : )
>
> Ironlake and g4x share the same bsd_ring, so they share the same
> bsd_ring_put/get_irq functions of the ring. Given this, we can't just
> change the function name to
On Wed, 27 Apr 2011 18:27:51 +1000, Paul McGarry wrote:
> On Wed, Apr 27, 2011 at 4:49 PM, Chris Wilson
> wrote:
> > DP has worked for most people the last 18 months or so... There is always
> > to unhappy exception. Can you please append drm.debug=0xe to you kernel
> > boot parameters and attac
Err...I just send another two patches before read this letter. : )
Ironlake and g4x share the same bsd_ring, so they share the same
bsd_ring_put/get_irq functions of the ring. Given this, we can't just
change the function name to g4x_ring_put/get_irq. If we do so, we
need ironlake_ring_put/get_irq
On Fri, 18 Mar 2011 16:12:48 -0700, Ben Widawsky wrote:
> The previous patches should fix enough of the known issues to try
> re-enabling rc6 for general consumption
Yay, and they bring back the old bugs! :)
So upon enabling fbc on a 2560x1440 external panel, it goes blank again.
The same sympto
On g4x, user interrupt in bsd ring is missed.
g4x and ironlake share the same bsd_ring, but their interrupt
control interfaces are different. G4x use I915 while ironlake
use GT. The interrupt mask reg address on g4x should be IMR,
user interrupt bit in bsd ring on g4x is I915_BSD_USER_INTERRUPT
Ad
Remove ring_put_irq/ring_get_irq:drivers/gpu/drm/i915/intel_ringbuffer.c
, they are only used by bsd_ring_put_irq/bsd_ring_get_irq.
Expand the code in bsd_ring_put_irq/bsd_ring_get_irq.
Signed-off-by: Feng, Boqun
Reviewed-by: Xiang, Haihao
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 48
On Wed, 27 Apr 2011 14:08:57 +0800, "Feng, Boqun" wrote:
> I am very sorry for my careless about whitespace.
>
> But my patch will not affect gen6+ paths, for gen6+, it use gen6_bsd_ring
> , bsd_ring is only used by g4x and ironlake.
Reviewer error, sorry. Saw the gen6_* in the diff header as th
On Tue, 26 Apr 2011 16:38:42 -0700, Jesse Barnes
wrote:
> Check for IVB desktop, mobile and other SKUs and set flags
> appropriately.
>
> Signed-off-by: Jesse Barnes
> ---
> static const struct pci_device_id pciidlist[] = {/* aka */
> INTEL_VGA_DEVICE(0x3577, &intel_i830_info
On Tue, 26 Apr 2011 16:38:46 -0700, Jesse Barnes
wrote:
> Ivy Bridge has a similar split display controller to Sandy Bridge, so
> use HAS_PCH_SPLIT. And gen7 also has the pipe control instruction, so
> use HAS_PIPE_CONTROL as well.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/
On Tue, 26 Apr 2011 16:38:42 -0700, Jesse Barnes
wrote:
> Check for IVB desktop, mobile and other SKUs and set flags
> appropriately.
>
> Signed-off-by: Jesse Barnes
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2a41118..0b5e263 100644
> --- a/driver
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