Re: [Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr

On 5/18/2018 3:01 PM, Jani Nikula wrote: On Fri, 18 May 2018, vathsala nagaraju wrote: From: Vathsala Nagaraju For psr block #9, the vbt description has moved to options [0-3] for TP1,TP2,TP3 Wakeup time from decimal value without

[Intel-gfx] ✓ Fi.CI.IGT: success for More ICL display patches

== Series Details == Series: More ICL display patches URL : https://patchwork.freedesktop.org/series/43546/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4213_full -> Patchwork_9074_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9074_full

[Intel-gfx] ✓ Fi.CI.BAT: success for More ICL display patches

== Series Details == Series: More ICL display patches URL : https://patchwork.freedesktop.org/series/43546/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4213 -> Patchwork_9074 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9074 need to be

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for More ICL display patches

== Series Details == Series: More ICL display patches URL : https://patchwork.freedesktop.org/series/43546/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/icl: Extend AUX F interrupts to ICL Okay! Commit: drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches

== Series Details == Series: More ICL display patches URL : https://patchwork.freedesktop.org/series/43546/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2ab358790967 drm/i915/icl: Extend AUX F interrupts to ICL 7f3648f2c0e1 drm/i915/icl: GSE interrupt moves from DE_MISC to

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/query: Protect tainted function pointer lookup

== Series Details == Series: drm/i915/query: Protect tainted function pointer lookup URL : https://patchwork.freedesktop.org/series/43535/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4213_full -> Patchwork_9073_full = == Summary - WARNING == Minor unknown changes

[Intel-gfx] [PATCH 04/24] drm/i915/icl: Support for TC North Display interrupts

From: Dhinakaran Pandiyan The hotplug interrupts for the ports can be routed to either North Display or South Display depending on the output mode. DP Alternate or DP over TBT outputs will have hotplug interrupts routed to the North Display while interrupts for

[Intel-gfx] [PATCH 19/24] drm/i915/icl: store the port type for TC ports

The type is detected based on the interrupt ISR bit. Once detected, it's not supposed to be changed, so we have some sanity checks for that. Cc: Animesh Manna Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE

From: Manasi Navare DFLEXDPMLE register is required to tell the FIA hardware which main links of DP are enabled on TCC Connectors. FIA uses this information to program PHY to Controller signal mapping. This register is applicable in both TC connector's Alternate mode

[Intel-gfx] [PATCH 08/24] drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin

From: "Sripada, Radhakrishna" On ICL we need to map VBT DDC Pin to BSpec DDC Pin. Adding ICL Pin Values. According to VBT Block 2 (General Bytes Definition) DDC Bus +--+---++ | DDI Type | VBT Value | BSpec Mapped Value |

[Intel-gfx] [PATCH 03/24] drm/i915/icl: introduce tc_port

Add and enum for TC ports and auxiliary functions to handle them. Icelake brings a lot of registers and other things that only apply to the TC ports and are indexed starting from 0, so having an enum for tc_ports that starts at 0 really helps the indexing. This patch is based on previous patches

[Intel-gfx] [PATCH 22/24] drm/i915/icl: Update FIA supported lane count for hpd.

From: Animesh Manna In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1, tbt and display controller. In DP alt mode FIA configure the number of lanes and will be used apart from DPCD read to calculate max available lanes for DP enablement. Signed-off-by:

[Intel-gfx] [PATCH 24/24] drm/i915/icl: toggle PHY clock gating around link training

The Gen11 TypeC PHY DDI Buffer chapter, PHY Clock Gating Programming section says that PHY clock gating should be disabled before starting voltage swing programming, then enabled after any link training is complete. Cc: Animesh Manna Cc: Manasi Navare

[Intel-gfx] [PATCH 13/24] drm/i915/icl: unconditionally init DDI for every port

On ICP, port present straps are no longer supported. Software should determine the presence through BIOS VBT, hotplug or other mechanisms. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-)

[Intel-gfx] [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.

From: Manasi Navare PLLs are the source clocks for the DDIs so in order to determine the ddi clock we need to check the PLL configuration. This gets a little tricky for ICL since there is no register bit that maps directly to the link clock. So this patch creates a

[Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers

Use the hardcoded tables provided by our spec. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 - 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c

[Intel-gfx] [PATCH 17/24] drm/i915/icl: Add 10-bit support for hdmi

From: "Sripada, Radhakrishna" Starting Icelake silicon supports 10-bpc hdmi to support certain media workloads. Currently hdmi supports 8 and 12 bpc. Plumbed in support for 10 bit hdmi. Cc: James Ausmus Cc: Jani Nikula

[Intel-gfx] [PATCH 23/24] drm/i915/icl: program MG_DP_MODE

Programming this register is part of the Enable Sequence for DisplayPort on ICL. Do as the spec says. Cc: Animesh Manna Cc: Manasi Navare Cc: Dhinakaran Pandiyan Signed-off-by: Paulo Zanoni

[Intel-gfx] [PATCH 07/24] drm/i915/icl: Add DDI HDMI level selection for ICL

From: Manasi Navare This patch adds a proper HDMI DDI entry level for vswing programming sequences on ICL. Spec doesn't specify any default for HDMI tables, so let's pick the last entry as the default for now to stay consistent with older platform like CNL. Cc: Paulo

[Intel-gfx] [PATCH 01/24] drm/i915/icl: Extend AUX F interrupts to ICL

From: Dhinakaran Pandiyan ICL has AUX F. Cc: Paulo Zanoni Cc: Anusha Srivatsa Signed-off-by: Dhinakaran Pandiyan Signed-off-by: Paulo Zanoni ---

[Intel-gfx] [PATCH 14/24] drm/i915/icl: start adding the TBT pll

This commit just adds the register addresses and the basic skeleton of the code. The next commits will expand on more specific functions. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_ddi.c | 16

[Intel-gfx] [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP

Implement the DFLEXDPPMS/DFLEXDPCSSS dance for DisplayPort. These functions need to be called during HPD assert/deassert, but due to how our driver works it's much simpler if we always call them when icl_digital_port_connected() is called, which means we won't call them exactly once per HPD event.

[Intel-gfx] [PATCH 18/24] drm/i915/icl: implement icl_digital_port_connected()

Do like the other functions and check for the ISR bits. We have plans to add a few more checks in this code in the next patches, that's why it's a little more verbose than it could be. Cc: Animesh Manna Signed-off-by: Paulo Zanoni

[Intel-gfx] [PATCH 21/24] drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI

Just like DP, HDMI needs to implement these flows. The side effect is that HDMI is now going to rely on the ISR bits, just like DP. Signed-off-by: Paulo Zanoni [Rodrigo: non-trivial rebase.] Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support

From: Anusha Srivatsa This patch addresses Interrupts from south display engine (SDE). ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. Introduce these registers and their intended values. Introduce icp_irq_handler(). Cc: Paulo Zanoni

[Intel-gfx] [PATCH 12/24] drm/i915/icl: Calculate link clock using the new registers

From: Arkadiusz Hiler Start using the new registers for ICL and on. Cc: Manasi Navare Cc: Rodrigo Vivi Cc: Paulo Zanoni Signed-off-by: Arkadiusz Hiler ---

[Intel-gfx] [PATCH 16/24] drm/i915/icl: Handle hotplug interrupts for DP over TBT

From: Dhinakaran Pandiyan This patch enables hotplug interrupts for DP over TBT output on TC ports. The TBT interrupts are enabled and handled irrespective of the actual output type which could be DP Alternate, DP over TBT, native DP or native HDMI. Cc: Animesh

[Intel-gfx] [PATCH 10/24] drm/i915/icl: add icelake_get_ddi_pll()

Implement the hardware state readout code. Thanks to Animesh Manna for spotting this problem. Cc: Animesh Manna Credits-to: Animesh Manna Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 42

[Intel-gfx] [PATCH 00/24] More ICL display patches

Hi This series contains some more ICL patches that haven't seen the mailing list yet. While I'll definitely help re-review the patches not authored by me, please help me with the ones I can't review. Thanks, Paulo Animesh Manna (1): drm/i915/icl: Update FIA supported lane count for hpd.

[Intel-gfx] [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC

From: Dhinakaran Pandiyan The Graphics System Event(GSE) interrupt bit has a new location in the GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the only DE_MISC interrupt that was enabled, with this change we don't enable/handle any of DE_MISC

[Intel-gfx] [PATCH 09/24] drm/i915/icl: Add Icelake PCH detection

From: Anusha Srivatsa This patch adds the support to detect PCH_ICP. Suggested-by: Paulo Zanoni Signed-off-by: Anusha Srivatsa Signed-off-by: Michel Thierry ---

Re: [Intel-gfx] [PATCH 5/6] drm/i915/psr: Fall back to max. synchronization latency if DPCD read fails

On Fri, 2018-05-11 at 12:51 -0700, Dhinakaran Pandiyan wrote: > Noticed that we assume the best case of 0 latency when the DPCD read > fails, reasonable pessimism is safer. > > eDP spec does say that if latency is greater than 8, the panel > supplier needs to provide it. I didn't see anything

Re: [Intel-gfx] [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR

On Thu, 2018-05-17 at 17:27 -0700, Tarun Vyas wrote: > On Fri, May 11, 2018 at 12:51:40PM -0700, Dhinakaran Pandiyan wrote: > > > > Ville noticed that we are unncessarily reading DPCD's after knowing > > panel did not support PSR. Looks like this check that was present > > earlier got removed

Re: [Intel-gfx] [PATCH] drm/i915/query: Protect tainted function pointer lookup

On 21/05/18 22:05, Chris Wilson wrote: Smatch identifies i915_query_ioctl() as being a potential victim of Spectre due to it use of a tainted user index into a function pointer array. Use array_index_nospec() to defang the user index before using it to lookup the function pointer. Fixes:

Re: [Intel-gfx] [PATCH 22/33] drm/i915: use match_string() helper

On Mon, May 21, 2018 at 2:57 PM, Yisheng Xie wrote: > match_string() returns the index of an array for a matching string, > which can be used intead of open coded variant. https://patchwork.kernel.org/patch/10382323/ > Cc: Jani Nikula > Cc:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/query: Protect tainted function pointer lookup

== Series Details == Series: drm/i915/query: Protect tainted function pointer lookup URL : https://patchwork.freedesktop.org/series/43535/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4213 -> Patchwork_9073 = == Summary - WARNING == Minor unknown changes coming with

[Intel-gfx] [PATCH] drm/i915/query: Protect tainted function pointer lookup

Smatch identifies i915_query_ioctl() as being a potential victim of Spectre due to it use of a tainted user index into a function pointer array. Use array_index_nospec() to defang the user index before using it to lookup the function pointer. Fixes: a446ae2c6e65 ("drm/i915: add query uAPI")

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

== Series Details == Series: series starting with [1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup URL : https://patchwork.freedesktop.org/series/43531/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4213_full -> Patchwork_9072_full = == Summary - WARNING ==

Re: [Intel-gfx] [PATCH] drm/i915/icl: Disable pipe CSC and gamma in cursor plane

On Mon, 2018-05-21 at 10:38 -0700, Paulo Zanoni wrote: > Em Sex, 2018-05-18 às 13:15 -0700, José Roberto de Souza escreveu: > > 'Pipe CSC enable' bit is more than just deprecated in ICL+, it was > > disabled in 077ef1f09c25 'drm/i915/icl: Don't set pipe CSC/Gamma in > > PLANE_COLOR_CTL' for

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

== Series Details == Series: series starting with [1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup URL : https://patchwork.freedesktop.org/series/43531/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4213 -> Patchwork_9072 = == Summary - WARNING == Minor unknown

Re: [Intel-gfx] [PATCH v2] drm/i915: Promote .format_mod_supported() to the lead role

Ville Syrjala writes: > From: Ville Syrjälä > > Up to now we've used the plane's modifier list as the primary > source of information for which modifiers are supported by a > given plane. In order to allow auxiliary metadata to be

[Intel-gfx] [PATCH 2/2] drm/i915: Configure SKL+ scaler initial phase correctly

From: Ville Syrjälä Set up the SKL+ scaler initial phase registers correctly. Otherwise we start fetching the data from the center of the first pixel instead of the top-left corner, which obviously then leads to right/bottom edges replicating data excessively as

[Intel-gfx] [PATCH 1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

From: Ville Syrjälä We already handle the color encoding mode properly. Remove the broken NV12 special case. Cc: Vidya Srinivas Cc: Maarten Lankhorst Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [PATCH] drm/i915/icl: Disable pipe CSC and gamma in cursor plane

Em Sex, 2018-05-18 às 13:15 -0700, José Roberto de Souza escreveu: > 'Pipe CSC enable' bit is more than just deprecated in ICL+, it was > disabled in 077ef1f09c25 'drm/i915/icl: Don't set pipe CSC/Gamma in > PLANE_COLOR_CTL' for primary and sprite planes as it was causing > those planes to be

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/skl+: ddb allocation algorithm optimization

== Series Details == Series: drm/i915/skl+: ddb allocation algorithm optimization URL : https://patchwork.freedesktop.org/series/43508/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4212_full -> Patchwork_9070_full = == Summary - WARNING == Minor unknown changes coming

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits (rev3)

== Series Details == Series: drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits (rev3) URL : https://patchwork.freedesktop.org/series/43420/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4212_full -> Patchwork_9069_full = == Summary - WARNING ==

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

On 21/05/18 17:00, Tvrtko Ursulin wrote: On 21/05/2018 14:22, Lionel Landwerlin wrote: On 15/05/18 10:05, Tvrtko Ursulin wrote: On 14/05/2018 16:56, Lionel Landwerlin wrote: From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

On 21/05/2018 14:22, Lionel Landwerlin wrote: On 15/05/18 10:05, Tvrtko Ursulin wrote: On 14/05/2018 16:56, Lionel Landwerlin wrote: From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: fix icl_unmap/map_plls_to_ports

== Series Details == Series: drm/i915/icl: fix icl_unmap/map_plls_to_ports URL : https://patchwork.freedesktop.org/series/43510/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4212_full -> Patchwork_9068_full = == Summary - WARNING == Minor unknown changes coming with

Re: [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Implement HDCP2.2 (rev5)

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Ramalingam C >Sent: Monday, May 21, 2018 8:34 PM >To: intel-gfx@lists.freedesktop.org; Patchwork >; lkp ; Jani Nikula

Re: [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Implement HDCP2.2 (rev5)

On Monday 21 May 2018 06:53 PM, Patchwork wrote: == Series Details == Series: drm/i915: Implement HDCP2.2 (rev5) URL : https://patchwork.freedesktop.org/series/38254/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm: hdcp2.2 authentication msg definitions Okay!

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add ChromeOS EC CEC Support (rev5)

== Series Details == Series: Add ChromeOS EC CEC Support (rev5) URL : https://patchwork.freedesktop.org/series/43162/ State : failure == Summary == Applying: media: cec-notifier: Get notifier by device and connector name Applying: drm/i915: hdmi: add CEC notifier to intel_hdmi Applying: mfd:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/skl+: ddb allocation algorithm optimization

== Series Details == Series: drm/i915/skl+: ddb allocation algorithm optimization URL : https://patchwork.freedesktop.org/series/43508/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4212 -> Patchwork_9070 = == Summary - WARNING == Minor unknown changes coming with

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits (rev3)

== Series Details == Series: drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits (rev3) URL : https://patchwork.freedesktop.org/series/43420/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4212 -> Patchwork_9069 = == Summary - WARNING == Minor unknown

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: fix icl_unmap/map_plls_to_ports

== Series Details == Series: drm/i915/icl: fix icl_unmap/map_plls_to_ports URL : https://patchwork.freedesktop.org/series/43510/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4212 -> Patchwork_9068 = == Summary - WARNING == Minor unknown changes coming with

[Intel-gfx] [PATCH v4 0/5] Add ChromeOS EC CEC Support

Hi All, The new Google "Fizz" Intel-based ChromeOS device is gaining CEC support through it's Embedded Controller, to enable the Linux CEC Core to communicate with it and get the CEC Physical Address from the correct HDMI Connector, the following must be added/changed: - Add the CEC sub-device

[Intel-gfx] [PATCH v4 3/5] mfd: cros-ec: Introduce CEC commands and events definitions.

The EC can expose a CEC bus, this patch adds the CEC related definitions needed by the cros-ec-cec driver. Having a 16 byte mkbp event size makes it possible to send CEC messages from the EC to the AP directly inside the mkbp event instead of first doing a notification and then a read.

[Intel-gfx] [PATCH v4 1/5] media: cec-notifier: Get notifier by device and connector name

In non device-tree world, we can need to get the notifier by the driver name directly and eventually defer probe if not yet created. This patch adds a variant of the get function by using the device name instead and will not create a notifier if not yet created. But the i915 driver exposes at

[Intel-gfx] [PATCH v4 4/5] mfd: cros_ec_dev: Add CEC sub-device registration

The EC can expose a CEC bus, thus add the cros-ec-cec MFD sub-device when the CEC feature bit is present. Signed-off-by: Neil Armstrong Reviewed-by: Enric Balletbo i Serra --- drivers/mfd/cros_ec_dev.c | 16 1 file

[Intel-gfx] [PATCH v4 5/5] media: platform: Add ChromeOS EC CEC driver

The ChromeOS Embedded Controller can expose a CEC bus, this patch add the driver for such feature of the Embedded Controller. This driver is part of the cros-ec MFD and will be add as a sub-device when the feature bit is exposed by the EC. The controller will only handle a single logical address

[Intel-gfx] [PATCH v4 2/5] drm/i915: hdmi: add CEC notifier to intel_hdmi

This patchs adds the cec_notifier feature to the intel_hdmi part of the i915 DRM driver. It uses the HDMI DRM connector name to differentiate between each HDMI ports. The changes will allow the i915 HDMI code to notify EDID and HPD changes to an eventual CEC adapter. Signed-off-by: Neil Armstrong

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement HDCP2.2 (rev5)

== Series Details == Series: drm/i915: Implement HDCP2.2 (rev5) URL : https://patchwork.freedesktop.org/series/38254/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4212 -> Patchwork_9067 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9067

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Implement HDCP2.2 (rev5)

== Series Details == Series: drm/i915: Implement HDCP2.2 (rev5) URL : https://patchwork.freedesktop.org/series/38254/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm: hdcp2.2 authentication msg definitions Okay! Commit: drm: HDMI and DP specific HDCP2.2 defines Okay!

Re: [Intel-gfx] [PATCH v5 7/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

On 15/05/18 10:05, Tvrtko Ursulin wrote: On 14/05/2018 16:56, Lionel Landwerlin wrote: From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow adjustment of the

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Implement HDCP2.2 (rev5)

== Series Details == Series: drm/i915: Implement HDCP2.2 (rev5) URL : https://patchwork.freedesktop.org/series/38254/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5534d5c8130b drm: hdcp2.2 authentication msg definitions e1983dd17552 drm: HDMI and DP specific HDCP2.2 defines

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/icl: fix icl_unmap/map_plls_to_ports

== Series Details == Series: drm/i915/icl: fix icl_unmap/map_plls_to_ports URL : https://patchwork.freedesktop.org/series/43510/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4212 -> Patchwork_9066 = == Summary - FAILURE == Serious unknown changes coming with

[Intel-gfx] [PATCH v4 40/41] drm/i915: Add HDCP2.2 support for DP connectors

On DP connector init, intel_hdcp_init is passed with a flag for hdcp2.2 support based on the platform capability. v2: Rebased. v3: No Changes. v4: Collected the reviewed-by received. Signed-off-by: Ramalingam C Reviewed-by: Uma Shankar ---

[Intel-gfx] [PATCH v4 41/41] drm/i915: Add HDCP2.2 support for HDMI connectors

On HDMI connector init, intel_hdcp_init is passed with a flag for hdcp2.2 support based on the platform capability. v2: Rebased. v3: No Changes. v4: Collected the reviewed-by received. Signed-off-by: Ramalingam C Reviewed-by: Uma Shankar ---

[Intel-gfx] [PATCH v4 39/41] drm/i915: Implement the HDCP2.2 support for HDMI

Implements the HDMI adaptation specific HDCP2.2 operations. Basically these are DDC read and write for authenticating through HDCP2.2 messages. v2: Rebased. v3: No Changes. v4: No more special handling of Gmbus burst read for AKE_SEND_CERT. Style fixed with few naming. [Uma]

[Intel-gfx] [PATCH v4 34/41] drm/i915: hdcp_check_link only on CP_IRQ

HDCP check link is invoked only on CP_IRQ detection, instead of all short pulses. v3: No Changes. v4: Added sean in cc and collected the reviewed-by received. Signed-off-by: Ramalingam C cc: Sean Paul Reviewed-by: Uma Shankar

[Intel-gfx] [PATCH v4 37/41] drm/i915/gmbus: Enable burst read

Support for Burst read in HW is added for HDCP2.2 compliance requirement. This patch enables the burst read for all the gmbus read of more than 511Bytes, on capable platforms. v2: Extra line is removed. v3: Macro is added for detecting the BURST_READ Support [Jani] Runtime detection of the

[Intel-gfx] [PATCH v4 35/41] drm/i915: Check HDCP 1.4 and 2.2 link on CP_IRQ

On DP HDCP1.4 and 2.2, when CP_IRQ is received, start the link integrity check for the HDCP version that is enabled. v2: Rebased. Function name is changed. v3: No Changes. v4: No Changes. Signed-off-by: Ramalingam C cc: Sean Paul ---

[Intel-gfx] [PATCH v4 33/41] drm/i915: Enable HDCP1.4 incase of HDCP2.2 failure

When HDCP2.2 enabling fails and HDCP1.4 is supported, HDCP1.4 is enabled. v2: Rebased. v3: No Changes. v4: Reviewed-by is collected. Signed-off-by: Ramalingam C Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/intel_hdcp.c | 4 +++- 1 file

[Intel-gfx] [PATCH v4 32/41] drm/i915: Enable superior HDCP ver that is capable

Considering that HDCP2.2 is more secure than HDCP1.4, When a setup supports HDCP2.2 and HDCP1.4, HDCP2.2 will be enabled. v2: Included few optimization suggestions [Chris Wilson] Commit message is updated as per the rebased version. v3: No changes. v4: Extra comment added and Style issue

[Intel-gfx] [PATCH v4 38/41] drm/i915: Implement the HDCP2.2 support for DP

Implements the DP adaptation specific HDCP2.2 functions. These functions perform the DPCD read and write for communicating the HDCP2.2 auth message back and forth. Note: Chris Wilson suggested alternate method for waiting for CP_IRQ, than completions concept. WIP to understand and implement

[Intel-gfx] [PATCH v4 36/41] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

GMBUS HW supports 511Bytes as Max Bytes per single RD/WR op. Instead of enabling the 511Bytes per RD/WR cycle on legacy platforms for no absolute ROIs, this change allows the max bytes per op upto 511Bytes from Gen9 onwards. v2: No Change. v3: Inline function for max_xfer_size and renaming of

[Intel-gfx] [PATCH v4 31/41] drm/i915: Schedule hdcp_check_link in _intel_hdcp_enable

As a preparation for making the intel_hdcp_enable as common function for both HDCP1.4 and HDCP2.2, HDCP1.4 check_link scheduling is moved into _intel_hdcp_enable() function. v3: No Changes. v4: Style fix. Signed-off-by: Ramalingam C Reviewed-by: Uma Shankar

[Intel-gfx] [PATCH v4 30/41] drm/i915: Initialize HDCP2.2 and its MEI interface

Initialize HDCP2.2 support. This includes the mei interface initialization along with required notifier registration. v2: mei interface handle is protected with mutex. [Chris Wilson] v3: Notifiers are used for the mei interface state. v4: Poll for mei client device state Error msg for out

[Intel-gfx] [PATCH v4 29/41] drm/i915: Pullout the bksv read and validation

For reusability purpose, this patch implements the hdcp1.4 bksv's read and validation as a functions. For detecting the HDMI panel's HDCP capability this fucntions will be used. v2: Rebased. v3: No Changes. v4: inline tag is removed with modified error msg. Signed-off-by: Ramalingam C

[Intel-gfx] [PATCH v4 28/41] drm/i915: Handle HDCP2.2 downstream topology change

When repeater notifies a downstream topology change, this patch reauthenticate the repeater alone without disabling the hdcp encryption. If that fails then complete reauthentication is executed. v2: Rebased. v3: No Changes. v4: Typo in commit msg is fixed [Uma] Signed-off-by: Ramalingam C

[Intel-gfx] [PATCH v4 24/41] drm/i915: Implement HDCP2.2 repeater authentication

Implements the HDCP2.2 repeaters authentication steps such as verifying the downstream topology and sending stream management information. v2: Rebased. v3: No Changes. v4: -EINVAL is returned for topology error and rollover scenario. Endianness conversion func from drm_hdcp.h is used

[Intel-gfx] [PATCH v4 25/41] drm/i915: Enable and Disable HDCP2.2 port encryption

Implements the enable and disable functions for HDCP2.2 encryption of the PORT. v2: intel_wait_for_register is used instead of wait_for. [Chris Wilson] v3: No Changes. v4: Debug msg is added for timeout at Disable of Encryption [Uma] %s/HDCP2_CTL/HDCP2_CTL Signed-off-by: Ramalingam C

[Intel-gfx] [PATCH v4 26/41] drm/i915: Implement HDCP2.2 En/Dis-able

Implements a sequence of enabling and disabling the HDCP2.2 (auth and encryption). v2: Rebased. v3: No Changes. v4: No Changes. Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/intel_hdcp.c | 75 +++ 1 file changed, 75

[Intel-gfx] [PATCH v4 27/41] drm/i915: Implement HDCP2.2 link integrity check

Implements the link integrity check once in 500mSec. Once encryption is enabled, an ongoing Link Integrity Check is performed by the HDCP Receiver to check that cipher synchronization is maintained between the HDCP Transmitter and the HDCP Receiver. On the detection of synchronization lost, the

[Intel-gfx] [PATCH v4 23/41] drm/i915: Implement HDCP2.2 receiver authentication

Implements HDCP2.2 authentication for hdcp2.2 receivers, with following steps: Authentication and Key exchange (AKE). Locality Check (LC). Session Key Exchange(SKE). DP Errata for stream type configuration for receivers. At AKE, the HDCP Receiver’s public key

[Intel-gfx] [PATCH v4 20/41] drm/i915: Define HDCP2.2 related variables

For upcoming implementation of HDCP2.2 in I915, important variable required for HDCP2.2 are defined. HDCP_shim is extended to support encoder specific HDCP2.2 flows. v2: 1.4 shim is extended to support hdcp2.2. [Sean Paul] platform's/panel's hdcp ver capability is removed. [Sean Paul] mei

[Intel-gfx] [PATCH v4 21/41] drm/i915: Define Intel HDCP2.2 registers

Intel HDCP2.2 registers are defined with addr offsets and bit details. v2: Replaced the arith calc with _PICK [Sean Paul] v3: No changes. v4: %s/HDCP2_CTR_DDI/HDCP2_CTL_DDI [Uma] Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/i915_reg.h | 32

[Intel-gfx] [PATCH v4 18/41] misc/mei/hdcp: Closing wired HDCP2.2 Tx Session

Request the ME to terminate the HDCP2.2 session for a port. On Success, ME FW will mark the intel port as Deauthenticated and terminate the wired HDCP2.2 Tx session started due to the cmd WIRED_INITIATE_HDCP2_SESSION. v2: Rebased. v3: cldev is passed as first parameter [Tomas] Redundant

[Intel-gfx] [PATCH v4 22/41] drm/i915: Wrappers for mei HDCP2.2 services

Adds the wrapper for all mei hdcp2.2 service functions. v2: Rebased. v3: cldev is moved from mei_hdcp_data to hdcp. v4: %s/hdcp2_store_paring_info/hdcp2_store_pairing_info Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/intel_hdcp.c | 194

[Intel-gfx] [PATCH v4 17/41] misc/mei/hdcp: Enabling the HDCP authentication

Request to ME to configure a port as authenticated. On Success, ME FW will mark the port as authenticated and provides HDCP cipher with the encryption keys. Enabling the Authentication can be requested once all stages of HDCP2.2 authentication is completed by interacting with ME FW. Only after

[Intel-gfx] [PATCH v4 19/41] drm/i915: wrapping all hdcp var into intel_hdcp

Considering significant number of HDCP specific variables, it will be clean to have separate struct for HDCP. New structure called intel_hdcp is added within intel_connector. v2: struct hdcp statically allocated. [Sean Paul] enable and disable function parameters are retained.[Sean Paul] v3:

[Intel-gfx] [PATCH v4 16/41] misc/mei/hdcp: Verify M_prime

Request to ME to verify the M_Prime received from the HDCP sink. ME FW will calculate the M and compare with M_prime received as part of RepeaterAuth_Stream_Ready, which is HDCP2.2 protocol msg. On successful completion of this stage, downstream propagation of the stream management info is

[Intel-gfx] [PATCH v4 13/41] misc/mei/hdcp: Verify L_prime

Request to ME to verify the LPrime received from HDCP sink. On Success, ME FW will verify the received Lprime by calculating and comparing with L. This represents the completion of Locality Check. v2: Rebased. v3: cldev is passed as first parameter [Tomas] Redundant comments and cast are

[Intel-gfx] [PATCH v4 14/41] misc/mei/hdcp: Prepare Session Key

Request to ME to prepare the encrypted session key. On Success, ME provides Encrypted session key. Function populates the HDCP2.2 authentication msg SKE_Send_Eks. v2: Rebased. v3: cldev is passed as first parameter [Tomas] Redundant comments and cast are removed [Tomas] v4: %zd for

[Intel-gfx] [PATCH v4 15/41] misc/mei/hdcp: Repeater topology verification and ack

Request ME to verify the downstream topology information received. ME FW will validate the Repeaters receiver id list and downstream topology. On Success ME FW will provide the Least Significant 128bits of VPrime, which forms the repeater ack. v2: Rebased. v3: cldev is passed as first

[Intel-gfx] [PATCH v4 12/41] misc/mei/hdcp: Initiate Locality check

Requests ME to start the second stage of HDCP2.2 authentication, called Locality Check. On Success, ME FW will provide LC_Init message to send to hdcp sink. v2: Rebased. v3: cldev is passed as first parameter [Tomas] Redundant comments and cast are removed [Tomas] v4: %zd used for

[Intel-gfx] [PATCH v4 11/41] misc/mei/hdcp: Store the HDCP Pairing info

Provides Pairing info to ME to store. Pairing is a process to fast track the subsequent authentication with the same HDCP sink. On Success, received HDCP pairing info is stored in non-volatile memory of ME. v2: Rebased. v3: cldev is passed as first parameter [Tomas] Redundant comments and

[Intel-gfx] [PATCH v4 10/41] misc/mei/hdcp: Verify H_prime

Requests for the verification of AKE_Send_H_prime. ME will calculate the H and comparing it with received H_Prime. The result will be returned as status. Here AKE_Send_H_prime is a HDCP2.2 Authentication msg. v2: Rebased. v3: cldev is passed as first parameter [Tomas] Redundant comments

[Intel-gfx] [PATCH v4 07/41] linux/mei: Header for mei_hdcp driver interface

Data structures and Enum for the I915-MEI_HDCP interface are defined at v2: Rebased. v3: mei_cl_device is removed from mei_hdcp_data [Tomas] v4: Comment style and typo fixed [Uma] Signed-off-by: Ramalingam C --- include/linux/mei_hdcp.h | 70

[Intel-gfx] [PATCH v4 06/41] misc/mei/hdcp: Define ME FW interface for HDCP2.2

Defines the HDCP specific ME FW interfaces such as Request CMDs, payload structure for CMDs and their response status codes. This patch defines payload size(Excluding the Header)for each WIRED HDCP2.2 CMDs. v2: Rebased. v3: Extra comments are removed. v4: %s/\/\*\*/\/\* Signed-off-by:

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