Developed on top of renesas-drivers-2018-05-15-v4.17-rc5
>
> Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt |2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Rob Herring
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f/irq.c | 5 +--
> drivers/pci/of.c | 101 --
> include/linux/of.h | 11 +
> include/linux/of_pci.h | 10 -
> 6 files changed, 117 insertions(+), 117 deletions(-)
Reviewed-by: Rob Herring
__
ude/linux/of_device.h | 8 ++--
> 10 files changed, 17 insertions(+), 19 deletions(-)
Reviewed-by: Rob Herring
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d-off-by: Nipun Gupta
> ---
> .../devicetree/bindings/misc/fsl,qoriq-mc.txt | 39
> ++
> 1 file changed, 39 insertions(+)
Reviewed-by: Rob Herring
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On Fri, Apr 27, 2018 at 03:57:02PM +0530, Nipun Gupta wrote:
> iommu-map property is also used by devices with fsl-mc. This
> patch moves the of_pci_map_rid to generic location, so that it
> can be used by other busses too.
>
> 'of_pci_map_rid' is renamed here to 'of_map_rid' and there is no
> fun
On Tue, Apr 10, 2018 at 01:26:41PM +0200, Heiko Stuebner wrote:
> Hi Robin,
>
> Am Dienstag, 10. April 2018, 13:18:48 CEST schrieb Robin Murphy:
> > On 10/04/18 10:26, Heiko Stuebner wrote:
> > > Rockchip IOMMUs are used without explicit clock handling for 4 years
> > > now, so we should keep comp
++---
> drivers/of/device.c | 6 --
> drivers/of/of_reserved_mem.c | 2 +-
> drivers/pci/pci-driver.c | 3 +--
> include/linux/device.h| 4
> include/linux/of_device.h | 8 ++++++--
> 10 files changed, 17 insertions(+), 19 deletions(-)
Reviewed-by:
On Fri, Mar 16, 2018 at 8:51 AM, Geert Uytterhoeven
wrote:
> Hi all,
>
> If NO_DMA=y, get_dma_ops() returns a reference to the non-existing
> symbol bad_dma_ops, thus causing a link failure if it is ever used.
>
> The intention of this is twofold:
> 1. To catch users of the DMA API on sy
; Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt |1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring
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On Fri, Mar 23, 2018 at 03:38:09PM +0800, Jeffy Chen wrote:
> Add clock property, since we are going to control clocks in rockchip
> iommu driver.
>
> Signed-off-by: Jeffy Chen
> Reviewed-by: Robin Murphy
> ---
Reviewed-by: Rob Herring
___
On Mon, Mar 05, 2018 at 07:59:21PM +0530, Nipun Gupta wrote:
> The existing IOMMU bindings cannot be used to specify the relationship
> between fsl-mc devices and IOMMUs. This patch adds a binding for
> mapping fsl-mc devices to IOMMUs, using a new iommu-parent property.
>
> Signed-off-by: Nipun G
On Wed, Mar 7, 2018 at 12:32 AM, Vivek Gautam
wrote:
> Qualcomm's arm-smmu 500 implementation supports runtime pm
> so enable the same.
That's a driver detail unrelated to the binding.
>
> Signed-off-by: Vivek Gautam
> ---
>
> Based on iommu/arm-smmu pm runtime support series [1]:
> [PATCH v8
es in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> Documentation/devicetree/bindings/iommu/rockchip,iommu.txt | 7 +++
> 1 file changed, 7 insertions(+)
Reviewed-by: Rob Herring
changed, 1 insertion(+)
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pasid-bits: Some masters support multiple address spaces for DMA, by
> + tagging DMA transactions with an address space identifier. By default,
> + this is 0, which means that the device only has one address space.
So 3 would mean 8 address spaces?
Maybe pasid-num-bits would be a bi
On Wed, Jan 31, 2018 at 1:52 AM, Tomasz Figa wrote:
> Hi Rob,
>
> On Wed, Jan 31, 2018 at 2:05 AM, Rob Herring wrote:
>> On Wed, Jan 24, 2018 at 06:35:11PM +0800, Jeffy Chen wrote:
>>> From: Tomasz Figa
>>>
>>> Current code relies on master driver ena
On Wed, Jan 24, 2018 at 06:35:11PM +0800, Jeffy Chen wrote:
> From: Tomasz Figa
>
> Current code relies on master driver enabling necessary clocks before
> IOMMU is accessed, however there are cases when the IOMMU should be
> accessed while the master is not running yet, for example allocating
>
gned-off-by: Vivek Gautam
> ---
> .../devicetree/bindings/iommu/arm,smmu.txt | 43
> ++
> drivers/iommu/arm-smmu.c | 13 +++
> 2 files changed, 56 insertions(+)
Reviewed-by: Rob Herring
___
On Tue, Jan 09, 2018 at 03:31:48PM +0530, Vivek Gautam wrote:
> qcom,smmu-v2 is an arm,smmu-v2 implementation with specific
> clock and power requirements. This smmu core is used with
> multiple masters on msm8996, viz. mdss, video, etc.
> Add bindings for the same.
>
> Signed-off-by: Vivek Gautam
On Mon, Oct 16, 2017 at 5:23 AM, Jean-Philippe Brucker
wrote:
> On 13/10/17 20:10, Rob Herring wrote:
>> On Fri, Oct 06, 2017 at 02:31:39PM +0100, Jean-Philippe Brucker wrote:
>>> On ARM systems, some platform devices behind an IOMMU may support stall
>>> and PASID fea
On Fri, Oct 06, 2017 at 02:31:39PM +0100, Jean-Philippe Brucker wrote:
> On ARM systems, some platform devices behind an IOMMU may support stall
> and PASID features. Stall is the ability to recover from page faults and
> PASID offers multiple process address spaces to the device. Together they
> a
On Wed, Oct 04, 2017 at 02:33:08PM +0200, Geert Uytterhoeven wrote:
> Use the preferred generic node name in the example.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied.
by: John Garry
> [Shameer: Modified to use compatible string for errata]
> Signed-off-by: Shameer Kolothum
> ---
> Documentation/arm64/silicon-errata.txt | 1 +
> Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 9 ++++++++-
>
; Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt |1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring
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; Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt |1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring
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On Thu, Sep 14, 2017 at 01:57:52PM +0100, Shameer Kolothum wrote:
> From: John Garry
>
> The HiSilicon erratum 161010801 describes the limitation of HiSilicon
> platforms
> hip06/hip07 to support the SMMU mappings for MSI transactions.
>
> On these platforms, GICv3 ITS translator is presented w
On Tue, Sep 12, 2017 at 05:31:07PM +0530, Vivek Gautam wrote:
> ARM MMU-500 implements a TBU (uTLB) for each connected master
> besides a single TCU which controls and manages the address
> translations. Each of these TBUs can either be in the same
> power domain as the master, or they can have a i
ed, SW can NOT adjust it.
>
> Signed-off-by: Yong Wu
> ---
> Hi Rob,
> Comparing with the v1, I add larb8 and larb9 in this version.
> So I don't add your ACK here.
Thanks for the explanation. That's minor enough you could have kept it.
Acked-by: Rob Herring
4 files changed, 102 insertions(+), 6 deletions(-)
> create mode 100644 include/dt-bindings/memory/mt2712-larb-port.h
Acked-by: Rob Herring
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Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring
Cc: Joerg Roedel
Cc: Heiko Stuebner
Cc: iommu@lists.linux-foundation.org
Cc: linux-arm-ker
On Thu, Jul 06, 2017 at 03:07:05PM +0530, Vivek Gautam wrote:
> qcom,msm8996-smmu-v2 is an arm,smmu-v2 implementation with
> specific clock and power requirements. This smmu core is used
> with multiple masters on msm8996, viz. mdss, video, etc.
> Add bindings for the same.
>
> Signed-off-by: Vive
On Thu, Jul 06, 2017 at 03:07:04PM +0530, Vivek Gautam wrote:
> From: Sricharan R
>
> The MMU400x/500 is the implementation of the SMMUv2
> arch specification. It is split in to two blocks
> TBU, TCU. TBU caches the page table, instantiated
> for each master locally, clocked by the TBUn_clk.
> TC
On Thu, Jun 01, 2017 at 01:28:01PM +0100, Jean-Philippe Brucker wrote:
> On 31/05/17 18:23, Rob Herring wrote:
> > On Wed, May 24, 2017 at 07:01:38PM +0100, Jean-Philippe Brucker wrote:
> >> Address Translation Service (ATS) is an extension to PCIe allowing
> >> endpoint
On Wed, May 24, 2017 at 07:01:38PM +0100, Jean-Philippe Brucker wrote:
> Address Translation Service (ATS) is an extension to PCIe allowing
> endpoints to manage their own IOTLB, called Address Translation Cache
> (ATC). Instead of having every memory transaction processed by the IOMMU,
> the endpo
On Tue, May 30, 2017 at 11:58:50AM +0100, Jean-Philippe Brucker wrote:
> On 30/05/17 11:01, Joerg Roedel wrote:
> > On Wed, May 24, 2017 at 07:01:38PM +0100, Jean-Philippe Brucker wrote:
> >> +- ats-supported: if present, the root complex supports the Address
> >> + Translation Service (ATS). It i
DT changes should go to DT list.
On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya
wrote:
> From: Linu Cherian
>
> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
> and PAGE0_REGS_ONLY option is enabled as an errata workaround.
> This option when turned on, replaces all
On Sat, May 13, 2017 at 4:47 AM, shameer
wrote:
> Signed-off-by: shameer
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
> b/Documentation/devicetree/
umentation/devicetree/bindings/iommu/qcom,iommu.txt
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On Fri, May 5, 2017 at 2:37 PM, Rob Clark wrote:
> On Fri, May 5, 2017 at 3:04 PM, Rob Herring wrote:
>> On Fri, May 5, 2017 at 1:21 PM, Rob Clark wrote:
>>> An iommu driver for Qualcomm "B" family devices which do not completely
>>> implement the ARM SMMU s
On Fri, May 5, 2017 at 1:21 PM, Rob Clark wrote:
> An iommu driver for Qualcomm "B" family devices which do not completely
> implement the ARM SMMU spec. These devices have context-bank register
> layout that is similar to ARM SMMU, but no global register space (or at
> least not one that is acce
On Thu, May 4, 2017 at 8:34 AM, Rob Clark wrote:
> An iommu driver for Qualcomm "B" family devices which do not completely
> implement the ARM SMMU spec. These devices have context-bank register
> layout that is similar to ARM SMMU, but no global register space (or at
> least not one that is acce
On Tue, May 2, 2017 at 11:46 PM, Oza Pawandeep wrote:
> current device framework and of framework integration assumes
> dma-ranges in a way where memory-mapped devices define their
> dma-ranges. (child-bus-address, parent-bus-address, length).
>
> of_dma_configure is specifically written to take c
On Tue, May 2, 2017 at 11:46 PM, Oza Pawandeep wrote:
> current device framework and of framework integration assumes
> dma-ranges in a way where memory-mapped devices define their
> dma-ranges. (child-bus-address, parent-bus-address, length).
>
> of_dma_configure is specifically written to take c
On Sat, Apr 22, 2017 at 3:08 AM, Oza Pawandeep wrote:
> current device frmework and of framework integration assumes dma-ranges
> in a way where memory-mapped devices define their dma-ranges.
> dma-ranges: (child-bus-address, parent-bus-address, length).
>
> but iproc based SOCs and other SOCs(suc
On Thu, Apr 6, 2017 at 5:24 AM, Robin Murphy wrote:
> On 06/04/17 08:01, Frank Rowand wrote:
>> On 04/04/17 03:18, Sricharan R wrote:
>>> Size of the dma-range is calculated as coherent_dma_mask + 1
>>> and passed to arch_setup_dma_ops further. It overflows when
>>> the coherent_dma_mask is set fo
> bus/driver is called. Similarly dma_deconfigure is called during
> device/driver_detach path.
For patches 3, 4, 6, 7, 8:
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On Fri, Mar 10, 2017 at 12:30:57AM +0530, Sricharan R wrote:
> From: Laurent Pinchart
>
> Failures to look up an IOMMU when parsing the DT iommus property need to
> be handled separately from the .of_xlate() failures to support deferred
> probing.
>
> The lack of a registered IOMMU can be caused
On Tue, Mar 28, 2017 at 12:27 AM, Oza Oza wrote:
> On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring wrote:
>> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep wrote:
>>> it is possible that PCI device supports 64-bit DMA addressing,
>>> and thus it's driver sets devi
On Thu, Mar 23, 2017 at 9:45 PM, Rob Clark wrote:
> On Thu, Mar 23, 2017 at 6:21 PM, Rob Herring wrote:
>> On Tue, Mar 14, 2017 at 11:18:05AM -0400, Rob Clark wrote:
>>> Cc: devicet...@vger.kernel.org
>>> Signed-off-by: Rob Clark
>>> ---
>>>
On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep wrote:
> it is possible that PCI device supports 64-bit DMA addressing,
> and thus it's driver sets device's dma_mask to DMA_BIT_MASK(64),
> however PCI host bridge may have limitations on the inbound
> transaction addressing. As an example, consider
On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep wrote:
> it jumps to the parent node without examining the child node.
> also with that, it throws "no dma-ranges found for node"
> for pci dma-ranges.
>
> this patch fixes device node traversing for dma-ranges.
What's the DT look like that doesn't
On Tue, Mar 14, 2017 at 11:18:05AM -0400, Rob Clark wrote:
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Rob Clark
> ---
> .../devicetree/bindings/iommu/qcom,iommu.txt | 113
> +
> 1 file changed, 113 insertions(+)
> create mode 100644 Documentation/devicetree/bind
On Thu, Mar 09, 2017 at 09:05:46PM +0530, Sricharan R wrote:
> The QCOM_SMMUV2 is an implementation of the arm,smmu-v2 architecture.
> The qcom,smmu is instantiated for each of the multimedia cores (for eg)
> Venus (video encoder/decoder), mdp (display) etc, and they are connected
> to the Multimed
On Thu, Mar 09, 2017 at 09:05:45PM +0530, Sricharan R wrote:
> The MMU400x/500 is the implementation of the SMMUv2
> arch specification. It is split in to two blocks
> TBU, TCU. TBU caches the page table, instantiated
> for each master locally, clocked by the TBUn_clk.
> TCU manages the address tra
On Wed, Mar 01, 2017 at 12:42:52PM -0500, Rob Clark wrote:
Nit: use "dt-bindings: iommu: ..." for subject. And a commit message
would be nice.
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Rob Clark
> ---
> .../devicetree/bindings/iommu/qcom,iommu.txt | 106
> +
>
On Fri, Feb 03, 2017 at 04:10:30PM +0200, Laurent Pinchart wrote:
> Hi Rob,
>
> On Monday 29 Feb 2016 23:33:09 Magnus Damm wrote:
> > From: Magnus Damm
> >
> > Update the IPMMU DT binding documentation to include the r8a7795 compat
> > string as well as the "renesas,ipmmu-main" property that on
On Fri, Dec 16, 2016 at 01:19:29PM +, Robin Murphy wrote:
> The current SMR masking support using a 2-cell iommu-specifier is
> primarily intended to handle individual masters with large and/or
> complex Stream ID assignments; it quickly gets a bit clunky in other SMR
> use-cases where we just
On Thu, Dec 15, 2016 at 06:16:13PM -0600, Stuart Yoder wrote:
> The generic IOMMU binding says that the meaning of an 'IOMMU specifier'
> is defined by the binding of a specific SMMU. The ARM SMMU binding
> never explicitly uses the term 'specifier' at all. Update implicit
> references to use the
since V1:
> - Added Acked-by from Laurent - thanks!
>
> Now broken out, however earlier V1 posted as part of:
> [PATCH 0/3] iommu/ipmmu-vmsa: Initial r8a7796 support
>
> Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt |1 +
> 1
On Mon, Sep 12, 2016 at 05:13:43PM +0100, Robin Murphy wrote:
> We're about to ratify our use of the generic binding, so document it.
>
> CC: Rob Herring
> CC: Mark Rutland
> Signed-off-by: Robin Murphy
>
> ---
>
> - Reference PCI "iommu-map" b
On Tue, Aug 23, 2016 at 08:05:27PM +0100, Robin Murphy wrote:
> Document how the generic "iommus" binding should be used to describe ARM
> SMMU stream IDs instead of the old "mmu-masters" binding.
>
> CC: Rob Herring
> CC: Mark Rutland
> Signed-off-by:
On Mon, Jul 25, 2016 at 10:09 AM, Robin Murphy wrote:
> Hi Lorenzo,
>
> On 20/07/16 12:23, Lorenzo Pieralisi wrote:
>> The iommu_fwspec structure, used to hold per device iommu configuration
>> data is not OF specific and therefore can be moved to a generic
>> and OF independent compilation unit.
g routine up yet another layer into the general OF-PCI code,
> and further generalise it for either kind of lookup in either flavour
> of map property.
>
> CC: Rob Herring
> CC: Frank Rowand
> Acked-by: Marc Zyngier
> Signed-off-by: Robin Murphy
I've only skimmed th
g routine up yet another layer into the general OF-PCI code,
> and further generalise it for either kind of lookup in either flavour
> of map property.
>
> CC: Rob Herring
> CC: Frank Rowand
> CC: Marc Zyngier
> Signed-off-by: Robin Murphy
> ---
>
> v2: No
ed micro-TLB.
> Adding the DT bindings for the same.
>
> Signed-off-by: Sricharan R
> ---
> .../devicetree/bindings/iommu/msm,iommu-v0.txt | 64
> ++
> 1 file changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iommu/msm
> 4 files changed, 115 insertions(+), 8 deletions(-)
> create mode 100644 include/dt-bindings/memory/mt2701-larb-port.h
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On Mon, May 16, 2016 at 12:18:56PM +0530, Sricharan R wrote:
> The MSM IOMMU is an implementation compatible with the ARM VMSA short
> descriptor page tables. It provides address translation for bus masters
> outside
> of the CPU, each connected to the IOMMU through a port called micro-TLB.
> Addi
On Mon, May 09, 2016 at 04:00:12PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> This patch defines the local arbitor port IDs for mediatek SoC MT2701 and
> add descriptions of binding for mediatek generation one iommu and smi.
>
> Signed-off-by: Honghui Zhang
> ---
> .../
v8:
> - Added this patch
> Changes for v9:
> - Added a list for the possible compatibles
> Changes for v10:
> - None
> ---
> Documentation/devicetree/bindings/arm/fsl.txt | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
Acked-by: Rob Herring
_
On Mon, May 02, 2016 at 12:24:30AM +0530, Sricharan R wrote:
> The MSM IOMMU is an implementation compatible with the ARM VMSA short
> descriptor page tables. It provides address translation for bus masters
> outside
> of the CPU, each connected to the IOMMU through a port called micro-TLB.
> Addi
On Mon, Apr 4, 2016 at 10:49 AM, Joerg Roedel wrote:
> Hi,
>
> here is a new version of the implementation of the iterator
> over phandles concept which Rob Herring suggested to me some
> time ago. My approach is a little bit different from what
> the diff showed back then, but
On Wed, Apr 06, 2016 at 07:59:31PM +0530, Sricharan R wrote:
> The driver currently works based on platform data. Remove this
> and add support for DT. A single master can have multiple ports
> connected to more than one iommu.
>
> master
> |
>
None
> ---
> Documentation/devicetree/bindings/{powerpc => soc}/fsl/guts.txt | 3 +++
> 1 file changed, 3 insertions(+)
> rename Documentation/devicetree/bindings/{powerpc => soc}/fsl/guts.txt (91%)
Acked-by: Rob Herring
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On Wed, Mar 23, 2016 at 6:54 AM, Joerg Roedel wrote:
> Hi Rob,
>
> On Tue, Mar 22, 2016 at 01:45:41PM -0500, Rob Herring wrote:
>> On Tue, Mar 22, 2016 at 12:58 PM, Joerg Roedel wrote:
>> > Please review. Patches are based on v4.5.
>>
>> Other than my one com
On Tue, Mar 22, 2016 at 12:58 PM, Joerg Roedel wrote:
> Hi,
>
> here is an implementation of the iterator over phandles
> concept which Rob Herring suggested to me some time ago. My
> approach is a little bit different from what the diff showed
> back then, but it gets rid of
On Tue, Mar 22, 2016 at 12:58 PM, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Remove the usage of of_parse_phandle_with_args() and replace
> it by the phandle-iterator implementation so that we can
> parse out all of the potentially present 128 stream-ids.
>
> Signed-off-by: Joerg Roedel
> ---
On Wed, Mar 09, 2016 at 06:08:49PM +0800, Yangbo Lu wrote:
> Move guts devicetree doc to Documentation/devicetree/bindings/soc/fsl/
> since it's used by not only PowerPC but also ARM. And add a specification
> for 'little-endian' property.
>
> Signed-off-by: Yangbo Lu
> ---
> Changes for v2:
>
On Thu, Mar 17, 2016 at 12:11 PM, Arnd Bergmann wrote:
> On Thursday 17 March 2016 12:06:40 Rob Herring wrote:
>> > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt
>> > b/Documentation/devicetree/bindings/soc/fsl/guts.txt
>> > similar
-...@vger.kernel.org;
> >> ulf.hans...@linaro.org; Zhao Qiang; Russell King; Bhupesh Sharma; Joerg
> >> Roedel; Santosh Shilimkar; Scott Wood; Rob Herring; Claudiu Manoil; Kumar
> >> Gala; Yang-Leo Li; Xiaobo Xie
> >> Subject: Re: [v6, 5/5] mmc: sdhci-of-
On Wed, Mar 16, 2016 at 11:42 AM, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Getting the arguments of phandles is somewhat limited at the
> moement, because the number of arguments supported by core
> code is limited to MAX_PHANDLE_ARGS, which is set to 16
> currently.
>
> In case of the arm sm
ndings/iommu/arm,smmu.txt | 40
> ++
> 1 file changed, 25 insertions(+), 15 deletions(-)
Acked-by: Rob Herring
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ions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/pci-iommu.txt
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ocumentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> create mode 100644 include/dt-bindings/memory/mt8173-larb-port.h
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On Fri, Dec 18, 2015 at 04:09:39PM +0800, Yong Wu wrote:
> This patch add mediatek iommu dts binding document.
>
> Signed-off-by: Yong Wu
Acked-by: Rob Herring
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On Tue, Dec 08, 2015 at 05:49:10PM +0800, Yong Wu wrote:
> This patch add smi binding document.
>
> Signed-off-by: Yong Wu
Acked-by: Rob Herring
> ---
> .../memory-controllers/mediatek,smi-common.txt | 24 +
> .../memory-controllers/mediatek,smi-l
On Tue, Dec 08, 2015 at 05:49:09PM +0800, Yong Wu wrote:
> This patch add mediatek iommu dts binding document.
>
> Signed-off-by: Yong Wu
> ---
> .../devicetree/bindings/iommu/mediatek,iommu.txt | 68 +
> include/dt-bindings/memory/mt8173-larb-port.h | 111
>
On Fri, Nov 20, 2015 at 10:25:07AM +0800, Chen Feng wrote:
> Documentation for hi6220 iommu driver.
>
> Signed-off-by: Chen Feng
Acked-by: Rob Herring
> ---
> .../bindings/iommu/hisi,hi6220-iommu.txt | 32
> ++
> 1 file changed, 32 inserti
ck.
>
> Signed-off-by: Magnus Damm
Acked-by: Rob Herring
> ---
>
> Changes since V1:
> - Updated compat string section to the following:
>"Must contain SoC-specific and generic entries from below."
>
> Thanks to Laurent for feedback!
>
> Docu
On Tue, Nov 17, 2015 at 5:57 AM, Chen Feng wrote:
> Documentation for hi6220 iommu driver.
Please use get_maintainers.pl and re-send to correct lists
(devicet...@vger.kernel.org).
>
> Signed-off-by: Chen Feng
> ---
> .../bindings/iommu/hisi,hi6220-iommu.txt | 32
> ++
On Thu, Nov 05, 2015 at 09:34:43PM +0800, Chen Feng wrote:
> Add Document for mtcmos driver on hi6220 SoC
>
> Signed-off-by: Chen Feng
> Signed-off-by: Fei Wang
> ---
> .../bindings/regulator/hisilicon,hi6220-mtcmos.txt | 32
> ++
> 1 file changed, 32 insertions(+)
> creat
On Mon, Aug 24, 2015 at 5:17 AM, Mark Rutland wrote:
> On Wed, Aug 05, 2015 at 05:51:20PM +0100, Mark Rutland wrote:
>> Rob,
>>
>> Do you have any objections to this, or are you happy to take this patch?
>>
>> There's a user of this binding (the GICv3 ITS) queued for v4.3 already in
>> the tip tre
On Thu, Jul 16, 2015 at 6:09 AM, Joerg Roedel wrote:
> Hi Will,
>
> On Thu, Jul 16, 2015 at 11:23:26AM +0100, Will Deacon wrote:
>> On Thu, Jul 16, 2015 at 09:30:43AM +0100, Joerg Roedel wrote:
>> > +struct of_phandle_args *of_alloc_phandle_args(int size)
>> > +{
>> > + struct of_phandle_args *a
On Thu, May 14, 2015 at 6:00 PM, Laurent Pinchart
wrote:
> The of_configure_dma() function configures both the DMA masks and ops.
> Moving DMA ops configuration to probe time would thus also delay
> configuration of the DMA masks, which might not be safe. To avoid issues
> split the configuration
function is.
>
> Signed-off-by: Laurent Pinchart
One minor fix below, but otherwise:
Acked-by: Rob Herring
> ---
> drivers/of/device.c | 12
> drivers/of/platform.c | 5 -
> include/linux/of_device.h | 3 +++
> 3 files changed, 15 insertions(+)
ation will change when moving DMA configuration to device probe
> time.
>
> Signed-off-by: Laurent Pinchart
> ---
> drivers/of/address.c | 20 ++--
> drivers/of/device.c | 15 ---
Please use get_maintainers.pl. Anyway, looks fine to me:
Acked-by: Ro
On Mon, May 4, 2015 at 3:15 AM, Marek Szyprowski
wrote:
> Some devices (like frame buffers) are enabled by bootloader and configured
> to perform DMA operations automatically (like displaying boot logo or splash
> screen). Such devices operate and perform DMA operation usually until the
> proper d
n the DMA
> configuration for the slave PCI device.
>
> Tested-by: Suravee Suthikulpanit (AMD Seattle)
> Signed-off-by: Murali Karicheri
> Signed-off-by: Bjorn Helgaas
> Reviewed-by: Catalin Marinas
> Acked-by: Will Deacon
> CC: Joerg Roedel
> CC: Grant Likely
> CC: Rob
On Wed, Jan 28, 2015 at 5:32 PM, Laurent Pinchart
wrote:
> Hi Will,
>
> On Wednesday 28 January 2015 13:32:19 Will Deacon wrote:
>> On Wed, Jan 28, 2015 at 01:15:10PM +, Laurent Pinchart wrote:
>> > On Wednesday 28 January 2015 12:29:42 Will Deacon wrote:
>> >> On Wed, Jan 28, 2015 at 12:23:03
DTS. So add a work around to
>> >> catch this and fix.
>> >>
>> >> Cc: Joerg Roedel
>> >> Cc: Grant Likely
>> >> Cc: Rob Herring
>> >> Cc: Bjorn Helgaas
>> >> Cc: Will Deacon
>> >> Cc: Russell King
implementing this.
>
> Cc: Joerg Roedel
> Cc: Grant Likely
> Cc: Rob Herring
Acked-by: Rob Herring
> Cc: Will Deacon
> Cc: Russell King
> Cc: Arnd Bergmann
> Cc: Suravee Suthikulpanit
>
> Acked-by: Bjorn Helgaas
> Signed-off-by: Murali Kari
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