This patch add some clock binding id for different modules
that under development and going to send upstream.
This patch also add the clock node in PD_VIDEO.
Changes in v2:
- split into two patches of add clock node in PD_VIDEO and
use new defined clock ID
Kever Yang (3):
clk: rockchip: add
This patch use the new defined clock ID to initial the clock nodes.
Signed-off-by: Kever Yang
Reviewed-by: Heiko Stuebner
---
Changes in v2:
- split into two patches of add clock node in PD_VIDEO and
use new defined clock ID
drivers/clk/rockchip/clk-rk3288.c | 68
This patch use the new defined clock ID to initial the clock nodes.
This patch also add the clock nodes in PD_VIDEO.
Signed-off-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3288.c | 79 ++-
1 file changed, 45 insertions(+), 34 deletions(-)
diff --git
This patch add some clock binding id for different modules
that under development and going to send upstream.
Signed-off-by: Kever Yang
---
include/dt-bindings/clock/rk3288-cru.h | 38 +-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/include/dt
This patch add some clock binding id for different modules
that under development and going to send upstream.
This patch also add the clock node in PD_VIDEO.
Kever Yang (2):
clk: rockchip: add some needed clock binding id for rk3288
clk: rockchip: use the clock id for nodes init
drivers
Heiko,
On 09/24/2014 01:52 AM, Heiko Stübner wrote:
Am Montag, 22. September 2014, 19:55:16 schrieb jinkun.hong:
From: "jinkun.hong"
Signed-off-by: Jack Dai
Signed-off-by: Wang Caesar
Signed-off-by: jinkun.hong
---
arch/arm/boot/dts/rk3288.dtsi | 45
Heiko,
On 09/24/2014 01:52 AM, Heiko Stübner wrote:
Am Montag, 22. September 2014, 19:55:16 schrieb jinkun.hong:
From: jinkun.hong jinkun.h...@rock-chips.com
Signed-off-by: Jack Dai jack@rock-chips.com
Signed-off-by: Wang Caesar caesar.w...@rock-chips.com
Signed-off-by: jinkun.hong
This patch add some clock binding id for different modules
that under development and going to send upstream.
This patch also add the clock node in PD_VIDEO.
Kever Yang (2):
clk: rockchip: add some needed clock binding id for rk3288
clk: rockchip: use the clock id for nodes init
drivers
This patch add some clock binding id for different modules
that under development and going to send upstream.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
include/dt-bindings/clock/rk3288-cru.h | 38 +-
1 file changed, 37 insertions(+), 1 deletion
This patch use the new defined clock ID to initial the clock nodes.
This patch also add the clock nodes in PD_VIDEO.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 79 ++-
1 file changed, 45 insertions(+), 34
This patch use the new defined clock ID to initial the clock nodes.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Reviewed-by: Heiko Stuebner he...@sntech.de
---
Changes in v2:
- split into two patches of add clock node in PD_VIDEO and
use new defined clock ID
drivers/clk/rockchip/clk
This patch add some clock binding id for different modules
that under development and going to send upstream.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Reviewed-by: Heiko Stuebner he...@sntech.de
---
Changes in v2: None
include/dt-bindings/clock/rk3288-cru.h | 38
This patch add some clock binding id for different modules
that under development and going to send upstream.
This patch also add the clock node in PD_VIDEO.
Changes in v2:
- split into two patches of add clock node in PD_VIDEO and
use new defined clock ID
Kever Yang (3):
clk: rockchip: add
This patch add the clock node in PD_VIDEO
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Reviewed-by: Heiko Stuebner he...@sntech.de
---
Changes in v2:
- split out the patch
drivers/clk/rockchip/clk-rk3288.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/clk
Hi Doug,
On 09/25/2014 03:48 AM, Doug Anderson wrote:
Kever,
On Wed, Sep 24, 2014 at 8:33 AM, Kever Yang kever.y...@rock-chips.com wrote:
This patch add the clock node in PD_VIDEO
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Reviewed-by: Heiko Stuebner he...@sntech.de
---
Changes
On 09/23/2014 10:55 AM, jinkun.hong wrote:
From: "jinkun.hong"
Any summary for rk3288 power controller?
Maybe you can say something about how rk3288 TRM described this module.
Signed-off-by: Jack Dai
Signed-off-by: Wang Caesar
Signed-off-by: jinkun.hong
---
return of_clk_set_defaults(cru_node, true);
+
+ return 0;
+}
+arch_initcall(rockchip_clk_set_defaults);
+
struct regmap *rockchip_clk_get_grf(void)
{
if (IS_ERR(grf))
This patch works on my rk3288 evb, so,
Tested-by: Kever Yang
--
To unsubscribe from this
works on my rk3288 evb, so,
Tested-by: Kever Yang kever.y...@rock-chips.com
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http
On 09/23/2014 10:55 AM, jinkun.hong wrote:
From: jinkun.hong jinkun.h...@rock-chips.com
Any summary for rk3288 power controller?
Maybe you can say something about how rk3288 TRM described this module.
Signed-off-by: Jack Dai jack@rock-chips.com
Signed-off-by: Wang Caesar
Hi Mark,
Thanks for your comment.
On 09/17/2014 02:54 AM, Mark Rutland wrote:
On Tue, Sep 16, 2014 at 11:44:28AM +0100, Kever Yang wrote:
This add documentation for rk3288 smp dt binding
Signed-off-by: Kever Yang
---
Changes in v2:
- add documentation
Documentation/devicetree
Sonny,
On 09/17/2014 04:17 AM, Sonny Rao wrote:
On Tue, Sep 16, 2014 at 3:44 AM, Kever Yang wrote:
This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
when get into kernel.
Signed-off-by: Heiko Stuebner
Signed-off-by: Kever Yang
---
Changes in v2:
- use rk3288_boot_secondary
This patch add intmem node des which is needed by platsmp.c
and enable the smp.
Signed-off-by: Heiko Stuebner
Signed-off-by: Kever Yang
---
Changes in v2:
- adjust the alignment
arch/arm/boot/dts/rk3288.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm
This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
when get into kernel.
Signed-off-by: Heiko Stuebner
Signed-off-by: Kever Yang
---
Changes in v2:
- use rk3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when
This add documentation for rk3288 smp dt binding
Signed-off-by: Kever Yang
---
Changes in v2:
- add documentation
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree
instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'
- adjust the alignment
Kever Yang (3):
Documentation: dt-bindings: add dt binding info for rk3288-smp
ARM: rockchip: add basic smp support for rk3288
ARM: dts: add intmem node
This add documentation for rk3288 smp dt binding
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- add documentation
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b
instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'
- adjust the alignment
Kever Yang (3):
Documentation: dt-bindings: add dt binding info for rk3288-smp
ARM: rockchip: add basic smp support for rk3288
ARM: dts: add intmem node
This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
when get into kernel.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- use rk3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain
This patch add intmem node des which is needed by platsmp.c
and enable the smp.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- adjust the alignment
arch/arm/boot/dts/rk3288.dtsi | 18 ++
1 file changed, 18
Sonny,
On 09/17/2014 04:17 AM, Sonny Rao wrote:
On Tue, Sep 16, 2014 at 3:44 AM, Kever Yang kever.y...@rock-chips.com wrote:
This patch add basic rk3288 smp support, cpu 1~3 are in wfe state
when get into kernel.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y
Hi Mark,
Thanks for your comment.
On 09/17/2014 02:54 AM, Mark Rutland wrote:
On Tue, Sep 16, 2014 at 11:44:28AM +0100, Kever Yang wrote:
This add documentation for rk3288 smp dt binding
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- add documentation
rk3288 is dual-core CPU Soc, we need to enable the smp.
This patchset works with either arch-timer use the phisical counter
in kernel or the firmware initialize the arch-timer virtual counter
offset and use virtual counter in kernel.
Kever Yang (2):
ARM: rockchip: add basic smp support
This patch add intmem node des which is needed by platsmp.c
and enable the smp.
Signed-off-by: Heiko Stuebner
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts
basic rk3288 smp support
Signed-off-by: Heiko Stuebner
Signed-off-by: Kever Yang
---
arch/arm/mach-rockchip/core.h| 1 +
arch/arm/mach-rockchip/platsmp.c | 60 +---
2 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip
This patch add intmem node des which is needed by platsmp.c
and enable the smp.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm
basic rk3288 smp support
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/mach-rockchip/core.h| 1 +
arch/arm/mach-rockchip/platsmp.c | 60 +---
2 files changed, 57 insertions(+), 4 deletions
rk3288 is dual-core CPU Soc, we need to enable the smp.
This patchset works with either arch-timer use the phisical counter
in kernel or the firmware initialize the arch-timer virtual counter
offset and use virtual counter in kernel.
Kever Yang (2):
ARM: rockchip: add basic smp support
Mark,
Thanks for your reply and advice.
On 08/28/2014 11:11 PM, Mark Rutland wrote:
On Thu, Aug 28, 2014 at 10:17:58AM +0100, Mark Rutland wrote:
Hi Kever,
On Thu, Aug 28, 2014 at 02:40:17AM +0100, Kever Yang wrote:
We need use the hrtimer, which need the arch-timer to be 'always-on'
I
Mark,
Thanks for your reply and advice.
On 08/28/2014 11:11 PM, Mark Rutland wrote:
On Thu, Aug 28, 2014 at 10:17:58AM +0100, Mark Rutland wrote:
Hi Kever,
On Thu, Aug 28, 2014 at 02:40:17AM +0100, Kever Yang wrote:
We need use the hrtimer, which need the arch-timer to be 'always-on'
I
We need use the hrtimer, which need the arch-timer to be 'always-on'
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a..698e6ea 100644
--- a/arch/arm/boot
We need use the hrtimer, which need the arch-timer to be 'always-on'
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a..698e6ea
We need use the hrtimer, which need the arch-timer to be 'always-on'
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a..698e6ea 100644
--- a/arch/arm/boot
Hi Russell,
I'd value your feedback on this if you have a moment.
I think this will need by rk3288 soc.
Thanks
On 08/18/2014 05:58 PM, Kever Yang wrote:
From: Huang Tao
On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of
two conditional store instructions
Hi Russell,
I'd value your feedback on this if you have a moment.
I think this will need by rk3288 soc.
Thanks
On 08/18/2014 05:58 PM, Kever Yang wrote:
From: Huang Tao huang...@rock-chips.com
On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of
two conditional store
We need use the hrtimer, which need the arch-timer to be 'always-on'
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a..698e6ea
instruction. This workaround setting bit[12] of the Feature Register
prevents the erratum. This bit disables an optimisation applied to a
sequence of 2 instructions that use opposing condition codes.
Signed-off-by: Huang Tao
Signed-off-by: Kever Yang
---
arch/arm/Kconfig | 13 +
arch
is an UNPREDICTABLE STR or STM
instruction. This workaround setting bit[12] of the Feature Register
prevents the erratum. This bit disables an optimisation applied to a
sequence of 2 instructions that use opposing condition codes.
Signed-off-by: Huang Tao huang...@rock-chips.com
Signed-off-by: Kever Yang kever.y
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
---
Changes in v5:
- change the sort order of dwc2 in rk3288
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang
Acked-by: Stephen Warren
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang
Acked-by: Paul Zimmerman
---
Changes in v5:
- max_transfer_size change to 65535 to met the requirement of
header file
Changes in v4:
- max_transfer_size
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang
---
Changes in v5:
- don't enable otg port for evb
Changes in v4: None
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi | 4
1 file changed, 4
had post it seprately.
Changes in v3:
- EHCI and HSIC move new for version 3.
- Rebase
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2
Kever Yang (4):
Documen
usbcfg &= ~GUSBCFG_FORCEHOSTMODE;
There may be a potential problem still need to fix, the grxfsiz may have
being changed,
the bootrom and uboot will change this value if they use the dwc2
controller.
The way we get the register value here can not make sure this is the
power-on
value which
Paul,
On 08/08/2014 02:26 AM, Paul Zimmerman wrote:
From: Kever Yang [mailto:kever.y...@gmail.com] On Behalf Of Kever Yang
Sent: Thursday, August 07, 2014 2:35 AM
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang
---
Changes in v4: None
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes in v2: None
arch/arm/boot
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang
---
Changes in v4: None
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi | 6 ++
1 file changed, 6
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang
Acked-by: Stephen Warren
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bin
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang
Acked-by: Paul Zimmerman
---
Changes in v4:
- max_transfer_size change to 65536, this should be enough
for most transfer, the hardware auto-detect
,dwc2" bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
usb: dwc2: add compatible data for rockchip soc
ARM: dts: add rk3288 dwc2 controller support
ARM: dts: Enab
bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
usb: dwc2: add compatible data for rockchip soc
ARM: dts: add rk3288 dwc2 controller support
ARM: dts: Enable USB otg
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v4:
- max_transfer_size change to 65536, this should be enough
for most
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v4: None
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v4: None
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi | 6
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Stephen Warren swar...@nvidia.com
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add
Paul,
On 08/08/2014 02:26 AM, Paul Zimmerman wrote:
From: Kever Yang [mailto:kever.y...@gmail.com] On Behalf Of Kever Yang
Sent: Thursday, August 07, 2014 2:35 AM
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off
this value if they use the dwc2
controller.
The way we get the register value here can not make sure this is the
power-on
value which we actually need.
Let me do more test for that, and maybe we need another patch.
Anyway, this patch works and reasonable.
Reviewed-by: Kever Yang kever.y...@rock
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v5:
- max_transfer_size change to 65535 to met the requirement
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v5:
- don't enable otg port for evb
Changes in v4: None
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi | 4
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Stephen Warren swar...@nvidia.com
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288
had post it seprately.
Changes in v3:
- EHCI and HSIC move new for version 3.
- Rebase
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible snps,dwc2 bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2
Kever Yang (4):
Documentation: dt
Indicate that the generic dr_mode binding should be used for dwc2.
Signed-off-by: Kever Yang
Reviewed-by: Doug Anderson
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
Documentation/devicetree/bindings/usb/dwc2.txt | 2 ++
1 file changed, 2
According to the "dr_mode", the otg controller can work as
device role and host role. Some boards always want to use host mode
and some other boards want to use gadget mode. We use the dts setting
to set dwc2's mode, rather than fixing it to whatever hardware says.
Signed-off-by:
struct
- From Jingoo's suggestion:
change the commit message
- add dr_mode init from Kconfig
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever Yang (2):
Documentation: dt
struct
- From Jingoo's suggestion:
change the commit message
- add dr_mode init from Kconfig
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever Yang (2):
Documentation: dt
According to the dr_mode, the otg controller can work as
device role and host role. Some boards always want to use host mode
and some other boards want to use gadget mode. We use the dts setting
to set dwc2's mode, rather than fixing it to whatever hardware says.
Signed-off-by: Kever Yang kever.y
Indicate that the generic dr_mode binding should be used for dwc2.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Reviewed-by: Doug Anderson diand...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
Documentation/devicetree
Doug,
On 08/05/2014 12:34 AM, Doug Anderson wrote:
Kever,
On Mon, Aug 4, 2014 at 6:45 AM, Kever Yang wrote:
According to the "dr_mode", the otg controller can work as
device role during firmware period, and work as host role in
the kernel, without use of usb_id pin. As the commit
According to the "dr_mode", the otg controller can work as
device role during firmware period, and work as host role in
the kernel, without use of usb_id pin. As the commit "usb: dwc3:
set 'mode' based on selected Kconfig choices".
Signed-off-by: Kever Yang
---
Changes
Indicate that the generic dr_mode binding should be used for dwc2.
Signed-off-by: Kever Yang
---
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
Documentation/devicetree/bindings/usb/dwc2.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation
bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever Yang (2):
Documentation: dt-bindings: add dt binding info for dwc2 dr_mode
usb: dwc2: add 'mode' which based on Kconfig select or dts setting
Documentation/devicetree/bindings
bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever Yang (2):
Documentation: dt-bindings: add dt binding info for dwc2 dr_mode
usb: dwc2: add 'mode' which based on Kconfig select or dts setting
Documentation/devicetree/bindings
Indicate that the generic dr_mode binding should be used for dwc2.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
Documentation/devicetree/bindings/usb/dwc2.txt | 2 ++
1 file changed, 2 insertions(+)
diff
According to the dr_mode, the otg controller can work as
device role during firmware period, and work as host role in
the kernel, without use of usb_id pin. As the commit usb: dwc3:
set 'mode' based on selected Kconfig choices.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes
Doug,
On 08/05/2014 12:34 AM, Doug Anderson wrote:
Kever,
On Mon, Aug 4, 2014 at 6:45 AM, Kever Yang kever.y...@rock-chips.com wrote:
According to the dr_mode, the otg controller can work as
device role during firmware period, and work as host role in
the kernel, without use of usb_id pin
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang
Acked-by: Stephen Warren
---
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info
Documentation/
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang
---
Changes in v3:
- Moved out of pin control and sort by base address
Changes in v2:
- change the node name from
I and HSIC in rk3288.dtsi
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
usb: dwc2: add compatible data for rockchip soc
ARM: dts: add rk3288 dwc2 controller support
ARM: dts: Enable USB otg and host1(dwc) on rk3288-evb
Documentation/devicetree/bindings/us
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang
Acked-by: Paul Zimmerman
---
Changes in v3: None
Changes in v2:
- set most parameters as driver auto-detect
drivers/usb/dwc2/platform.c | 29
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang
---
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi |6 ++
1 file changed, 6 insertions(+)
diff
From: Doug Anderson
The EHCI and HSIC device tree nodes were added in the wrong place.
Fix them.
Signed-off-by: Doug Anderson
Signed-off-by: Kever Yang
---
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 41
and rk3288 bindings.
- add compatible "snps,dwc2" bingding info
- set most parameters as driver auto-detect
- change the node name from 'dwc2' to 'usb'
- evb patch added in version 2
Doug Anderson (1):
ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi
Kever Yang (4):
Documen
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang
Acked-by: Paul Zimmerman
---
Changes in v3: None
Changes in v2:
- set most parameters as driver auto-detect
drivers/usb/dwc2/platform.c | 29
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
Signed-off-by: Kever Yang
Acked-by: Stephen Warren
---
Changes in v3: None
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible "snps,dwc2" bingding info
Documentation/
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang
---
Changes in v3:
- Moved out of pin control and sort by base address
Changes in v2:
- change the node name from
From: Doug Anderson
The EHCI and HSIC device tree nodes were added in the wrong place.
Fix them.
Signed-off-by: Doug Anderson
Signed-off-by: Kever Yang
---
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 41
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang
---
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi |6 ++
1 file changed, 6 insertions(+)
diff
USB otg port is the usb3.0 b-port on the board.
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- Rebase
Changes in v2:
- evb patch added in version 2
arch/arm/boot/dts/rk3288-evb.dtsi |6 ++
1 file changed
From: Doug Anderson diand...@chromium.org
The EHCI and HSIC device tree nodes were added in the wrong place.
Fix them.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- EHCI and HSIC move new for version 3.
Changes in v2
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- Moved out of pin control and sort by base address
Changes in v2
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