On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> The property pinctrl-names is totally superfluous. It would be good to
> remove the property to keep the node neatness. There is actually
> unnecessary to set up any pins for data path TRGMII between main SoC and
>
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> It should be good that no use "_" is in DT node name. Consequently,
> those nodes in certain files which have an inappropriate name containing
> "_" are all being replaced with "-".
>
>
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> It should be good that no use "_" is in DT node name. Consequently,
> those nodes in certain files which have an inappropriate name containing
> "_" are all being replaced with "-".
>
> Signed-off-by: Sean Wang
> Cc:
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Complement the missing clock properties cpu[1-3] should depend on.
>
> Signed-off-by: Sean Wang
> Cc: "Rafael J. Wysocki"
> Cc: Viresh Kumar
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> On bpi-r2 board, totally there're four UARTs which we usually called
> uart[0-3] helpful to extend slow-I/O devices. Among those ones, uart2 has
> dedicated pin slot which is used to console
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Complement the missing clock properties cpu[1-3] should depend on.
>
> Signed-off-by: Sean Wang
> Cc: "Rafael J. Wysocki"
> Cc: Viresh Kumar
> Cc: linux...@vger.kernel.org
Pushed to v4.16-next/dts32
Thanks!
>
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> On bpi-r2 board, totally there're four UARTs which we usually called
> uart[0-3] helpful to extend slow-I/O devices. Among those ones, uart2 has
> dedicated pin slot which is used to console log. uart[0-1] appear at
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Both mmc devices on bananapi-r2 board should all use the fixed regulators
> as their power source instead of PMIC MT6323 exports.
>
> Signed-off-by: Sean Wang
Pushed
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Both mmc devices on bananapi-r2 board should all use the fixed regulators
> as their power source instead of PMIC MT6323 exports.
>
> Signed-off-by: Sean Wang
Pushed to v4.16-next/dts32
Thanks!
> ---
>
On 03/02/2018 11:46 PM, Sean Wang wrote:
> On Fri, 2018-03-02 at 09:40 -0600, Rob Herring wrote:
>> On Fri, Feb 23, 2018 at 06:16:33PM +0800, sean.w...@mediatek.com wrote:
>>> From: Sean Wang
>>>
>>> Since those LEDs are parts of PMIC MT6323, it is reasonable to merge
On 03/02/2018 11:46 PM, Sean Wang wrote:
> On Fri, 2018-03-02 at 09:40 -0600, Rob Herring wrote:
>> On Fri, Feb 23, 2018 at 06:16:33PM +0800, sean.w...@mediatek.com wrote:
>>> From: Sean Wang
>>>
>>> Since those LEDs are parts of PMIC MT6323, it is reasonable to merge
>>> those LEDs node
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Since those LEDs are parts of PMIC MT6323, it is reasonable to merge
> those LEDs node definition back into mt6323.dtsi. This way can improve
> the reusability of those nodes among different
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Since those LEDs are parts of PMIC MT6323, it is reasonable to merge
> those LEDs node definition back into mt6323.dtsi. This way can improve
> the reusability of those nodes among different boards with the same PMIC.
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Fix below a lot of warnings that dtc complains so much
>
> Warning (unit_address_vs_reg): Node /oscillator@1 has a unit name, but no reg
> property
> Warning (unit_address_vs_reg): Node
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Fix below a lot of warnings that dtc complains so much
>
> Warning (unit_address_vs_reg): Node /oscillator@1 has a unit name, but no reg
> property
> Warning (unit_address_vs_reg): Node /oscillator@0 has a unit name,
On 03/16/2018 09:36 PM, Stephen Boyd wrote:
> Quoting sean.w...@mediatek.com (2018-02-17 11:54:36)
>> From: Sean Wang
>>
>> All ethsys, pciesys and ssusbsys internally include reset controller, so
>> explicitly add back these missing cell definitions to related bindings
On 03/16/2018 09:36 PM, Stephen Boyd wrote:
> Quoting sean.w...@mediatek.com (2018-02-17 11:54:36)
>> From: Sean Wang
>>
>> All ethsys, pciesys and ssusbsys internally include reset controller, so
>> explicitly add back these missing cell definitions to related bindings
>> and examples.
>>
>>
The driver implementation returns support for private flags, while
no private flags are present. When asked for the number of private
flags it returns the number of statistic flag names.
Fix this by returning EOPNOTSUPP for not implemented ethtool flags.
Signed-off-by: Matthias Brugger <mb
The driver implementation returns support for private flags, while
no private flags are present. When asked for the number of private
flags it returns the number of statistic flag names.
Fix this by returning EOPNOTSUPP for not implemented ethtool flags.
Signed-off-by: Matthias Brugger
On 03/12/2018 06:25 AM, Chunfeng Yun wrote:
> There are two parameters, ref_clk and coefficient, for U2 slew rate
> calibrate which may vary on different SoCs, here allow them to be
> configurable
>
> Signed-off-by: Chunfeng Yun <chunfeng@mediatek.com>
Reviewed
On 03/12/2018 06:25 AM, Chunfeng Yun wrote:
> Add two properties of ref_clk and coefficient used by U2 slew rate
> calibrate which may vary on different SoCs
>
> Signed-off-by: Chunfeng Yun <chunfeng@mediatek.com>
Reviewed-by: Matthias Brugger <m
On 03/12/2018 06:25 AM, Chunfeng Yun wrote:
> There are two parameters, ref_clk and coefficient, for U2 slew rate
> calibrate which may vary on different SoCs, here allow them to be
> configurable
>
> Signed-off-by: Chunfeng Yun
Reviewed-by: Matthias Brugger
> ---
>
On 03/12/2018 06:25 AM, Chunfeng Yun wrote:
> Add two properties of ref_clk and coefficient used by U2 slew rate
> calibrate which may vary on different SoCs
>
> Signed-off-by: Chunfeng Yun
Reviewed-by: Matthias Brugger
> ---
> Documentation/devicetree/bindings/phy/ph
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Fix that USB initialization fails as below runtime log is present during
> booting on bananapi-r2 board by adding missing regulators the USB device
> requires. Current regulators USB device uses
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Fix that USB initialization fails as below runtime log is present during
> booting on bananapi-r2 board by adding missing regulators the USB device
> requires. Current regulators USB device uses are being updated with
On 03/02/2018 05:00 PM, Rob Herring wrote:
> On Fri, Feb 23, 2018 at 06:16:24PM +0800, sean.w...@mediatek.com wrote:
>> From: Sean Wang
>>
>> Update binding document for more mt7623[A,N] reference boards being
>> supported.
>>
>> Signed-off-by: Sean Wang
On 03/02/2018 05:00 PM, Rob Herring wrote:
> On Fri, Feb 23, 2018 at 06:16:24PM +0800, sean.w...@mediatek.com wrote:
>> From: Sean Wang
>>
>> Update binding document for more mt7623[A,N] reference boards being
>> supported.
>>
>> Signed-off-by: Sean Wang
>> Cc: Rob Herring
>> Cc: Mark Rutland
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> add BTIF, HSDMA and SPI-NOR device nodes and enable it on relevant boards
AFAIK hsdma controller is not upstream yet.
Please resubmit when at least the binding got merged.
Thanks,
Matthias
>
On 02/23/2018 11:16 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> add BTIF, HSDMA and SPI-NOR device nodes and enable it on relevant boards
AFAIK hsdma controller is not upstream yet.
Please resubmit when at least the binding got merged.
Thanks,
Matthias
>
> Signed-off-by: Sean
On 02/08/2018 07:07 PM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Fix the pointer to struct scp_subdomian not being moved forward
> when each sub-domain is expected to be iteratively added through
> pm_genpd_add_subdomain call.
>
> Cc: sta...@vger.kernel.org
On 02/08/2018 07:07 PM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Fix the pointer to struct scp_subdomian not being moved forward
> when each sub-domain is expected to be iteratively added through
> pm_genpd_add_subdomain call.
>
> Cc: sta...@vger.kernel.org
> Fixes: 53fddb1a66dd
On 03/07/2018 10:17 AM, Sean Wang wrote:
> Hi, Matthias
>
> just a gentle ping to the four related patches
>
All four pushed with Ulf's reviewed-by to v4.16-next/soc
Thanks a lot!
> Sean
>
> On Wed, 2018-02-07 at 18:22 +0800, sean.w...@mediatek.com wrote:
>> From: Sean Wang
On 03/07/2018 10:17 AM, Sean Wang wrote:
> Hi, Matthias
>
> just a gentle ping to the four related patches
>
All four pushed with Ulf's reviewed-by to v4.16-next/soc
Thanks a lot!
> Sean
>
> On Wed, 2018-02-07 at 18:22 +0800, sean.w...@mediatek.com wrote:
>> From: Sean Wang
>>
>>
On 03/02/2018 03:23 AM, Weiyi Lu wrote:
> On Thu, 2018-03-01 at 16:45 -0600, Rob Herring wrote:
>> On Thu, Feb 22, 2018 at 01:48:49PM +0800, Weiyi Lu wrote:
>>> add new clocks according to ECO design change
>>>
>>> Signed-off-by: Weiyi Lu
>>> ---
>>>
On 03/02/2018 03:23 AM, Weiyi Lu wrote:
> On Thu, 2018-03-01 at 16:45 -0600, Rob Herring wrote:
>> On Thu, Feb 22, 2018 at 01:48:49PM +0800, Weiyi Lu wrote:
>>> add new clocks according to ECO design change
>>>
>>> Signed-off-by: Weiyi Lu
>>> ---
>>> include/dt-bindings/clock/mt2712-clk.h |
On 02/17/2018 08:54 PM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Changes since v2:
> - rebase to 4.16-rc1 and solve all conflicts
> - add proper list Cc in patch 1
> - add fixup in patch 4 in v2 with the uniform pinmux definition
> that is always adding
On 02/17/2018 08:54 PM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Changes since v2:
> - rebase to 4.16-rc1 and solve all conflicts
> - add proper list Cc in patch 1
> - add fixup in patch 4 in v2 with the uniform pinmux definition
> that is always adding property function before
On 02/17/2018 08:54 PM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> add High-Speed DMA (HSDMA) nodes
>
> Signed-off-by: Sean Wang
NAK. AFAIK the driver is not yest upstream
Regards,
Matthias
> ---
>
On 02/17/2018 08:54 PM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> add High-Speed DMA (HSDMA) nodes
>
> Signed-off-by: Sean Wang
NAK. AFAIK the driver is not yest upstream
Regards,
Matthias
> ---
> arch/arm64/boot/dts/mediatek/mt7622.dtsi | 10 ++
> 1 file changed, 10
t; Signed-off-by: Sean Wang <sean.w...@mediatek.com>
> Cc: Rob Herring <r...@kernel.org>
> Cc: Michael Turquette <mturque...@baylibre.com>
> Cc: Stephen Boyd <sb...@codeaurora.org>
> Cc: linux-...@vger.kernel.org
> Reviewed-by: Rob Herring <r.
t; Cc: Rob Herring
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-...@vger.kernel.org
> Reviewed-by: Rob Herring
Reviewed-by: Matthias Brugger
> ---
> Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
> Documentation/devicetree/bi
765c7..fcdc10ec28a3 100644
> --- a/drivers/watchdog/mtk_wdt.c
> +++ b/drivers/watchdog/mtk_wdt.c
> @@ -57,7 +57,7 @@
> #define DRV_VERSION "1.0"
>
> static bool nowayout = WATCHDOG_NOWAYOUT;
> -static unsigned int timeout = WDT_MAX_TIMEOUT;
> +static unsigned int timeout;
>
> struct mtk_wdt_dev {
> struct watchdog_device wdt_dev;
>
Acked-by: Matthias Brugger <matthias@gmail.com>
mtk_wdt.c
> +++ b/drivers/watchdog/mtk_wdt.c
> @@ -57,7 +57,7 @@
> #define DRV_VERSION "1.0"
>
> static bool nowayout = WATCHDOG_NOWAYOUT;
> -static unsigned int timeout = WDT_MAX_TIMEOUT;
> +static unsigned int timeout;
>
> struct mtk_wdt_dev {
> struct watchdog_device wdt_dev;
>
Acked-by: Matthias Brugger
On 02/12/2018 12:28 PM, Ryder Lee wrote:
> As the new MFD device is in place, switch probing method to adapt it.
>
> Signed-off-by: Ryder Lee
> ---
> drivers/clk/mediatek/clk-mt7622-aud.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git
On 02/12/2018 12:28 PM, Ryder Lee wrote:
> As the new MFD device is in place, switch probing method to adapt it.
>
> Signed-off-by: Ryder Lee
> ---
> drivers/clk/mediatek/clk-mt7622-aud.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git
include/dt-bindings/clock/mt7622-clk.h | 3 ++-
> 2 files changed, 3 insertions(+), 1 deletion(-)>
Reviewed-by: Matthias Brugger <matthias@gmail.com>
> diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c
> b/drivers/clk/mediatek/clk-mt7622-aud.c
> index fad7d9f..13f752
> 2 files changed, 3 insertions(+), 1 deletion(-)>
Reviewed-by: Matthias Brugger
> diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c
> b/drivers/clk/mediatek/clk-mt7622-aud.c
> index fad7d9f..13f752d 100644
> --- a/drivers/clk/mediatek/clk-mt7622-aud.c
> +++ b/drivers/clk/me
On 02/09/2018 04:51 AM, Sean Wang wrote:
> On Wed, 2018-02-07 at 12:43 +0100, Matthias Brugger wrote:
>>
>> On 02/06/2018 10:53 AM, sean.w...@mediatek.com wrote:
>>> From: Sean Wang <sean.w...@mediatek.com>
>>>
>>> add nodes for the thermal cont
On 02/09/2018 04:51 AM, Sean Wang wrote:
> On Wed, 2018-02-07 at 12:43 +0100, Matthias Brugger wrote:
>>
>> On 02/06/2018 10:53 AM, sean.w...@mediatek.com wrote:
>>> From: Sean Wang
>>>
>>> add nodes for the thermal controller and associated therma
On 02/08/2018 06:57 AM, Ryder Lee wrote:
> On Wed, 2018-02-07 at 16:18 +0100, Matthias Brugger wrote:
>>
>> On 02/05/2018 05:07 AM, Ryder Lee wrote:
>>> On Sat, 2018-02-03 at 15:26 +0100, Matthias Brugger wrote:
>>>>
>>>> On 01/31/2018 08:42
On 02/08/2018 06:57 AM, Ryder Lee wrote:
> On Wed, 2018-02-07 at 16:18 +0100, Matthias Brugger wrote:
>>
>> On 02/05/2018 05:07 AM, Ryder Lee wrote:
>>> On Sat, 2018-02-03 at 15:26 +0100, Matthias Brugger wrote:
>>>>
>>>> On 01/31/2018 08:42
On 02/08/2018 03:44 AM, Ulf Magnusson wrote:
> The AVR32 symbol was removed in commit 26202873bb51 ("avr32: remove
> support for AVR32 architecture").
You forgot the Signed-off-by tag.
> ---
> Changes in v2:
> Remove the AVR32 reference from the help text too.
>
> drivers/spi/Kconfig | 4
On 02/08/2018 03:44 AM, Ulf Magnusson wrote:
> The AVR32 symbol was removed in commit 26202873bb51 ("avr32: remove
> support for AVR32 architecture").
You forgot the Signed-off-by tag.
> ---
> Changes in v2:
> Remove the AVR32 reference from the help text too.
>
> drivers/spi/Kconfig | 4
On 01/23/2018 09:51 AM, Sean Wang wrote:
> On Sat, 2017-12-23 at 23:35 +0800, Sean Wang wrote:
>> On Sat, 2017-12-23 at 08:52 +0100, Matthias Brugger wrote:
>>>
>>> On 12/22/2017 07:06 AM, sean.w...@mediatek.com wrote:
>>>> From: Sean Wang <sean.w.
On 01/23/2018 09:51 AM, Sean Wang wrote:
> On Sat, 2017-12-23 at 23:35 +0800, Sean Wang wrote:
>> On Sat, 2017-12-23 at 08:52 +0100, Matthias Brugger wrote:
>>>
>>> On 12/22/2017 07:06 AM, sean.w...@mediatek.com wrote:
>>>> From: Sean Wang
>>>>
On 02/05/2018 05:07 AM, Ryder Lee wrote:
> On Sat, 2018-02-03 at 15:26 +0100, Matthias Brugger wrote:
>>
>> On 01/31/2018 08:42 AM, Ryder Lee wrote:
>>> As the new MFD parent is in place, switch probing method to adapt it.
>>>
>>> Signed
On 02/05/2018 05:07 AM, Ryder Lee wrote:
> On Sat, 2018-02-03 at 15:26 +0100, Matthias Brugger wrote:
>>
>> On 01/31/2018 08:42 AM, Ryder Lee wrote:
>>> As the new MFD parent is in place, switch probing method to adapt it.
>>>
>>> Signed-off-by: Ryder
On 02/06/2018 10:53 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> add nodes for the thermal controller and associated thermal zone using
> CPU as the cooling device for each trip point. In addition, add a fixup
> for thermal_calibration on nvmem should be 12
On 02/06/2018 10:53 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> add nodes for the thermal controller and associated thermal zone using
> CPU as the cooling device for each trip point. In addition, add a fixup
> for thermal_calibration on nvmem should be 12 bytes as the minimal
>
On 02/06/2018 10:52 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> add pinctrl device nodes and rfb1 board, additionally include all pin
> groups possible being used on rfb1 board and available gpio keys.
>
> Signed-off-by: Sean Wang
>
On 02/06/2018 10:52 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> add pinctrl device nodes and rfb1 board, additionally include all pin
> groups possible being used on rfb1 board and available gpio keys.
>
> Signed-off-by: Sean Wang
> ---
>
On 02/06/2018 10:52 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> All ethsys, pciesys and ssusbsys internally include reset controller, so
> explicitly add back these missing cell definitions to related bindings
> and examples.
>
> Signed-off-by: Sean Wang
On 02/06/2018 10:52 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> All ethsys, pciesys and ssusbsys internally include reset controller, so
> explicitly add back these missing cell definitions to related bindings
> and examples.
>
> Signed-off-by: Sean Wang
> Cc: Rob Herring
> Cc:
om>
> Cc: Zhi Mao <zhi@mediatek.com>
> Cc: John Crispin <j...@phrozen.org>
> Cc: Matthias Brugger <matthias@gmail.com>
> ---
> drivers/pwm/pwm-mediatek.c | 24 +---
> 1 file changed, 21 insertions(+), 3 deletions(-)
>
Reviewed-by:
put as expected.
> Thus, the patch adds the extra condition for fixing up the weird case to
> let PWM4 or PWM5 able to work on MT7623.
>
> v1 -> v2: use pwm45_fixup naming instead of pwm45_quirk
>
> Signed-off-by: Sean Wang
> Cc: Zhi Mao
> Cc: John Crispin
> Cc: Matthias
On 02/07/2018 09:58 AM, Matthias Brugger wrote:
>
>
> On 02/06/2018 11:55 PM, Ulf Magnusson wrote:
>> The AVR32 symbol was removed in commit 26202873bb51 ("avr32: remove
>> support for AVR32 architecture").
>>
>> Signed-off-by: Ulf Magnusson
On 02/07/2018 09:58 AM, Matthias Brugger wrote:
>
>
> On 02/06/2018 11:55 PM, Ulf Magnusson wrote:
>> The AVR32 symbol was removed in commit 26202873bb51 ("avr32: remove
>> support for AVR32 architecture").
>>
>> Signed-off-by: Ulf Magnusson
>>
On 02/06/2018 11:55 PM, Ulf Magnusson wrote:
> The AVR32 symbol was removed in commit 26202873bb51 ("avr32: remove
> support for AVR32 architecture").
>
> Signed-off-by: Ulf Magnusson <ulfali...@gmail.com>
> ---
Reviewed-by: Matthias Brugger <matthias@gmai
On 02/06/2018 11:55 PM, Ulf Magnusson wrote:
> The AVR32 symbol was removed in commit 26202873bb51 ("avr32: remove
> support for AVR32 architecture").
>
> Signed-off-by: Ulf Magnusson
> ---
Reviewed-by: Matthias Brugger
> drivers/spi/Kconfig | 2 +-
> 1
On 01/31/2018 08:42 AM, Ryder Lee wrote:
> As the new MFD parent is in place, switch probing method to adapt it.
>
> Signed-off-by: Ryder Lee
> ---
> drivers/clk/mediatek/clk-mt7622-aud.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git
On 01/31/2018 08:42 AM, Ryder Lee wrote:
> As the new MFD parent is in place, switch probing method to adapt it.
>
> Signed-off-by: Ryder Lee
> ---
> drivers/clk/mediatek/clk-mt7622-aud.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git
On 02/01/2018 11:12 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Add SCPSYS power domain driver for MT7623A SoC. The MT7623A's power
> domains are the subset of MT7623 SoC's ones. As MT7623 SoC has full
> features whereas MT7623A is being designed just for
On 02/01/2018 11:12 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Add SCPSYS power domain driver for MT7623A SoC. The MT7623A's power
> domains are the subset of MT7623 SoC's ones. As MT7623 SoC has full
> features whereas MT7623A is being designed just for router applications.
>
On 01/29/2018 10:09 AM, argus@mediatek.com wrote:
> From: Argus Lin
>
> We add pwrap support for MT6797 SoCs.
>
> Signed-off-by: Argus Lin
> ---
> Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +
> 1 file changed, 1
On 01/29/2018 10:09 AM, argus@mediatek.com wrote:
> From: Argus Lin
>
> We add pwrap support for MT6797 SoCs.
>
> Signed-off-by: Argus Lin
> ---
> Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On 01/29/2018 10:09 AM, argus@mediatek.com wrote:
> From: Argus Lin
>
> mt6797 is a highly integrated SoCs, and it uses
> mt6351 as Power Management IC.
> We need to add pwrap device to communicate with
> mt6351 by SPI.
> The base address of pwrap is 0x1000d000, and
On 01/29/2018 10:09 AM, argus@mediatek.com wrote:
> From: Argus Lin
>
> mt6797 is a highly integrated SoCs, and it uses
> mt6351 as Power Management IC.
> We need to add pwrap device to communicate with
> mt6351 by SPI.
> The base address of pwrap is 0x1000d000, and IRQ
> number is 178. It
On 01/29/2018 10:09 AM, argus@mediatek.com wrote:
> From: Argus Lin
>
> New pwrap support int1_en flag for starvation and channel
> request exception. We need to register it for interrupt
> handler.
> We also add pwrap capability flag used to declare if we
"We
On 01/29/2018 10:09 AM, argus@mediatek.com wrote:
> From: Argus Lin
>
> New pwrap support int1_en flag for starvation and channel
> request exception. We need to register it for interrupt
> handler.
> We also add pwrap capability flag used to declare if we
"We also" wording is nearly
On 01/23/2018 04:36 AM, argus@mediatek.com wrote:
> From: Argus Lin
>
> mt6797 is a highly integrated SoCs, and it uses
> mt6351 as Power Management IC.
> We need to add pwrap device to communicate with
> mt6351 by SPI.
> The base address of pwrap is 0x1000d000, and
On 01/23/2018 04:36 AM, argus@mediatek.com wrote:
> From: Argus Lin
>
> mt6797 is a highly integrated SoCs, and it uses
> mt6351 as Power Management IC.
> We need to add pwrap device to communicate with
> mt6351 by SPI.
> The base address of pwrap is 0x1000d000, and IRQ
> number is 178. It
On 01/23/2018 04:36 AM, argus@mediatek.com wrote:
> From: Argus Lin
>
> mt6351 is a new power management IC and it is used for mt6797 SoCs.
> We need to add mt6351_regs for pmic register mapping and add
> mt6797_regs for MT6797 SoCs register mapping. It also has new
On 01/23/2018 04:36 AM, argus@mediatek.com wrote:
> From: Argus Lin
>
> mt6351 is a new power management IC and it is used for mt6797 SoCs.
> We need to add mt6351_regs for pmic register mapping and add
> mt6797_regs for MT6797 SoCs register mapping. It also has new
> interrupt event, so
ff-by: Sean Wang <sean.w...@mediatek.com>
> --> drivers/pinctrl/mediatek/pinctrl-mt7622.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
Reviewed-by: Matthias Brugger <matthias@gmail.com>
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
> b/dri
rpenter <dan.carpen...@oracle.com>
> Signed-off-by: Sean Wang <sean.w...@mediatek.com>
> ---
> drivers/pinctrl/mediatek/pinctrl-mt7622.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
Reviewed-by: Matthias Brugger <matthias@gmail.com>
&
pinctrl/mediatek/pinctrl-mt7622.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
Reviewed-by: Matthias Brugger
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
> b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
> index dc32e3c..06e8406 100644
> --- a
Sean Wang
> ---
> drivers/pinctrl/mediatek/pinctrl-mt7622.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
Reviewed-by: Matthias Brugger
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
> b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
> index 382
On 12/25/2017 03:59 PM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
> control PWM4 or PWM5 are distinct from the other PWMs, whose wrong
> programming on PWM hardware causes waveform cannot be
On 12/25/2017 03:59 PM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
> control PWM4 or PWM5 are distinct from the other PWMs, whose wrong
> programming on PWM hardware causes waveform cannot be output as expected.
>
Hi Catalin,
On 01/08/2018 07:53 PM, Catalin Marinas wrote:
> On Mon, Jan 08, 2018 at 05:32:25PM +, Will Deacon wrote:
>> Jayachandran C (1):
>> arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs
>>
>> Marc Zyngier (3):
>> arm64: Move post_ttbr_update_workaround to C code
>>
Hi Catalin,
On 01/08/2018 07:53 PM, Catalin Marinas wrote:
> On Mon, Jan 08, 2018 at 05:32:25PM +, Will Deacon wrote:
>> Jayachandran C (1):
>> arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs
>>
>> Marc Zyngier (3):
>> arm64: Move post_ttbr_update_workaround to C code
>>
On 12/22/2017 07:06 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> On bpi-r2 board, totally there're four uarts which we usually called
> uart[0-3] helpful to extend slow I/O devices. Among those ones, uart2 has
> dedicated pin slot which is used to conolse
On 12/22/2017 07:06 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> On bpi-r2 board, totally there're four uarts which we usually called
> uart[0-3] helpful to extend slow I/O devices. Among those ones, uart2 has
> dedicated pin slot which is used to conolse log. uart[0-1] appear at
On 12/01/2017 11:43 AM, Matthias Brugger wrote:
> The mtk_thermal has some defiens which are never used within the driver.
> This patch delets them.
>
> Signed-off-by: Matthias Brugger <mbrug...@suse.com>
> ---
Rui, Eduardo, do you have any comments on this patc
On 12/01/2017 11:43 AM, Matthias Brugger wrote:
> The mtk_thermal has some defiens which are never used within the driver.
> This patch delets them.
>
> Signed-off-by: Matthias Brugger
> ---
Rui, Eduardo, do you have any comments on this patch?
Regards,
Matthias
>
On 11/28/2017 08:28 AM, Weiyi Lu wrote:
> Add clock controller nodes for MT2712, include topckgen, infracfg,
> pericfg, mcucfg and apmixedsys. This patch also add six oscillators that
> provide clocks for MT2712.
>
> Signed-off-by: Weiyi Lu
> ---
>
On 11/28/2017 08:28 AM, Weiyi Lu wrote:
> Add clock controller nodes for MT2712, include topckgen, infracfg,
> pericfg, mcucfg and apmixedsys. This patch also add six oscillators that
> provide clocks for MT2712.
>
> Signed-off-by: Weiyi Lu
> ---
> arch/arm64/boot/dts/mediatek/mt2712e.dtsi |
On 12/15/2017 06:50 AM, Weiyi Lu wrote:
> On Tue, 2017-11-28 at 15:28 +0800, Weiyi Lu wrote:
>
> Hi Matthias,
> Just gentle ping. Many thanks.
>
Now pushed to v4.15-next thanks
>> This series is based on v4.15-rc1 and composed of
>> scpsys control (PATCH 1-4) and device tree (PATCH 5-6)
>>
On 12/15/2017 06:50 AM, Weiyi Lu wrote:
> On Tue, 2017-11-28 at 15:28 +0800, Weiyi Lu wrote:
>
> Hi Matthias,
> Just gentle ping. Many thanks.
>
Now pushed to v4.15-next thanks
>> This series is based on v4.15-rc1 and composed of
>> scpsys control (PATCH 1-4) and device tree (PATCH 5-6)
>>
On 12/19/2017 02:32 AM, Stephen Boyd wrote:
> On 12/14, Matthias Brugger wrote:
>> Hi Stephen, Michael,
>>
>> On 12/01/2017 01:07 PM, Matthias Brugger wrote:
>>> The ethsys registers a reset controller, so we need to specify a
>>> reset cell. This patch
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