On Thu, Feb 23, 2017 at 12:44:37PM +0200, Peter De Schrijver wrote:
> A number of bug fixes for the Tegra210 clock implementation.
>
> Changelog:
>
> v2: add better description for 'remove non-existing pll_m_out1 clock'
>
> Peter De Schrijver (7):
> clk: tegra: fix pll_a1 iddq register, add pl
Series,
Reviewed-by: Mikko Perttunen
Tested-by: Mikko Perttunen
On 02/23/2017 12:44 PM, Peter De Schrijver wrote:
A number of bug fixes for the Tegra210 clock implementation.
Changelog:
v2: add better description for 'remove non-existing pll_m_out1 clock'
Peter De Schrijver (7):
clk: teg
A number of bug fixes for the Tegra210 clock implementation.
Changelog:
v2: add better description for 'remove non-existing pll_m_out1 clock'
Peter De Schrijver (7):
clk: tegra: fix pll_a1 iddq register, add pll_a1
clk: tegra: fix isp clock modelling
clk: tegra: correct afi parent
clk: t
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