LS1043A have a RCPM module (Run Control and Power Management), which
performs all device-level tasks associated with power management.
Signed-off-by: Chenhui Zhao
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts
. The devices can be
waked up by specified sources, such as Flextimer, GPIO and so on.
Signed-off-by: Chenhui Zhao
---
drivers/soc/fsl/Makefile | 1 +
drivers/soc/fsl/pm/Makefile | 1 +
drivers/soc/fsl/pm/ls-rcpm.c | 144 +++
3 files changed
On Thu, Aug 27, 2015 at 4:55 AM, Scott Wood
wrote:
On Wed, Aug 26, 2015 at 08:09:47PM +0800, Chenhui Zhao wrote:
+int check_cpu_dead(unsigned int cpu)
+{
+ return per_cpu(cpu_state, cpu) == CPU_DEAD;
+}
I'm not sure this needs to be a function versus open-coded, but if
y
On Thu, Aug 27, 2015 at 6:42 AM, Scott Wood
wrote:
On Wed, Aug 26, 2015 at 08:09:48PM +0800, Chenhui Zhao wrote:
+ .globl booting_thread_hwid
+booting_thread_hwid:
+ .long INVALID_THREAD_HWID
+ .align 3
The commit message goes into no detail about the changes you&#x
On Tue, Mar 11, 2014 at 06:42:51PM -0500, Scott Wood wrote:
> On Fri, 2014-03-07 at 12:57 +0800, Chenhui Zhao wrote:
> > diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
> > b/arch/powerpc/platforms/85xx/corenet_generic.c
> > index b756f3d..3fdf9f3 100644
&
On Tue, Mar 11, 2014 at 06:48:13PM -0500, Scott Wood wrote:
> On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
> > diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
> > index ac2621a..f3f4401 100644
> > --- a/arch/powerpc/kernel/smp.c
> > +++
On Tue, Mar 11, 2014 at 06:51:20PM -0500, Scott Wood wrote:
> On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
> > In 64-bit mode, kernel just clears the irq soft-enable flag
> > in struct paca_struct to disable external irqs. But, in
> > the case of suspend, irqs
On Tue, Mar 11, 2014 at 07:00:27PM -0500, Scott Wood wrote:
> On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
> > In sleep mode, the clocks of e500 cores and unused IP blocks is
> > turned off. The IP blocks which are allowed to wake up the processor
> > are still
On Tue, Mar 11, 2014 at 07:08:43PM -0500, Scott Wood wrote:
> On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
> > From: Hongbo Zhang
> >
> > In the last stage of deep sleep, software will trigger a Finite
> > State Machine (FSM) to control the hardware p
On Tue, Mar 11, 2014 at 07:45:14PM -0500, Scott Wood wrote:
> On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
> > From: Wang Dongsheng
> >
> > Add booke_cpu_state_save() and booke_cpu_state_restore() functions which
> > can be
> > used to save/restore CP
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
> On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
> > From: Zhao Chenhui
> >
> > T1040 supports deep sleep feature, which can switch off most parts of
> > the SoC when it is in deep sleep mode
On Fri, Mar 14, 2014 at 05:41:41PM -0500, Scott Wood wrote:
> On Wed, 2014-03-12 at 15:46 +0800, Chenhui Zhao wrote:
> > On Tue, Mar 11, 2014 at 06:51:20PM -0500, Scott Wood wrote:
> > > On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
> > > > In 64-bit mode, k
On Fri, Mar 14, 2014 at 05:51:09PM -0500, Scott Wood wrote:
> On Wed, 2014-03-12 at 16:34 +0800, Chenhui Zhao wrote:
> > On Tue, Mar 11, 2014 at 07:08:43PM -0500, Scott Wood wrote:
> > > On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
> > > > From: Hongbo Zhang
On Fri, Mar 14, 2014 at 06:01:45PM -0500, Scott Wood wrote:
> On Wed, 2014-03-12 at 17:42 +0800, Chenhui Zhao wrote:
> > On Tue, Mar 11, 2014 at 07:45:14PM -0500, Scott Wood wrote:
> > > On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
> > > > From: Wang D
On Fri, Mar 14, 2014 at 06:18:27PM -0500, Scott Wood wrote:
> On Wed, 2014-03-12 at 18:40 +0800, Chenhui Zhao wrote:
> > On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
> > > On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
> > > > From: Zhao C
On Tue, Mar 18, 2014 at 06:21:22PM -0500, Scott Wood wrote:
> On Mon, 2014-03-17 at 18:27 +0800, Chenhui Zhao wrote:
> > On Fri, Mar 14, 2014 at 05:51:09PM -0500, Scott Wood wrote:
> > > On Wed, 2014-03-12 at 16:34 +0800, Chenhui Zhao wrote:
> > > > On Tue, Mar 11, 2
On Tue, Mar 18, 2014 at 05:42:09PM -0500, Scott Wood wrote:
> On Mon, 2014-03-17 at 19:19 +0800, Chenhui Zhao wrote:
> > On Fri, Mar 14, 2014 at 06:18:27PM -0500, Scott Wood wrote:
> > > On Wed, 2014-03-12 at 18:40 +0800, Chenhui Zhao wrote:
> > > > On Tue, Mar 11, 2
From: Zhang Zhuoyu
This implements CPU hotplug for ls1. When cpu is down, it will be put
in WFI state. When cpu is up, it will be waked by a IPI interrupt and
reinitialized.
Signed-off-by: Zhang Zhuoyu
Signed-off-by: Chenhui Zhao
---
arch/arm/mach-imx/common.h |4 ++
arch/arm/mach-imx
These patches are for supporting deep sleep on LS1.
They are based on the platform patches for LS1.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Ple
LS1 supports deep sleep feature that can switch off most parts of
the SoC when it is in deep sleep state.
The DDR controller will also be powered off in deep sleep. Therefore,
copy the last stage code to enter deep sleep to SRAM and run it
with disabling MMU and caches.
Signed-off-by: Chenhui
For some Freescale's SoCs which support deep sleep, such as T1040,
LS1021, software will start a Finite State Machine (FSM) to control
the hardware precedure to enter deep sleep and return from it.
This patch configures parameters of the FSM preparing for deep sleep.
Signed-off-by: Chenhui
On Fri, Sep 26, 2014 at 09:51:53PM +0100, Russell King - ARM Linux wrote:
> On Fri, Sep 26, 2014 at 01:02:01PM +0100, Russell King - ARM Linux wrote:
> > On Fri, Sep 26, 2014 at 07:25:02PM +0800, Chenhui Zhao wrote:
> > > +void fsm_write32(void __iomem *addr, u32 val)
>
On Fri, Sep 26, 2014 at 01:14:27PM +0100, Russell King - ARM Linux wrote:
> On Fri, Sep 26, 2014 at 07:25:03PM +0800, Chenhui Zhao wrote:
> > +static int ls1_start_deepsleep(unsigned long addr)
> > +{
> > + ls1_do_deepsleep(addr);
> > +
> > + return 0;
On Sun, Sep 28, 2014 at 03:26:33PM +0100, Russell King - ARM Linux wrote:
> On Sun, Sep 28, 2014 at 07:06:40PM +0800, Chenhui Zhao wrote:
> > On Fri, Sep 26, 2014 at 01:14:27PM +0100, Russell King - ARM Linux wrote:
> > > On Fri, Sep 26, 2014 at 07:25:03PM +0800,
From: Wang Dongsheng
Signed-off-by: Wang Dongsheng
---
arch/powerpc/include/asm/reg.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 62b114e..cd7b630 100644
--- a/arch/powerpc/include/asm/reg.h
+++
of register map in RCPM, which is specified by
the compatible entry in the RCPM node of device tree.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/include/asm/fsl_guts.h | 105
arch/powerpc/platforms/85xx/Kconfig |1 +
arch/powerpc/platforms/85xx
Implemented CPU hotplug on e500mc and e5500. On e5500 both 32-bit and
64-bit modes can work. Used some callback functions implemented in RCPM
driver.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/kernel/smp.c |6 ++-
arch/powerpc/mm
ff-by: Chenhui Zhao
---
arch/powerpc/include/asm/booke_save_regs.h | 96
arch/powerpc/kernel/Makefile |1 +
arch/powerpc/kernel/booke_save_regs.S | 361
3 files changed, 458 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/in
In 64-bit mode, kernel just clears the irq soft-enable flag
in struct paca_struct to disable external irqs. But, in
the case of suspend, irqs should be disabled by hardware.
Therefore, hook a function to ppc_md.suspend_disable_irqs
to really disable irqs.
Signed-off-by: Chenhui Zhao
---
arch
caches in the current cpu.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/include/asm/cacheflush.h |2 -
arch/powerpc/include/asm/cputable.h | 11 +++
arch/powerpc/kernel/asm-offsets.c |3 +
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 114
early resume precedure.
This patch configure the EPU FSM preparing for deep sleep.
Signed-off-by: Hongbo Zhang
Signed-off-by: Chenhui Zhao
---
arch/powerpc/platforms/85xx/Kconfig |1 +
arch/powerpc/sysdev/fsl_soc.h |3 +
drivers/platform/Kconfig|4 +
drivers
-by: Chenhui Zhao
---
arch/powerpc/Kconfig |4 +-
arch/powerpc/platforms/85xx/Makefile |3 +
arch/powerpc/platforms/85xx/qoriq_pm.c | 78
3 files changed, 83 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/platforms/8
/deepsleep.c
new file mode 100644
index 000..ddd7185
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/deepsleep.c
@@ -0,0 +1,201 @@
+/*
+ * Support deep sleep feature
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Author: Chenhui Zhao
+ *
+ * This program is free software; you can redist
LS1 supports deep sleep feature that can switch off most parts of
the SoC when it is in deep sleep state.
The DDR controller will also be powered off in deep sleep. Therefore,
copy the last stage code to enter deep sleep to SRAM and run it
with disabling MMU and caches.
Signed-off-by: Chenhui
For some Freescale's SoCs which support deep sleep, such as T1040,
LS1021, software will start a Finite State Machine (FSM) to control
the hardware precedure to enter deep sleep and return from it.
This patch configures parameters of the FSM preparing for deep sleep.
Signed-off-by: Chenhui
Core reset may cause issue if using the proxy mode of MPIC.
Use the mixed mode of MPIC if enabling CPU hotplug.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/platforms/85xx/corenet_generic.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
Linux Power Management.
Command to enter sleep mode.
echo standby > /sys/power/state
Command to enter deep sleep mode.
echo mem > /sys/power/state
Signed-off-by: Li Yang
Signed-off-by: Chenhui Zhao
---
arch/powerpc/include/asm/cacheflush.h | 5 +
arch/powerpc/platforms/85xx/Ma
On Tue, Aug 4, 2015 at 4:23 AM, Scott Wood
wrote:
On Mon, 2015-08-03 at 19:14 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 8:45 AM, Scott Wood
wrote:
> On Fri, 2015-06-26 at 15:44 +0800,
Yuantian.Tang@freescale.comwrote:
> > +static void rcpm_v1_set_ip_power(bool en
On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood
wrote:
On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
>
On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood
wrote:
>
> Could you explain irq_mask()? Why would there still be IRQs
destined
> for
> this CPU at thi
On Tue, Aug 4, 2015 at 5:18 AM, Scott Wood
wrote:
[Added linuxppc-...@lists.ozlabs.org. Besides that list being
required for
review of PPC patches, it feeds the patchwork that I use to track and
apply
patches.]
On Mon, 2015-08-03 at 19:52 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015
On Sat, Aug 1, 2015 at 8:22 AM, Scott Wood
wrote:
On Fri, 2015-07-31 at 17:20 +0800, b29...@freescale.com wrote:
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index 7f0dadb..8652a49 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/pl
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
wrote:
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood
wrote:
> On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
> > >
>
> > On Sat, Aug 1, 2015 at 7:59 AM, Scot
On Thu, Aug 6, 2015 at 11:16 AM, Scott Wood
wrote:
On Wed, 2015-08-05 at 19:08 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 8:22 AM, Scott Wood
wrote:
> On Fri, 2015-07-31 at 17:20 +0800, b29983@freescale.comwrote:
> > + /*
> > + * If b
On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood
wrote:
On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
wrote:
> On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
> > On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood
&
Support Freescale E6500 core-based platforms, like t4240.
Support disabling/enabling individual CPU thread dynamically.
Signed-off-by: Chenhui Zhao
---
major changes for v2:
* start Thread1 by Thread0 when we want to boot Thread1 only replacing
the method of changing cpu physical id
arch
caches inside the current cpu.
Signed-off-by: Chenhui Zhao
Signed-off-by: Tang Yuantian
---
arch/powerpc/include/asm/cacheflush.h | 2 -
arch/powerpc/include/asm/cputable.h | 11 +++
arch/powerpc/kernel/asm-offsets.c | 3 +
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 112
Freescale E500MC and E5500 core-based platforms, like P4080, T1040,
support disabling/enabling CPU dynamically.
This patch adds this feature on those platforms.
Signed-off-by: Chenhui Zhao
Signed-off-by: Tang Yuantian
---
major changes for v2:
* factor out smp_85xx_start_cpu()
* move
G_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o
fsl_85xx_cache_sram.o
diff --git a/arch/powerpc/sysdev/fsl_rcpm.c b/arch/powerpc/sysdev/fsl_rcpm.c
new file mode 100644
index 000..ed59881
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rcpm.c
@@ -0,0 +1,390 @@
+/*
+ * RCPM(Run Control/Power Management) sup
Freescale CoreNet-based and Non-CoreNet-based platforms require
different PM operations. This patch extracted existing PM operations
on Non-CoreNet-based platforms to a new file which can accommodate
both platforms.
In this way, PM operation codes are clearer structurally.
Signed-off-by: Chenhui
On Fri, Aug 7, 2015 at 2:02 AM, Scott Wood
wrote:
On Thu, 2015-08-06 at 13:54 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood
wrote:
> On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
> > On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
> &g
For T1040, T1042, T1023, and T1024, they should use the compatible
string "fsl,qoriq-rcpm-2.1".
Signed-off-by: Chenhui Zhao
---
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
di
-by: Chenhui Zhao
---
arch/powerpc/Kconfig | 3 +-
arch/powerpc/platforms/85xx/Kconfig| 5 +++
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/qoriq_pm.c | 59 ++
arch/powerpc/platforms/86xx/Kconfig| 1 +
5 fi
caches inside the current cpu.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/include/asm/cacheflush.h | 2 -
arch/powerpc/include/asm/cputable.h | 11 +++
arch/powerpc/kernel/asm-offsets.c | 3 +
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 114
power
state). When the core is up again, Thread0 is up first, and it will be
bound with the present booting cpu. This way, all CPUs can hotplug
separately.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/include/asm/fsl_pm.h | 4 +
arch/powerpc/include
.o
diff --git a/arch/powerpc/sysdev/fsl_rcpm.c b/arch/powerpc/sysdev/fsl_rcpm.c
new file mode 100644
index 000..e30f1bc
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rcpm.c
@@ -0,0 +1,353 @@
+/*
+ * RCPM(Run Control/Power Management) support
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+
Add RCPM and DCSR nodes.
Signed-off-by: Chenhui Zhao
---
arch/arm/boot/dts/ls1021a-qds.dts | 6 +-
arch/arm/boot/dts/ls1021a.dtsi| 117 ++
2 files changed, 122 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts
b/arch/arm/boot
: Chenhui Zhao
---
arch/arm/mach-imx/Kconfig | 1 +
arch/arm/mach-imx/Makefile| 2 +
arch/arm/mach-imx/pm-ls1.c| 374 ++
arch/arm/mach-imx/sleep-ls1.S | 137
arch/arm/mach-imx/sleep-ls1.h | 19 +++
5 files changed, 533
and clears the FSM registers for deep sleep. Note
that the sequence of clearing the FSM registers does matter, should follow
the sequence mentioned in the reference manual.
Signed-off-by: Chenhui Zhao
---
drivers/platform/Kconfig | 2 +
drivers/platform/Makefile| 1 +
drivers
If a device works as a wakeup source, it will keep working in the period of
sleep/deep sleep. This patch sets the wakeup devices according to the wakeup
attribute of device.
Signed-off-by: Chenhui Zhao
---
arch/arm/boot/dts/ls1021a.dtsi | 2 +
arch/arm/mach-imx/pm-ls1.c | 101
The functions, cpu_pm_enter and cpu_pm_exit, assume that CPU would
be reset when entering and exiting a idle state. If that is not the
case, they would cause issue.
Signed-off-by: Chenhui Zhao
---
include/linux/cpuidle.h | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a
Signed-off-by: Chenhui Zhao
---
Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 13 +
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 3 +++
2 files changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
b/Documentation/devicetree
access. This piece of code and related TLBs are prefetched in advance.
Due to the different initialization code between 32-bit and 64-bit, they
have separate resume entry and precedure.
The feature supports 32-bit and 64-bit kernel mode.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/include/asm
Some CCSR registers will lost during deep sleep. Therefore,
should save them before entering deep sleep, and restore them
when resuming from deep sleep.
Signed-off-by: Tang Yuantian
Signed-off-by: Chenhui Zhao
---
arch/powerpc/include/asm/fsl_pm.h | 2 +
arch/powerpc/platforms/85xx
precedure.
This patch configure the EPU FSM preparing for deep sleep.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/platforms/85xx/Makefile| 2 +-
arch/powerpc/platforms/85xx/sleep_fsm.c | 267
arch/powerpc/platforms/85xx/sleep_fsm.h | 92 +++
3 files
-by: Chenhui Zhao
---
arch/powerpc/Kconfig | 3 +-
arch/powerpc/include/asm/fsl_pm.h | 2 +-
arch/powerpc/platforms/85xx/Kconfig| 5 +++
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/qoriq_pm.c | 59 ++
arch/powe
Signed-off-by: Chenhui Zhao
---
Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 13 +
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 3 +++
2 files changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
b/Documentation/devicetree
deep sleep
http://patchwork.ozlabs.org/patch/502548/
[4/4] powerpc: pm: support deep sleep feature on T104x
http://patchwork.ozlabs.org/patch/502550/
Chenhui Zhao (5):
powerpc/dts: add mcke-gpios for PM feature
powerpc/85xx: support sleep feature on QorIQ SoCs with RCPM
powerpc: pm: a
On Mon, Aug 1, 2016 at 9:22 PM, Marc Zyngier wrote:
>
> On 01/08/16 10:49, Chenhui Zhao wrote:
> > The NXP's QorIQ Processors based on ARM Core have a RCPM module
> > (Run Control and Power Management), which performs all device-level
> > tasks associated with power m
On Mon, Aug 1, 2016 at 8:25 PM, Arnd Bergmann wrote:
> On Monday, August 1, 2016 5:49:03 PM CEST Chenhui Zhao wrote:
>> The NXP's QorIQ Processors based on ARM Core have a RCPM module
>> (Run Control and Power Management), which performs all device-level
>> tasks associ
-by: Chenhui Zhao
---
Note: This patch set is based on CPU hotplug patches.
arch/powerpc/Kconfig | 3 +-
arch/powerpc/platforms/85xx/Kconfig| 5 +++
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/qoriq_pm.c | 59 ++
a
access. This piece of code and related TLBs are prefetched in advance.
Due to the different initialization code between 32-bit and 64-bit, they
have separate resume entry and precedure.
The feature supports 32-bit and 64-bit kernel mode.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/include/asm
precedure.
This patch configure the EPU FSM preparing for deep sleep.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/platforms/85xx/Makefile| 2 +-
arch/powerpc/platforms/85xx/sleep_fsm.c | 256
arch/powerpc/platforms/85xx/sleep_fsm.h | 104 +
3 files
Add get_dcsrbase() to get the physical base address of DCSR.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/sysdev/fsl_soc.c | 31 +++
arch/powerpc/sysdev/fsl_soc.h | 1 +
2 files changed, 32 insertions(+)
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc
On Sat, Aug 1, 2015 at 10:57 AM, Scott Wood
wrote:
On Fri, 2015-07-24 at 20:46 +0800, Chenhui Zhao wrote:
+static void mpc85xx_pmc_set_wake(struct device *dev, void *enable)
{
int ret;
+ u32 value[2];
+
+ if (!device_may_wakeup(dev))
+ return;
+
+ if
On Sat, Aug 1, 2015 at 8:45 AM, Scott Wood
wrote:
On Fri, 2015-06-26 at 15:44 +0800, yuantian.t...@freescale.com wrote:
+static void rcpm_v1_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(&rcpm_v1_regs->ippdexpcr, *mask);
+ else
+ clrb
On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood
wrote:
On Fri, 2015-07-31 at 17:20 +0800, b29...@freescale.com wrote:
@@ -71,7 +56,7 @@ static void mpc85xx_give_timebase(void)
barrier();
tb_req = 0;
- mpc85xx_timebase_freeze(1);
+ qoriq_pm_ops->freeze_time_base(1
platforms.
Signed-off-by: Chenhui Zhao
Signed-off-by: Tang Yuantian
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/include/asm/smp.h| 1 +
arch/powerpc/kernel/smp.c | 5 +
arch/powerpc/platforms/85xx/smp.c | 39
---
4
On Sat, Aug 1, 2015 at 8:41 AM, Scott Wood
wrote:
On Fri, 2015-07-31 at 20:53 +0800, Chenhui Zhao wrote:
In the last stage of deep sleep, software will trigger a Finite
State Machine (FSM) to control the hardware precedure, such as
board isolation, killing PLLs, removing power, and so on
On e6500, in the case of cpu hotplug, either thread in one core
may be the first thread initilzing the TLB1. The subsequent threads
must not setup it again.
The code is derived from the comment of Scott Wood.
Signed-off-by: Chenhui Zhao
---
Changes for v4:
* added CONFIG_BOOKE
arch/powerpc
79 matches
Mail list logo
