Hi,
On 10/26/2017 3:31 AM, Alex Elder wrote:
> No Qualcomm SoC requires the "ehci-msm.c" code any more. So remove it.
>
> Suggested-by: Stephen Boyd
> Signed-off-by: Alex Elder
> Acked-by: Bjorn Andersson
> Acked-by: Andy Gross
> ---
> drivers/usb/host/Makefile | 1 -
> drivers/usb/host
Hi,
On 10/26/2017 3:31 AM, Alex Elder wrote:
> No Qualcomm SoC requires the "phy-msm-usb.c" USB phy driver support
> any more, so remove the code.
>
> Suggested-by: Stephen Boyd
> Signed-off-by: Alex Elder
> Acked-by: Bjorn Andersson
> Acked-by: Andy Gross
> ---
> drivers/usb/phy/Makefile
Hi,
On 1/10/2018 6:18 PM, Roger Quadros wrote:
> Hi Manu,
>
> On 27/09/17 14:19, Manu Gautam wrote:
>> Driver powers-off PHYs and reinitializes DWC3 core and gadget on
>> resume. While this works fine for gadget mode but in host
>> mode there is not re-initial
Hi Felipe,
On 1/11/2018 1:44 PM, Felipe Balbi wrote:
> Hi,
>
> Manu Gautam writes:
>>> On 27/09/17 14:19, Manu Gautam wrote:
>>>> Driver powers-off PHYs and reinitializes DWC3 core and gadget on
>>>> resume. While this works fine for gadget
Hi Vivek,
On 1/12/2018 2:14 PM, Vivek Gautam wrote:
> On Wed, Jan 3, 2018 at 4:58 PM, Manu Gautam wrote:
>> PHY block or asynchronous reset requires signal
>> to be asserted before de-asserting. Driver is only
>> de-asserting signal which is already low, hence
>> rese
Hi,
On 1/22/2018 6:31 PM, Roger Quadros wrote:
> Adding/removing host/gadget controller before .pm_complete()
> causes a lock-up. Let's prevent any dual-role state change
> between .pm_prepare() and .pm_complete() to fix this.
What kind of lock-up are you seeing? Some hardware lockup or software
Hi,
On 1/5/2018 4:31 PM, Kishon Vijay Abraham I wrote:
>> +enum phy_mode phy_get_mode(struct phy *phy)
>> +{
>> +enum phy_mode ret;
>> +
>> +if (!phy || !phy->ops->get_mode)
>> +return PHY_MODE_INVALID;
>> +
>> +mutex_lock(&phy->mutex);
>> +ret = phy->ops->get_mode(phy)
Hi Roger,
On 1/15/2018 9:10 PM, Roger Quadros wrote:
> Hi Manu,
[snip]
>> I think it will be better to separate runtime_suspend and pm_suspend
>> handling for
>> host mode in dwc3. Powering offf/on PHYs and dwc3_core_exit/init across
>> system
>> suspend-resume should be ok but doing that for r
+0x10/0x50
Fix this by disabling it as the first thing in phy_exit().
Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Signed-off-by: Vivek Gautam
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 4 ++--
1 file changed, 2 insertions(+),
From: Vivek Gautam
Move from using array of clocks to clk_bulk_* APIs that
are available now.
Signed-off-by: Vivek Gautam
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 50 -
1 file changed, 16 insertions(+), 34 deletions(-)
diff
PHY and some
core drivers e.g. PCIe follow specific sequence after phy_init()
that mandates pipe_clk to be enabled from power_on() only.
On similar lines move clk_enable from init() to com_init() which
executes once for multi lane PHYs.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy
poweron callback from phy_ops and explicitly perform
this from init, similar changes needed for poweroff.
Signed-off-by: Manu Gautam
Reviewed-by: Vivek Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 47 +++
1 file changed, 15 insertions(+), 32 deletions(-)
diff
Driver is currently performing PHY reset after starting
SERDES/PCS. As per hardware datasheet reset must be done
before starting PHY. Hence, update the sequence.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
New version of QUSB2 PHY has some registers offset changed.
Add support to have register layout for a target and update
the same in phy_configuration.
Signed-off-by: Manu Gautam
Reviewed-by: Vivek Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 149 +-
1 file
Use register layout to add additional registers present
on QUSB2 PHY V2 version for PHY initialization.
Other than new registers on V2, following two register's
offset and bit definitions are different: POWERDOWN control
and PLL_STATUS.
Signed-off-by: Manu Gautam
Reviewed-by: Vivek G
New revision (v3) of QMP PHY uses different offsets
for almost all of the registers. Hence, move these
definitions to header file so that updated offsets
can be added for QMP v3.
Signed-off-by: Manu Gautam
Reviewed-by: Vivek Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 119
Registers offsets for QMP V3 PHY are changed from
previous versions (1/2), update same in header file.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 149
1 file changed, 149 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom
Disable clocks and enable DP/DM wakeup interrupts when
suspending PHY.
Core driver should notify speed to PHY driver to enable
appropriate DP/DM wakeup interrupts polarity in suspend state.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 176
QMP V3 USB3 PHY is a DisplayPort (DP) and USB combo PHY
with dual RX/TX lanes to support type-c. There is a
separate block DP_COM for configuration related to type-c
or DP. Add support for dp_com region and secondary rx/tx
lanes initialization.
Signed-off-by: Manu Gautam
---
drivers/phy
The SPDX identifier is a legally binding shorthand, which
can be used instead of the full boiler plate text.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 11 +--
drivers/phy/qualcomm/phy-qcom-qusb2.c | 10 +-
2 files changed, 2 insertions(+), 19
Disable clocks and enable PHY autonomous mode to detect
wakeup events when PHY is suspended.
Core driver should notify speed to PHY driver to enable
LFPS and/or RX_DET interrupts.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 177
wakeup
events for detection. E.g. QUSB2 PHY monitors DP/DM line state
depending on whether speed is LS or FS/HS to detect resume.
Similarly QMP USB3 PHY in SS mode should monitor RX terminations
attach/detach and LFPS events depending on SSPHY is active or not.
Signed-off-by: Manu Gautam
Update compatible string and clock names for QMP version V3
USB PHY.
Acked-by: Rob Herring
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom
Update generic compatible string for QUSB2 V2 PHY. This will allow
all targets using QUSB2 V2 use same string.
Acked-by: Rob Herring
Signed-off-by: Manu Gautam
Reviewed-by: Vivek Gautam
---
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt | 5 -
1 file changed, 4 insertions(+), 1
that as well.
Signed-off-by: Manu Gautam
Reviewed-by: Vivek Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 1b82cea
Hi Doug,
On 3/27/2018 9:56 AM, Doug Anderson wrote:
> Manu
>
> On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam wrote:
>> QMP PHY for USB mode requires pipe_clk for calibration and PLL lock
>> to take place. This clock is output from PHY to GCC clock_ctl and then
>>
Hi Vivek,
On 3/27/2018 12:21 PM, Vivek Gautam wrote:
> Hi Manu,
>
>
> On 3/23/2018 11:41 AM, Manu Gautam wrote:
>> QMP PHY for USB mode requires pipe_clk for calibration and PLL lock
>> to take place.
>
> AFAIK, that's not true. The pipe clock is the *output*
Hi,
On 3/27/2018 12:26 PM, Vivek Gautam wrote:
>
>
> On 3/27/2018 10:37 AM, Manu Gautam wrote:
>> Hi Doug,
>>
>>
>> On 3/27/2018 9:56 AM, Doug Anderson wrote:
>>> Manu
>>>
>>> On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam
>>&g
Hi,
On 4/11/2018 12:02 AM, Stephen Boyd wrote:
> Quoting Doug Anderson (2018-04-10 08:05:27)
>> On Mon, Apr 9, 2018 at 11:36 PM, Manu Gautam wrote:
>>> On 3/30/2018 2:24 AM, Doug Anderson wrote:
>>>> Oh! This is what you did in the previous version of
Hi,
On 4/13/2018 2:08 AM, Stephen Boyd wrote:
> Quoting Manu Gautam (2018-04-11 08:37:38)
>>> I ask because it may be easier to never expose these clks in Linux, hit
>>> the enable bits in the branches during clk driver probe, and then act
>>> like they never exi
phy_init() and phy_exit() calls, and phy_power_on() and
phy_power_off() already accept NULL as valid PHY reference
and act as NOP. Extend same concept to phy runtime_pm APIs
to keep drivers (e.g. dwc3) code simple while dealing with
optional PHYs.
Signed-off-by: Manu Gautam
---
Changes for v2
Hi,
On 3/19/2018 11:21 PM, Evan Green wrote:
> Hi Manu,
>
> On Fri, Mar 16, 2018 at 2:46 AM Manu Gautam wrote:
[snip]
>> index d1c6905..5d78d43 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
>>
Hi,
On 3/20/2018 3:53 PM, Vivek Gautam wrote:
> Hi Manu,
>
>
> On 3/16/2018 3:14 PM, Manu Gautam wrote:
>> Update compatible strings for USB2 PHYs on sdm845.
>> There are two QUSB2 PHYs present on sdm845. Few PHY registers
>> programming is different for th
Hi Can,
On 3/21/2018 8:12 AM, c...@codeaurora.org wrote:
> On 2018-03-20 19:30, Can Guo wrote:
>> Add UFS PHY support to make SDM845 UFS work with common PHY framework.
>>
>> Signed-off-by: Can Guo
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp.c | 120
>> +++-
>>
d-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 6470c5d..73aa282 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/driver
since v1:
- Updated qusb2 compatibility name as per comment from Vivek.
Manu Gautam (6):
phy: qcom-qmp: Enable pipe_clk before checking USB3 PHY_STATUS
phy: qcom-qusb2: Fix crash if nvmem cell not specified
dt-bindings: phy-qcom-qmp: Update bindings for sdm845
phy: qcom-qmp: Add QMP V3
Update compatible strings for USB3 PHYs on SDM845.
One is QMPv3 DisplayPort-USB combo PHY and other one
is USB UNI PHY which is single lane USB3 PHY without
DP capability.
Reviewed-by: Rob Herring
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 4 +++-
1
There are two QUSB2 PHYs present on sdm845. Update PHY
registers programming for both the PHYs related to
electrical parameters to improve eye diagram.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 39 +++
1 file changed, 39 insertions
ivek Gautam
Cc: stable # 4.14+
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 94afeac..40fdef8 100644
--- a/drivers/phy/qualcomm/p
P
PHY configuration.
Reviewed-by: Evan Green
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 148
drivers/phy/qualcomm/phy-qcom-qmp.h | 5 ++
2 files changed, 153 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/driver
Update compatible strings for USB2 PHYs on sdm845.
There are two QUSB2 PHYs present on sdm845. Few PHY registers
programming is different for these PHYs related to electrical
parameters, otherwise both are same.
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qusb2
Hi Stephen,
On 3/23/2018 12:13 AM, Stephen Boyd wrote:
> Quoting Manu Gautam (2018-03-22 01:50:41)
>> QMP PHY for USB mode requires pipe_clk for calibration and PLL lock
>> to take place. This lock is output from PHY to GCC clock_ctl and then
> s/lock/clock/
Yes, will fix ty
since v2:
- Use separate phy_ops for USB to not register power_on op.
- And other minor changes as per review comments from Stephen.
Changes since v1:
- Updated qusb2 compatibility name as per comment from Vivek.
Manu Gautam (6):
phy: qcom-qmp: Enable pipe_clk before checking USB3 PHY_STATUS
igned-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 6470c5d..5d8df6a 100644
--- a/drivers/phy/qualcom
ivek Gautam
Cc: stable # 4.14+
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 94afeac..40fdef8 100644
--- a/drivers/phy/qualcomm/p
Update compatible strings for USB3 PHYs on SDM845.
One is QMPv3 DisplayPort-USB combo PHY and other one
is USB UNI PHY which is single lane USB3 PHY without
DP capability.
Reviewed-by: Rob Herring
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 4 +++-
1
There are two QUSB2 PHYs present on sdm845. Update PHY
registers programming for both the PHYs related to
electrical parameters to improve eye diagram.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 39 +++
1 file changed, 39 insertions
P
PHY configuration.
Reviewed-by: Evan Green
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 148
drivers/phy/qualcomm/phy-qcom-qmp.h | 5 ++
2 files changed, 153 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/driver
Update compatible strings for USB2 PHYs on sdm845.
There are two QUSB2 PHYs present on sdm845. Few PHY registers
programming is different for these PHYs related to electrical
parameters, otherwise both are same.
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qusb2
Hi,
On 3/30/2018 2:24 AM, Doug Anderson wrote:
> Hi,
>
> On Thu, Mar 29, 2018 at 11:44 AM, Doug Anderson wrote:
>> Hi,
>>
>> On Thu, Mar 29, 2018 at 4:04 AM, Manu Gautam wrote:
>>> QMP PHY for USB/PCIE requires pipe_clk for locking of
>>> retime buf
Hi,
On 4/6/2018 1:37 AM, Stephen Boyd wrote:
> Quoting Doug Anderson (2018-03-29 13:55:55)
>> Hi,
>>
>> On Thu, Mar 29, 2018 at 4:04 AM, Manu Gautam wrote:
>>> The USB and PCIE pipe clocks are sourced from external clocks
>>> inside the QMP USB/PCIE
Hi,
On 3/30/2018 2:08 AM, Doug Anderson wrote:
> Hi,
>
> On Thu, Mar 29, 2018 at 4:04 AM, Manu Gautam wrote:
>> @@ -241,6 +252,18 @@ struct qusb2_phy_cfg {
>> * @tcsr: TCSR syscon register map
>> * @cell: nvmem cell containing phy tuning value
>> *
>
On 4/10/2018 1:48 AM, Rob Herring wrote:
> On Thu, Mar 29, 2018 at 01:38:23PM -0700, Doug Anderson wrote:
>> Hi,
>>
>> On Thu, Mar 29, 2018 at 4:04 AM, Manu Gautam wrote:
>>> To improve eye diagram for PHYs on different boards of same SOC,
>>> some par
Existing documentation has lot of incorrect information as it
was originally added for a driver that no longer exists.
Signed-off-by: Manu Gautam
---
.../devicetree/bindings/usb/qcom,dwc3.txt | 87 +++---
1 file changed, 59 insertions(+), 28 deletions(-)
diff --git a
Qscratch wrapper there
are some limitations on QCOM SOCs that require special handling
of power management e.g. suspending PHY using GUSB2PHYCFG
register and ensuring PHY enters L2 before turning off clocks etc.
Signed-off-by: Manu Gautam
---
drivers/usb/dwc3/Kconfig | 11 +
drivers/usb/dwc3
Hi,
On 3/13/2018 4:38 PM, Felipe Balbi wrote:
> Hi,
>
> +Andy
>
> Manu Gautam writes:
>> DWC3 controller on Qualcomm SOCs has a Qscratch wrapper.
>> Some of its uses are described below resulting in need to
>> have a separate glue driver instead of using
Hi,
On 6/19/2018 2:06 PM, Can Guo wrote:
> +static int qcom_qmp_phy_poweron(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qmp->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void __i
++---
> 1 file changed, 14 insertions(+), 11 deletions(-)
Reviewed-by: Manu Gautam
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
+---
> 1 file changed, 12 insertions(+), 7 deletions(-)
Reviewed-by: Manu Gautam
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Hi,
On 5/26/2018 3:37 AM, Douglas Anderson wrote:
> It appears that a "#define DEBUG" was left in on the recent patch
> landed for the Qualcomm DWC3 glue driver. Let's remove it.
>
> Fixes: a4333c3a6ba9 ("usb: dwc3: Add Qualcomm DWC3 glue driver")
> Signed-off-by: Douglas Anderson
> ---
>
> dr
Hi,
On 12/20/2018 4:39 PM, Shawn Guo wrote:
> Hi Manu,
>
> On Thu, Dec 20, 2018 at 09:33:43AM +0530, mgau...@codeaurora.org wrote:
>> Hi Shawn,
>>
>> On 2018-12-20 06:31, Shawn Guo wrote:
>>> It adds Synopsys 28nm Femto High-Speed USB PHY driver support, which
>>> is usually paired with Synopsys D
d and
dwc3 core already takes care of explicitly suspending PHY
during suspend if quirks are specified.
Signed-off-by: Manu Gautam
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/ms
Fix HSTX_TRIM tuning logic which instead of using fused value
as HSTX_TRIM, incorrectly performs bitwise OR operation with
existing default value.
Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
Signed-off-by: Manu Gautam
Reviewed-by: Dougla
Tune1 register on sdm845 is used to update HSTX_TRIM with fused
setting. Enable same by specifying update_tune1_with_efuse flag
for sdm845, otherwise driver ends up programming tune2 register.
Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845")
Signed-off-by: M
performs bitwise OR
operation with existing default value.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index
Correct address for pcs_misc register region of USB3 QMP UNI PHY.
These registers are used during runtime-suspend/resume routines
of phy.
Fixes: ca4db2b538a1 ("arm64: dts: qcom: sdm845: Add USB-related nodes")
Signed-off-by: Manu Gautam
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2
Hi,
On 3/28/2018 1:44 AM, Doug Anderson wrote:
> Hi,
>
> On Tue, Mar 27, 2018 at 12:50 AM, Manu Gautam wrote:
>> Hi,
>>
>>
>> On 3/27/2018 12:26 PM, Vivek Gautam wrote:
>>>
>>> On 3/27/2018 10:37 AM, Manu Gautam wrote:
>>>> Hi
Hi,
On 3/28/2018 3:07 AM, Doug Anderson wrote:
> Hi,
>
> On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam wrote:
>> Update compatible strings for USB3 PHYs on SDM845.
>> One is QMPv3 DisplayPort-USB combo PHY and other one
>> is USB UNI PHY which is single lane USB3 P
Hi,
On 3/28/2018 3:27 AM, Doug Anderson wrote:
> Hi,
>
> On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam wrote:
>> Update compatible strings for USB2 PHYs on sdm845.
>> There are two QUSB2 PHYs present on sdm845. Few PHY registers
>> programming is different for these
Hi,
On 3/28/2018 4:22 AM, Doug Anderson wrote:
> Hi,
>
> On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam wrote:
>> There are two QUSB2 PHYs present on sdm845. Update PHY
>> registers programming for both the PHYs related to
>> electrical parameters to improve eye diagra
qusb2 compatibility name as per comment from Vivek.
Manu Gautam (7):
clk: msm8996-gcc: change halt check for USB/PCIE pipe_clk
phy: qcom-qmp: Enable pipe_clk before PHY initialization
phy: qcom-qusb2: Fix crash if nvmem cell not specified
dt-bindings: phy-qcom-qmp: Update bindings for sdm845
phy:
disabling
the clocks. It allows to simplify PHY client driver code which
is both user and source of the pipe_clk and avoid error logging
related status check on clk_disable/enable.
Signed-off-by: Manu Gautam
---
drivers/clk/qcom/gcc-msm8996.c | 4
1 file changed, 4 insertions(+)
diff --git a
: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 6470c5d..fddb1c9 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b
le string which
was earlier added for sdm845 only as there wouldn't be
any user of same.
While at it, fix has_pwrdn_delay attribute for USB-DP
PHY configuration and.
Reviewed-by: Evan Green
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 147 +
as earlier added for
sdm845 only.
Signed-off-by: Manu Gautam
---
.../devicetree/bindings/phy/qcom-qusb2-phy.txt| 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
b/Documentation/devicetree/bi
There are two QUSB2 PHYs present on sdm845. In order
to improve eye diagram for both the PHYs some parameters
need to be changed. Provide device tree properties to
override these from board specific device tree files.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 112
y: Vivek Gautam
Reviewed-by: Evan Green
Cc: stable # 4.14+
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 94afeac..40fdef8 100644
--
ouldn't be any user of same.
Reviewed-by: Rob Herring
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
b/Documentation/devicetr
ges as per review comments from Stephen.
Changes since v1:
- Updated qusb2 compatibility name as per comment from Vivek.
Manu Gautam (7):
clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk
phy: qcom-qmp: Enable pipe_clk before PHY initialization
phy: qcom-qusb2: Fix crash if
ges as per review comments from Stephen.
Changes since v1:
- Updated qusb2 compatibility name as per comment from Vivek.
Manu Gautam (7):
clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk
phy: qcom-qmp: Enable pipe_clk before PHY initialization
phy: qcom-qusb2: Fix crash if
as earlier added for
sdm845 only.
Signed-off-by: Manu Gautam
---
.../devicetree/bindings/phy/qcom-qusb2-phy.txt | 23 +-
include/dt-bindings/phy/phy-qcom-qusb2.h | 37 ++
2 files changed, 59 insertions(+), 1 deletion(-)
create mode 100644 include/d
: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 6470c5d..fddb1c9 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b
le string which
was earlier added for sdm845 only as there wouldn't be
any user of same.
While at it, fix has_pwrdn_delay attribute for USB-DP
PHY configuration and.
Reviewed-by: Evan Green
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 147 +
There are two QUSB2 PHYs present on sdm845. In order
to improve eye diagram for both the PHYs some parameters
need to be changed. Provide device tree properties to
override these from board specific device tree files.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 126
ouldn't be any user of same.
Reviewed-by: Douglas Anderson
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
b/Documentation/devi
y: Vivek Gautam
Reviewed-by: Evan Green
Cc: stable # 4.14+
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 94afeac..40fdef8 100644
--
disabling
the clocks. It allows to simplify PHY client driver code which
is both user and source of the pipe_clk and avoid error logging
related status check on clk_disable/enable.
Signed-off-by: Manu Gautam
---
drivers/clk/qcom/gcc-msm8996.c | 4
1 file changed, 4 insertions(+)
diff --git a
Hi,
On 6/11/2020 7:58 PM, Sandeep Maheswaram wrote:
> Avoiding phy powerdown in host mode so that it can be wake up by devices.
> Set usb controller wakeup capable when wakeup capable devices are
> connected to the host.
>
> Signed-off-by: Sandeep Maheswaram
> ---
> drivers/usb/dwc3/core.c
Hi,
On 1/11/2019 2:51 PM, Felipe Balbi wrote:
> Hi,
>
> Manu Gautam writes:
>>> Manu Gautam writes:
>>>> If a function driver tries to re-submit an already queued request,
>>>> it can results in corruption of pending/started request lists.
>&
If a function driver tries to re-submit an already queued request,
it can results in corruption of pending/started request lists.
Catch such conditions and fail the request submission to DCD.
Signed-off-by: Manu Gautam
---
drivers/usb/dwc3/gadget.c | 6 ++
1 file changed, 6 insertions
Hi,
On 1/11/2019 1:13 PM, Felipe Balbi wrote:
> Hi,
>
> Manu Gautam writes:
>> If a function driver tries to re-submit an already queued request,
>> it can results in corruption of pending/started request lists.
>> Catch such conditions and fail the request submission
Hi,
On 9/5/2018 3:04 AM, Prakruthi Deepak Heragu wrote:
> Add support for control peripheral of EUD (Embedded USB Debugger) to
> listen to events such as USB attach/detach, charger enable/disable, pet
> EUD to indicate software is functional.
>
> Signed-off-by: Satya Durga Srinivasu Prabhala
> S
Hi,
On 5/29/2018 10:07 AM, Can Guo wrote:
> All PHYs should be powered on before register configuration starts. And
> only PCIe PHYs need an extra power control before deasserts reset state.
>
> Signed-off-by: Can Guo
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 5 -
> 1 file changed, 4 ins
HI,
On 4/19/2018 4:03 AM, Masahiro Yamada wrote:
> In the current design of DWC3 driver,
> the DT typically becomes a nested structure like follows:
>
> dwc3-glue {
> compatible = "foo,dwc3";
> ...
>
> dwc3 {
> compatible = "snps,dwc3";
>
Hi,
On 3/18/2018 6:19 PM, Rob Herring wrote:
> On Tue, Mar 13, 2018 at 04:06:00PM +0530, Manu Gautam wrote:
>> Existing documentation has lot of incorrect information as it
>> was originally added for a driver that no longer exists.
>>
>> Signed-off-by: Manu Gautam
Hi,
On 3/18/2018 6:22 PM, Rob Herring wrote:
> On Fri, Mar 16, 2018 at 03:14:58PM +0530, Manu Gautam wrote:
>> Update compatible strings for USB2 PHYs on sdm845.
>> There are two QUSB2 PHYs present on sdm845. Few PHY registers
>> programming is different for these PHYs
o POR value in case of any initalization by boot code.
Manu Gautam (3):
dt-bindings: usb: Update documentation for Qualcomm DWC3 driver
usb: dwc3: Add Qualcomm DWC3 glue driver
usb: dwc3: core: Suspend PHYs on runtime suspend in host mode
.../devicetree/bindings/usb/qcom,dwc3.txt
Existing documentation has lot of incorrect information as it
was originally added for a driver that no longer exists.
Signed-off-by: Manu Gautam
---
.../devicetree/bindings/usb/qcom,dwc3.txt | 85 --
1 file changed, 63 insertions(+), 22 deletions(-)
diff --git a
platform glue drivers e.g.
dwc3-qcom handle remote wakeup during bus suspend by waking up
devices on receiving wakeup event from PHY.
Signed-off-by: Manu Gautam
---
drivers/usb/dwc3/core.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers
.
- Support for wakeup interrupts lines that are asserted whenever
there is any wakeup event on USB3 or USB2 bus.
- Support to replace pip3 clock going to DWC3 with utmi clock
for hardware configuration where SSPHY is not used with DWC3.
Signed-off-by: Manu Gautam
---
drivers/usb/dwc3/Kconfig
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