Driver is currently performing PHY reset after starting
SERDES/PCS. As per hardware datasheet reset must be done
before starting PHY. Hence, update the sequence.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++---
1 file changed, 3 inse
Use register layout to add additional registers present
on QUSB2 PHY V2 version for PHY initialization.
Other than new registers on V2, following two register's
offset and bit definitions are different: POWERDOWN control
and PLL_STATUS.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
Re
New revision (v3) of QMP PHY uses different offsets
for almost all of the registers. Hence, move these
definitions to header file so that updated offsets
can be added for QMP v3.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
Reviewed-by: Vivek Gautam <vivek.gau...@codea
Registers offsets for QMP V3 PHY are changed from
previous versions (1/2), update same in header file.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 149
1 file changed, 149 insertions(+)
diff --git a/d
QMP V3 USB3 PHY is a DisplayPort (DP) and USB combo PHY
with dual RX/TX lanes to support type-c. There is a
separate block DP_COM for configuration related to type-c
or DP. Add support for dp_com region and secondary rx/tx
lanes initialization.
Signed-off-by: Manu Gautam <mgau...@codeaurora.
Disable clocks and enable DP/DM wakeup interrupts when
suspending PHY.
Core driver should notify speed to PHY driver to enable
appropriate DP/DM wakeup interrupts polarity in suspend state.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c
New version of QUSB2 PHY has some registers offset changed.
Add support to have register layout for a target and update
the same in phy_configuration.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
Reviewed-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
drivers/phy/qualc
Update compatible string and clock names for QMP version V3
USB PHY.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
Hi Vivek,
On 1/12/2018 2:14 PM, Vivek Gautam wrote:
> On Wed, Jan 3, 2018 at 4:58 PM, Manu Gautam <mgau...@codeaurora.org> wrote:
>> PHY block or asynchronous reset requires signal
>> to be asserted before de-asserting. Driver is only
>> de-asserting signal which is
Hi,
On 12/26/2017 8:22 AM, Lipengcheng wrote:
> The value is 4, it can cache four descriptors. When streaming_interval = 1,
> it can tolerate 500us. Some busy scenes, it may be more than 500us because
> cpu scheduling is not timely. There will have some problems. It is better
> set to eight.
>
>
Hi,
On 12/28/2017 4:34 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
[snip]
>
>>> I'd prefer adding modes in enum phy_mode according to speed and using
>>> phy_set_mode.
>> yeah, that also seems good idea. How about something like this:
>>
>> --- a/include/linux/phy/phy.h
>> +++
Hi,
On 12/29/2017 11:58 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 29 December 2017 09:54 AM, Manu Gautam wrote:
>> Hi,
[snip]
>
> suggest using switch in such case.. and not all PHY drivers do specific
> configurations for specific speeds.
>> This loo
poweron callback from phy_ops and explicitly perform
this from init, similar changes needed for poweroff.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 47 +++
1 file changed, 15 insertions(+), 32 deletions(-)
/0x12c
[ 33.381776] [] ret_from_fork+0x10/0x50
Fix this by disabling it as the first thing in phy_exit().
Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Signed-off-by: Manu Gautam <mgau...@codeaur
PHY and some
core drivers e.g. PCIe follow specific sequence after phy_init()
that mandates pipe_clk to be enabled from power_on() only.
On similar lines move clk_enable from init() to com_init() which
executes once for multi lane PHYs.
Signed-off-by: Manu Gautam <mgau...@codeaurora.
From: Vivek Gautam <vivek.gau...@codeaurora.org>
Move from using array of clocks to clk_bulk_* APIs that
are available now.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/p
Disable clocks and enable DP/DM wakeup interrupts when
suspending PHY.
Core driver should notify speed to PHY driver to enable
appropriate DP/DM wakeup interrupts polarity in suspend state.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c
QMP V3 USB3 PHY is a DisplayPort (DP) and USB combo PHY
with dual RX/TX lanes to support type-c. There is a
separate block DP_COM for configuration related to type-c
or DP. Add support for dp_com region and secondary rx/tx
lanes initialization.
Signed-off-by: Manu Gautam <mgau...@codeaurora.
Registers offsets for QMP V3 PHY are changed from
previous versions (1/2), update same in header file.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 149
1 file changed, 149 insertions(+)
diff --git a/d
New revision (v3) of QMP PHY uses different offsets
for almost all of the registers. Hence, move these
definitions to header file so that updated offsets
can be added for QMP v3.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c
Use register layout to add additional registers present
on QUSB2 PHY V2 version for PHY initialization.
Other than new registers on V2, following two register's
offset and bit definitions are different: POWERDOWN control
and PLL_STATUS.
Signed-off-by: Manu Gautam <mgau...@codeaurora.
Update generic compatible string for QUSB2 V2 PHY. This will allow
all targets using QUSB2 V2 use same string.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt | 5 -
1 fil
Update compatible string and clock names for QMP version V3
USB PHY.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
New version of QUSB2 PHY has some registers offset changed.
Add support to have register layout for a target and update
the same in phy_configuration.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 149 +-
Driver is currently performing PHY reset after starting
SERDES/PCS. As per hardware datasheet reset must be done
before starting PHY. Hence, update the sequence.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++---
1 file changed, 3 inse
Disable clocks and enable PHY autonomous mode to detect
wakeup events when PHY is suspended.
Core driver should notify speed to PHY driver to enable
LFPS and/or RX_DET interrupts.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c
of wakeup
events for detection. E.g. QUSB2 PHY monitors DP/DM line state
depending on whether speed is LS or FS/HS to detect resume.
Similarly QMP USB3 PHY in SS mode should monitor RX terminations
attach/detach and LFPS events depending on SSPHY is active or not.
Signed-off-by: Manu Gautam <m
that as well.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 1
Hi,
On 9/5/2018 3:04 AM, Prakruthi Deepak Heragu wrote:
> Add support for control peripheral of EUD (Embedded USB Debugger) to
> listen to events such as USB attach/detach, charger enable/disable, pet
> EUD to indicate software is functional.
>
> Signed-off-by: Satya Durga Srinivasu Prabhala
>
Hi,
On 1/22/2018 6:31 PM, Roger Quadros wrote:
> Adding/removing host/gadget controller before .pm_complete()
> causes a lock-up. Let's prevent any dual-role state change
> between .pm_prepare() and .pm_complete() to fix this.
What kind of lock-up are you seeing? Some hardware lockup or
in Qscratch wrapper there
are some limitations on QCOM SOCs that require special handling
of power management e.g. suspending PHY using GUSB2PHYCFG
register and ensuring PHY enters L2 before turning off clocks etc.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/usb/dwc3/K
Existing documentation has lot of incorrect information as it
was originally added for a driver that no longer exists.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
.../devicetree/bindings/usb/qcom,dwc3.txt | 87 +++---
1 file changed, 59 insertions(
Hi,
On 3/13/2018 4:38 PM, Felipe Balbi wrote:
> Hi,
>
> +Andy
>
> Manu Gautam <mgau...@codeaurora.org> writes:
>> DWC3 controller on Qualcomm SOCs has a Qscratch wrapper.
>> Some of its uses are described below resulting in need to
>> have a separate glue
phy_init() and phy_exit() calls, and phy_power_on() and
phy_power_off() already accept NULL as valid PHY refernece
and act as NOP. Extend same concept to phy runtime_pm APIs
to keep drivers (e.g. dwc3) code simple while dealing with
optional PHYs.
Signed-off-by: Manu Gautam <m
-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 6470c5d..73aa282 100644
--- a/drivers/phy/qualcomm/phy-qcom
Driver currently crashes due to NULL pointer deference
while updating PHY tune register if nvmem cell is NULL.
Since, fused value for Tune1/2 register is optional,
we'd rather bail out.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 4
Update compatible strings for USB3 PHYs on SDM845.
One is QMPv3 DisplayPort-USB combo PHY and other one
is USB UNI PHY which is single lane USB3 PHY without
DP capability.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 4 +
configuration.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 148
drivers/phy/qualcomm/phy-qcom-qmp.h | 5 ++
2 files changed, 153 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drive
Update compatible strings for USB2 PHYs on sdm845.
There are two QUSB2 PHYs present on sdm845. Few PHY registers
programming is different for these PHYs related to electrical
parameters, otherwise both are same.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devi
There are two QUSB2 PHYs present on sdm845. Update PHY
registers programming for both the PHYs related to
electrical parameters to improve eye diagram.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 39 +++
Hi,
On 3/14/2018 2:20 PM, Felipe Balbi wrote:
> Hi,
>
> Manu Gautam <mgau...@codeaurora.org> writes:
>
[snip]
>>>> - Support to replace pip3 clock going to DWC3 with utmi clock
>>>>for hardware configuration where SSPHY is not used with DWC3.
>&g
Hi,
On 4/11/2018 12:02 AM, Stephen Boyd wrote:
> Quoting Doug Anderson (2018-04-10 08:05:27)
>> On Mon, Apr 9, 2018 at 11:36 PM, Manu Gautam <mgau...@codeaurora.org> wrote:
>>> On 3/30/2018 2:24 AM, Doug Anderson wrote:
>>>> Oh! This is what you did
Hi Jack,
On 4/13/2018 11:03 PM, Jack Pham wrote:
> Hi Manu,
>
> On Fri, Apr 13, 2018 at 10:21:23PM +0530, Manu Gautam wrote:
>> DWC3 controller on Qualcomm SOCs has a Qscratch wrapper.
>> Some of its uses are described below resulting in need to
>> have a separate g
review comment from Felipe.
- Addressed other review comments from Felipe and Rob.
- Some other minor code changes related to redability.
- Add reset_control assert in driver probe to ensure core registers
are reset to POR value in case of any initalization by boot code.
Manu Gautam (3):
dt
platform glue drivers e.g.
dwc3-qcom handle remote wakeup during bus suspend by waking up
devices on receiving wakeup event from PHY.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/usb/dwc3/core.c | 36 +---
1 file changed, 33 insertions(+), 3 del
.
- Support for wakeup interrupts lines that are asserted whenever
there is any wakeup event on USB3 or USB2 bus.
- Support to replace pip3 clock going to DWC3 with utmi clock
for hardware configuration where SSPHY is not used with DWC3.
Signed-off-by: Manu Gautam <mgau...@codeaurora.
Existing documentation has lot of incorrect information as it
was originally added for a driver that no longer exists.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
.../devicetree/bindings/usb/qcom,dwc3.txt | 78 --
1 file changed, 57 insertions(
On 4/10/2018 1:48 AM, Rob Herring wrote:
> On Thu, Mar 29, 2018 at 01:38:23PM -0700, Doug Anderson wrote:
>> Hi,
>>
>> On Thu, Mar 29, 2018 at 4:04 AM, Manu Gautam <mgau...@codeaurora.org> wrote:
>>> To improve eye diagram for PHYs on different boards of sa
Hi,
On 3/30/2018 2:24 AM, Doug Anderson wrote:
> Hi,
>
> On Thu, Mar 29, 2018 at 11:44 AM, Doug Anderson <diand...@chromium.org> wrote:
>> Hi,
>>
>> On Thu, Mar 29, 2018 at 4:04 AM, Manu Gautam <mgau...@codeaurora.org> wrote:
>>> QMP PHY for USB/
Hi,
On 4/6/2018 1:37 AM, Stephen Boyd wrote:
> Quoting Doug Anderson (2018-03-29 13:55:55)
>> Hi,
>>
>> On Thu, Mar 29, 2018 at 4:04 AM, Manu Gautam <mgau...@codeaurora.org> wrote:
>>> The USB and PCIE pipe clocks are sourced from external clocks
>&g
Hi,
On 3/30/2018 2:08 AM, Doug Anderson wrote:
> Hi,
>
> On Thu, Mar 29, 2018 at 4:04 AM, Manu Gautam <mgau...@codeaurora.org> wrote:
>> @@ -241,6 +252,18 @@ struct qusb2_phy_cfg {
>> * @tcsr: TCSR syscon register map
>> * @cell: nvmem
Hi,
On 4/13/2018 2:08 AM, Stephen Boyd wrote:
> Quoting Manu Gautam (2018-04-11 08:37:38)
>>> I ask because it may be easier to never expose these clks in Linux, hit
>>> the enable bits in the branches during clk driver probe, and then act
>>> like they never exi
Hi Amit,
On 4/18/2018 6:33 PM, Amit Nischal wrote:
>>> + /* Disable the GPLL0 active input to MMSS and GPU via MISC
>>> registers */
>>> + regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
>>> + regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
>>
>> I think we'll have to throw in
Hi Kishon,
On 3/20/2018 11:31 AM, Manu Gautam wrote:
> phy_init() and phy_exit() calls, and phy_power_on() and
> phy_power_off() already accept NULL as valid PHY reference
> and act as NOP. Extend same concept to phy runtime_pm APIs
> to keep drivers (e.g. dwc3) code simple w
Hi,
On 4/13/2018 2:17 AM, Doug Anderson wrote:
>> Thanks for review Rob. I too agree with both the viewpoints.
>> Doug, if it is not of much concern then can I stick with current approach?
> I certainly would appreciate the #defines and believe they add to the
> readability, but if you're dead
HI,
On 4/19/2018 4:03 AM, Masahiro Yamada wrote:
> In the current design of DWC3 driver,
> the DT typically becomes a nested structure like follows:
>
> dwc3-glue {
> compatible = "foo,dwc3";
> ...
>
> dwc3 {
> compatible = "snps,dwc3";
>
Hi Rob,
On 4/17/2018 2:08 AM, Rob Herring wrote:
> On Fri, Apr 13, 2018 at 10:21:22PM +0530, Manu Gautam wrote:
>> Existing documentation has lot of incorrect information as it
>> was originally added for a driver that no longer exists.
>>
>> Signed-off-by: Manu Gau
Hi,
On 3/27/2018 12:26 PM, Vivek Gautam wrote:
>
>
> On 3/27/2018 10:37 AM, Manu Gautam wrote:
>> Hi Doug,
>>
>>
>> On 3/27/2018 9:56 AM, Doug Anderson wrote:
>>> Manu
>>>
>>> On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam <mgau...
Hi Vivek,
On 3/27/2018 12:21 PM, Vivek Gautam wrote:
> Hi Manu,
>
>
> On 3/23/2018 11:41 AM, Manu Gautam wrote:
>> QMP PHY for USB mode requires pipe_clk for calibration and PLL lock
>> to take place.
>
> AFAIK, that's not true. The pipe clock is the *output*
Hi Doug,
On 3/27/2018 9:56 AM, Doug Anderson wrote:
> Manu
>
> On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam <mgau...@codeaurora.org> wrote:
>> QMP PHY for USB mode requires pipe_clk for calibration and PLL lock
>> to take place. This clock is output from PHY to GC
Hi,
On 3/28/2018 3:27 AM, Doug Anderson wrote:
> Hi,
>
> On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam <mgau...@codeaurora.org> wrote:
>> Update compatible strings for USB2 PHYs on sdm845.
>> There are two QUSB2 PHYs present on sdm845. Few PHY registers
>> progra
Hi,
On 3/28/2018 3:07 AM, Doug Anderson wrote:
> Hi,
>
> On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam <mgau...@codeaurora.org> wrote:
>> Update compatible strings for USB3 PHYs on SDM845.
>> One is QMPv3 DisplayPort-USB combo PHY and other one
>> is USB UNI
Hi,
On 3/28/2018 4:22 AM, Doug Anderson wrote:
> Hi,
>
> On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam <mgau...@codeaurora.org> wrote:
>> There are two QUSB2 PHYs present on sdm845. Update PHY
>> registers programming for both the PHYs related to
>> electrical
Hi,
On 3/28/2018 1:44 AM, Doug Anderson wrote:
> Hi,
>
> On Tue, Mar 27, 2018 at 12:50 AM, Manu Gautam <mgau...@codeaurora.org> wrote:
>> Hi,
>>
>>
>> On 3/27/2018 12:26 PM, Vivek Gautam wrote:
>>>
>>> On 3/27/2018 10:37 AM, Manu Gautam
compatibility name as per comment from Vivek.
Manu Gautam (7):
clk: msm8996-gcc: change halt check for USB/PCIE pipe_clk
phy: qcom-qmp: Enable pipe_clk before PHY initialization
phy: qcom-qusb2: Fix crash if nvmem cell not specified
dt-bindings: phy-qcom-qmp: Update bindings for sdm845
phy: qcom
-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 6470c5d..fddb1c9 100644
--- a/drive
ring which
was earlier added for sdm845 only as there wouldn't be
any user of same.
While at it, fix has_pwrdn_delay attribute for USB-DP
PHY configuration and.
Reviewed-by: Evan Green <evgr...@chromium.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcom
or disabling
the clocks. It allows to simplify PHY client driver code which
is both user and source of the pipe_clk and avoid error logging
related status check on clk_disable/enable.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/clk/qcom/gcc-msm8996.c | 4
1 file chan
There are two QUSB2 PHYs present on sdm845. In order
to improve eye diagram for both the PHYs some parameters
need to be changed. Provide device tree properties to
override these from board specific device tree files.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qu
vek Gautam <vivek.gau...@codeaurora.org>
Reviewed-by: Evan Green <evgr...@chromium.org>
Cc: stable <sta...@vger.kernel.org> # 4.14+
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 4
1 file changed, 4 insertions(+)
diff --g
e wouldn't be any user of same.
Reviewed-by: Rob Herring <r...@kernel.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/binding
as earlier added for
sdm845 only.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
.../devicetree/bindings/phy/qcom-qusb2-phy.txt| 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
Hi,
On 3/19/2018 11:21 PM, Evan Green wrote:
> Hi Manu,
>
> On Fri, Mar 16, 2018 at 2:46 AM Manu Gautam <mgau...@codeaurora.org> wrote:
[snip]
>> index d1c6905..5d78d43 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
>> +++ b/drivers/phy/qualcomm/p
Hi,
On 3/20/2018 3:53 PM, Vivek Gautam wrote:
> Hi Manu,
>
>
> On 3/16/2018 3:14 PM, Manu Gautam wrote:
>> Update compatible strings for USB2 PHYs on sdm845.
>> There are two QUSB2 PHYs present on sdm845. Few PHY registers
>> programming is different for th
-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 6470c5d..73aa282 100644
--- a/drivers/phy/qualcomm/phy-qcom
vek Gautam <vivek.gau...@codeaurora.org>
Cc: stable <sta...@vger.kernel.org> # 4.14+
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/p
There are two QUSB2 PHYs present on sdm845. Update PHY
registers programming for both the PHYs related to
electrical parameters to improve eye diagram.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 39 +++
since v1:
- Updated qusb2 compatibility name as per comment from Vivek.
Manu Gautam (6):
phy: qcom-qmp: Enable pipe_clk before checking USB3 PHY_STATUS
phy: qcom-qusb2: Fix crash if nvmem cell not specified
dt-bindings: phy-qcom-qmp: Update bindings for sdm845
phy: qcom-qmp: Add QMP V3
Update compatible strings for USB3 PHYs on SDM845.
One is QMPv3 DisplayPort-USB combo PHY and other one
is USB UNI PHY which is single lane USB3 PHY without
DP capability.
Reviewed-by: Rob Herring <r...@kernel.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentatio
configuration.
Reviewed-by: Evan Green <evgr...@chromium.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 148
drivers/phy/qualcomm/phy-qcom-qmp.h | 5 ++
2 files changed, 153 insertions(+)
diff --g
Update compatible strings for USB2 PHYs on sdm845.
There are two QUSB2 PHYs present on sdm845. Few PHY registers
programming is different for these PHYs related to electrical
parameters, otherwise both are same.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devi
Hi Can,
On 3/21/2018 8:12 AM, c...@codeaurora.org wrote:
> On 2018-03-20 19:30, Can Guo wrote:
>> Add UFS PHY support to make SDM845 UFS work with common PHY framework.
>>
>> Signed-off-by: Can Guo
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp.c | 120
>>
Update compatible strings for USB2 PHYs on sdm845.
There are two QUSB2 PHYs present on sdm845. Few PHY registers
programming is different for these PHYs related to electrical
parameters, otherwise both are same.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devi
since v2:
- Use separate phy_ops for USB to not register power_on op.
- And other minor changes as per review comments from Stephen.
Changes since v1:
- Updated qusb2 compatibility name as per comment from Vivek.
Manu Gautam (6):
phy: qcom-qmp: Enable pipe_clk before checking USB3 PHY_STATUS
configuration.
Reviewed-by: Evan Green <evgr...@chromium.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 148
drivers/phy/qualcomm/phy-qcom-qmp.h | 5 ++
2 files changed, 153 insertions(+)
diff --g
-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 6470c5d..5d8df6a
vek Gautam <vivek.gau...@codeaurora.org>
Cc: stable <sta...@vger.kernel.org> # 4.14+
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/p
Update compatible strings for USB3 PHYs on SDM845.
One is QMPv3 DisplayPort-USB combo PHY and other one
is USB UNI PHY which is single lane USB3 PHY without
DP capability.
Reviewed-by: Rob Herring <r...@kernel.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentatio
There are two QUSB2 PHYs present on sdm845. Update PHY
registers programming for both the PHYs related to
electrical parameters to improve eye diagram.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 39 +++
Hi Stephen,
On 3/23/2018 12:13 AM, Stephen Boyd wrote:
> Quoting Manu Gautam (2018-03-22 01:50:41)
>> QMP PHY for USB mode requires pipe_clk for calibration and PLL lock
>> to take place. This lock is output from PHY to GCC clock_ctl and then
> s/lock/clock/
Yes, will fix
phy_init() and phy_exit() calls, and phy_power_on() and
phy_power_off() already accept NULL as valid PHY reference
and act as NOP. Extend same concept to phy runtime_pm APIs
to keep drivers (e.g. dwc3) code simple while dealing with
optional PHYs.
Signed-off-by: Manu Gautam <m
Hi,
On 3/18/2018 6:22 PM, Rob Herring wrote:
> On Fri, Mar 16, 2018 at 03:14:58PM +0530, Manu Gautam wrote:
>> Update compatible strings for USB2 PHYs on sdm845.
>> There are two QUSB2 PHYs present on sdm845. Few PHY registers
>> programming is different for these PHYs
Hi,
On 3/18/2018 6:19 PM, Rob Herring wrote:
> On Tue, Mar 13, 2018 at 04:06:00PM +0530, Manu Gautam wrote:
>> Existing documentation has lot of incorrect information as it
>> was originally added for a driver that no longer exists.
>>
>> Signed-off-by: Manu Gau
Hi,
On 6/19/2018 2:06 PM, Can Guo wrote:
> +static int qcom_qmp_phy_poweron(struct phy *phy)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qmp->cfg;
> + void __iomem *pcs = qphy->pcs;
> + void
+---
> 1 file changed, 12 insertions(+), 7 deletions(-)
Reviewed-by: Manu Gautam
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
++---
> 1 file changed, 14 insertions(+), 11 deletions(-)
Reviewed-by: Manu Gautam
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Tune1 register on sdm845 is used to update HSTX_TRIM with fused
setting. Enable same by specifying update_tune1_with_efuse flag
for sdm845, otherwise driver ends up programming tune2 register.
Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845")
Signed-off-by: M
Fix HSTX_TRIM tuning logic which instead of using fused value
as HSTX_TRIM, incorrectly performs bitwise OR operation with
existing default value.
Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
Signed-off-by: Manu Gautam
Reviewed-by: Dougla
Correct address for pcs_misc register region of USB3 QMP UNI PHY.
These registers are used during runtime-suspend/resume routines
of phy.
Fixes: ca4db2b538a1 ("arm64: dts: qcom: sdm845: Add USB-related nodes")
Signed-off-by: Manu Gautam
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2
performs bitwise OR
operation with existing default value.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index
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