On Wednesday 14 October 2009 17:48:39 ext e...@gmx.de wrote:
Mem clock is both times 166MHz. I don't know whether are differences in
cycle access and timing, but memclock is fine.
Following Siarhei hints of initialize the buffers (around 1.2 MByte
each)
I get different results in
Mem clock is both times 166MHz. I don't know whether are differences in cycle
access and timing, but memclock is fine.
Following Siarhei hints of initialize the buffers (around 1.2 MByte each)
I get different results in 22kernel for use of
malloc alone
memcpy = 473.764, loop4 = 448.430,
Mem clock is both times 166MHz. I don't know whether are differences in
cycle
access and timing, but memclock is fine.
How did you physically verify this?
Oszi show 166MHz, also the kernel message about freq are in both kernels the
same.
Following Siarhei hints of initialize the
Can you upgrade to a newer u-boot? Either from the PSP release
OR u-boot tree hosted at git.denx.de (atleast 2009.03)?
Also, it will be good to see the sample program you are using.
~sanjeev
There is no newer u-boot from TI available. There is a SDK 02.01.03.11
but it contains the
The L2 cache is set and running.
I don't know - can it be configured or misconfigured somehow?
I just checked the output of 2.6.22 kernel and get these lines (which I don't
have in newer kernels):
CPU0: D VIPT write-through cache
CPU0: cache: 768 bytes, associativity 1, 8 byte lines, 64 sets
Linux version 2.6.31 (s...@localhost) (gcc version 4.3.3 (Sourcery G++ Lite
2009q1-203) ) #1 Mon Oct 12 08:30:58 CEST 2009
CPU: ARMv7 Processor [411fc082] revision 2 (ARMv7), cr=10c53c7f
CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
Machine: OMAP3 EVM
Memory policy: ECC
