rt
Changes in v2:
- Keep author name list no changed (Jingoo)
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4: None
Changes in v3
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
from exynos_dp code, and rephrase reasonable commit
2Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
directly, but we can take those a
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Correct the misspell in commit message. (Krzysztof)
Changes in v4:
- Separate all DTS changes to a separate patch. (Krzysztof)
Changes in v3
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
numbers in the example
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
Changes
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Remove "reg" D
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v5:
- Fix compiled error (Heiko)
- Using the connector display info
;;
clock-names = "24m";
#phy-cells = <0>;
};
Signed-off-by: Yakir Yang
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
elemets in documen
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge
: Yakir Yang
---
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool" to get backword timing values, but that interfa
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
flag. (Thierry)
Changes in
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Chan
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.
Changes in v3:
- m
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in .get_modes function
Hi Krzysztof,
On 09/30/2015 01:17 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:29, Yakir Yang wrote:
Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.
Beside the new analogix_dp driver
Hi Krzysztof,
On 09/30/2015 01:22 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:34, Yakir Yang wrote:
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Resequence
Hi Krzysztof,
On 09/30/2015 01:39 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:43, Yakir Yang wrote:
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from
Hi Krzysztof,
On 09/30/2015 04:26 PM, Krzysztof Kozlowski wrote:
On 30.09.2015 17:20, Yakir Yang wrote:
Hi Krzysztof,
On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
On 30.09.2015 16:19, Yakir Yang wrote:
Hi Krzysztof,
On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16
Hi all,
Friendly ping. :)
Best regards,
- Yakir
On 09/22/2015 03:20 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288
Hi Javier,
On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 08:25 AM, Yakir Yang wrote:
Hi all,
Friendly ping. :)
Best regards,
- Yakir
Do you have a tree that I can use to test these patches?
Wow, thanks a lot, I do have a tree on github
Hi Javier,
On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 01:05 PM, Yakir Yang wrote:
Hi Javier,
On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 11:02 AM, Yakir Yang wrote:
Hi Javier,
On 10/07/2015 04:46 PM, Javier
Hi Javier,
On 10/08/2015 08:40 AM, Yakir Yang wrote:
On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
On 10/07/2015 01:05 PM, Yakir Yang wrote:
On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
On 10/07/2015 11:02 AM, Yakir Yang wrote:
On 10/07/2015 04:46 PM, Javier Martinez
due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i2c(...
...);
+ retval =
+ exynos_dp_read_bytes_from_i2c(..);
- G
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v6:
- Fix the wrong code in previous series
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool" to get backword timing valu
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Yakir Yang
---
Changes in v6:
- Fix Peach Pit hpd property name error:
- hpd-gpio = <&gpx2 6 0>;
+ hpd-gpios =
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Remove
;;
clock-names = "24m";
#phy-cells = <0>;
};
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Fix compiled error (Heiko)
- Using the
2Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
directly, but w
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
flag
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit me
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Chan
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup
On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 09:37, Yakir Yang wrote:
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video
On 10/12/2015 11:51 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 11:43, Yakir Yang wrote:
On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 09:37, Yakir Yang wrote:
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be
: Yakir Yang
---
*just add a note that this is v7 of only fifth patch.*
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avoid -EOVERFLOW error (Krzysztof)
On 10/12/2015 02:54 PM, Krzysztof Kozlowski wrote:
On 12.10.2015 13:29, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT
Hi Kishon
On 10/12/2015 11:02 PM, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on
Hi Kishon,
On 10/13/2015 06:28 AM, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
This phy driver is binded with the Rockchip DisplayPort
driver, here are the brief properties:
edp_phy: edp-phy@ff770274 {
compatible
Hi Javierm
On 10/13/2015 05:21 PM, Javier Martinez Canillas wrote:
Hello Yakir,
Sorry for the delay but I was on holidays.
On 10/10/2015 04:31 PM, Yakir Yang wrote:
Hi Javier,
[snip]
Maybe you can email me the method the run mainline kernel on Peach
Pit, so I can debug the analogix_dp
Hi Javier,
On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/10/2015 05:35 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge
Hi Javier,
On 10/20/2015 05:48 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/20/2015 04:10 AM, Yakir Yang wrote:
Hi Javier,
On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/10/2015 05:35 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP
sspell
- Improved commit message more readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i2c(...
...);
+ retval =
+ exynos_dp_read_bytes_from_i2c(..);
- Get panel node with remote-endpoi
: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avoid -EOVERFLOW er
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
2Gbps, 2.7Gbps, 5.4Gbps}.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shou
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6:
- Fix Peach Pit hpd property name error:
- hpd
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- Remove the empty
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6:
- Simply the commit message. (Kishon)
- Symmetrical enable/disbale the phy
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- Split binding doc's from d
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- Fix compiled error (Heiko
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Tested-by: Javier Martinez Canillas
Signed-off
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable
Add dt binding documentation for rockchip display port PHY.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correc
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
C
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes
On 10/28/2015 05:23 AM, Heiko Stuebner wrote:
Am Samstag, 24. Oktober 2015, 11:06:04 schrieb Yakir Yang:
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
On 10/28/2015 05:23 AM, Heiko Stuebner wrote:
Am Samstag, 24. Oktober 2015, 11:06:04 schrieb Yakir Yang:
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avo
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6:
- Fix Peach Pit hpd property name
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5
rse support
Changes in v2:
- Keep author name list no changed (Jingoo)
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_fr
2Gbps, 2.7Gbps, 5.4Gbps}.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rat
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Modify the commit subject name. (Heiko)
Changes in v7: None
Changes in v6: None
Add dt binding documentation for rockchip display port PHY.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Remove the specific address in the example node name. (Heiko)
Changes in v7:
- Simplify the commit message. (Kishon)
Changes in v6: None
Changes in v5
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Fix the mixed spacers on macro definitions. (Heiko)
- Remove the unnecessary empty line after
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Fix
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
C
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v9:
- Removed the unused the variable "res" in probe function. (Heiko)
- Removed the unused
anillas
Signed-off-by: Yakir Yang
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
hpd when hpd detect failed.
Changes in v2: No
On 10/31/2015 12:42 AM, Rob Herring wrote:
On Wed, Oct 28, 2015 at 3:31 AM, Yakir Yang wrote:
Add dt binding documentation for rockchip display port PHY.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Thanks,
- Yakir
---
Changes in v8:
- Remove the
Hi Rob,
On 10/31/2015 12:46 AM, Rob Herring wrote:
On Wed, Oct 28, 2015 at 3:28 AM, Yakir Yang wrote:
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
---
Changes in v9:
- Document more details for 'ports' property
On 10/31/2015 02:30 PM, Yakir Yang wrote:
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
Sorry about the duplicate
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v10:
- Removed the duplicated signed-of.
Changes in v9:
- Document more details for
On 11/01/2015 02:37 AM, Rob Herring wrote:
On Sat, Oct 31, 2015 at 1:42 AM, Yakir Yang wrote:
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
Hi Brain,
On 11/03/2015 12:38 PM, Brian Norris wrote:
Hi Yakir,
On Thu, Oct 29, 2015 at 09:58:38AM +0800, Yakir Yang wrote:
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir
Hi Brian,
Thank you for debugging, and fell sorry for the delay reply
On 11/06/2015 07:45 AM, Brian Norris wrote:
Hi,
A few updates:
On Tue, Nov 03, 2015 at 05:13:48PM -0800, Brian Norris wrote:
On Wed, Nov 04, 2015 at 08:48:38AM +0800, Yakir Yang wrote:
On 11/03/2015 12:38 PM, Brian
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v10:
- Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK (Brian)
BIT(4) -> BIT
thout new changes but rebased on the latest kernel again and
again. If you thought those patches is fine, it would be very grateful to
give some ACKs to those changes.
Thanks,
- Yakir
On 10/28/2015 04:15 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP cont
atchwork.kernel.org/patch/7279801
[Rebased on] Vladimir Zapolskiy: https://patchwork.kernel.org/patch/7279801
Thanks
- Yakir
Sean Paul (1):
drm: Add Content Protection properties to drm
Yakir Yang (1):
drm: bridgw/dw_hdmi: add basic hdmi hdcp driver
drivers/gpu/d
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