On Fri, 2016-04-01 at 00:22 -0300, Thiago Jung Bauermann wrote:
> In the ppc64 big endian ABI, function symbols point to function
> descriptors. The symbols which point to the function entry points
> have a dot in front of the function name. Consequently, when the
> ftrace filter mechanism searche
Hello, Waiman
On 2016年04月13日 23:53, Waiman Long wrote:
> On 04/13/2016 07:15 AM, Pan Xinhui wrote:
>> Hello Peter,
>>
>> On 2016年04月12日 22:30, Peter Zijlstra wrote:
>>
I am working on the qspinlock implementation on PPC.
Your and Waiman's patches are so nice. :)
>>> Thanks!, last time I
On Thu, 14 Apr 2016 17:11:35 +1000
Michael Ellerman wrote:
> >
> > diff --git a/arch/powerpc/include/asm/ftrace.h
> > b/arch/powerpc/include/asm/ftrace.h
> > index 50ca7585abe2..68f1858796c6 100644
> > --- a/arch/powerpc/include/asm/ftrace.h
> > +++ b/arch/powerpc/include/asm/ftrace.h
> > @@ -58
On Wed, 13 Apr 2016, Michael Ellerman wrote:
> When livepatch tries to patch a function it takes the function address
> and asks ftrace to install the livepatch handler at that location.
> ftrace will look for an mcount call site at that exact address.
>
> On powerpc the mcount location is not th
On Wed, 13 Apr 2016, Michael Ellerman wrote:
> Add the powerpc specific livepatch definitions. In particular we provide
> a non-default implementation of klp_get_ftrace_location().
>
> This is required because the location of the mcount call is not constant
> when using -mprofile-kernel (which we
On Thu, 14 Apr 2016, Miroslav Benes wrote:
> On Wed, 13 Apr 2016, Michael Ellerman wrote:
>
> > Add the powerpc specific livepatch definitions. In particular we provide
> > a non-default implementation of klp_get_ftrace_location().
> >
> > This is required because the location of the mcount call
On Thu, Apr 14, 2016 at 04:49:50PM +1000, Michael Ellerman wrote:
> On Wed, 2016-04-13 at 15:22 +0200, Jiri Kosina wrote:
> > On Wed, 13 Apr 2016, Miroslav Benes wrote:
> > > > This series adds live patching support for powerpc (ppc64le only ATM).
> > > >
> > > > It's unchanged since the version I
On Thu, 2016-04-14 at 14:01 +0200, Miroslav Benes wrote:
> On Wed, 13 Apr 2016, Michael Ellerman wrote:
> > diff --git a/kernel/livepatch/core.c b/kernel/livepatch/core.c
> > index d68fbf63b083..b0476bb30f92 100644
> > --- a/kernel/livepatch/core.c
> > +++ b/kernel/livepatch/core.c
> > @@ -298,6 +2
On Thu, 2016-04-14 at 14:57 +0200, Torsten Duwe wrote:
> On Thu, Apr 14, 2016 at 04:49:50PM +1000, Michael Ellerman wrote:
> > On Wed, 2016-04-13 at 15:22 +0200, Jiri Kosina wrote:
> > > On Wed, 13 Apr 2016, Miroslav Benes wrote:
> > > > > This series adds live patching support for powerpc (ppc64le
On Thu, 2016-04-14 at 14:23 +0200, Miroslav Benes wrote:
> On Thu, 14 Apr 2016, Miroslav Benes wrote:
> > On Wed, 13 Apr 2016, Michael Ellerman wrote:
> > > diff --git a/arch/powerpc/include/asm/livepatch.h
> > > b/arch/powerpc/include/asm/livepatch.h
> > > new file mode 100644
> > > index 000
On Wed, 13 Apr 2016, Jessica Yu wrote:
> +++ Miroslav Benes [13/04/16 15:01 +0200]:
> > On Wed, 13 Apr 2016, Michael Ellerman wrote:
> >
> > > This series adds live patching support for powerpc (ppc64le only ATM).
> > >
> > > It's unchanged since the version I posted on March 24, with the except
On Thu, 14 Apr 2016, Michael Ellerman wrote:
> On Thu, 2016-04-14 at 14:01 +0200, Miroslav Benes wrote:
> > On Wed, 13 Apr 2016, Michael Ellerman wrote:
>
> > > static void klp_disable_func(struct klp_func *func)
> > > {
> > > struct klp_ops *ops;
> > > @@ -312,8 +325,14 @@ static void kl
On Thu, 14 Apr 2016, Torsten Duwe wrote:
> > > > > It's unchanged since the version I posted on March 24, with the
> > > > > exception that
> > > > > I've dropped the first patch, which was a testing-only patch.
>
> Confirmed. And it still works on top of 4.6-rc3, even with the
> additional tes
On Thu, Apr 14, 2016 at 11:08:02PM +1000, Michael Ellerman wrote:
> On Thu, 2016-04-14 at 14:57 +0200, Torsten Duwe wrote:
>
> > FTR: then I still have a few ppc64 hunks floating around to support certain
> > consistency
> > models...
>
> OK. I'm not quite sure what you mean but post them and we
Hi Balbir,
On 04/14/2016 11:10 AM, Balbir Singh wrote:
On 13/04/16 04:06, Akshay Adiga wrote:
This patch brings down global pstate at a slower rate than the local
pstate. As the frequency transition latency from pmin to pmax is
observed to be in few millisecond granurality. It takes a performa
On Thu, Apr 14, 2016 at 05:20:29PM +0200, Torsten Duwe wrote:
> On Thu, Apr 14, 2016 at 11:08:02PM +1000, Michael Ellerman wrote:
> > On Thu, 2016-04-14 at 14:57 +0200, Torsten Duwe wrote:
> >
> > > FTR: then I still have a few ppc64 hunks floating around to support
> > > certain consistency
> >
> I'm not sure that works on processes before power8.
>
> There DSCR SPR number 0x11 will always trap and emulate from userspace
> (see arch/powerpc/kernel/traps.c:emulate_instruction()). That is not
> controlled by FSCR and should work on POWER7 where FSCR is not
> present. We need to set the in
+++ Miroslav Benes [14/04/16 15:28 +0200]:
On Wed, 13 Apr 2016, Jessica Yu wrote:
+++ Miroslav Benes [13/04/16 15:01 +0200]:
> On Wed, 13 Apr 2016, Michael Ellerman wrote:
>
> > This series adds live patching support for powerpc (ppc64le only ATM).
> >
> > It's unchanged since the version I pos
On Wed, Jan 27, 2016 at 09:35:46AM +0100, Peter Zijlstra wrote:
> On Tue, Jan 26, 2016 at 12:11:43PM -0800, Paul E. McKenney wrote:
> > So Peter, would you like to update your patch to include yourself
> > and Will as authors?
>
> Sure, here goes.
>
> ---
> Subject: documentation: Add disclaimer
On Wed, Jan 27, 2016 at 02:57:07PM +, David Howells wrote:
> Peter Zijlstra wrote:
>
> > +==
> > +DISCLAIMER
> > +==
> > +
> > +This document is not a specification; it is intentionally (for the sake of
> > +brevity) and unintentionally (due to being human) incomplete. This
>
The domain/PHB field of PCI addresses has its value obtained from a
global variable, incremented each time a new domain (represented by
struct pci_controller) is added on the system. The domain addition
process happens during boot or due to PCI device hotplug.
As recent kernels are using predictab
Hi Raghav,
Are we planning to send a new version of this patch? Btw, I see that
the current patch covers NOR/GPCM related registers, but the driver is
only built when IFC NAND is enabled right now. Do we want to change
the Kconfig to make it not depending on NAND?
Regards,
Leo
On Wed, Feb 17,
On Thu, 2016-04-14 at 13:39 -0500, Jack Miller wrote:
> > I'm not sure that works on processes before power8.
> >
> > There DSCR SPR number 0x11 will always trap and emulate from userspace
> > (see arch/powerpc/kernel/traps.c:emulate_instruction()). That is not
> > controlled by FSCR and should
Am Donnerstag, 14 April 2016, 06:58:05 schrieb Steven Rostedt:
> On Thu, 14 Apr 2016 17:11:35 +1000
>
> Michael Ellerman wrote:
> > Presumably Steve will have a preference for which style you use.
>
> Actually, what I usually do is simply make a "weak" stub function and
> let the arch override i
Hi Gavin,
I was reading through this to understand how it all works and noticed a couple
of things, comments below.
- Alistair
On Wed, 17 Feb 2016 14:44:28 Gavin Shan wrote:
> +
> +static void pnv_php_handle_poweron(struct pnv_php_slot *php_slot)
> +{
> + void *fdt, *fdt1, *dt;
> + in
On 04/14/2016 11:40 AM, David Gibson wrote:
On Fri, Apr 08, 2016 at 04:36:44PM +1000, Alexey Kardashevskiy wrote:
When SRIOV is disabled, the existing code presumes there is no
virtual function (VF) in use and destroys all associated PEs.
However it is possible to get into the situation when the
On Fri, Apr 15, 2016 at 10:47:52AM +1000, Alistair Popple wrote:
>Hi Gavin,
>
>I was reading through this to understand how it all works and noticed a couple
>of things, comments below.
>
Alistair, thanks for your time on review.
>
>On Wed, 17 Feb 2016 14:44:28 Gavin Shan wrote:
>
>
>
>> +
>> +st
The real LE feature entry in the ibm_pa_feature struct has the
wrong number of elements. Instead of checking for byte 5, bit 0,
we check for byte 0, bit 0, and we also incorrectly update cpu user
feature bit 5.
Fixes: 44ae3ab3358e ("powerpc: Free up some CPU feature bits by moving out
MMU-related
scan_features() updates cpu_user_features but not cpu_user_features2.
Amongst other things, cpu_user_features2 contains the user TM feature
bits which we must keep in sync with the kernel TM feature bit.
Signed-off-by: Anton Blanchard
Cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/prom.c |
We need to update the user TM feature bits (PPC_FEATURE2_HTM and
PPC_FEATURE2_HTM) to mirror what we do with the kernel TM feature
bit.
At the moment, if firmware reports TM is not available we turn off
the kernel TM feature bit but leave the userspace ones on. Userspace
thinks it can execute TM i
On Fri, Apr 15, 2016 at 11:29:32AM +1000, Alexey Kardashevskiy wrote:
> On 04/14/2016 11:40 AM, David Gibson wrote:
> >On Fri, Apr 08, 2016 at 04:36:44PM +1000, Alexey Kardashevskiy wrote:
> >>When SRIOV is disabled, the existing code presumes there is no
> >>virtual function (VF) in use and destro
The frequency transition latency from pmin to pmax is observed to be in few
millisecond granurality. And it usually happens to take a performance penalty
during sudden frequency rampup requests.
This patch set solves this problem by using a chip-level entity called "global
pstates". Global pstate
From: Shilpasri G Bhat
commit 1b0289848d5d ("cpufreq: powernv: Add sysfs attributes to show
throttle stats") used policy->driver_data as a flag for one-time creation
of throttle sysfs files. Instead of this use 'kernfs_find_and_get()' to
check if the attribute already exists. This is required as
The frequency transition latency from pmin to pmax is observed to be in
few millisecond granurality. And it usually happens to take a performance
penalty during sudden frequency rampup requests.
This patch set solves this problem by using an entity called "global
pstates". The global pstate is a C
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