So,if we're talk about address...
EA0 is actually bit 63 for any kernel address. This means[1] the
effective address is
the real address ( the physical address), because MSR_HV=1.
1. What does it mean PA=EA ? How does the translation work now ?
2. in interrupts, the program counter is set to EA 0c0
Hi Raz,
On 10/04/2018 04:41 AM, Raz wrote:
Frankly, the more I read the more perplexed I get. For example,
according to BOOK III-S, chapter 3,
the MSR bits are differ from the ones described in
arch/powerpc/include/asm/reg.h.
Bit zero, is LE, but in the book it is 64-bit mode.
Would someone be
On Mon, Oct 08, 2018 at 07:44:12PM +0300, Raz wrote:
> Both systemsim and my powerpc server boots with MSR_HV=1, i.e, hypervisor
> state.
> Is there away to fix that ? writing to the MSR cannot work according
> the documentation ( and reality ).
But that is what you do: you write HV=0 in MSR. Af
Both systemsim and my powerpc server boots with MSR_HV=1, i.e, hypervisor state.
Is there away to fix that ? writing to the MSR cannot work according
the documentation ( and reality ).
On Sat, Oct 6, 2018 at 3:27 PM Segher Boessenkool
wrote:
>
> On Sat, Oct 06, 2018 at 12:19:45PM +0300, Raz wro
On Sat, Oct 06, 2018 at 12:19:45PM +0300, Raz wrote:
> Hey
> How does HVSC works ?
> I looked in the code and LoPAR documentation. It looks like there is
> vector called
> system_call_pSeries ( at 0xc00 ) that is supposed to be called when we
> invoke HVSC from kernel
> mode.
> Now, I wrote a NULL
Hey
How does HVSC works ?
I looked in the code and LoPAR documentation. It looks like there is
vector called
system_call_pSeries ( at 0xc00 ) that is supposed to be called when we
invoke HVSC from kernel
mode.
Now, I wrote a NULL call HSVC and patched the exceptions-64s.S to
return RFID immediately
On Thu, Oct 04, 2018 at 10:41:13AM +0300, Raz wrote:
> Frankly, the more I read the more perplexed I get. For example,
> according to BOOK III-S, chapter 3,
> the MSR bits are differ from the ones described in
> arch/powerpc/include/asm/reg.h.
> Bit zero, is LE, but in the book it is 64-bit mode.
On Thu, Oct 04, 2018 at 10:41:13AM +0300, Raz wrote:
> Frankly, the more I read the more perplexed I get. For example,
> according to BOOK III-S, chapter 3,
> the MSR bits are differ from the ones described in
> arch/powerpc/include/asm/reg.h.
> Bit zero, is LE, but in the book it is 64-bit mode.
Frankly, the more I read the more perplexed I get. For example,
according to BOOK III-S, chapter 3,
the MSR bits are differ from the ones described in
arch/powerpc/include/asm/reg.h.
Bit zero, is LE, but in the book it is 64-bit mode.
Would someone be kind to explain what I do not understand?
Tha
Raz writes:
> Hello
>
> I want to learn about powerpc architecture, mainly hypervisor and
> partioning. I download the books (1,2, and 3 ) but I feel it lacks
> a lot of information. Are there other books ?
The ISA describes how the CPU works to allow you to implement a
hypervisor, but it doesn
On Sun, Sep 30, 2018 at 10:05:01AM +0300, Raz wrote:
> First, thank you.
> And another question, is there a development environment that
> resembles Fixed Virtual Platform for ARM ( FVP ARM) ?
I don't know FVP, but that seems similar to systemsim?
https://www14.software.ibm.com/webapp/set2/sas/f/p
First, thank you.
And another question, is there a development environment that
resembles Fixed Virtual Platform for ARM ( FVP ARM) ?
On Sun, Sep 30, 2018 at 1:13 AM Segher Boessenkool
wrote:
>
> Hi Raz,
>
> On Sun, Sep 30, 2018 at 12:24:35AM +0300, Raz wrote:
> > I want to learn about powerp
Hi Raz,
On Sun, Sep 30, 2018 at 12:24:35AM +0300, Raz wrote:
> I want to learn about powerpc architecture, mainly hypervisor and
> partioning. I download the books (1,2, and 3 ) but I feel it lacks
> a lot of information. Are there other books ?
I suspect you are looking at an ancient version of
Hello
I want to learn about powerpc architecture, mainly hypervisor and
partioning. I download the books (1,2, and 3 ) but I feel it lacks
a lot of information. Are there other books ?
Kind regards
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