Re: [Mesa-dev] [PATCH v2 08/20] i965/fs: Add emit_cs_terminate to emit CS_OPCODE_CS_TERMINATE

On 2015-04-24 23:11:13, Kenneth Graunke wrote: > On Friday, April 24, 2015 04:33:00 PM Jordan Justen wrote: > > v2: > > * Do more work at the visitor level. g0 is loaded and sent to the > >generator now. > > > > Signed-off-by: Jordan Justen > > --- > > src/mesa/drivers/dri/i965/brw_fs.h

Re: [Mesa-dev] [PATCH v2 11/20] i965/cs: Add brw_cs_prog_data, brw_cs_prog_key and brw_context::cs.

On Friday, April 24, 2015 04:33:03 PM Jordan Justen wrote: > From: Paul Berry > > jordan.l.jus...@intel.com: > * Added brw_cs_prog_key structure > * Added brw_cs_prog_data::dispatch_grf_start_reg_16 > * Added brw_cs_prog_data::no_8 > * Added brw_cs_prog_data::local_size > * Added brw_cs_prog

Re: [Mesa-dev] [PATCH v2 19/20] i965/cs: Upload brw_cs_state

On Friday, April 24, 2015 04:33:11 PM Jordan Justen wrote: > Signed-off-by: Jordan Justen > --- > src/mesa/drivers/dri/i965/brw_cs.cpp | 80 > > src/mesa/drivers/dri/i965/brw_defines.h | 3 ++ > src/mesa/drivers/dri/i965/brw_state.h| 1 + > src

Re: [Mesa-dev] [PATCH v2 18/20] i965: Remove comment about chv device numbers relating to hsw gt1

On Friday, April 24, 2015 04:33:10 PM Jordan Justen wrote: > Remove comment "These were copied from Haswell GT1, above.". Many of > these numbers have been modified by this point, so the HSW GT1 > reference no longer seems helpful. > > The comment "Thread counts and URB limits are placeholders, an

Re: [Mesa-dev] [PATCH v2 08/20] i965/fs: Add emit_cs_terminate to emit CS_OPCODE_CS_TERMINATE

On Friday, April 24, 2015 04:33:00 PM Jordan Justen wrote: > v2: > * Do more work at the visitor level. g0 is loaded and sent to the >generator now. > > Signed-off-by: Jordan Justen > --- > src/mesa/drivers/dri/i965/brw_fs.h | 1 + > src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |

Re: [Mesa-dev] [RFC 6/9] nir: Add an entirely C-based linked list implementation

On Apr 24, 2015 4:46 PM, "Rob Clark" wrote: > > On Fri, Apr 24, 2015 at 7:32 PM, Jason Ekstrand wrote: > > This commit adds a C-based linked list implementation for NIR. Unlike > > exec_list in glsl/list.h, there is no C++ API. Also, this list is based on > > wl_list (from the Wayland project)

Re: [Mesa-dev] [PATCH] i965/fs: Strip trailing contant zeroes in sample messages

Kenneth Graunke writes: > I like this idea! > > We definitely need to skip this optimization on Gen4, since the Gen4/G45 > sampler infers the texturing opcode based on the message length. But > for Gen5+, it should be no problem. Ah ok, yes, I will add this. > Matt mentioned that we have to em

Re: [Mesa-dev] [PATCH] i965/fs: Strip trailing contant zeroes in sample messages

On Fri, Apr 24, 2015 at 5:15 PM, Neil Roberts wrote: > Matt Turner writes: > >>> + foreach_block_and_inst(block, fs_inst, inst, cfg) { >>> + if ((inst->opcode == SHADER_OPCODE_TEX || >>> + inst->opcode == SHADER_OPCODE_TXF) && >>> + !inst->shadow_compare) { >>> +

Re: [Mesa-dev] [PATCH] i965/fs: Strip trailing contant zeroes in sample messages

Matt Turner writes: >> + foreach_block_and_inst(block, fs_inst, inst, cfg) { >> + if ((inst->opcode == SHADER_OPCODE_TEX || >> + inst->opcode == SHADER_OPCODE_TXF) && >> + !inst->shadow_compare) { >> + fs_inst *load_payload = (fs_inst *) inst->prev; >> + >> +

Re: [Mesa-dev] [PATCH V2 15/22] i965/gen9: Use _mesa_meta_pbo_TexSubImage to write to YF/YS surfaces

On Fri, Apr 24, 2015 at 05:12:34PM -0700, Anuj Phogat wrote: > On Fri, Apr 24, 2015 at 12:22 PM, Pohjolainen, Topi > wrote: > > On Fri, Apr 17, 2015 at 04:51:36PM -0700, Anuj Phogat wrote: > >> No other path currently supports uploading data to these surfaces. > >> > >> Signed-off-by: Anuj Phogat

Re: [Mesa-dev] [PATCH V2 15/22] i965/gen9: Use _mesa_meta_pbo_TexSubImage to write to YF/YS surfaces

On Fri, Apr 24, 2015 at 12:22 PM, Pohjolainen, Topi wrote: > On Fri, Apr 17, 2015 at 04:51:36PM -0700, Anuj Phogat wrote: >> No other path currently supports uploading data to these surfaces. >> >> Signed-off-by: Anuj Phogat >> --- >> src/mesa/drivers/dri/i965/intel_tex_image.c| 24 +

Re: [Mesa-dev] [RFC 6/9] nir: Add an entirely C-based linked list implementation

On Fri, Apr 24, 2015 at 7:32 PM, Jason Ekstrand wrote: > This commit adds a C-based linked list implementation for NIR. Unlike > exec_list in glsl/list.h, there is no C++ API. Also, this list is based on > wl_list (from the Wayland project) which is, in turn, based on the kernel > list. As such

[Mesa-dev] [PATCH] mesa: the function name appears to have a gl prefix already

Currently we're producing errors like User error: GL_INVALID_OPERATION in glglDeleteProgramsARB(invalid call) And noop_warn appears to be called with the full function name. Don't prepend a gl prefix. Signed-off-by: Ilia Mirkin --- src/mesa/main/context.c | 4 ++-- 1 file changed, 2 insertions

[Mesa-dev] [PATCH] i965: Upload atomic buffer state for compute shaders

Signed-off-by: Jordan Justen --- git://people.freedesktop.org/~jljusten/mesa i965-cs-atomic-counters-v1 src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_state.h| 1 + src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++ src/mesa/drivers/dr

[Mesa-dev] [PATCH 6/7] i965/cs: Implement brw_emit_gpgpu_walker

Tested on Ivybridge, Haswell and Broadwell. Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_compute.c | 39 - src/mesa/drivers/dri/i965/brw_defines.h | 1 + 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/br

[Mesa-dev] [PATCH 1/7] i965/cs: Emit state base address

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 7fd50f4

[Mesa-dev] [PATCH 4/7] i965: Implement DispatchCompute() back-end

From: Paul Berry brw_emit_gpgpu_walker will be implemented in a subsequent patch. Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_compute.c| 121 + src/mesa/drivers/dri/i965/brw_context.c| 1

[Mesa-dev] [PATCH 7/7] i965/cs: Emit MEDIA_STATE_FLUSH after WALKER

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_compute.c | 5 + src/mesa/drivers/dri/i965/brw_defines.h | 1 + 2 files changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_compute.c b/src/mesa/drivers/dri/i965/brw_compute.c index 06ef448..d41d68a 100644 --- a/

[Mesa-dev] [PATCH 2/7] mesa/cs: Add DispatchCompute() to driver function table.

From: Paul Berry Reviewed-by: Jordan Justen --- src/mesa/main/dd.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h index 0c1a13f..a329d9c 100644 --- a/src/mesa/main/dd.h +++ b/src/mesa/main/dd.h @@ -1005,6 +1005,13 @@ struct dd_function_table {

[Mesa-dev] [PATCH 5/7] i965/state: Emit pipeline select when changing pipelines

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_misc_state.c | 23 +-- src/mesa/drivers/dri/i965/brw_state.h| 12 src/mesa/drivers/dri/i965/brw_state_upload.c | 5 + 4 files change

[Mesa-dev] [PATCH 0/7] i965 DispatchCompute support

git://people.freedesktop.org/~jljusten/mesa i965-dispatch-compute-v1 Jordan Justen (4): i965/cs: Emit state base address i965/state: Emit pipeline select when changing pipelines i965/cs: Implement brw_emit_gpgpu_walker i965/cs: Emit MEDIA_STATE_FLUSH after WALKER Paul Berry (3): mesa/cs

[Mesa-dev] [PATCH 3/7] main/cs: Implement front end code for glDispatchCompute().

From: Paul Berry Reviewed-by: Jordan Justen --- src/mesa/main/compute.c | 20 +++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/src/mesa/main/compute.c b/src/mesa/main/compute.c index 575..37a4ba7 100644 --- a/src/mesa/main/compute.c +++ b/src/mesa/main/comp

Re: [Mesa-dev] [RFC 7/9] nir/nir: Use a linked list instead of a has set for use/def sets

On Fri, Apr 24, 2015 at 4:32 PM, Jason Ekstrand wrote: > This commit switches us from the current setup of using hash sets for > use/def sets to using linked lists. Doing so should save us quite a bit of > memory because we aren't carrying around 3 hash sets per register and 2 per > SSA value. I

[Mesa-dev] [PATCH v2 10/20] i965/cs: Add generator support for CS_OPCODE_CS_TERMINATE

v2: * Don't rely on brw_eu* to generate the send instruction. We now generate the send here, and drop the "i965/cs: Add support for the SEND message that terminates a CS thread" brw_eu* patch. Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_fs.h | 1 + src/mesa

[Mesa-dev] [PATCH v2 01/20] i965/cs: Add BRW_NEW_COMPUTE_PROGRAM state flag.

From: Paul Berry Also add code to brw_upload_state to set it when the compute program changes. Reviewed-by: Jordan Justen Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/brw_context.h | 3 +++ src/mesa/drivers/dri/i965/brw_state_upload.c | 6 ++ 2 files changed, 9 insert

[Mesa-dev] [PATCH v2 14/20] i965/cs: Add max_cs_threads

Add some values for gen7 & gen8. These are the number threads in a subslice. Signed-off-by: Jordan Justen Cc: Ben Widawsky Cc: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.c | 1 + src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_device_info.c

[Mesa-dev] [PATCH v2 20/20] i965/fs: Add CS shader time support

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.h | 3 +++ src/mesa/drivers/dri/i965/brw_cs.cpp| 8 src/mesa/drivers/dri/i965/brw_fs.cpp| 11 +++ src/mesa/drivers/dri/i965/brw_program.c | 13 +++-- 4 files changed, 33 insertions(+), 2 dele

[Mesa-dev] [PATCH v2 08/20] i965/fs: Add emit_cs_terminate to emit CS_OPCODE_CS_TERMINATE

v2: * Do more work at the visitor level. g0 is loaded and sent to the generator now. Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_fs.h | 1 + src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 19 +++ 2 files changed, 20 insertions(+) diff --git a/sr

[Mesa-dev] [PATCH v2 06/20] i965/cs: Add BRW_NEW_CS_PROG_DATA and BRW_CACHE_CS_PROG

Signed-off-by: Jordan Justen Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_state_dump.c | 3 +++ src/mesa/drivers/dri/i965/brw_state_upload.c | 1 + 3 files changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/

[Mesa-dev] [PATCH v2 04/20] mesa/cs: Add compute support to update_program().

From: Paul Berry Reviewed-by: Jordan Justen Reviewed-by: Kristian Høgsberg --- src/mesa/main/state.c | 21 + 1 file changed, 21 insertions(+) diff --git a/src/mesa/main/state.c b/src/mesa/main/state.c index cc84c61..99db37b 100644 --- a/src/mesa/main/state.c +++ b/src/mesa

Re: [Mesa-dev] [PATCH V2 14/22] i965/gen9: Set vertical and horizontal surface alignments

On Thu, Apr 23, 2015 at 6:05 PM, Pohjolainen, Topi wrote: > On Fri, Apr 17, 2015 at 04:51:35PM -0700, Anuj Phogat wrote: >> Patch sets the alignments for texture and renderbuffer surfaces. >> >> Signed-off-by: Anuj Phogat >> --- >> src/mesa/drivers/dri/i965/gen8_surface_state.c | 34 >>

[Mesa-dev] [PATCH v2 11/20] i965/cs: Add brw_cs_prog_data, brw_cs_prog_key and brw_context::cs.

From: Paul Berry jordan.l.jus...@intel.com: * Added brw_cs_prog_key structure * Added brw_cs_prog_data::dispatch_grf_start_reg_16 * Added brw_cs_prog_data::no_8 * Added brw_cs_prog_data::local_size * Added brw_cs_prog_data::simd_size Signed-off-by: Jordan Justen Reviewed-by: Kristian Høgsb

[Mesa-dev] [PATCH v2 00/20] i965 basic CS program generation support

git://people.freedesktop.org/~jljusten/mesa i965-cs-prog-v2 These patches could use review: * [08/20] i965/fs: Add emit_cs_terminate to emit CS_OPCODE_CS_TERMINATE * [10/20] i965/cs: Add generator support for CS_OPCODE_CS_TERMINATE * [13/20] i965/fs: Support compute programs in fs_visitor * [1

[Mesa-dev] [PATCH v2 02/20] mesa/cs: Add inline functions for dealing with compute shaders.

From: Paul Berry Reviewed-by: Jordan Justen Reviewed-by: Kristian Høgsberg --- src/mesa/program/program.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a/src/mesa/program/program.h b/src/mesa/program/program.h index 0b0d1ac..2d92ab2 100644 --- a/src/mesa/program/pro

[Mesa-dev] [PATCH v2 05/20] i965: Add an INTEL_DEBUG=cs option.

From: Paul Berry At the moment it's not wired up to anything. Later patches will hook it up to the compute shader back-end. Reviewed-by: Jordan Justen Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/intel_debug.c | 3 ++- src/mesa/drivers/dri/i965/intel_debug.h | 1 + 2 files ch

[Mesa-dev] [PATCH v2 17/20] i965/cs: Support CS program precompile

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.h | 6 ++ src/mesa/drivers/dri/i965/brw_cs.cpp | 28 src/mesa/drivers/dri/i965/brw_shader.cpp | 4 src/mesa/drivers/dri/i965/brw_shader.h | 3 +++ 4 files changed, 41 insertions(

[Mesa-dev] [PATCH v2 09/20] i965/cs: Mark g0 as used by CS_OPCODE_CS_TERMINATE

Signed-off-by: Jordan Justen Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 94e1a0a..582d099 10

[Mesa-dev] [PATCH v2 03/20] mesa/cs: Update program.c for compute shaders.

From: Paul Berry Reviewed-by: Jordan Justen Reviewed-by: Kristian Høgsberg --- src/mesa/program/program.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/program/program.c b/src/mesa/program/program.c index 4f28e2a..fb61f4d 100644 --- a/src/mesa/program/program.c +++ b/src/mesa

[Mesa-dev] [PATCH v2 07/20] i965/cs: Add CS_OPCODE_CS_TERMINATE

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_defines.h | 5 + src/mesa/drivers/dri/i965/brw_shader.cpp | 2 ++ 2 files changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index bd3218a..f6f8962 100644 ---

[Mesa-dev] [PATCH v2 15/20] i965/cs: Emit compute shader code and upload programs

v2: * Don't bother checking for 'gen > 5' (krh) * Populate sampler data in key (krh) Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_cs.cpp | 224 +++ src/mesa/drivers/dri/i965/brw_state_upload

[Mesa-dev] [PATCH v2 19/20] i965/cs: Upload brw_cs_state

Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_cs.cpp | 80 src/mesa/drivers/dri/i965/brw_defines.h | 3 ++ src/mesa/drivers/dri/i965/brw_state.h| 1 + src/mesa/drivers/dri/i965/brw_state_upload.c | 2 + 4 files changed, 86 inse

[Mesa-dev] [PATCH v2 13/20] i965/fs: Support compute programs in fs_visitor

v2: * Clean out some unneeded code copied from run_fs (krh) * Always use NIR * Split shader time out into a separate commit Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.c | 2 + src/mesa/drivers/dri/i965/brw_fs.cpp | 61 ++-- src

[Mesa-dev] [PATCH v2 16/20] i965: Add brw_setup_tex_for_precompile. Use in VS, GS & FS.

Suggested-by: Kristian Høgsberg Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_fs.cpp | 32 src/mesa/drivers/dri/i965/brw_fs.h | 3 +++ src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 + 3 files changed, 24 insertions(+), 24 deletio

[Mesa-dev] [PATCH v2 18/20] i965: Remove comment about chv device numbers relating to hsw gt1

Remove comment "These were copied from Haswell GT1, above.". Many of these numbers have been modified by this point, so the HSW GT1 reference no longer seems helpful. The comment "Thread counts and URB limits are placeholders, and may not be accurate." is retained for now. Signed-off-by: Jordan J

[Mesa-dev] [PATCH v2 12/20] i965/cache: Add support for CS in program state cache

Signed-off-by: Jordan Justen Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_cs.cpp| 48 + src/mesa/drivers/dri/i965/brw_cs.h | 2 ++ src/mesa/drivers/dri/i965/brw_state_cache.c |

[Mesa-dev] [RFC 9/9] SQUASH: nir: Update various components for the new list-based use/def sets

--- src/glsl/nir/nir_from_ssa.c | 11 +-- src/glsl/nir/nir_lower_locals_to_regs.c | 14 ++ src/glsl/nir/nir_lower_to_source_mods.c | 20 src/glsl/nir/nir_lower_vars_to_ssa.c| 3 ++- src/glsl/nir/nir_opt_gcm.c | 14 ++---

[Mesa-dev] [RFC 7/9] nir/nir: Use a linked list instead of a has set for use/def sets

This commit switches us from the current setup of using hash sets for use/def sets to using linked lists. Doing so should save us quite a bit of memory because we aren't carrying around 3 hash sets per register and 2 per SSA value. It should also save us CPU time because adding/removing things fr

[Mesa-dev] [RFC 3/9] nir: Add and use initializer #defines for nir_src and nir_dest

--- src/glsl/nir/glsl_to_nir.cpp | 2 +- src/glsl/nir/nir.h | 13 +++-- src/glsl/nir/nir_builder.h | 6 ++ src/glsl/nir/nir_lower_samplers.cpp| 5 ++--- src/glsl/nir/nir_lower_tex_projector.c | 5 ++--- src/glsl/nir/nir_search.c

[Mesa-dev] [RFC 0/9] Use linked lists for use/def sets in NIR

This patch series is an experiment that I ran this week to see what would happen if we used a linked list instead of a hash set for use/def sets in NIR. The first 5 patches are cleanups that we probably want anyway. The 6th adds a C-based linked list to NIR. The last 3, which need to be squashed

[Mesa-dev] [RFC 2/9] nir: Modernize the out-of-SSA pass

The out-of-SSA pass was one of the first passes written when getting SSA up-and-going (for obvious reasons). As such, it came before a lot of the nifty SSA-based helpers were introduced. This commit modernizes it so that we're no longer doing nearly as much manual banging on use/def sets. --- sr

[Mesa-dev] [RFC 6/9] nir: Add an entirely C-based linked list implementation

This commit adds a C-based linked list implementation for NIR. Unlike exec_list in glsl/list.h, there is no C++ API. Also, this list is based on wl_list (from the Wayland project) which is, in turn, based on the kernel list. As such, it should be fairly familiar to people who have done anything

[Mesa-dev] [RFC 5/9] nir: Use nir_instr_rewrite_src in copy propagation

We were rolling our own rewrite_src variant in copy-propagation. Let's stop doing that and use the ones in core NIR. --- src/glsl/nir/nir_opt_copy_propagate.c | 71 +-- 1 file changed, 10 insertions(+), 61 deletions(-) diff --git a/src/glsl/nir/nir_opt_copy_propag

[Mesa-dev] [RFC 8/9] SQUASH: nir: Add a helper for moving a source and use it in texture lowering

One of the side-effects of using a linked list for use/def sets is that you can no longer simply copy them around. There were a couple of places in the texture lowering passes that realloced or used memmove on lists of sources. Instead, this commit adds a helper for moving a source and uses it fo

[Mesa-dev] [RFC 1/9] nir/validate: Validate SSA def parent instructiosn

--- src/glsl/nir/nir_validate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/glsl/nir/nir_validate.c b/src/glsl/nir/nir_validate.c index a7aa798..35a853d 100644 --- a/src/glsl/nir/nir_validate.c +++ b/src/glsl/nir/nir_validate.c @@ -236,6 +236,8 @@ validate_ssa_def(nir_ssa_def *def, v

[Mesa-dev] [RFC 4/9] nir: Add a function for rewriting the condition of an if statement

--- src/glsl/nir/nir.c | 22 ++ src/glsl/nir/nir.h | 1 + 2 files changed, 23 insertions(+) diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c index 4cc074b..b8f5dd4 100644 --- a/src/glsl/nir/nir.c +++ b/src/glsl/nir/nir.c @@ -1895,6 +1895,28 @@ nir_instr_rewrite_src(nir_in

[Mesa-dev] [PATCH] st/mesa: update stencil surface if it comes from texture

Now that ARB_texture_stencil8 is supported, this might happen. Signed-off-by: Ilia Mirkin --- src/mesa/state_tracker/st_atom_framebuffer.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/state_tracker/st_atom_framebuffer.c b/src/mesa/state_tracker/st_atom_frameb

Re: [Mesa-dev] [PATCH V2 13/22] i965: Use BRW_SURFACE_* in place of GL_TEXTURE_*

On Thu, Apr 23, 2015 at 6:10 PM, Pohjolainen, Topi wrote: > On Fri, Apr 17, 2015 at 04:51:34PM -0700, Anuj Phogat wrote: >> Makes no functional changes in the code. >> >> Signed-off-by: Anuj Phogat >> Reviewed-by: Chris Forbes >> --- >> src/mesa/drivers/dri/i965/gen8_surface_state.c | 15 ++

Re: [Mesa-dev] [PATCH 12/13] i965: Add typed surface access opcodes.

"Pohjolainen, Topi" writes: > On Fri, Feb 27, 2015 at 05:34:55PM +0200, Francisco Jerez wrote: >> --- >> src/mesa/drivers/dri/i965/brw_defines.h| 4 + >> src/mesa/drivers/dri/i965/brw_eu.h | 24 +++ >> src/mesa/drivers/dri/i965/brw_eu_emit.c| 169 >> ++

[Mesa-dev] [Bug 90167] [softpipe] piglit depthstencil-default_fb-drawpixels-32f_24_8_rev regression

https://bugs.freedesktop.org/show_bug.cgi?id=90167 Bug ID: 90167 Summary: [softpipe] piglit depthstencil-default_fb-drawpixels-32f_24_8_rev regression Product: Mesa Version: git Hardware: x86-64 (AMD64)

Re: [Mesa-dev] [PATCH V2 12/22] i965: Rename use_linear_1d_layout() and make it global

On Fri, Apr 24, 2015 at 2:39 PM, Pohjolainen, Topi wrote: > On Fri, Apr 17, 2015 at 04:51:33PM -0700, Anuj Phogat wrote: >> This function will be utilised in later patches. >> >> Signed-off-by: Anuj Phogat >> --- >> src/mesa/drivers/dri/i965/brw_context.h| 4 >> src/mesa/drivers/dri/i9

Re: [Mesa-dev] [PATCH 16/16] st/nine: Rework texture data allocation

On Fri, Apr 24, 2015 at 6:13 PM, Axel Davy wrote: > Le 25/04/2015 00:02, Ilia Mirkin a écrit : >> >> >> I'm having trouble understanding what you're changing here... perhaps >> a better commit description could go a ways to clearing things up? >> Were you allocating it a level at a time before? Ho

Re: [Mesa-dev] [PATCH] i965: Fill out the rest of brw_debug_recompile_sampler_key().

On Thu, Apr 23, 2015 at 11:24:11PM -0700, Kenneth Graunke wrote: > This makes INTEL_DEBUG=perf report shader recompiles due to CMS vs. > UMS/IMS differences and Sandybridge textureGather workarounds. > > Previously, we just flagged them as "Something else". > > Signed-off-by: Kenneth Graunke Re

Re: [Mesa-dev] [PATCH 12/13] i965: Add typed surface access opcodes.

On Fri, Feb 27, 2015 at 05:34:55PM +0200, Francisco Jerez wrote: > --- > src/mesa/drivers/dri/i965/brw_defines.h| 4 + > src/mesa/drivers/dri/i965/brw_eu.h | 24 +++ > src/mesa/drivers/dri/i965/brw_eu_emit.c| 169 > + > src/mesa/drive

Re: [Mesa-dev] [PATCH V2 06/22] i965/gen9: Set tiled resource mode for the miptree

On Thu, Apr 23, 2015 at 4:51 PM, Pohjolainen, Topi wrote: > On Fri, Apr 17, 2015 at 04:51:27PM -0700, Anuj Phogat wrote: >> Signed-off-by: Anuj Phogat >> --- >> src/mesa/drivers/dri/i965/brw_tex_layout.c| 2 ++ >> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ++ >> 2 files changed,

Re: [Mesa-dev] [PATCH 16/16] st/nine: Rework texture data allocation

Le 25/04/2015 00:02, Ilia Mirkin a écrit : I'm having trouble understanding what you're changing here... perhaps a better commit description could go a ways to clearing things up? Were you allocating it a level at a time before? How did that work, I don't see a per-level structure... I'm guessin

[Mesa-dev] Mesa 10.5.4

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Mesa 10.5.4 is now available. This release includes fixes for the mesa state-tracker used by all the gallium drivers, a drirc workaround for Second Life, plus i965 fixes. For the Android users out there, this release includes many compilation fixes wit

Re: [Mesa-dev] [PATCH 16/16] st/nine: Rework texture data allocation

On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > Some applications assume the memory for multilevel > textures is allocated per continuous blocks. > > This patch implements that behaviour. > > Signed-off-by: Axel Davy > --- > src/gallium/state_trackers/nine/cubetexture9.c | 42 +++

Re: [Mesa-dev] [PATCH 15/16] st/nine: Fix update_vertex_elements bad rebase

Reviewed-by: Ilia Mirkin On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > This code was supposed to be removed, but a rebase seems to have > made it stay. > > Signed-off-by: Axel Davy > --- > src/gallium/state_trackers/nine/nine_state.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --g

Re: [Mesa-dev] [PATCH 14/16] st/nine: Add debug warning when application uses sw processing

Reviewed-by: Ilia Mirkin On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > Signed-off-by: Axel Davy > --- > src/gallium/state_trackers/nine/cubetexture9.c | 3 +++ > src/gallium/state_trackers/nine/device9.c| 5 + > src/gallium/state_trackers/nine/indexbuffer9.c | 14 ++

Re: [Mesa-dev] [PATCH 13/16] st/nine: Rework update_vertex_buffers

On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > Previous code was trying to optimise to call set_vertex_buffers on > big packets, and thus avoids as many calls as possible. > > However in practice doing so won't be faster (drivers implement > set_vertex_buffers by a loop over the buffers we wa

Re: [Mesa-dev] [PATCH 08/16] st/nine: Change x86 FPU Control word on device creation as on wined3d and windows

On 24 April 2015 at 22:09, Axel Davy wrote: > +static void nine_setup_fpu(void) > +{ > +#if defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__)) > +WORD cw; > +__asm__ volatile ("fnstcw %0" : "=m" (cw)); > +cw = (cw & ~0xf3f) | 0x3f; > +__asm__ volatile ("fldcw %0" : : "

Re: [Mesa-dev] [PATCH 12/16] st/nine: Fix computation of const_used_size

On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > From: Xavier Bouchoux > > Was sometimes too large for PS. > > Reviewed-by: Axel Davy > Signed-off-by: Xavier Bouchoux > --- > src/gallium/state_trackers/nine/nine_shader.c | 8 +--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > di

Re: [Mesa-dev] [PATCH V2 12/22] i965: Rename use_linear_1d_layout() and make it global

On Fri, Apr 17, 2015 at 04:51:33PM -0700, Anuj Phogat wrote: > This function will be utilised in later patches. > > Signed-off-by: Anuj Phogat > --- > src/mesa/drivers/dri/i965/brw_context.h| 4 > src/mesa/drivers/dri/i965/brw_tex_layout.c | 10 +- > 2 files changed, 9 insertio

Re: [Mesa-dev] [PATCH 11/16] st/nine: Ignore D3DUSAGE_QUERY_POSTPIXELSHADER_BLENDING when D3DUSAGE_RENDERTARGET is specified

Oups, yep I changed the commit message to make it shorter, but I made it say the opposite that what it was suppose to... Le 24/04/2015 23:32, Ilia Mirkin a écrit : The diff does not agree with the commit description. Also please limit commit descriptions to 72 chars. On Fri, Apr 24, 2015 at 4:

Re: [Mesa-dev] [PATCH V2 11/22] i965/gen9: Set tiled resource mode in surface state

On Fri, Apr 17, 2015 at 04:51:32PM -0700, Anuj Phogat wrote: > This patch sets the tiled resource mode for texture and renderbuffer > surfaces. > > Signed-off-by: Anuj Phogat > --- > src/mesa/drivers/dri/i965/brw_defines.h| 6 ++ > src/mesa/drivers/dri/i965/gen8_surface_state.c | 22

Re: [Mesa-dev] [PATCH 11/16] st/nine: Ignore D3DUSAGE_QUERY_POSTPIXELSHADER_BLENDING when D3DUSAGE_RENDERTARGET is specified

On Fri, Apr 24, 2015 at 5:32 PM, Ilia Mirkin wrote: > The diff does not agree with the commit description. Also please limit > commit descriptions to 72 chars. er, of course I meant commit *subjects*. Although the each line of the commit description should also be wrapped at 72. (Because they're

Re: [Mesa-dev] [PATCH 11/16] st/nine: Ignore D3DUSAGE_QUERY_POSTPIXELSHADER_BLENDING when D3DUSAGE_RENDERTARGET is specified

The diff does not agree with the commit description. Also please limit commit descriptions to 72 chars. On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > From: Xavier Bouchoux > > This behaviour matches windows drivers. > > Reviewed-by: Axel Davy > Signed-off-by: Xavier Bouchoux > --- > src

Re: [Mesa-dev] [PATCH 10/16] st/nine: Improve D3DQUERYTYPE_TIMESTAMP

That makes sense. Probably the FLUSH is supposed to imply something else, which in turn just makes the timestamp query succeed... something like if (flush) pipe->flush() or something. That's basically what telling it to wait does though, so this is fine. Reviewed-by: Ilia Mirkin On Fri, Apr

Re: [Mesa-dev] [PATCH V2 18/22] i965/skl: Modify the conditions to use blitter on skl+

On Fri, Apr 17, 2015 at 04:51:39PM -0700, Anuj Phogat wrote: > Conditions modified allow skl+ to use blitter: > - for all tiling formats > - to write data to YF/YS tiled surfaces > > Signed-off-by: Anuj Phogat > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 +--- > 1 file ch

Re: [Mesa-dev] [PATCH 09/16] st/nine: Fix D3DQUERYTYPE_TIMESTAMPFREQ query

From https://msdn.microsoft.com/en-us/library/windows/desktop/bb172594%28v=vs.85%29.aspx D3DQUERYTYPE_TIMESTAMPFREQ This query result is TRUE if the values from D3DQUERYTYPE_TIMESTAMP queries cannot be guaranteed to be continuous throughout the duration of the D3DQUERYTYPE_TIMESTAMPDISJOINT query

Re: [Mesa-dev] [PATCH 07/16] st/nine: Do not advertise D3DDEVCAPS_TEXTURESYSTEMMEMORY

Reviewed-by: Ilia Mirkin On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > No major vendor advertises it, and we weren't supporting it. > > Signed-off-by: Axel Davy > --- > src/gallium/state_trackers/nine/adapter9.c | 2 +- > src/gallium/state_trackers/nine/device9.c | 10 ++ > 2 f

Re: [Mesa-dev] [PATCH 06/16] st/nine: Fix comment in update_viewport

Reviewed-by: Ilia Mirkin On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > Signed-off-by: Axel Davy > --- > src/gallium/state_trackers/nine/nine_state.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/src/gallium/state_trackers/nine/nine_state.c > b/src/gallium

Re: [Mesa-dev] [PATCH 05/16] st/nine: Workaround barycentrics issue on some cards

On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > Signed-off-by: Axel Davy > --- > src/gallium/state_trackers/nine/device9.c| 4 +++- > src/gallium/state_trackers/nine/device9.h| 4 > src/gallium/state_trackers/nine/nine_state.c | 24 > 3 files changed,

Re: [Mesa-dev] [PATCH 04/16] st/nine: Clear struct pipe_blit_info before use.

On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > From: Xavier Bouchoux > > render_condition_enable was uninitialized. > > Reviewed-by: Axel Davy > Signed-off-by: Xavier Bouchoux I assume d3d9 doesn't have conditional rendering? If it does, you should double-check whether StretchRect and Res

Re: [Mesa-dev] [PATCH 03/16] st/nine: NineDevice9_Clear skip fastpath for bigger depth-buffers

Le 24/04/2015 23:10, Ilia Mirkin a écrit : What if the depth buffer is smaller than the color RT? I'd assume that the fb would be reduced in that case as well... or does This->state.fb.width/height only represent the min of the color RT's sizes? It is forbidden by the spec to have depth buffer

Re: [Mesa-dev] [PATCH 01/16] st/nine: Handle special LIT case

On Fri, Apr 24, 2015 at 5:08 PM, Axel Davy wrote: > Le 24/04/2015 23:04, Ilia Mirkin a écrit : >> >> On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: >>> >>> Signed-off-by: Axel Davy >>> --- >>> src/gallium/state_trackers/nine/nine_shader.c | 19 ++- >>> 1 file changed, 18 in

Re: [Mesa-dev] [PATCH 03/16] st/nine: NineDevice9_Clear skip fastpath for bigger depth-buffers

What if the depth buffer is smaller than the color RT? I'd assume that the fb would be reduced in that case as well... or does This->state.fb.width/height only represent the min of the color RT's sizes? On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > From: Patrick Rudolph > > This adds an ad

Re: [Mesa-dev] [PATCH 01/16] st/nine: Handle special LIT case

Le 24/04/2015 23:04, Ilia Mirkin a écrit : On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: Signed-off-by: Axel Davy --- src/gallium/state_trackers/nine/nine_shader.c | 19 ++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/nine/nin

Re: [Mesa-dev] [PATCH 02/16] st/nine: Fix wrong assert in nine_shader

Reviewed-by: Ilia Mirkin On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > The sampler src index was wrong for texldl and texldd > > Signed-off-by: Axel Davy > --- > src/gallium/state_trackers/nine/nine_shader.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a

Re: [Mesa-dev] [PATCH 01/16] st/nine: Handle special LIT case

On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > Signed-off-by: Axel Davy > --- > src/gallium/state_trackers/nine/nine_shader.c | 19 ++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/src/gallium/state_trackers/nine/nine_shader.c > b/src/gallium/state_tra

Re: [Mesa-dev] [PATCH 6/7] i965: ensure execution of fragment shader when fragment shader has atomic buffer access

One more comment, that I neglected to add: there are other checks for _CurrentFragmentProgram to be non-NULL, indeed function brw_upload_wm_abo_surface() [file brw_wm_surface_state.c], also has a check for it being non-NULL. That function is the emit for the atom brw_wm_abo_surfaces which is pre

Re: [Mesa-dev] [PATCH 08/16] st/nine: Change x86 FPU Control word on device creation as on wined3d and windows

Can you use the fe* class of functions for this? Not entirely sure what this is setting, but you should be able to do it with fegetenv/fesetenv, or the more specialized functions. On Fri, Apr 24, 2015 at 4:09 PM, Axel Davy wrote: > From: Tiziano Bacocco > > Signed-off-by: Tiziano Bacocco > ---

Re: [Mesa-dev] [PATCH 0/4] clover: this serie remove util/compat.*

On Fri, Apr 24, 2015 at 12:59:53PM +0200, EdB wrote: > Since clover should compile use -std=c++11, > compat classes are no longer neccessary > Thank you for working on this, it is a nice improvement. I will try to review/test these early next week. Thanks, Tom > EdB (4): > clover: remove com

[Mesa-dev] [PATCH 03/16] st/nine: NineDevice9_Clear skip fastpath for bigger depth-buffers

From: Patrick Rudolph This adds an additional check to make sure the bound depth-buffer doesn't exceed the rendertarget size when clearing depth and color buffer at once. D3D9 clears only a rectangle with the same dimensions as the viewport, leaving other parts of the depth-buffer intact. This f

[Mesa-dev] [PATCH 16/16] st/nine: Rework texture data allocation

Some applications assume the memory for multilevel textures is allocated per continuous blocks. This patch implements that behaviour. Signed-off-by: Axel Davy --- src/gallium/state_trackers/nine/cubetexture9.c | 42 -- src/gallium/state_trackers/nine/cubetexture9.h | 1 + s

[Mesa-dev] [PATCH 14/16] st/nine: Add debug warning when application uses sw processing

Signed-off-by: Axel Davy --- src/gallium/state_trackers/nine/cubetexture9.c | 3 +++ src/gallium/state_trackers/nine/device9.c| 5 + src/gallium/state_trackers/nine/indexbuffer9.c | 14 -- src/gallium/state_trackers/nine/texture9.c | 5 + src/gallium/state

[Mesa-dev] [PATCH 01/11] st/nine: Encapsulate variables for MANAGED resource

Signed-off-by: Axel Davy --- src/gallium/state_trackers/nine/basetexture9.c | 82 src/gallium/state_trackers/nine/basetexture9.h | 19 +++--- src/gallium/state_trackers/nine/cubetexture9.c | 2 +- src/gallium/state_trackers/nine/device9.c| 2 +- src/galliu

[Mesa-dev] [PATCH 03/11] st/nine: Simplify Surface9 Managed resources implementation

Remove the Surface9 code for dirty rects, used only for Managed resources. Instead convey the information to the parent texture. According to documentation, this seems to be the expected behaviour, and if documentation is wrong there, that's not a problem since it can only leads to more texture up

[Mesa-dev] [PATCH 04/11] st/nine: Bound the dirty regions to resource size

Signed-off-by: Axel Davy --- src/gallium/state_trackers/nine/cubetexture9.c | 4 src/gallium/state_trackers/nine/texture9.c | 3 +++ src/gallium/state_trackers/nine/volumetexture9.c | 9 + 3 files changed, 16 insertions(+) diff --git a/src/gallium/state_trackers/nine/cubetex

[Mesa-dev] [PATCH 05/11] st/nine: Rewrite Managed texture uploads

That part of the code was quite obscure. This new implementation tries to make it clearer by separating the differents parts, and commenting more. Signed-off-by: Axel Davy --- src/gallium/state_trackers/nine/basetexture9.c | 221 ++--- 1 file changed, 125 insertions(+), 96 de

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