Several steppings of Skylake fail when using SIMD16 with 3-source
instructions (such as MAD).
This implements WaDisableSIMD16On3SrcInstr and fixes ~190 Piglit
tests.
Based on a patch by Neil Roberts.
Signed-off-by: Kenneth Graunke
Cc: Neil Roberts
Cc: Matt Turner
---
src/mesa/drivers/dri
Ben noticed that I said each PIPE_CONTROL was 4 DWords, but it's
actually 5 DWords on Gen6-7. We've been reserving insufficient space
for performance monitoring on Sandybridge, which means it would likely
break if you used that functionality. (Thankfully, no one does...)
Signed-off-b
e longstanding bugs - for now,
put things back to the status quo).
Signed-off-by: Kenneth Graunke
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89430
Cc: "10.5"
Cc: Mark Janes
---
src/mesa/drivers/dri/i965/intel_fbo.c | 50 ++-
1 file changed, 49
t; >
> > Signed-off-by: Ville Syrjälä
>
> Ping?
Oh, sorry! I thought I'd reviewed this. It does indeed appear to be
192kB.
Reviewed-by: Kenneth Graunke
Have you tested it? Assuming it doesn't explode, feel free to push
this. Thanks for catching the mistake!
signature.a
Being able to see both location and driver_location can be useful when
debugging IO mistakes.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_print.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir_print.c b/src/glsl/nir/nir_print.c
index 6a3c6a0
set in the calculation. Noticed by Jan.
>
> Signed-off-by: Ian Romanick
> Cc: Kenneth Graunke
> Cc: Jan Vesely
Huh. I could've sworn I reviewed this patch a while back, but I can't
find any evidence of that. Thanks for fixing this!
The spec isn't particularly clear
On Gen8+, AND/OR/XOR/NOT don't support the abs() source modifier, and
negate changes meaning to bitwise-not (~, not -). This isn't what NIR
expects, so we should resolve the source modifers via a MOV.
+30 Piglits (fs-op-bit{and,or,xor}-not-abs-*).
Signed-off-by: Kenneth Graunke
---
On Thursday, March 05, 2015 09:39:58 PM Jason Ekstrand wrote:
> This looks fine to me. I just kicked off a build on our test farm and,
> assuming that looks good (I'll send another e-mail in the morning if it
> does),
>
> Reviewed-by: Jason Ekstrand
>
> I ran shader-db on the change and I was k
o
a vec4[2], which is highly illegal.
This tripped assertions in nir_split_var_copies with scalar VS.
Signed-off-by: Kenneth Graunke
Cc: mesa-sta...@lists.freedesktop.org
---
src/glsl/ast_to_hir.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/glsl_to_nir.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index ddad207..047cb51 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
Nothing actually uses these, and the only caller of glsl_to_nir()
(brw_fs_nir.cpp) always passes NULL for the _mesa_glsl_parse_state
pointer, meaning they'll always be NULL and 0, respectively.
Just delete them.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/glsl_to_nir.cpp
The next commit needs to know the shader stage in glsl_to_nir().
To facilitate that, we pass the gl_shader rather than the raw exec_list
of instructions. This has both the exec_list and the stage.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/glsl_to_nir.cpp | 14
glsl_to_nir, tgsi_to_nir, and prog_to_nir all want to know whether the
driver supports native integers. Presumably other passes may as well.
Adding this to nir_shader_compiler_options is an easy way to provide
that information, as it's accessible via nir_shader::options.
Signed-off-by: Ke
he shader compiler options as a mandatory argument. It creates an
(empty) options struct in the i965 driver, and makes NirOptions point
to that. It marks the pointer const so that we can actually do so
without generating "discards const qualifier" compiler warnings.
Signed-off-by: Kenn
On Friday, March 06, 2015 03:20:26 PM Pohjolainen, Topi wrote:
> On Fri, Mar 06, 2015 at 02:46:51PM +0200, Francisco Jerez wrote:
> > "Pohjolainen, Topi" writes:
> >
> > > On Fri, Mar 06, 2015 at 02:29:15PM +0200, Francisco Jerez wrote:
> > >> "Pohjolainen, Topi" writes:
> > >>
> > >> > On Fri,
On Friday, February 27, 2015 05:34:44 PM Francisco Jerez wrote:
> ---
> src/mesa/drivers/dri/i965/brw_eu.h | 19 ++--
> src/mesa/drivers/dri/i965/brw_eu_emit.c | 58
> ++--
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 55 +
On Saturday, March 07, 2015 10:09:15 PM Jason Ekstrand wrote:
> LGTM.
Jason,
Sean doesn't have commit access (it's actually his first patch) - if
this is good to go, would you mind pushing it for him?
Nice work, Sean!
--Ken
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On Friday, February 27, 2015 11:37:01 PM Pohjolainen, Topi wrote:
> On Fri, Feb 27, 2015 at 11:15:35AM -0800, Kenneth Graunke wrote:
> > This makes another part of the INTEL_DEBUG=shader_time code emittable
> > at arbitrary locations, rather than just at the end of the instruc
These computations don't have anything to do with the currently
executing channels, so they should use force_writemask_all.
This fixes assert failures.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86974
Signed-off-by: Kenneth Graunke
Cc: mesa-sta...@lists.freedesktop.org
---
src
Instead of emit_shader_time_write, we now do emit(SHADER_TIME_ADD(...)).
The advantage is that we can also insert a shader time write at an
arbitrary location in the instruction stream, rather than being
restricted to emitting at the end.
Signed-off-by: Kenneth Graunke
Reviewed-by: Topi
This makes another part of the INTEL_DEBUG=shader_time code emittable
at arbitrary locations, rather than just at the end of the instruction
stream.
v2: Don't lose smear! Caught by Topi Pohjolainen.
v3: Don't set smear on the destination of the MOV. Thanks Topi!
Signed-off-by: Kenne
Welcome to the rabbit trail. In order to fix Football Manager, I had to
rework INTEL_DEBUG=shader_time in the FS backend. While doing that, I
hit two assertion failures. After fixing that, I compared numbers.
I noticed that VS again accounted for 0 cycles.
Matt - could you take a look at brw_ve
time fixes.
Signed-off-by: Kenneth Graunke
Reviewed-by: Topi Pohjolainen [v1]
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 28 ++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 13 -
2 files changed, 18 insertions(+), 23 deletions(-)
diff --git a/src/mesa/d
desktop.org/show_bug.cgi?id=86974
Signed-off-by: Kenneth Graunke
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 45a5793..db8affa 10064
On Sunday, March 08, 2015 01:32:33 PM Matt Turner wrote:
> On Sun, Mar 8, 2015 at 1:08 AM, Kenneth Graunke wrote:
> > These computations don't have anything to do with the currently
> > executing channels, so they should use force_writemask_all.
> >
>
On Friday, March 06, 2015 06:22:00 PM Ben Widawsky wrote:
> It looks like this has existed since:
> commit f5a477ab76b6e0b268387699cd2253a43db0dfae
> Author: Ian Romanick
> Date: Mon Dec 16 11:54:08 2013 -0800
>
> meta: Refactor shader generation code out of mipmap generation path
>
> Valg
to me that we could just set up a pointer in the
constructor, and skip having a function altogether.
This patch also converts all existing users to use key_tex.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +
src/mesa/drivers/dri/i965/brw_fs_nir.cpp |
No functional change. In preparation for supporting vertex shaders,
this adds a switch statement on shader stage (since vertex attributes
and fragment shader varyings will need different handling). It also
renames "varying" to "input", to be more general.
Signed-off
Adapted from fs_visitor::visit(ir_variable *).
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
Array variable copy splitting generates a bunch of stuff we want to
clean up before proceeding.
Signed-off-by: Kenneth Graunke
Cc: Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 428234f..ee5bc4a 100644
--- a/src/mesa/drivers/dri/i965
Ian and I added these around the time Connor was developing NIR. Now
that both exist, we should make them work together!
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_intrinsics.h | 2 ++
src/glsl/nir/nir_lower_system_values.c | 6 ++
2 files changed, 8 insertions(+)
diff
We can't safely call nir_optimize() with register present, since several
passes called in the loop can't handle registers, and will fail asserts.
Notably, nir_lower_vec_alus() and nir_opt_algebraic() really don't want
registers.
Signed-off-by: Kenneth Graunke
---
src/mesa/d
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 3baafc4..1734d03 100644
--- a/src
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 51
1 file changed, 51 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index c5ed55c..d700523 100644
--- a/src/mesa
ap generation path
>
> Valgrind was complaining on fbo-generatemipmap-formats
>
> v2: Instead, do the allocation after the early return block (v2)
>
> Cc: Ian Romanick
> Cc: Brian Paul
> Cc: Eric Anholt
> Cc: Kenneth Graunke
> Signed-off-by: Ben Widawsky
> ---
>
st NULL will tell us whether the node is
already in the list.
Pair programming with Jason Ekstrand.
Signed-off-by: Jason Ekstrand
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_lower_vars_to_ssa.c | 123 ---
1 file changed, 26 insertions(+), 97 deletions(-)
d
From: Jason Ekstrand
__next and __prev are pointers to the structure containing the exec_node
link, not the embedded exec_node. NULL checks would fail unless the
embedded exec_node happened to be at offset 0 in the parent struct.
Signed-off-by: Jason Ekstrand
Reviewed-by: Kenneth Graunke
ed programs: 2724564 -> 2708831 (-0.58%)
instructions in affected programs: 593696 -> 577963 (-2.65%)
helped:3134
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs_copy_propagation
assert(value > -(1 << 15));
>brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
> }
> }
Isn't -32768 legal? It would be excluded by the above assertions.
A patch to make them:
assert(value <= (1 << 15) - 1);
assert(value >= -(1 <
fo
> *devinfo,
> int scale = 16 / brw_jump_scale(devinfo);
> int jip = devinfo->gen == 6 ? brw_inst_gen6_jump_count(devinfo, insn)
> : brw_inst_jip(devinfo, insn);
> + assert(jip < 0);
> return while_offset + jip * scale <= st
...and provide a better citation for the existing one.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 32 +---
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa
On Sunday, January 29, 2017 6:20:10 PM PST Matt Turner wrote:
> This partially reverts commit 97217a40f97cdeae0304798b607f704deb0c3558.
> It leaves ES 2.0 support in place per Ian's suggestion, because ES 2.0
> is designed to work on hardware like i915.
Your commit message should mention why dropp
y be a problem but, given how hard these things are to debug, we
> might as well make sure.
That's kind of a separate change from applying the flushes on Gen7/7.5.
It also seems like a fine thing to do. Might make sense to split into
two patches.
At minimum, assuming you update the commi
ECT_RED] = clear_color.u32[2];
> + old.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = clear_color.u32[3];
> + swizzle = ISL_SWIZZLE_IDENTITY;
Are ISL_CHANNEL_SELECT_{ZERO,ONE} disallowed by a higher level? If not,
this will break rather spectacularly (old.u32[-4] = ...). Maybe add
asserts?
Assum
e. We definitely don't want to advertise
rendering to this if it doesn't work.
You can always do your clever hacks in BLORP to make it work for e.g.
copyimage etc, like you did for RGB9E5 and friends.
Reviewed-by: Kenneth Graunke
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On Wednesday, February 1, 2017 2:36:02 PM PST Brian Paul wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95460
> ---
> docs/features.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/docs/features.txt b/docs/features.txt
> index 55b1fbb..300442b 100644
> --- a/docs/f
On Wednesday, February 1, 2017 12:35:15 PM PST Eero Tamminen wrote:
> Hi,
>
> On 31.01.2017 21:12, Matt Turner wrote:
> > On Sun, Jan 29, 2017 at 8:29 PM, Kenneth Graunke
> > wrote:
> >> On Sunday, January 29, 2017 6:20:10 PM PST Matt Turner wrote:
>
On Thursday, February 2, 2017 7:35:20 AM PST Chad Versace wrote:
> On Thu 02 Feb 2017, Dave Airlie wrote:
> > On 2 February 2017 at 13:09, Emil Velikov wrote:
> > > On 2 February 2017 at 02:58, Michel Dänzer wrote:
> > >> On 02/02/17 09:10 AM, Emil Velikov wrote:
> > >>> On 1 February 2017 at 23:
;
> > Doing the latter will lead to combinatoric explosion and in all fairness
> > things will likely be broken most of the time.
> >
> > To make things even more confusing the kernel UAPI is provided by libdrm
> > itself.
> >
> > Cc: Vinson Lee
> >
dEQP-EGL.functional.create_context.no_config tries to create a context
with no config, then immediately destroys it. The drawbuffer is never
set up, so we can't dereference it asking if it's double buffered, or
we'll crash on a null pointer dereference.
Just bail early.
Signed-
nX_pipeline.c | 49
> +---
> 1 file changed, 26 insertions(+), 23 deletions(-)
looks good to me.
Reviewed-by: Kenneth Graunke
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-http://dri.freedesktop.org/wiki/MissingFunctionality
> +
> +A graphical representation of this information can be found at
> +http://mesamatrix.net/
>
Yeah, we haven't used that page in years...
Acked-by: Kenneth Graunke
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that STATE_BASE_ADDRESS is necessary, as the
depth related commands use graphics addresses, not ones relative
to the base address...but we're likely to set it as part of the
next operation anyway, so we should just do it right away.
Cc: "17.0"
Signed-off-by: Kenneth Graunke
---
On Monday, February 6, 2017 8:54:40 PM PST Marek Olšák wrote:
> On Mon, Feb 6, 2017 at 8:20 PM, Ernst Sjöstrand wrote:
> > FYI glmark2 segfaults with mesa_glthread=true. Expected that some programs
> > will segfault?
>
> Yes, even segfaults are expected with mesa_glthread=true.
>
> Marek
Would
y adding another delegate to check for compute
> shader support instead of only whether the current stage is compute
>
> This allows some fragment shaders in Dirt Rally to compile
>
> CC: "17.0"
>
> Reviewed-by: Anuj Phogat
Reviewed-by: Kenneth Graunk
On Thursday, February 9, 2017 5:23:47 PM PST Ian Romanick wrote:
[snip]
> Not achieving the desired performance is vastly different from
> segfaults. Does the threaded mode in NVIDIA's driver crash? I'd wager
> not.
Sadly, yes it does. A while back, I tried running some Steam games
on Linux usi
On Friday, February 10, 2017 5:45:03 AM PST Ilia Mirkin wrote:
> On Fri, Feb 10, 2017 at 8:41 AM, Samuel Pitoiset
> wrote:
> > Hi,
> >
> > Mesa currently doesn't allow to create 3.1+ compatibility profiles mainly
> > because various features are unimplemented and bugs can happen.
> >
> > However,
,get_error,log}.shader.compile_compute_shader.
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl/ast_to_hir.cpp | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index b31b61d1ed6..851a7d6ef4d 100644
--- a/src
++
> 1 file changed, 7 insertions(+), 4 deletions(-)
Thanks! I missed this patch on the mailing list and independently
arrived at the same solution today, so we'll call that a:
Reviewed-by: Kenneth Graunke
and pushed:
To ssh://git.freedesktop.org/git/mesa/
On Friday, February 10, 2017 3:01:10 PM PST Ilia Mirkin wrote:
> Seems pretty similar to https://patchwork.freedesktop.org/patch/138274/
So it does! I hadn't seen that patch yet. I just pushed his patch
instead with my R-b. Thanks!
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Signed-off-by: Kenneth Graunke
---
src/mesa/main/shader_query.cpp | 98 --
1 file changed, 56 insertions(+), 42 deletions(-)
diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index 30e5b087abb..6e077623e15 100644
--- a/
EQP-GLES31.functional.program_interface_query.program_output.
array_size.separable_tess_ctrl.var.
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl/ast_to_hir.cpp | 3 --
src/compiler/glsl/ir.h | 6
src/compiler/glsl/linker.cpp | 32 -
OpenGL ES actually has spec text to prohibit this. It's just OpenGL
that's confusing.
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl/linker.cpp | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker
some SSO pipeline validation changes I'm making.
Cc: "17.0"
Signed-off-by: Kenneth Graunke
---
src/mesa/main/api_validate.c | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_v
egative_coverage.*.tessellation.single_tessellation_stage
Signed-off-by: Kenneth Graunke
---
src/mesa/main/api_validate.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
index d64264fe1e9..41d2611eec4 100644
--- a/src/mesa/main/api_validate.c
+++
On Saturday, February 11, 2017 12:21:36 AM PST Alejandro Piñeiro wrote:
> On 11/02/17 08:52, Kenneth Graunke wrote:
> > Now that we have OES_tessellation_shader, the same situation can occur
> > in ES too, not just GL core profile.
> >
> > Having a TCS but no TES may con
For GS input arrays, we may turn a packed_type of ivec4 into an
array of ivec4s. We still want flat qualification.
Found by inspection. Not known to help anything.
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl/lower_packed_varyings.cpp | 3 ++-
1 file changed, 2 insertions(+), 1
rface_query.program_input.type.
separable_geometry.{int,ivec2,ivec3,ivec4,uint,uvec2,uvec3,uvec4}.
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl/lower_packed_varyings.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/compiler/glsl/lower_packed_var
n on the subject, so let's go with it for now :)
Series is:
Reviewed-by: Kenneth Graunke
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On Tuesday, February 14, 2017 12:38:45 PM PST Chad Versace wrote:
> On Tue 14 Feb 2017, Matt Turner wrote:
>
>
> > static bool
> > -anv_get_function_timestamp(void *ptr, uint32_t* timestamp)
> > +anv_device_get_cache_uuid(void *uuid)
> > {
> > - Dl_info info;
> > - struct stat st;
> > - i
assertions.
By marking the helper as inline, the code for unused buffers should
be constant folded away.
Signed-off-by: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen6_constant_state.c | 169 +---
1 file changed, 118 insertions(+), 51 deletions
This is more convenient than OUT_BATCH'ing both halves.
Signed-off-by: Kenneth Graunke
Cc: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen8_depth_state.c | 3 +--
src/mesa/drivers/dri/i965/gen8_ds_state.c | 3 +--
src/mesa/drivers/dri/i965/gen8_gs_state.c | 3 +--
src/mesa/driver
On Monday, February 13, 2017 6:58:39 PM PST Jason Ekstrand wrote:
> On Mon, Feb 13, 2017 at 6:35 PM, Francisco Jerez
> wrote:
>
> > Jason Ekstrand writes:
> >
> > > The AccessUAV bit is not quite what we want because it's more about
> > > coherency between storage operations than it is about dis
nir_instr *parent_instr = instr->src[i].src.ssa->parent_instr;
>
Series is:
Reviewed-by: Kenneth Graunke
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hook, just
like we did for the KHR_debug functionality.
This may impact freedreno, which actually puts markers in its command
buffers.
Signed-off-by: Kenneth Graunke
---
src/mesa/main/debug_output.c | 4 +---
src/mesa/main/extensions_table.h | 2 +-
src/mesa/state_tracker/st_de
On Wednesday, February 15, 2017 3:23:14 PM PST Jordan Justen wrote:
> On 2017-02-14 13:45:49, Kenneth Graunke wrote:
[snip]
> > diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c
> > b/src/mesa/drivers/dri/i965/gen6_constant_state.c
> > index 6c0c32b26f7..7e6fa92
assertions.
By marking the helper as inline, the code for unused buffers should
be constant folded away.
v2: Don't lose MOCS setting on Gen7-7.5.
Signed-off-by: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen6_constant_state.c | 170
1
On Thursday, February 16, 2017 4:29:50 AM PST Lionel Landwerlin wrote:
> Since we're already asking the driver to generate code for a different
> hardware than what we're running on, better not even bother with emitting
> any batch.
>
> Signed-off-by: Lionel Landwerlin
> ---
> run.c | 1 +
> 1 f
Sandybridge and earlier only have a single counter.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/gen6_sol.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c
b/src/mesa/drivers/dri/i965/gen6_sol.c
index
to copy them to another
internal counter which 3DPRIMITIVE can use...but there's no good way to
extract that either.
So, once again, we use SO_NUM_PRIMS_WRITTEN to calculate the vertex
numbers. Thankfully, we can reuse most of the existing Gen7+ code.
Signed-off-by: Kenneth Graunke
---
src/m
I plan to use these functions on Sandybridge soon. I changed the prefix
on a couple of functions to "brw" instead of "gen7" as in theory they
should be usable all the way back to G45.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.h| 6 ++
I'm going to need this in a new Resume hook shortly.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.h | 6 ++
src/mesa/drivers/dri/i965/gen6_sol.c| 6 --
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cont
These driver hooks are not used when MI_MATH and MI_LOAD_REGISTER_REG
are supported, which Gen8+ can always do. So this code is dead.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/gen7_sol_state.c | 50 ++
1 file changed, 24 insertions(+), 26
bGL 2.0 on Sandybridge.
Note that we don't need pipelined register writes like Gen7+ because
we use the 3DSTATE_SVB_INDEX command rather than MI_LOAD_REGISTER_MEM.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99842
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_con
This way on Sandybridge we'll only do 1 stream worth of math, since
we only have one SO_NUM_PRIMS_WRITTEN counter.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/gen6_sol.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/src
f us would
need this lowering...if it were required. But it isn't, so goodbye
code! :)
Reviewed-by: Kenneth Graunke
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le for it here:
>
> https://github.com/rantogno/piglit/tree/review/overflow_query-v05
>
> Regards,
> Rafael
Looks great! Series is:
Reviewed-by: Kenneth Graunke
I'm guessing you don't have commit access, so I'll try and push it...
query_object
> +{
> + GLuint Id;/**< hash table ID/name */
> + GLuint Used:1;/**< has been used for 1 or more queries */
> + GLuint Active:1; /**< inside Begin/EndPerfQuery */
> + GLuint Ready:1; /**< result is ready? */
Please use "unsigned Id&qu
On Thursday, February 16, 2017 5:20:37 AM PST Robert Bragg wrote:
[snip]
> + switch(obj->query->kind) {
Space after "switch" please.
Patch 3 is:
Reviewed-by: Kenneth Graunke
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On Wednesday, February 22, 2017 10:35:24 AM PST Robert Bragg wrote:
> On Wed, Feb 22, 2017 at 1:24 AM, Kenneth Graunke
> wrote:
> > On Wednesday, February 15, 2017 1:37:36 PM PST Robert Bragg wrote:
[snip]
> >> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
approach taken in
this patch is more restrictive, but should still allow any valid ES
programs to work in GL.
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl/linker.cpp | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
> - if (_mesa_is_gles3(ctx) && !ctx->Extensions.OES_geometry_shader &&
> + if (_mesa_is_gles3(ctx) &&
> + !_mesa_has_OES_geometry_shader(ctx) &&
> _mesa_is_xfb_active_and_unpaused(ctx)) {
>_mesa_error(ctx, GL_INVALID_OPERATIO
On Thursday, February 23, 2017 4:03:36 AM PST Andres Gomez wrote:
> I would welcome a reference to the text in Secption 7.3 of the OpenGL
> ES 3.2 specs as a code comment and commit text but, other than that,
> this is:
>
> Reviewed-by: Andres Gomez
I'll add it to the commit message. I wasn't s
On Thursday, February 23, 2017 10:46:54 AM PST Ilia Mirkin wrote:
> The assumption was that if you're setting that ext, you can do gles31. Is
> there a driver/hw combo where that's not the case? If so, we should fix
> that instead...
ChromeOS/ARC++ currently disables GLES 3.1 on i965 because we ha
-by: Kenneth Graunke
---
src/util/ralloc.c | 18 --
src/util/ralloc.h | 9 -
2 files changed, 27 deletions(-)
diff --git a/src/util/ralloc.c b/src/util/ralloc.c
index 980e4e4f138..d5cc16766b1 100644
--- a/src/util/ralloc.c
+++ b/src/util/ralloc.c
@@ -323,24 +323,6
from Mesa's
one_time_fini() function, which Mesa installs as an atexit() handler.
The one advantage here is that it ensures the built-in functions are
destroyed before the types.
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl_types.cpp | 5 -
1 file changed, 4 insertions(+), 1 del
This patch makes glCopyImageSubData require mipmap completeness when the
texture object's built-in sampler object has a mipmapping MinFilter.
Fixes (on i965):
dEQP-GLES31.functional.debug.negative_coverage.*.buffer.copy_image_sub_data
Signed-off-by: Kenneth Graunke
---
src/mesa
I have no idea why these were part of the compiler files. They're
miptree related code, and the compiler doesn't appear to use them.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
On Monday, February 27, 2017 4:54:37 AM PST Kenneth Graunke wrote:
> This patch makes glCopyImageSubData require mipmap completeness when the
> texture object's built-in sampler object has a mipmapping MinFilter.
>
> Fixes (on i965):
> dEQP-GLES31.functional.deb
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