On 3/13/23 16:38, Ilya Leoshkevich wrote:
The code uses the wrong base for relative addressing: it should use the
target instruction address and not the EXECUTE's address.
Fix by storing the target instruction address in the new CPUS390XState
member and loading it from the code generated by
From: Ross Lagerwall
The scancodes for the Lang1 and Lang2 keys (i.e. Hangeul, Hanja) are
special since they already have the 0x80 bit set which is commonly used
to indicate a key release in AT set 1. Reportedly, real hardware does
not send a key release scancode. So, skip sending a release for
From: Willem van de Velde
To be able to use the function keys F13 to F24 these should be defined in de
keycodemapdb and added to the qapi.
The keycodemapdb is updated in its own repository, this patch enables the use
of those keys within qemu.
Signed-off-by: Willem van de Velde
The following changes since commit 5cfda4ce79dd455f1726874a555260a70f84b2ec:
Merge tag 'pull-request-2023-03-13' of https://gitlab.com/thuth/qemu into
staging (2023-03-13 17:09:33 +)
are available in the Git repository at:
https://gitlab.com/berrange/qemu tags/misc-next-pull-request
From: Matheus Tavares Bernardino
This leakage can be seen through test-io-channel-tls:
$ ../configure --target-list=aarch64-softmmu --enable-sanitizers
$ make ./tests/unit/test-io-channel-tls
$ ./tests/unit/test-io-channel-tls
Indirect leak of 104 byte(s) in 1 object(s) allocated from:
#0
I am currently developing tests under avocado to help debugging.
And... it helps.
There is a bug here in s390_topology_set_cpus_entitlement for dedicated
CPUs.
On 3/9/23 13:15, Pierre Morel wrote:
[...]
--- a/hw/s390x/cpu-topology.c
+++ b/hw/s390x/cpu-topology.c
@@ -87,6 +87,84 @@ static
On Monday, February 20, 2023 11:08:03 AM CET Bin Meng wrote:
> From: Guohuai Shi
>
> This commit implements Windows specific xxxdir() APIs for safety
> directory access.
That comment is seriously too short for this patch.
1. You should describe the behaviour implementation that you have chosen
The 03/03/2023 15:09, Jonathan Cameron wrote:
> Inject poison using qmp command cxl-inject-poison to add an entry to the
> poison list.
>
> For now, the poison is not returned CXL.mem reads, but only via the
> mailbox command Get Poison List.
>
> See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list
The 03/03/2023 15:09, Jonathan Cameron wrote:
> Very simple implementation to allow testing of corresponding
> kernel code. Note that for now we track each 64 byte section
> independently. Whilst a valid implementation choice, it may
> make sense to fuse entries so as to prove out more complex
>
The 03/03/2023 15:09, Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
One minor thing as mentioned below.
> v4:
> - Fix off by
On 3/13/23 14:46, Philippe Mathieu-Daudé wrote:
+CodeSourcery folks
On 13/3/23 19:33, Thomas Huth wrote:
Marek and Chris haven't been active for Nios II since years
(the last time seems to have been in 2017), and we've got
unhandled severe Nios II bug tickets in the bug tracker since
a long
On 14/03/2023 14:21, Chuck Zmudzinski wrote:
On 3/14/2023 9:41 AM, Mark Cave-Ayland wrote:
On 14/03/2023 13:26, Chuck Zmudzinski wrote:
On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
On 14/03/2023 06:33, Michael S. Tsirkin
On Mon, 13 Mar 2023 at 18:59, Richard Henderson
wrote:
>
> Version 3 fixes a rebase error from v2 affecting ARM BFC insn.
>
>
> r~
>
>
> The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
>
> Merge tag 'linux-user-for-8.0-pull-request' of
>
On 14/03/2023 15.08, Peter Maydell wrote:
On Tue, 14 Mar 2023 at 14:01, Thomas Huth wrote:
On 14/03/2023 14.33, Peter Maydell wrote:
The postcopy/preempt tests seem to have a race which makes them hang
on the s390x CI runner. Disable them for the moment, while we
investigate. As with the
On Tue, 14 Mar 2023 at 14:14, Thomas Huth wrote:
>
> On 14/03/2023 15.08, Peter Maydell wrote:
> > On Tue, 14 Mar 2023 at 14:01, Thomas Huth wrote:
> >>
> >> On 14/03/2023 14.33, Peter Maydell wrote:
> >>> The postcopy/preempt tests seem to have a race which makes them hang
> >>> on the s390x CI
On 3/14/2023 9:41 AM, Mark Cave-Ayland wrote:
> On 14/03/2023 13:26, Chuck Zmudzinski wrote:
>
> > On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
> >> On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
> >>> On 14/03/2023 06:33, Michael S. Tsirkin wrote:
> >>>
> On Tue, Mar
On 3/14/2023 9:41 AM, Mark Cave-Ayland wrote:
> On 14/03/2023 13:26, Chuck Zmudzinski wrote:
>
> > On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
> >> On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
> >>> On 14/03/2023 06:33, Michael S. Tsirkin wrote:
> >>>
> On Tue, Mar
On Tue, 14 Mar 2023 at 14:01, Thomas Huth wrote:
>
> On 14/03/2023 14.33, Peter Maydell wrote:
> > The postcopy/preempt tests seem to have a race which makes them hang
> > on the s390x CI runner. Disable them for the moment, while we
> > investigate. As with the other disabled subtest, you can
On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
> On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
> > On 14/03/2023 06:33, Michael S. Tsirkin wrote:
> >
> > > On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> > > > Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot
On 14/03/2023 14.33, Peter Maydell wrote:
The postcopy/preempt tests seem to have a race which makes them hang
on the s390x CI runner. Disable them for the moment, while we
investigate. As with the other disabled subtest, you can opt back in
by setting QEMU_TEST_FLAKY_TESTS=1 in your
From: Markus Armbruster
Ben is no longer with intel. He told me he expected to get back to
CXL, but it's not happening as quickly as he'd like, and that it's
best to remove him as maintainer. So let's do that.
Thank you for serving as maintainer, Ben!
Signed-off-by: Markus Armbruster
Daniel P. Berrangé writes:
> To just repeat the patch 5 description...
>
Queued to for-8.0/tweaks-and-fixes, thanks.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
From: Damien Hedde
Also update mailmap
Signed-off-by: Damien Hedde
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Message-Id: <20230213105227.2357-1-damien.he...@dahe.fr>
Signed-off-by: Laurent Vivier
---
.mailmap| 1 +
MAINTAINERS | 2 +-
2 files changed, 2 insertions(+),
/trivial-branch-for-8.0-pull-request
for you to fetch changes up to fcc8f37ca3eca968932e5da716ec5e7fc05fdcf4:
MAINTAINERS: Remove CXL maintainer Ben Widawsky (2023-03-14 14:46:38 +0100)
trivial branch pull request 20230314
Update
On 14/03/2023 13:26, Chuck Zmudzinski wrote:
On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
On 14/03/2023 06:33, Michael S. Tsirkin wrote:
On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
Commit
From: John Snow
Signed-off-by: John Snow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230202223121.252073-1-js...@redhat.com>
Signed-off-by: Laurent Vivier
---
qemu-options.hx | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> The postcopy/preempt tests seem to have a race which makes them hang
> on the s390x CI runner. Disable them for the moment, while we
> investigate. As with the other disabled subtest, you can opt back in
> by setting QEMU_TEST_FLAKY_TESTS=1 in
The postcopy/preempt tests seem to have a race which makes them hang
on the s390x CI runner. Disable them for the moment, while we
investigate. As with the other disabled subtest, you can opt back in
by setting QEMU_TEST_FLAKY_TESTS=1 in your environment.
Suggested-by: Dr. David Alan Gilbert
On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
> On 14/03/2023 06:33, Michael S. Tsirkin wrote:
>
> > On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> > > Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> > > uses slot_reserved_mask
On Tue, Mar 14, 2023 at 08:33:02AM -0400, Chuck Zmudzinski wrote:
> On 3/14/2023 2:33 AM, Michael S. Tsirkin wrote:
> > On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> > > Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> > > uses slot_reserved_mask to
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Tue, 14 Mar 2023 at 10:12, Dr. David Alan Gilbert
> wrote:
> >
> > Copying Peter Xu on this one since it's poscopy, especially the newer
> > postcopy preempt.
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > On Sun, 12 Mar 2023
On Tue, Mar 14, 2023 at 12:46:18PM +, Peter Maydell wrote:
> On Tue, 14 Mar 2023 at 10:12, Dr. David Alan Gilbert
> wrote:
> >
> > Copying Peter Xu on this one since it's poscopy, especially the newer
> > postcopy preempt.
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > On
On Tue, 14 Mar 2023 at 10:12, Dr. David Alan Gilbert
wrote:
>
> Copying Peter Xu on this one since it's poscopy, especially the newer
> postcopy preempt.
>
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > On Sun, 12 Mar 2023 at 14:06, Peter Maydell
> > wrote:
> > > Here's another one, on
On 14/03/2023 06:33, Michael S. Tsirkin wrote:
On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
uses slot_reserved_mask to reserve slot 2 for the Intel IGD for the
xenfv machine when the guest is
On 3/14/2023 2:33 AM, Michael S. Tsirkin wrote:
> On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> > Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> > uses slot_reserved_mask to reserve slot 2 for the Intel IGD for the
> > xenfv machine when the guest
On Thu, Mar 09, 2023 at 11:39:44AM +, Richard W.M. Jones wrote:
> To implement multi-conn, we will put multiple underlying NBD
> connections (ie. NBDClientConnection) inside the NBD block device
> handle (BDRVNBDState). This requires first breaking the one-to-one
> relationship between
> > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> > index 7e5ad65c1d..d589f78202 100644
> > --- a/include/hw/cxl/cxl_device.h
> > +++ b/include/hw/cxl/cxl_device.h
> > @@ -232,6 +232,14 @@ REG64(CXL_MEM_DEV_STS, 0)
> > FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
> >
Hi Volker,
Thank you for the clarification. I see the problem now.
So is it safe to say that:
@@ -104,8 +104,9 @@ playback_on_process(void *data)
/* calculate the total no of bytes to read data from buffer */
req = b->requested * v->frame_size;
if (req == 0) {
-req = 4096
Currently, the kerneldoc Sphinx plugin doesn't honour the
--enable-werror configure option, so its warnings are never fatal.
This is because although we do pass sphinx-build the -W switch, the
warnings from kerneldoc are produced by the scripts/kernel-doc script
directly and don't go through
Chuang Xu writes:
> From: Peter Xu
>
> Calling RCU variance of address_space_get|to_flatview() during memory
"variants" rather than "variance", perhaps?
> commit (flatview updates, triggering memory listeners, or updating
> ioeventfds, etc.) is not 100% accurate, because commit() requires BQL
A PCI device can't magically become MSI-capable at runtime.
Guests aren't expecting that. Assert MSI is initialized
_before_ a device instance is realized.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci/msi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci/msi.c b/hw/pci/msi.c
This 'used' array is allocated via:
pci_qdev_realize() -> do_pci_register_device() -> pci_config_alloc()
In a perfect world where all device models are correctly QOM'ified
this can't happen. Still it occured to me while refactoring QDev and
it was not obvious to figure out. This assert helped,
PCI capabilities can't appear magically at runtime.
Guests aren't expecting that. Assert all capabilities
are added _before_ a device instance is realized.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci/pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c
Fix this format string warning when defining MSI_DEBUG:
hw/pci/msi.c:209:28: warning: format specifies type 'char' but the argument
has type 'unsigned int' [-Wformat]
offset, nr_vectors, msi64bit, msi_per_vector_mask);
Per MST in [*]: "Calling pci_add_capability when VM is running is
likely to confuse guests".
Ensure this can't happen by asserting pci_add_capability() is never
called after a PCI device is realized.
[*]
https://lore.kernel.org/qemu-devel/20230308071628-mutt-send-email-...@kernel.org/
Based-on:
On Monday, March 13, 2023 8:06:15 PM CET Dorinda Bassey wrote:
> >
> > Are you sure about sizeof(n_bytes) here? That's 4. ;-)
> >
> my bad!
>
> >
> > Volker's point was that "silence" is the center of the wave range. With
> > signed
> > range that's zero, yes, but with unsigned range that's
Hi,
Currently loading bad PSW flags does not lead to an exception, which is
not correct. This series fixes this by implementing what PoP calls
"Early Exception Recognition". Since it applies to both loading PSW with
LPSW/LPSWE and to interrupt handling, s390_cpu_set_psw() looks like the
right
Generate specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addresing
mode.
Reported-by: Nina Schoetterl-Glausch
Signed-off-by: Ilya Leoshkevich
---
target/s390x/cpu.c | 26 ++
Add a small test that checks whether early exceptions are recognized
and whether the correct ILC and old PSW are stored when they happen.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.softmmu-target | 1 +
tests/tcg/s390x/early-exception-recognition.S | 38
On Tue, Mar 14, 2023 at 4:35 AM David Woodhouse wrote:
>
> From: David Woodhouse
>
> When dm_restrict is set, QEMU isn't permitted to update the XenStore node
> to indicate its running status. Previously, the xs_write() call would fail
> but the failure was ignored.
>
> However, in refactoring
On Tue, Jan 17, 2023 at 07:16:35PM +0100, Pavel Pisa wrote:
> Dear Ben,
>
> sorry for longer response times...
I think we've both dropped the ball on this one, just got reminded about
this set and found it got deleted from work email.
We've done review upates and will try and get some branches
On 14/3/23 11:00, Dinah Baum wrote:
Moved architecture agnostic data types to their own
file to avoid "attempt to use poisoned TARGET_*"
error that results when including qapi header
with commands that aren't defined for all architectures.
Required to implement enabling
On 27/2/23 17:31, Jonathan Cameron wrote:
From: Gregory Price
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 84
Both TCG and KVM emulate ckc, cputm, last_break and prefix, and it's
quite useful to have them during debugging. Right now they are grouped
together with KVM-only pp, pfault_token, pfault_select and
pfault_compare in s390-virt.xml, and are not available when debugging
TCG-emulated code.
Move
Copying Peter Xu on this one since it's poscopy, especially the newer
postcopy preempt.
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Sun, 12 Mar 2023 at 14:06, Peter Maydell wrote:
> >
> > On Tue, 7 Mar 2023 at 09:53, Peter Maydell wrote:
> > >
> > > On Sat, 4 Mar 2023 at 15:39, Peter
On Mon, 13 Mar 2023 at 14:11, Thomas Huth wrote:
>
> Hi Peter!
>
> The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
>
> Merge tag 'linux-user-for-8.0-pull-request' of
> https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00
> +)
>
> are
This patch enables 'query-cpu-model-expansion' on all
architectures. Only architectures that implement
the command will return results, others will return an
error message as before.
This patch lays the groundwork for parsing a
-cpu cpu,help option as specified in
Change parsing of -cpu argument to allow -cpu cpu,help
to print options for the CPU type similar to
how the '-device' option works.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1480
Signed-off-by: Dinah Baum
---
cpu.c | 41 +++
Moved architecture agnostic data types to their own
file to avoid "attempt to use poisoned TARGET_*"
error that results when including qapi header
with commands that aren't defined for all architectures.
Required to implement enabling `query-cpu-model-expansion`
on all architectures
Part 1 is a refactor/code motion patch for
qapi/machine target required for setup of
Part 2 which enables query-cpu-model-expansion
on all architectures
Part 3 implements the ',help' feature
Limitations:
Currently only 'FULL' expansion queries are implemented since
that's the only type enabled
On Tue, 2023-03-14 at 08:06 +0100, Christian Borntraeger wrote:
>
>
> Am 13.03.23 um 22:16 schrieb Ilya Leoshkevich:
> > TCG emulates ckc, cputm, last_break and prefix, and it's quite
> > useful
> > to have them during debugging.
>
> KVM provides those as well so I dont get what you are trying
On Mon, Mar 13, 2023 at 5:32 PM Kevin Wolf wrote:
> > So I still think that this bug is a symptom of a problem in the design
> > of request queuing.
> >
> > In fact, shouldn't request queuing was enabled at the _end_ of
> > bdrv_drained_begin (once the BlockBackend has reached a quiescent
> >
On 14.03.23 00:38, Ilya Leoshkevich wrote:
The code uses the wrong base for relative addressing: it should use the
target instruction address and not the EXECUTE's address.
Fix by storing the target instruction address in the new CPUS390XState
member and loading it from the code generated by
On 14/03/2023 08:35, David Woodhouse wrote:
From: David Woodhouse
When dm_restrict is set, QEMU isn't permitted to update the XenStore node
to indicate its running status. Previously, the xs_write() call would fail
but the failure was ignored.
However, in refactoring to allow for emulated
From: David Woodhouse
When dm_restrict is set, QEMU isn't permitted to update the XenStore node
to indicate its running status. Previously, the xs_write() call would fail
but the failure was ignored.
However, in refactoring to allow for emulated XenStore operations, a new
call to xs_open() was
On Mon, 2023-03-13 at 19:17 -0400, Jason Andryuk wrote:
> This looks good, better than what I posted, and seems to work for both
> dm_restrict set and unset.
Thanks.
> For dm_restricted, xs_write() does fail. I verified that with a print
> statement. I think "shouldn't even try" makes sense.
On 3/13/23 19:21, Richard Henderson wrote:
On 3/13/23 04:44, Luis Machado wrote:
Luis: I think that rather than doing (2) with a QEMU namespace,
we should define a gdb namespace for this. That makes it clear
that this is still a gdb-upstream-sanctioned way of exposing
the pauth registers.
Am 13.03.23 um 22:16 schrieb Ilya Leoshkevich:
TCG emulates ckc, cputm, last_break and prefix, and it's quite useful
to have them during debugging.
KVM provides those as well so I dont get what you are trying to do here. (I
would understand moving out the pfault things into a KVM section)
I'm sorry for sending ill-formed thread twice.
This problem was because the SMTP server overwrites Message-ID,
and git-sendemail does not reflect it to In-Reply-To: and Reply-To: in the
header.
I will test well before sending the next patch.
The original cover letter was
This patch series adds qemu_strerror() function, which is thread-safe
version of the libc strerror(). The first patch introduces the
qemu_strerror() function, and the second patch replaces strerror()
function in linux-user/* with qemu_strerror() function.
Because it involves thread safety,
strerror() is not guaranteed to be thread-safe as described in
(https://gitlab.com/qemu-project/qemu/-/issues/416).
This commit changes files under /linux-user that call strerror() to call
the safer qemu_strerror().
Signed-off-by: Yohei Kojima
---
linux-user/elfload.c | 4 ++--
Add qemu_strerror() which follows the POSIX specification for
strerror(). While strerror() is not guaranteed to be thread-safe, this
function is thread-safe.
This function is added to solve the following issue:
https://gitlab.com/qemu-project/qemu/-/issues/416
Signed-off-by: Yohei Kojima
---
From: Ivan Klokov
The decoding of the slli_uw currently contains decoding
error: shamt part of opcode has six bits, not five.
Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw")
Signed-off-by: Ivan Klokov
Reviewed-by: Philipp Tomsich
Acked-by: Alistair Francis
From: Mikhail Tyutin
Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg
instructions
Signed-off-by: Mikhail Tyutin
Reviewed-by: Alistair Francis
Message-Id: <3454991f-7f64-24c3-9a36-f5fa2cc38...@yadro.com>
Signed-off-by: Alistair Francis
---
disas/riscv.c | 19
/alistair23/qemu.git tags/pull-riscv-to-apply-20230314
for you to fetch changes up to 0d581506de803204c5a321100afa270573382932:
Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
(2023-03-14 16:36:43 +1000
On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> uses slot_reserved_mask to reserve slot 2 for the Intel IGD for the
> xenfv machine when the guest is configured for igd-passthru.
>
> A desired
Hi Jonathan,
On 3/3/23 16:09, Jonathan Cameron wrote:
Note there are several series ahead of this one and in particular
the RAS error injection series needs some QAPI review.
The QAPI stuff in this patch is similar but in essence very similar
to what we have in that series.
Whilst I'm an
On 3/3/23 16:09, Jonathan Cameron wrote:
Very simple implementation to allow testing of corresponding
kernel code. Note that for now we track each 64 byte section
independently. Whilst a valid implementation choice, it may
make sense to fuse entries so as to prove out more complex
corners of
On 3/13/23 7:40 PM, Philippe Mathieu-Daudé wrote:
On 25/2/23 07:35, Gavin Shan wrote:
For some architectures like ARM64, multiple CPUs in one cluster can be
associated with different NUMA nodes, which is irregular configuration
because we shouldn't have this in baremetal environment. The
On 3/3/23 16:09, Jonathan Cameron wrote:
Inject poison using qmp command cxl-inject-poison to add an entry to the
poison list.
For now, the poison is not returned CXL.mem reads,
What do you mean?
but only via the
mailbox command Get Poison List.
See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison
On Wed, Mar 8, 2023 at 4:10 AM Philipp Tomsich wrote:
>
> The Zicond standard extension implements the same instruction
> semantics as XVentanaCondOps, although using different mnemonics and
> opcodes.
>
> Point XVentanaCondOps to the (newly implemented) Zicond implementation
> to reduce the
On Wed, Mar 8, 2023 at 4:10 AM Philipp Tomsich wrote:
>
> After the original Zicond support was stuck/fell through the cracks on
> the mailing list at v3 (and a different implementation was merged in
> the meanwhile), we need to refactor Zicond to prepare it to be reused
> by XVentanaCondOps.
>
>
On 3/3/23 16:09, Jonathan Cameron wrote:
From: Ira Weiny
CXL has 24 bit unaligned fields which need to be stored to. CXL is
specified as little endian.
Define st24_le_p() and the supporting functions to store such a field
from a 32 bit host native value.
The use of b, w, l, q as the size
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