On 12.08.23 08:21, ThinerLogoer wrote:
At 2023-08-11 22:31:36, "Peter Xu" wrote:
On Fri, Aug 11, 2023 at 01:49:52PM +0800, ThinerLogoer wrote:
At 2023-08-11 05:24:43, "Peter Xu" wrote:
On Fri, Aug 11, 2023 at 01:06:12AM +0800, ThinerLogoer wrote:
I think we have the following options (there
On 22/8/23 14:52, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/loongarch/insn_trans/trans_bit.c.inc | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/target/loongarch/insn_trans/trans_bit.c.inc
b/target/loongarch/insn_trans/
On 22.08.23 15:27, Markus Armbruster wrote:
David Hildenbrand writes:
For now, "share=off,readonly=on" would always result in us opening the
file R/O and mmap'ing the opened file MAP_PRIVATE R/O -- effectively
turning it into ROM.
Especially for VM templating, "share=off" is a common use case
On 22/8/23 14:51, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/loongarch/insn_trans/trans_bit.c.inc | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/target/loongarch/insn_trans/trans_bit.c.inc
b/target/loongarch/insn_trans/
On 22/8/23 14:40, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/cris/translate.c | 20 +---
target/cris/translate_v10.c.inc | 2 +-
2 files changed, 2 insertions(+), 20 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/
David Hildenbrand writes:
> For now, "share=off,readonly=on" would always result in us opening the
> file R/O and mmap'ing the opened file MAP_PRIVATE R/O -- effectively
> turning it into ROM.
>
> Especially for VM templating, "share=off" is a common use case. However,
> that use case is impossib
On Tue, 22 Aug 2023 at 14:06, Philippe Mathieu-Daudé wrote:
>
> On 22/8/23 13:44, Peter Maydell wrote:
> > On Tue, 22 Aug 2023 at 12:01, Philippe Mathieu-Daudé
> > wrote:
> >>
> >> Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
> >> introduced the generic hswap_i32(). Use it in
Hi Claudio,
On 22/8/23 14:00, Claudio Fontana wrote:
Hello,
this series is all reviewed,
and is needed as a precondition for further work to improve dramatically the
performance of virsh save, virsh restore
when migrating to disk, can it be merged?
$ ./scripts/get_maintainer.pl -f migration
On 22.08.23 15:13, ThinerLogoer wrote:
Hello,
At 2023-08-22 19:44:50, "David Hildenbrand" wrote:
There is a difference between how we open a file and how we mmap it,
and we want to support writable private mappings of readonly files. Let's
define RAM_READONLY and RAM_READONLY_FD flags, to repl
On 22.08.23 15:21, ThinerLogoer wrote:
Hello,
At 2023-08-22 19:44:56, "David Hildenbrand" wrote:
"-mem-path" corresponds to "memory-backend-file,share=off" and,
therefore, creates a private COW mapping of the file. For multi-proces
QEMU, we need proper shared file-backed memory.
Let's make th
Hello,
At 2023-08-22 19:44:56, "David Hildenbrand" wrote:
>"-mem-path" corresponds to "memory-backend-file,share=off" and,
>therefore, creates a private COW mapping of the file. For multi-proces
>QEMU, we need proper shared file-backed memory.
>
>Let's make that clearer.
>
>Signed-off-by: David H
On 16.06.23 12:47, Philippe Mathieu-Daudé wrote:
On 15/6/23 00:57, Alexander Graf wrote:
Instead of device tree or other more standardized means, VMApple passes
platform configuration to the first stage boot loader in a binary
encoded
format that resides at a dedicated RAM region in physical
On Tue, 22 Aug 2023 at 08:57, Philippe Mathieu-Daudé wrote:
>
> In early 2021 (see commit 2ad784339e "docs: update README to use
> GitLab repo URLs") almost all of the code base was converted to
> point to GitLab instead of git.qemu.org. During 2023, git.qemu.org
> switched from a git mirror to a
On Tue, 22 Aug 2023 at 03:57, Philippe Mathieu-Daudé wrote:
>
> In early 2021 (see commit 2ad784339e "docs: update README to use
> GitLab repo URLs") almost all of the code base was converted to
> point to GitLab instead of git.qemu.org. During 2023, git.qemu.org
> switched from a git mirror to a
Hello,
At 2023-08-22 19:44:50, "David Hildenbrand" wrote:
>There is a difference between how we open a file and how we mmap it,
>and we want to support writable private mappings of readonly files. Let's
>define RAM_READONLY and RAM_READONLY_FD flags, to replace the single
>"readonly" parameter fo
On 16.06.23 12:39, Philippe Mathieu-Daudé wrote:
On 15/6/23 00:56, Alexander Graf wrote:
The VMApple machine exposes AUX and ROOT block devices (as well as
USB OTG
emulation) via virtio-pci as well as a special, simple backdoor platform
device.
This patch implements this backdoor platform de
On 22/8/23 13:44, Peter Maydell wrote:
On Tue, 22 Aug 2023 at 12:01, Philippe Mathieu-Daudé wrote:
Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
introduced the generic hswap_i32(). Use it instead of open-coding
it as t_gen_swapw().
Signed-off-by: Philippe Mathieu-Daudé
---
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 08ee745a6d..822b932262 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mip
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 4f34ea9b6a..08ee745a6d 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/t
In early 2021 (see commit 2ad784339e "docs: update README to use
GitLab repo URLs") almost all of the code base was converted to
point to GitLab instead of git.qemu.org. During 2023, git.qemu.org
switched from a git mirror to a http redirect to GitLab (see [1]).
Update the LICENSE URL to match its
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/translate.c | 10 +-
target/ppc/translate/vsx-impl.c.inc | 19 ++-
2 files changed, 3 insertions(+), 26 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 74796ec7ba..91a9ec2d1c
Signed-off-by: Philippe Mathieu-Daudé
---
target/loongarch/insn_trans/trans_bit.c.inc | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/target/loongarch/insn_trans/trans_bit.c.inc
b/target/loongarch/insn_trans/trans_bit.c.inc
index c04806dc21..9d564a0999 100644
Signed-off-by: Philippe Mathieu-Daudé
---
target/loongarch/insn_trans/trans_bit.c.inc | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/target/loongarch/insn_trans/trans_bit.c.inc
b/target/loongarch/insn_trans/trans_bit.c.inc
index 95b4ee5bc8..c04806dc21 100644
tcg_gen_hrev32_i64() is similar to tcg_gen_hrev64_i64() but
only modifies the lower 32-bit of a 64-bit value.
tcg_gen_hrev_i64() can be used when we don't know at build
time whether to clear the 32 high bits of the value or not.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/tcg-ops.rst
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate-a64.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 5fa1257d32..2973831b38 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/t
Similarly to tcg_gen_hrev32_i32() for 32-bit values,
extract tcg_gen_hrev64_i64() for 64-bit ones.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/tcg-ops.rst | 4 +++-
include/tcg/tcg-op-common.h | 1 +
tcg/tcg-op.c| 29 +++--
3 files changed,
Signed-off-by: Philippe Mathieu-Daudé
---
target/cris/translate.c | 20 +---
target/cris/translate_v10.c.inc | 2 +-
2 files changed, 2 insertions(+), 20 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 925ed2c6f6..00bbe6c645 100644
--- a
This series factor the "byteswap each halfword within a
32/64-bit value" code duplication as generic helpers.
Modulo the documentation added, there is a good negative
diff-stat, so I believe this is a win from a maintainance
point of view.
I used "hrev" to follow the other bswap/hswap/rev helpers
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate-a32.h | 1 -
target/arm/tcg/translate-neon.c | 2 +-
target/arm/tcg/translate.c | 14 +-
3 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate
Byteswapping each halfword is a common operation, so
extract to a new tcg_gen_hrev32_i32() generic helper.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/tcg-ops.rst | 4
include/tcg/tcg-op-common.h | 1 +
tcg/tcg-op.c| 29 +++--
3 files
Signed-off-by: Philippe Mathieu-Daudé
---
target/rx/translate.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index f552a0319a..75590ae05e 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -1513,13 +1513,7
Implement the callback for getting the architecture-dependent CPU
ID, the cpu ID is physical id described in ACPI MADT table, this
will be used for cpu hotplug.
Signed-off-by: Bibo Mao
Change-Id: I53bcfb9f4279e491f33e8b99a9102534ad53409e
---
hw/loongarch/virt.c| 2 ++
target/loongarch/cpu.c
Hello,
this series is all reviewed,
and is needed as a precondition for further work to improve dramatically the
performance of virsh save, virsh restore
when migrating to disk, can it be merged?
Thanks,
Claudio
On 8/16/23 20:28, Fabiano Rosas wrote:
> For v2 I fixed patch 3 which had a hunk
Apologies, already reviewed, will ping for the merge of the series momentarily,
Claudio
On 8/22/23 14:18, Claudio Fontana wrote:
> Hello,
>
> this patch would still need a review,
>
> and is needed as a precondition for further work to improve dramatically the
> performance of virsh save, virs
Hello,
this patch would still need a review,
and is needed as a precondition for further work to improve dramatically the
performance of virsh save, virsh restore
when migrating to disk, since Peter Xu already reviewed PATCH 1, 2, 3, maybe it
makes sense to look at 4 too?
Thanks,
Claudio
On
Hello,
this patch is reviewed,
and is needed as a precondition for further work to improve dramatically the
performance of virsh save, virsh restore
when migrating to disk, can it be merged?
Thanks,
Claudio
On 7/25/23 15:26, Fabiano Rosas wrote:
> From: Nikolay Borisov
>
> Extract the rambl
Hello,
this series is all reviewed,
and is needed as a precondition for further work to improve dramatically the
performance of virsh save, virsh restore
when migrating to disk, can it be merged?
Thanks,
Claudio
On 7/12/23 21:07, Fabiano Rosas wrote:
> Based-on:
> [PATCH V4 0/2] migration fil
Hello,
this series is all reviewed,
and is needed as a precondition for further work to improve dramatically the
performance of virsh save, virsh restore
when migrating to disk, can it be merged?
Thanks,
Claudio
On 6/30/23 16:25, Steve Sistare wrote:
> Add the migration URI "file:filename[,of
On Tue, 22 Aug 2023 at 12:02, Philippe Mathieu-Daudé wrote:
>
> Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
> introduced the generic hswap_i32(). Use it instead of open-coding
> it in gen_bshfl().
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/tcg/translate.c
Hi all,
we currently have to maintain something downstream for this, since the current
behavior can compound problems on top of existing bad NFS latency,
could someone continue to help reviewing this work?
Thanks,
Claudio
On 6/9/23 22:19, Fabiano Rosas wrote:
> Hi,
>
> The major change from
"-mem-path" corresponds to "memory-backend-file,share=off" and,
therefore, creates a private COW mapping of the file. For multi-proces
QEMU, we need proper shared file-backed memory.
Let's make that clearer.
Signed-off-by: David Hildenbrand
---
docs/devel/multi-process.rst | 5 +++--
1 file cha
Let's add some details about VM templating, focusing on the VM memory
configuration only.
There is much more to VM templating (VM state? block devices?), but I leave
that as future work.
Signed-off-by: David Hildenbrand
---
docs/vm-templating.txt | 109 +
fallocate() will fail, let's print a nicer error message.
Suggested-by: Peter Xu
Signed-off-by: David Hildenbrand
---
softmmu/physmem.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 2ed83fcefe..817a7811ee 100644
--- a/softmmu/physmem
open() does not fail on directories when opening them readonly (O_RDONLY).
Currently, we succeed opening such directories and fail later during
mmap(), resulting in a misleading error message.
$ ./qemu-system-x86_64 \
-object memory-backend-file,id=ram0,mem-path=tmp,readonly=true,size=1g
qem
Currently, if a file does not exist yet, file_ram_open() will create new
empty file and open it writable. However, it even does that when
readonly=true was specified.
Specifying O_RDONLY instead to create a new readonly file would
theoretically work, however, ftruncate() will refuse to resize the
For now, "share=off,readonly=on" would always result in us opening the
file R/O and mmap'ing the opened file MAP_PRIVATE R/O -- effectively
turning it into ROM.
Especially for VM templating, "share=off" is a common use case. However,
that use case is impossible with files that lack write permissio
Let's remap with the proper protection that we can derive from
RAM_READONLY.
Signed-off-by: David Hildenbrand
---
softmmu/physmem.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 16d7a16aa8..2ed83fcefe 100644
--- a/softm
This is the result of the previous discussion of:
* "[PATCH v2] softmmu/physmem: try opening file readonly before failure
in file_ram_open" [1]
* "[PATCH v1 0/3] softmmu/physmem: file_ram_open() readonly
improvements" [2]
After looking into various ways to avoid a new parameter for
memory-ba
On Tue, 22 Aug 2023 at 12:01, Philippe Mathieu-Daudé wrote:
>
> Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
> introduced the generic hswap_i32(). Use it instead of open-coding
> it as t_gen_swapw().
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/cris/translate.c
Currently, when using a true R/O NVDIMM (ROM memory backend) with a label
area, the VM can easily crash QEMU by trying to write to the label area,
because the ROM memory is mmap'ed without PROT_WRITE.
[root@vm-0 ~]# ndctl disable-region region0
disabled 1 region
[root@vm-0 ~]# ndctl ze
There is a difference between how we open a file and how we mmap it,
and we want to support writable private mappings of readonly files. Let's
define RAM_READONLY and RAM_READONLY_FD flags, to replace the single
"readonly" parameter for file-related functions.
In memory_region_init_ram_from_fd() a
Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
introduced the generic hswap_i32(). Use it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/sh4/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index
Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
introduced the generic hswap_i32(). Use it instead of open-coding
it as gen_swaph().
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/translate.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/
Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
introduced the generic hswap_i32(). Use it instead of open-coding
it as gen_revh_d().
Signed-off-by: Philippe Mathieu-Daudé
---
target/loongarch/insn_trans/trans_bit.c.inc | 16 +---
1 file changed, 1 insertion(+), 15 d
Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
introduced the generic hswap_i32(). Use it instead of open-coding
it in gen_bshfl().
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff -
Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
introduced the generic hswap_i32(). Use it instead of open-coding
it as gen_swap_half().
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate-a32.h | 6 --
target/arm/tcg/translate-neon.c | 4 ++--
target/arm/tcg
Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
introduced the generic hswap_i32(). Use it instead of open-coding
it as t_gen_swapw().
Signed-off-by: Philippe Mathieu-Daudé
---
target/cris/translate.c | 14 +-
target/cris/translate_v10.c.inc | 2 +-
2 files
Some targets open-code gen_hswap();
replace by the generic helper.
Philippe Mathieu-Daudé (6):
target/arm: Use hswap_i32() in VREV/SMLAD opcodes
target/cris: Use hswap_i32() in SWAPW opcode
target/microblaze: Use hswap_i32() in SWAPH opcode
target/sh4: Use hswap_i32() in SWAP.W opcode
ta
> On Aug 22, 2023, at 12:49 AM, Li Feng wrote:
>
>
>
>> On 22 Aug 2023, at 8:38 AM, Raphael Norwitz
>> wrote:
>>
>>>
>>> On Aug 17, 2023, at 2:40 AM, Li Feng wrote:
>>>
>>>
2023年8月14日 下午8:11，Raphael Norwitz 写道：
Why can’t we rather fix this by adding a “event_cb” param
When clearing a bitfield we don't need to lead the
source register. Use deposit_z_i32() with the BFC
opcode to save a load_reg() call.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/arm/tcg/
On Tue, 22 Aug 2023 at 10:01, Alex Bennée wrote:
>
>
> Igor Lesik writes:
>
> > Hi.
> >
> > I am wondering why trace events like trace_exec_tb(tb, pc) do not have
> > cpu index, how to make sense of the trace in case of multiple vCPUs?
> > I have changed it to trace_exec_tb(tb, pc, cpu->cpu_index
On Tue, 22 Aug 2023 at 05:25, Richard Henderson
wrote:
>
> This is an update of Aaron's v3 [1].
> There are a fair number of changes beyond a mere rebase:
>
> * Updates to the test cases which fail with the new features.
> * Updates to the documentation.
> * Preserve pauth feature set when c
Signed-off-by: Philippe Mathieu-Daudé
---
target/cris/translate.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 0b3d724281..42103b5558 100644
--- a/target/cris/translate.c
+++ b/target/cris/transla
Signed-off-by: Philippe Mathieu-Daudé
---
tcg/tcg-op.c | 48
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 7aadb37756..f164ddc95e 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1021,6 +1021,13 @
Document wswap_i64(), added in commit 46be8425ff
("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}").
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/tcg-ops.rst | 4
tcg/tcg-op.c | 5 +
2 files changed, 9 insertions(+)
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops
Signed-off-by: Philippe Mathieu-Daudé
---
tcg/tcg-op.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index e6b0d74a46..f4fe13e040 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1828,6 +1828,11 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int
fl
Document deposit_z_i32() and deposit_z_i64(), added in
commit 07cc68d528 ("tcg: Add deposit_z expander").
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/tcg-ops.rst | 4
1 file changed, 4 insertions(+)
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
index 306025ece7..7ea
Document hswap_i32() and hswap_i64(), added in commit
46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}").
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/tcg-ops.rst | 4
tcg/tcg-op.c | 26 +++---
2 files changed, 23 insertions(+), 7 deletions(-)
Signed-off-by: Philippe Mathieu-Daudé
---
tcg/tcg-op.c | 12
1 file changed, 12 insertions(+)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index f164ddc95e..e6b0d74a46 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1061,6 +1061,11 @@ void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg
While reviewing a recent patch from Richard optimizing
deposit() [*] I ended looking at the *swap friends, taking
some notes, which then evolved to proper documentation.
[*]
https://lore.kernel.org/qemu-devel/20230816145547.477974-3-richard.hender...@linaro.org/
Philippe Mathieu-Daudé (7):
tcg
Igor Lesik writes:
> Hi.
>
> I am wondering why trace events like trace_exec_tb(tb, pc) do not have
> cpu index, how to make sense of the trace in case of multiple vCPUs?
> I have changed it to trace_exec_tb(tb, pc, cpu->cpu_index) to read my
> trace, and now wondering should not it be there by
On Tue, Aug 22, 2023 at 4:53 PM Eugenio Pérez wrote:
>
> Doing that way allows CVQ to be enabled before the dataplane vqs,
> restoring the state as MQ or MAC addresses properly in the case of a
> migration.
>
> The patch does it by defining a ->load NetClientInfo callback also for
> dataplane. Id
Previous to this patch the only way CVQ would be shadowed is if it does
support to isolate CVQ group or if all vqs were shadowed from the
beginning. The second condition was checked at the beginning, and no
more configuration was done.
After this series we need to check if data queues are shadowe
The vhost-vdpa net backend needs to enable vrings in a different order
than default, so export it.
No functional change intended except for tracing, that now includes the
(virtio) index being enabled and the return value of the ioctl.
Still ignoring return value of this function if called from
vh
Now that we have add migration blockers if the device does not support
all the needed features, remove the general blocker applied to all net
devices with CVQ.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
net/vhost-vdpa.c | 12
1 file changed, 12 deletions(-)
diff --git a
Volker Rümelin writes:
> Am 21.08.23 um 08:06 schrieb Manos Pitsidianakis:
>
> Hello Volker!
>
> On Sun, 20 Aug 2023 12:33, Volker Rümelin wrote:
>
> I think the virtio-snd.c code, the trace events and the Kconfig VIRTIO_SND
> should be moved to hw/audio. The
> code for nearly all audio
At this moment the migration of net features that depends on CVQ is not
possible, as there is no reliable way to restore the device state like mac
address, number of enabled queues, etc to the destination. This is mainly
caused because the device must only read CVQ, and process all the commands
be
Next patches will add the corresponding data load.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
---
net/vhost-vdpa.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index a772540250..9251351b4b 100644
--- a/net/vhost-vdpa.c
+++ b/
Doing that way allows CVQ to be enabled before the dataplane vqs,
restoring the state as MQ or MAC addresses properly in the case of a
migration.
The patch does it by defining a ->load NetClientInfo callback also for
dataplane. Ideally, this should be done by an independent patch, but
the functio
On 8/22/2023 2:27 PM, Markus Armbruster wrote:
Daniel P. Berrangé writes:
On Fri, Aug 18, 2023 at 05:49:58AM -0400, Xiaoyao Li wrote:
Bit 28 of TD attribute, named SEPT_VE_DISABLE. When set to 1, it disables
EPT violation conversion to #VE on guest TD access of PENDING pages.
Some guest OS (
On Tue, Aug 22, 2023 at 4:09 PM Eugenio Perez Martin
wrote:
>
> On Mon, Aug 14, 2023 at 8:57 AM Jason Wang wrote:
> >
> > On Thu, Aug 10, 2023 at 11:36 PM Eugenio Pérez wrote:
> > >
> > > Doing that way allows CVQ to be enabled before the dataplane vqs,
> > > restoring the state as MQ or MAC add
On Tue, Aug 22, 2023 at 09:56:12AM +0200, Philippe Mathieu-Daudé wrote:
> In early 2021 (see commit 2ad784339e "docs: update README to use
> GitLab repo URLs") almost all of the code base was converted to
> point to GitLab instead of git.qemu.org. During 2023, git.qemu.org
> switched from a git mir
On Tue, Aug 22, 2023 at 08:52:30AM +0200, Markus Armbruster wrote:
> Xiaoyao Li writes:
>
> > From: Isaku Yamahata
> >
> > For GetQuote, delegate a request to Quote Generation Service. Add property
> > of address of quote generation server and On request, connect to the
> > server, read request
在 2023/8/22 下午3:13, Philippe Mathieu-Daudé 写道:
Based-on: https://patchew.org/QEMU/20230821125959.28666-1-phi...@linaro.org/
(all series reviewed, for Song Gao to pick whichever v4/v5 is preferred)
Hi,
This series adds some checks before translating instructions
This includes:
CPUCFG[1].IOCSR
On Tue, Aug 22, 2023 at 03:31:44PM +0800, Xiaoyao Li wrote:
> On 8/21/2023 4:46 PM, Daniel P. Berrangé wrote:
> > On Fri, Aug 18, 2023 at 05:49:49AM -0400, Xiaoyao Li wrote:
> > > KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of
> > > IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capab
On Mon, Aug 14, 2023 at 8:57 AM Jason Wang wrote:
>
> On Thu, Aug 10, 2023 at 11:36 PM Eugenio Pérez wrote:
> >
> > Doing that way allows CVQ to be enabled before the dataplane vqs,
> > restoring the state as MQ or MAC addresses properly in the case of a
> > migration.
> >
>
> A typo in the subje
On 8/18/2023 3:33 AM, Isaku Yamahata wrote:
> On Wed, Aug 16, 2023 at 04:06:56PM +0800,
> Qian Wen wrote:
>
>> CPUID.1.EBX[23:16]: Maximum number of addressable IDs for logical
>> processors in this physical package.
>> CPUID.4:EAX[31:26]: Maximum number of addressable IDs for processor cores
>> i
In early 2021 (see commit 2ad784339e "docs: update README to use
GitLab repo URLs") almost all of the code base was converted to
point to GitLab instead of git.qemu.org. During 2023, git.qemu.org
switched from a git mirror to a http redirect to GitLab (see [*]).
Update the LICENSE URL to match its
On 8/21/2023 4:48 PM, Daniel P. Berrangé wrote:
On Fri, Aug 18, 2023 at 05:49:50AM -0400, Xiaoyao Li wrote:
It will need special handling for TDX VMs all around the QEMU.
Introduce is_tdx_vm() helper to query if it's a TDX VM.
Cache tdx_guest object thus no need to cast from ms->cgs every time.
On 22/8/23 02:00, Gurchetan Singh wrote:
This adds basic documentation for virtio-gpu.
Suggested-by: Akihiko Odaki
Signed-off-by: Gurchetan Singh
Tested-by: Alyssa Ross
Tested-by: Emmanouil Pitsidianakis
Reviewed-by: Emmanouil Pitsidianakis
---
docs/system/device-emulation.rst | 1
Hi,
On 22/8/23 02:00, Gurchetan Singh wrote:
This adds initial support for gfxstream and cross-domain. Both
features rely on virtio-gpu blob resources and context types, which
are also implemented in this patch.
[...]
hw/display/virtio-gpu-pci-rutabaga.c | 48 ++
hw/display/virtio-gpu-r
On 8/21/2023 4:46 PM, Daniel P. Berrangé wrote:
On Fri, Aug 18, 2023 at 05:49:49AM -0400, Xiaoyao Li wrote:
KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of
IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capabilities when initializing
TDX context. It will be used to validate user's s
Guests typically enable MSI-X with all of the vectors masked in the MSI-X
vector table. To match the guest state of device, Qemu enables MSI-X by
enabling vector 0 with userspace triggering and immediately release.
However the release function actually does not release it due to already
using users
Changes since RFC v1:
- RFC v1: https://www.mail-archive.com/qemu-devel@nongnu.org/msg978637.html
- Revise the comments. (Alex)
- Report error of getting irq info and remove the trace of failure
case. (Alex, Cédric)
- Only store dynamic allocation flag as a bool type and test
accordingly. (Alex
From: Song Gao
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-ID: <20230822032724.1353391-15-gaos...@loongson.cn>
---
target/loongarch/translate.h|2 +
target/loongarch/insn_trans/trans_lsx.c.inc | 1396 +++
2 files changed, 780 insertions(+)
The vector_use callback is used to enable vector that is unmasked in
guest. The kernel used to only support static MSI-X allocation. When
allocating a new interrupt using "static MSI-X allocation" kernels,
Qemu first disables all previously allocated vectors and then
re-allocates all including the
During migration restoring, vfio_enable_vectors() is called to restore
enabling MSI-X interrupts for assigned devices. It sets the range from
0 to nr_vectors to kernel to enable MSI-X and the vectors unmasked in
guest. During the MSI-X enabling, all the vectors within the range are
allocated accord
Kernel provides the guidance of dynamic MSI-X allocation support of
passthrough device, by clearing the VFIO_IRQ_INFO_NORESIZE flag to
guide user space.
Fetch the flags from host to determine if dynamic MSI-X allocation is
supported.
Originally-by: Reinette Chatre
Signed-off-by: Jing Liu
---
Ch
On Thu, Aug 17, 2023 at 12:29:03PM -0300, Daniel Henrique Barboza wrote:
> In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times
> longer to boot than the 'rv64' KVM CPU.
>
> The reason is an unintended behavior of riscv_cpu_satp_mode_finalize()
> when satp_mode.supported = 0, i.e. wh
From: Song Gao
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-ID: <20230822032724.1353391-16-gaos...@loongson.cn>
---
target/loongarch/translate.h | 2 +-
.../loongarch/insn_trans/trans_privileged.c.inc | 16
2 files changed, 9 insertions(
201 - 300 of 331 matches
Mail list logo
