On Sat, 25 May 2024 at 00:28, Richard Henderson
wrote:
>
> No need for a full comparison; xor produces non-zero bits
> for QC just fine.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On 5/27/2024 1:45 PM, Peter Xu wrote:
On Tue, May 21, 2024 at 07:46:12AM -0400, Steven Sistare wrote:
I understand, thanks. If I can help with any of your todo list,
just ask - steve
Thanks for offering the help, Steve. Started looking at this today, then I
found that I miss something high-l
On 5/27/2024 2:20 PM, Peter Xu wrote:
On Mon, Apr 29, 2024 at 08:55:16AM -0700, Steve Sistare wrote:
Define a type for the 256 byte id string to guarantee the same length is
used and enforced everywhere.
Signed-off-by: Steve Sistare
---
include/exec/ramblock.h | 3 ++-
include/migration
On 5/27/2024 2:31 PM, Peter Xu wrote:
On Mon, Apr 29, 2024 at 08:55:17AM -0700, Steve Sistare wrote:
Define VMSTATE_VOID_PTR so the value of a pointer (but not its target)
can be saved in the migration stream. This will be needed for CPR.
Signed-off-by: Steve Sistare
This is really tricky.
Am 30.04.2024 um 19:02 hat Denis V. Lunev via geschrieben:
> This parameter is always passed as 'false' from the caller.
>
> Signed-off-by: Denis V. Lunev
> CC: Andrey Zhadchenko
> CC: Kevin Wolf
> CC: Hanna Reitz
Let me add a "Since commit 72373e40fbc" to the commit message.
Thanks, applied
Am 28.05.2024 um 14:49 hat Vladimir Sementsov-Ogievskiy geschrieben:
> On 30.04.24 12:13, Vladimir Sementsov-Ogievskiy wrote:
> > We want to have similar QMP objects in different tests. Reworking these
> > objects to make common parts by calling some helper functions doesn't
> > seem good. It's a l
On 23/5/24 21:41, Inès Varhol wrote:
Expose the clock period via the QOM 'qtest-clock-period' property so it
can be used in QTests. This property is only accessible in QTests (not
via HMP).
Signed-off-by: Philippe Mathieu-Daudé
Addressing Luc and Peter comments, you can replace that line by:
Calling qemu_plugin_vcpu_init__async() on the vCPU thread
is a detail of plugins, not relevant to TCG vCPU management.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/cpu-exec-common.c | 11 ++-
plugins/core.c | 8 +++-
2 files changed, 9 insertions(+), 10 deletions
system/runstate.c never required "qemu/plugin.h".
Signed-off-by: Philippe Mathieu-Daudé
---
system/runstate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/system/runstate.c b/system/runstate.c
index cb4905a40f..ec32e270cb 100644
--- a/system/runstate.c
+++ b/system/runstate.c
@@ -45,7 +45,
Use the AccelClass::cpu_common_[un]realize_assigned() handlers
to [un]register the TCG plugin handlers, allowing to remove
accel specific code from the common hw/core/cpu-common.c file.
Remove the now unnecessary qemu_plugin_vcpu_init_hook() and
qemu_plugin_vcpu_exit_hook() stub.
Signed-off-by: P
Introduce handlers called while the vCPU has an assigned
index and is still in the global %cpus_queue.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/accel.h | 20
accel/accel-target.c | 23 +++
cpu-target.c | 6 ++
3 files changed, 4
In preparation of introducing [un]realize handlers for
when vCPUs are assigned, rename current handlers using
the '_unassigned' suffix.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-common.h | 4 ++--
include/qemu/accel.h| 17 +++--
accel/accel-target.c
'internal-target.h' is meant for target-specific declarations,
while 'internal-common.h' for common ones. Move common declarations
to it.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-common.h | 15 +++
accel/tcg/internal-target.h | 14 --
accel/tcg/tcg-all
Hi,
TL;DR; this series remove TCG plugin code from generic accel code.
Since the introduction of the scoreboard in plugins, the INIT
hook use the vCPU index, which is only available somewhere
during the vCPU REALIZE() step (see below for call tree).
In order to clarify that, we split accel_cpu_c
On Thu, 23 May 2024 at 20:44, Inès Varhol wrote:
>
> Expose the clock period via the QOM 'qtest-clock-period' property so it
> can be used in QTests. This property is only accessible in QTests (not
> via HMP).
>
> Signed-off-by: Philippe Mathieu-Daudé
> Signed-off-by: Inès Varhol
> ---
> docs/d
On Mon, 2024-05-27 at 14:13 +0200, Thomas Huth wrote:
> It's not used anywhere, so let's simply remove it.
>
> Signed-off-by: Thomas Huth
> ---
> include/hw/s390x/s390_flic.h | 3 ---
> 1 file changed, 3 deletions(-)
Reviewed-by: Eric Farman
On Thu, 23 May 2024 at 20:44, Inès Varhol wrote:
>
> For USART, GPIO and SYSCFG devices, check that clock frequency before
> and after enabling the peripheral clock in RCC is correct.
>
> Signed-off-by: Inès Varhol
> ---
> tests/qtest/stm32l4x5.h | 43 +
>
On Thu, 23 May 2024 at 20:44, Inès Varhol wrote:
>
> This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the
> corresponding clock from STM32L4x5 RCC.
>
> Signed-off-by: Inès Varhol
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, 23 May 2024 at 20:44, Inès Varhol wrote:
>
> `vmstate_stm32l4x5_usart_base` namely uses `VMSTATE_CLOCK` so
> version needs to be 2.
>
> Signed-off-by: Inès Varhol
> ---
> hw/char/stm32l4x5_usart.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/char/stm32l
On Wed, 22 May 2024 at 21:40, Inès Varhol wrote:
>
> The previous implementation for EXTI interrupts only handled
> "configurable" interrupts, like those originating from STM32L4x5 SYSCFG
> (the only device currently connected to the EXTI up until now).
>
> In order to connect STM32L4x5 USART to t
On 4/30/24 19:02, Denis V. Lunev wrote:
This parameter is always passed as 'false' from the caller.
Signed-off-by: Denis V. Lunev
CC: Andrey Zhadchenko
CC: Kevin Wolf
CC: Hanna Reitz
---
block/file-posix.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/block/f
On 4/30/24 19:05, Denis V. Lunev wrote:
Preallocate filter allows to implement really interesting setups.
Assume that we have
* shared block device, f.e. iSCSI LUN, implemented with some HW device
* clustered LVM on top of it
* QCOW2 image stored inside LVM volume
This allows very cheap cluster
Reviewed-by: Glenn Miles
Thanks,
Glenn
On Tue, 2024-05-28 at 16:20 +1000, Nicholas Piggin wrote:
> From: Glenn Miles
>
> The LPC HC irq status register bits are set when an LPC IRQSER input
> is
> asserted. These irq status bits drive the PSI irq to the CPU
> interrupt
> controller. The LPC H
On Tue, May 28, 2024 at 03:53:55PM +0800, Zhao Liu wrote:
> Hi Stefan,
>
> [snip]
>
> > > diff --git a/scripts/simpletrace-rust/.rustfmt.toml
> > > b/scripts/simpletrace-rust/.rustfmt.toml
> > > new file mode 100644
> > > index ..97a97c24ebfb
> > > --- /dev/null
> > > +++ b/scripts/s
From: Richard Henderson
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate.h |5 +
target/arm/tcg/gengvec.c | 1612 +++
From: Zenghui Yu
We wrongly encoded ID_AA64PFR1_EL1 using {3,0,0,4,2} in hvf_sreg_match[] so
we fail to get the expected ARMCPRegInfo from cp_regs hash table with the
wrong key.
Fix it with the correct encoding {3,0,0,4,1}. With that fixed, the Linux
guest can properly detect FEAT_SSBS2 on my M1
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-31-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 7 -
target/arm/tcg/translate-neon.c | 55 ++---
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 21 +++--
target/arm/tcg/translate-a64.c | 86 +++
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-17-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 43 +++-
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-36-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 10 +++
target/arm/tcg/translate-a64.c | 144 ++-
From: Richard Henderson
These are the last instructions within handle_simd_3same_pair
so remove it.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-34-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h|
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 11
target/arm/tcg/translate-a64.c | 97
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-18-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 13 +
target/arm/tcg/translate-a64.c | 426 +++--
From: Richard Henderson
All of these insns have "if sz == '1' then UNDEFINED" in their pseudocode.
Fixes a RISU miscompare for invalid insn 0x5ef0c87a.
Fixes: 5c36d89567c ("arm/translate-a64: add all FP16 ops in
simd_scalar_pairwise")
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-15-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 8 ++
target/arm/tcg/translate-a64.c | 132 +++-
From: Alexandra Diupina
Add xlnx_dpdma_read_descriptor() and
xlnx_dpdma_write_descriptor() functions.
xlnx_dpdma_read_descriptor() combines reading a
descriptor from desc_addr by calling dma_memory_read()
and swapping the desc fields from guest memory order
to host memory order. xlnx_dpdma_write_
From: Dorjoy Chowdhury
The value of the mp-affinity property being set in npcm7xx_realize is
always the same as the default value it would have when arm_cpu_realizefn
is called if the property is not set here. So there is no need to set
the property value in npcm7xx_realize function.
Signed-off-
From: Richard Henderson
These are the last instructions within disas_simd_three_reg_same_fp16,
so remove it.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-30-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 11 +
target/arm/tcg/translate-a64.c | 78 +--
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-21-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 4 +
target/arm/tcg/a64.decode | 17
target/arm/tcg/translate-a6
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-29-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 4 ++
target/arm/tcg/a64.decode | 12 +
target/arm/tcg/translate-a6
From: Richard Henderson
The decode of FMOV (vector, immediate, half-precision) vs
invalid cases of MOVI are incorrect.
Fixes RISU mismatch for invalid insn 0x2f01fd31.
Fixes: 70b4e6a4457 ("arm/translate-a64: add FP16 FMOV to simd_mod_imm")
Signed-off-by: Richard Henderson
Reviewed-by: Peter Ma
From: Philippe Mathieu-Daudé
Check the function index is in range and use an unsigned
variable to avoid the following warning with GCC 13.2.0:
[666/5358] Compiling C object libcommon.fa.p/hw_input_tsc2005.c.o
hw/input/tsc2005.c: In function 'tsc2005_timer_tick':
hw/input/tsc2005.c:416:26:
From: Richard Henderson
Load and zero-extend float16 into a TCGv_i32 before
all scalar operations.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240524232121.284515-22-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-vfp.c | 3
From: Inès Varhol
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Message-id: 20240505141613.387508-1-ines.var...@telecom-paris.fr
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/char/stm32l4x5_usart.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
From: Richard Henderson
Split some routines out of translate-a64.c and translate-sve.c
that are used by both.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-9-richard.hender...@linaro.org
Signed-off-by: Peter M
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-20-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-a64.h| 4 +
target/arm/tcg/translate.h | 5 +
target/arm/tcg/a64.decode
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-35-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-neon.c | 78 ++---
1 file changed, 4 insertions(+), 74 de
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-23-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 6
target/arm/tcg/translate.h | 30 +++
target/arm/
From: Richard Henderson
Convert all forms (scalar, vector, scalar indexed, vector indexed),
which allows us to remove switch table entries elsewhere.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-19-richard.hender...@linaro.org
Signed-off-by: Pet
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-25-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 2 +
target/arm/tcg/a64.decode | 22 +++
target/arm/tcg/translate-a64
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-32-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 5 ++
target/arm/tcg/translate.h | 3 +
target/arm/tcg/a64.decode
From: Tanmay Patil
Some of the source files for older devices use hardcoded tabs
instead of our current coding standard's required spaces.
Fix these in the following files:
- hw/arm/boot.c
- hw/char/omap_uart.c
- hw/gpio/zaurus.c
- hw/input/tsc2005.c
This commit i
From: Richard Henderson
This includes AND, ORR, EOR, BIC, ORN, BSF, BIT, BIF.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-37-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 10 +
target/arm/t
From: Richard Henderson
Fixes RISU mismatch for "fcvtzs h31, h0, #14".
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240524232121.284515-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 3 +++
1 file changed, 3 inser
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-33-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 2 --
target/arm/tcg/neon_helper.c| 5 -
target/arm/tcg/translate-ne
re available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20240528
for you to fetch changes up to f240df3c31b40e4cf1af1f156a88efc1a1df406c:
target/arm: Convert disas_simd_3same_logic to decodetree (2024-05-28
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-27-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 1 +
target/arm/tcg/a64.decode | 6
target/arm/tcg/translate-a64.
From: Richard Henderson
This fixes a bug in that neither PLI nor PLDW are present in ARMv6T2,
but are introduced with ARMv7 and ARMv7MP respectively.
For clarity, do not use NOP for PLD.
Note that there is no PLDW (literal). Architecturally in the
T1 encoding of "PLD (literal)" bit 5 is "(0)", w
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 5
target/arm/tcg/translate-a64.c | 50 ++--
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-26-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 5 +
target/arm/tcg/a64.decode | 30 ++
target/arm/tcg/translate-
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-12-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 6
target/arm/tcg/translate-a64.c | 54 +++-
From: Rayhan Faizel
None of the RPi boards have ADC on-board. In real life, an external ADC chip
is required to operate on analog signals.
Signed-off-by: Rayhan Faizel
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240512085716.222326-1-rayhan.fai...@gmail.com
Signed-off-by: Peter Maydell
From: Richard Henderson
This is the last instruction within disas_fp_2src,
so remove that and its subroutines.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-24-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.dec
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 10
target/arm/tcg/translate-a64.c | 43 ++--
From: Richard Henderson
These are the last instructions within handle_3same_float
and disas_simd_scalar_three_reg_same_fp16 so remove them.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240524232121.284515-28-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
On Mon, 20 May 2024 at 23:24, Cord Amfmgm wrote:
> On Mon, May 20, 2024 at 12:05 PM Peter Maydell
> wrote:
>> For the "zero length buffer" case, do you have a more detailed
>> pointer to the bit of the spec that says that "cbp = be + 1" is a
>> valid way to specify a zero length buffer? Table 4-
The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into
staging (2024-05-27 06:40:42 -0700)
are available in the Git repository at:
https://gitlab.com/vsementsov/qemu.git tags/pull-block-jobs-2024-
We want to have similar QMP objects in different tests. Reworking these
objects to make common parts by calling some helper functions doesn't
seem good. It's a lot more comfortable to see the whole QAPI request in
one place.
So, let's increase the limit, to unblock further commit
"iotests: add bac
On Tue, May 28, 2024 at 12:35 PM Thomas Huth wrote:
> > diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
> > index 84bc7fbe36cd..c4a6ea5a687f 100644
> > --- a/hw/usb/Kconfig
> > +++ b/hw/usb/Kconfig
> > @@ -17,7 +17,6 @@ config USB_OHCI_SYSBUS
> >
> > config USB_OHCI_PCI
> > bool
> > -defa
Nicholas Piggin writes:
> There is no need to use /dev/shm for file-backed memory devices, and
> it is too small to be usable in gitlab CI. Switch to using a regular
> file in /tmp/ which will usually have more space available.
>
> Signed-off-by: Nicholas Piggin
> ---
> Am I missing something? A
On Tue, May 28, 2024 at 08:07:57AM GMT, Chao Du wrote:
> This patch implements insert/remove software breakpoint process.
>
> For RISC-V, GDB treats single-step similarly to breakpoint: add a
> breakpoint at the next step address, then continue. So this also
> works for single-step debugging.
>
>
> -Original Message-
> From: Peter Xu
> Sent: Tuesday, May 28, 2024 4:51 AM
> To: Liu, Yuan1
> Cc: faro...@suse.de; qemu-devel@nongnu.org; Zou, Nanhai
>
> Subject: Re: [PATCH v6 2/7] migration/multifd: put IOV initialization into
> compression method
>
> On Mon, May 06, 2024 at 12:57:46
On Tue, May 28, 2024 at 02:27:57PM +1000, Nicholas Piggin wrote:
> There is no need to use /dev/shm for file-backed memory devices, and
> it is too small to be usable in gitlab CI. Switch to using a regular
> file in /tmp/ which will usually have more space available.
>
> Signed-off-by: Nicholas P
On 5/28/24 12:35, Thomas Huth wrote:
On 28/05/2024 11.54, Gerd Hoffmann wrote:
The xhci host adapter is the much better choice.
Signed-off-by: Gerd Hoffmann
---
hw/usb/hcd-ohci-pci.c | 1 +
hw/usb/Kconfig | 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/usb/hcd
On Sat, 25 May 2024 at 00:25, Richard Henderson
wrote:
>
> For all, rm == 15 is invalid.
> Prior to v8, thumb with rm == 13 is invalid.
> For PLDW, rn == 15 is invalid.
> Fixes a RISU mismatch for the HINTSPACE pattern in t32.risu
> compared to a neoverse-n1 host.
These are UNPREDICTABLE cases,
On Sat, 25 May 2024 at 00:23, Richard Henderson
wrote:
>
> This fixes a bug in that neither PLI nor PLDW are present in ARMv6T2,
> but are introduced with ARMv7 and ARMv7MP respectively.
> For clarity, do not use NOP for PLD.
>
> Note that there is no PLDW (literal) -- bit 5 of the first word
> is
On Tue, May 28, 2024 at 02:48:42PM +0800, Zhao Liu wrote:
> Hi Stefan,
>
> On Mon, May 27, 2024 at 03:59:44PM -0400, Stefan Hajnoczi wrote:
> > Date: Mon, 27 May 2024 15:59:44 -0400
> > From: Stefan Hajnoczi
> > Subject: Re: [RFC 0/6] scripts: Rewrite simpletrace printer in Rust
> >
> > On Mon,
- According to RISC-V crypto spec, Zvkb extension is a proper subset of the
Zvbb extension.
- Reference:
https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10
Signed-off-by: Jerry Zhang Jian
---
target/riscv/tc
在 2024/5/28 上午9:07, maobibo 写道:
Hi Philippe,
Thanks for reviewing my patch.
I reply inline.
On 2024/5/27 下午6:37, Philippe Mathieu-Daudé wrote:
Hi Bibo,
On 27/5/24 10:35, Bibo Mao wrote:
Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch regis
Philippe Mathieu-Daudé writes:
> Hi Alex,
>
> On 21/5/24 14:53, Alex Bennée wrote:
>> There are a few more bits referencing centos8 in the tree which needed
>> cleaning up. After this we can remove the dedicated runner from the
>> gitlab registration. If we want to keep a dedicated Centos runner
On 30.04.24 12:13, Vladimir Sementsov-Ogievskiy wrote:
We want to have similar QMP objects in different tests. Reworking these
objects to make common parts by calling some helper functions doesn't
seem good. It's a lot more comfortable to see the whole QAPI request in
one place.
So, let's increa
On Sat, 25 May 2024 at 00:23, Richard Henderson
wrote:
>
> Fixes RISU mismatch for "fcvtzs h31, h0, #14".
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-a64.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/transl
On 28/5/24 12:38, Stefano Garzarella wrote:
`memory-backend-shm` can be used with vhost-user devices, so let's
add a new test case for it.
Acked-by: Thomas Huth
Acked-by: Stefan Hajnoczi
Reviewed-by: David Hildenbrand
Signed-off-by: Stefano Garzarella
---
tests/qtest/vhost-user-test.c | 23
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On Sat, 25 May 2024 at 00:30, Richard Henderson
wrote:
>
> The decode of FMOV (vector, immediate, half-precision) vs
> invalid cases of MOVI are incorrect.
>
> Fixes RISU mismatch for invalid insn 0x2f01fd31.
>
> Fixes: 70b4e6a4457 ("arm/translate-a64: add FP16 FMOV to simd_mod_imm")
> Signed-off-
On Sat, 25 May 2024 at 00:22, Richard Henderson
wrote:
>
> All of these insns have "if sz == '1' then UNDEFINED" in their pseudocode.
> Fixes a RISU miscompare for invalid insn 0x5ef0c87a.
>
> Fixes: 5c36d89567c ("arm/translate-a64: add all FP16 ops in
> simd_scalar_pairwise")
> Signed-off-by: Ri
Sorry, I had the bad mail client setting. Please ignore the previous email,
and I will resubmit the patch.
--
Jerry
Jerry ZJ 於 2024年5月28日 週二 下午8:12寫道：
>
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> Read Secure Email
>
On Sat, 25 May 2024 at 00:23, Richard Henderson
wrote:
>
> Load and zero-extend float16 into a TCGv_i32 before
> all scalar operations.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
Based-on:
https://lore.kernel.org/qemu-devel/20240429115157.2260885-1-vsement...@yandex-team.ru/
Discussion for v1:
https://lore.kernel.org/qemu-devel/20240308155158.830258-1-f.eb...@proxmox.com/
Changes in v2:
* Use 'size' type in QAPI.
* Remove option in cbw_parse_options(), i.e. before parsin
In the context of backup fleecing, discarding the source will not work
when the fleecing image has a larger granularity than the one used for
block-copy operations (can happen if the backup target has smaller
cluster size), because cbw_co_pdiscard_snapshot() will align down the
discard requests and
In the context of backup fleecing, discarding the source will not work
when the fleecing image has a larger granularity than the one used for
block-copy operations (can happen if the backup target has smaller
cluster size), because cbw_co_pdiscard_snapshot() will align down the
discard requests and
Akihiko Odaki writes:
> -fsanitize=undefined complains if function pointers are casted. It
> also prevents enabling teh strict mode of CFI which is currently
Typo: the
> disabled with -fsanitize-cfi-icall-generalize-pointers.
The above describes the problem the patch solves. Good! Two
sugges
On 28/05/2024 11.54, Gerd Hoffmann wrote:
Signed-off-by: Gerd Hoffmann
---
hw/usb/Kconfig | 10 ++
hw/usb/meson.build | 4 ++--
2 files changed, 12 insertions(+), 2 deletions(-)
Reviewed-by: Thomas Huth
`memory-backend-memfd` is available only on Linux while the new
`memory-backend-shm` can be used on any POSIX-compliant operating
system. Let's use it so we can run the test in multiple environments.
Since we are here, let`s remove `share=on` which is the default for shm
(and also for memfd).
Ack
`memory-backend-shm` can be used with vhost-user devices, so let's
add a new test case for it.
Acked-by: Thomas Huth
Acked-by: Stefan Hajnoczi
Reviewed-by: David Hildenbrand
Signed-off-by: Stefano Garzarella
---
tests/qtest/vhost-user-test.c | 23 +++
1 file changed, 23 in
shm_open() creates and opens a new POSIX shared memory object.
A POSIX shared memory object allows creating memory backend with an
associated file descriptor that can be shared with external processes
(e.g. vhost-user).
The new `memory-backend-shm` can be used as an alternative when
`memory-backen
Let's make the code more portable by adding defines from
block/file-posix.c to support O_DIRECT in other systems (e.g. macOS).
vhost-user-server.c is a dependency, let's enable it for any POSIX
system.
Acked-by: Stefan Hajnoczi
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Dau
libvhost-user will panic when receiving VHOST_USER_GET_INFLIGHT_FD
message if MFD_ALLOW_SEALING is not defined, since it's not able
to create a memfd.
VHOST_USER_GET_INFLIGHT_FD is used only if
VHOST_USER_PROTOCOL_F_INFLIGHT_SHMFD is negotiated. So, let's mask
that feature if the backend is not ab
The vhost-user protocol is not really Linux-specific so let's enable
libvhost-user for any POSIX system.
Compiling it on macOS and FreeBSD some problems came up:
- avoid to include linux/vhost.h which is available only on Linux
(vhost_types.h contains many of the things we need)
- macOS doesn't
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