This is an sh2a device.
Signed-off-by: Phil Edworthy
---
arch/sh/include/asm/cpu_sh2.h |2 +
arch/sh/include/asm/cpu_sh7269.h | 26 +
board/renesas/rsk7269/Makefile| 27 +
board/renesas/rsk7269/lowlevel_init.S | 182 +
board
This is an sh2a device (max 266MHz) with FPU, video display
controller (VDC), 8 serial ports, 4 I2C channels, 3 CAN ports,
SD and on-chip USB.
The RSK2+SH7269 board uses the SH7269 processor. It is often
referred to as just rsk7269.
Signed-off-by: Phil Edworthy
---
v2: added more info in the
Build error was with board/renesas/ecovec/lowlevel_init.S
include/version.h: Assembler messages:
include/version.h:41: Error: unknown opcode
lowlevel_init.S:48: Error: unknown opcode
lowlevel_init.S:51: Error: unknown opcode
etc
Signed-off-by: Phil Edworthy
---
board/renesas/ecovec/Makefile
the same structure as the other SH boards.
I checked and found that the build error only occurs with out-of-tree builds.
> 2012/3/17 Phil Edworthy :
> > Build error was with board/renesas/ecovec/lowlevel_init.S
> > include/version.h: Assembler messages:
> > include/versi
This sets up the external ethernet IRQ pin.
Signed-off-by: Phil Edworthy
---
board/renesas/rsk7264/lowlevel_init.S |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/renesas/rsk7264/lowlevel_init.S
b/board/renesas/rsk7264/lowlevel_init.S
index fc759bd..39acfa7
The generalised calculation of the serial bit rate reg also applies
to sh7264, it was just the clock speed that was set incorrectly.
Signed-off-by: Phil Edworthy
---
drivers/serial/serial_sh.h |2 --
include/configs/rsk7264.h |2 +-
2 files changed, 1 insertions(+), 3 deletions
Hi,
I'm doing some work with U-Boot SPL, and noticed the following code in the
spl_parse_image_header function (common/spl/spl.c):
if (image_get_magic(header) == IH_MAGIC) {
if (spl_image.flags & SPL_COPY_PAYLOAD_ONLY) {
...
} else {
Hi,
I'm doing some work with U-Boot SPL, and noticed the following code in the
spl_parse_image_header function (common/spl/spl.c):
if (image_get_magic(header) == IH_MAGIC) {
if (spl_image.flags & SPL_COPY_PAYLOAD_ONLY) {
...
} else {
Hi Joe,
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Joe
> Hershberger
> Sent: 10 May 2015 21:23
> To: u-boot@lists.denx.de
> Cc: Rob Herring; Thierry Reding; Stephen Warren; Joe Hershberger; Hisashi
> Nakamura; Masahiro Yamada; Tom Rini; York Sun;
family
as 88E1518.
Signed-off-by: Phil Edworthy
---
drivers/net/phy/marvell.c | 45 -
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index ab0c443..8041922 100644
--- a/drivers/net/phy
The code currently defaults to the slowest clock speed that can be
achieved, which can be significantly lower than the SD spec.
Signed-off-by: Phil Edworthy
---
drivers/mmc/mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index
The offset was applied to write, but not read, now its applied to
both.
Signed-off-by: Phil Edworthy
---
This was previously reviewed and Acked, but vanished somewhere...
See https://patchwork.ozlabs.org/patch/694574
---
drivers/dfu/dfu_sf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
The branch instruction only has an 11-bit relative target address, which
is sometimes not enough.
Signed-off-by: Phil Edworthy
---
arch/arm/cpu/armv7m/start.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7m/start.S b/arch/arm/cpu/armv7m/start.S
index
Hi Vikas,
> On 24 May 2017 18:32 Vikas MANOCHA wrote:
> Hi Phil,
>
> > On Wednesday, May 24, 2017 7:34 AM Phil Edworthy wrote:
> > The branch instruction only has an 11-bit relative target address, which is
> sometimes not enough.
> >
> > Signed-off-by: Phil
Hi Vikas,
On 25 May 2017 10:16 Phil Edworthy wrote:
> > On 24 May 2017 18:32 Vikas MANOCHA wrote:
> > Hi Phil,
> >
> > > On Wednesday, May 24, 2017 7:34 AM Phil Edworthy wrote:
> > > The branch instruction only has an 11-bit relative target address, whic
Hi Jaehoon Chung,
On 25 May 2017 14:50 Jaehoon Chung wrote:
> Hi,
>
> On 05/24/2017 10:54 PM, Phil Edworthy wrote:
> > The code currently defaults to the slowest clock speed that can be
> > achieved, which can be significantly lower than the SD spec.
>
> Is there
Hi Jaehoon Chung,
On 25 May 2017 15:10 Jaehoon Chung wrote:
> On 05/25/2017 11:02 PM, Phil Edworthy wrote:
> > On 25 May 2017 14:50 Jaehoon Chung wrote:
> >> On 05/24/2017 10:54 PM, Phil Edworthy wrote:
> >>> The code currently defaults to the slowest clock speed tha
Hi Jaehoon Chung,
On 26 May 2017 04:38 Jaehoon Chung wrote:
> On 05/25/2017 11:14 PM, Phil Edworthy wrote:
> > On 25 May 2017 15:10 Jaehoon Chung wrote:
> >> On 05/25/2017 11:02 PM, Phil Edworthy wrote:
> >>> On 25 May 2017 14:50 Jaehoon Chung wrote:
> >>&
Hi Vikas,
On 26 May 2017 00:58 Vikas MANOCHA wrote:
> On Thursday, May 25, 2017 6:58 AM Phil Edworthy wrote:
> > On 25 May 2017 10:16 Phil Edworthy wrote:
> > > > On 24 May 2017 18:32 Vikas MANOCHA wrote:
> > > > Hi Phil,
> > > >
> > > >
Hi Vikas,
On 27 May 2017 00:55 Vikas MANOCHA wrote:
> On Friday, May 26, 2017 1:27 AM Phil Edworthy wrote:
> > On 26 May 2017 00:58 Vikas MANOCHA wrote:
> > > On Thursday, May 25, 2017 6:58 AM Phil Edworthy wrote:
> > > > On 25 May 2017 10:16 Phil Edworthy wrote:
&g
The branch instruction only has an 11-bit relative target address, which
is sometimes not enough.
Signed-off-by: Phil Edworthy
---
v2:
- Use W(b) instead of ldr+mov. Using this macro requires
CONFIG_ARM_ASM_UNIFIED and CONFIG_THUMB2_KERNEL to be defined.
---
arch/arm/cpu/armv7m/Makefile | 3
Hi Tom,
On 31 May 2017 14:10 Tom Rini wrote:
> On Wed, May 31, 2017 at 08:27:05AM +0100, Phil Edworthy wrote:
>
> > The branch instruction only has an 11-bit relative target address,
> > which is sometimes not enough.
> >
> > Signed-off-by: Phil Edworthy
> >
Rather than change asm files that come from Linux, add the symbols
to Kconfig. Since one of the symbols is for thumb2 builds, make
CPU_V7M always select them.
Signed-off-by: Phil Edworthy
---
arch/arm/Kconfig | 10 ++
arch/arm/lib/Makefile | 2 --
2 files changed, 10 insertions
The branch instruction only has an 11-bit relative target address, which
is sometimes not enough.
Signed-off-by: Phil Edworthy
---
v3:
- Move CONFIG_ARM_ASM_UNIFIED and CONFIG_THUMB2_KERNEL to Kconfig
v2:
- Use W(b) instead of ldr+mov. Using this macro requires
CONFIG_ARM_ASM_UNIFIED and
Hi Vikas,
On 12 February 2017 20:53, Vikas MANOCHA wrote:
> > On Fri, Feb 03, 2017 at 02:48:40PM +, Phil Edworthy wrote:
> >
> > > The SysTick is a 24-bit down counter that is found on all ARM Cortex
> > > M3, M4, M7 devices and is always located at a fixed addr
Hi Vikas,
On 12 February 2017 21:10, Vikas MANOCHA wrote:
> Hi Phil,
>
> > -Original Message-
> > From: Phil Edworthy [mailto:phil.edwor...@renesas.com]
> > Sent: Tuesday, February 07, 2017 6:34 AM
> > To: Tom Rini
> > Cc: Kamil Lulko ; Vikas M
The SysTick is a 24-bit down counter that is found on all ARM Cortex
M3, M4, M7 devices and is always located at a fixed address.
Signed-off-by: Phil Edworthy
---
v2:
- Variables & constant renamed.
- Use the calibration reg to determine if we use the cpu or ref clk
- Use the calibration
Hi Vikas,
On 15 February 2017 23:50, Vikas MANOCHA wrote:
> Hi Phil,
>
> > -Original Message-
> > From: Phil Edworthy [mailto:phil.edwor...@renesas.com]
> > Sent: Monday, February 13, 2017 11:48 PM
> > To: Albert Aribaud
> > Cc: Tom Rini ; Vik
is is wrong, so this driver allows the clock rate to be defined
using CONFIG_SYS_HZ_CLOCK.
Signed-off-by: Phil Edworthy
---
v3:
- Add comments about where we get the ref clock rate from.
v2:
- Variables & constant renamed.
- Use the calibration reg to determine if we use the cpu or ref clk
CONFIG_SPL_STACK_SIZE is not a config option, so rename it.
Signed-off-by: Phil Edworthy
---
include/configs/microblaze-generic.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/microblaze-generic.h
b/include/configs/microblaze-generic.h
index 24de528
CONFIG_SPL_STACK_SIZE is not a config option, so rename it.
Signed-off-by: Phil Edworthy
---
Not tested at all since I don't have the HW
---
include/configs/ti_armv7_keystone2.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/ti_armv7_keystone2
The SysTick is a 24-bit down counter that is found on all ARM Cortex
M3, M4, M7 devices and is always located at a fixed address.
Signed-off-by: Phil Edworthy
---
arch/arm/cpu/armv7m/Makefile| 2 +
arch/arm/cpu/armv7m/systick-timer.c | 91 +
2 files
The SysTick is a 24-bit down counter that is found on all ARM Cortex
M3, M4, M7 devices and is always located at a fixed address.
Signed-off-by: Phil Edworthy
---
Resend with Albert's new email address - get_maintainer.pl gave the old one.
---
arch/arm/cpu/armv7m/Makefile| 2 +
Some devices/boards have their own way to reset the cpu.
Signed-off-by: Phil Edworthy
---
arch/arm/cpu/armv7m/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c
index 58cde93..c3e4734 100644
--- a/arch/arm/cpu/armv7m
Hi Kamil,
On 07 February 2017 14:12, Kamil Lulko wrote:
> On Mon, Feb 6, 2017 at 12:16 AM, Tom Rini wrote:
> > On Fri, Feb 03, 2017 at 02:48:40PM +0000, Phil Edworthy wrote:
> >
> > > The SysTick is a 24-bit down counter that is found on all ARM Cortex
> > >
Hi Tom,
On 07 February 2017 14:23, Tom Rini wrote:
> On Tue, Feb 07, 2017 at 02:19:39PM +0000, Phil Edworthy wrote:
> > Hi Kamil,
> >
> > On 07 February 2017 14:12, Kamil Lulko wrote:
> > > On Mon, Feb 6, 2017 at 12:16 AM, Tom Rini wrote:
> > > > On F
Or'ing together bit positions is clearly wrong.
Signed-off-by: Phil Edworthy
---
drivers/spi/cadence_qspi_apb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e285d3c..2403e71 100644
--- a/driver
This series has fixes, patches to clean the code up, and add support for
specifying the sampling edge.
Phil Edworthy (7):
spi: cadence_qspi: Fix clearing of pol/pha bits
spi: cadence_qspi: Fix baud rate calculation
spi: cadence_qspi: Use #define for bits instead of bit shifts
spi
A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remove _MASK from them.
Whilst doing so, also remove the unneccesary brackets around the
constants.
Signed-off-by: Phil Edworthy
---
drivers/spi
Signed-off-by: Phil Edworthy
---
drivers/spi/cadence_qspi_apb.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 639780c..a0edeb8 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
Most of the code already uses #defines for the bit value, rather
than the shift required to get the value. This changes the remaining
code over.
Whislt at it, fix the names of the "Rd Data Capture" register defs.
Signed-off-by: Phil Edworthy
---
drivers/spi/cadence_qspi_
This change copes with the delay being less than a SCLK period.
Signed-off-by: Phil Edworthy
---
drivers/spi/cadence_qspi_apb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index a0edeb8..533274d 100644
--- a
up the divider to generate
25MHz.
This change fixes the calculation.
Signed-off-by: Phil Edworthy
---
drivers/spi/cadence_qspi_apb.c | 23 +++
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index
The HW manual does not give details about what the register
value for this bit actually does, other than "Choose edge on
which data outputs from flash memory will be sampled".
Signed-off-by: Phil Edworthy
---
Our HW engineers tell me that it needs to be set for our hardware.
---
The IP supports two ports, A and B, each providing up to 32 gpios.
The driver already creates a 2nd gpio bank by reading the 2nd node
from DT, so this is quite a simple change to support the 2nd bank.
Signed-off-by: Phil Edworthy
---
drivers/gpio/dwapb_gpio.c | 40
Hi Marek,
On 02 November 2016 19:39, Marek Vasut wrote:
> On 11/02/2016 04:15 PM, Phil Edworthy wrote:
> > With the existing code, when the requested SPI clock rate is near
> > to the lowerest that can be achieved by the hardware (max divider
> > of the ref clock is 32), the
Hi Marek,
On 02 November 2016 19:38, Marek Vasut wrote:
> On 11/02/2016 04:24 PM, Phil Edworthy wrote:
> > The IP supports two ports, A and B, each providing up to 32 gpios.
> > The driver already creates a 2nd gpio bank by reading the 2nd node
> > from DT, so this is qui
The IP supports two ports, A and B, each providing up to 32 gpios.
The driver already creates a 2nd gpio bank by reading the 2nd node
from DT, so this is quite a simple change to support the 2nd bank.
Signed-off-by: Phil Edworthy
---
v2:
Use an offset element in the platform data instead of if
The IP supports two ports, A and B, each providing up to 32 gpios.
The driver already creates a 2nd gpio bank by reading the 2nd node
from DT, so this is quite a simple change to support the 2nd bank.
Signed-off-by: Phil Edworthy
---
v3:
Pass the bank nr to the register offset macro, to cope
the divider to generate
25MHz.
This change fixes the calculation.
Signed-off-by: Phil Edworthy
---
v2:
- Use the DIV_ROUND_UP macro
---
drivers/spi/cadence_qspi_apb.c | 23 +++
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b
Hi Simon,
>On 2 November 2016 at 13:38, Marek Vasut wrote:
>> On 11/02/2016 04:24 PM, Phil Edworthy wrote:
>>> The IP supports two ports, A and B, each providing up to 32 gpios.
>>> The driver already creates a 2nd gpio bank by reading the 2nd node
>>> from
Hi Simon,
On 03 November 2016 15:49, Simon Glass wrote:
> On 3 November 2016 at 08:02, Phil Edworthy
> wrote:
> > >On 2 November 2016 at 13:38, Marek Vasut wrote:
> > >> On 11/02/2016 04:24 PM, Phil Edworthy wrote:
> > >>> The IP supports two por
Hi Marek,
On 03 November 2016 17:49, Marek Vasut wrote:
> On 11/03/2016 02:56 PM, Simon Glass wrote:
> > On 2 November 2016 at 13:38, Marek Vasut > <mailto:ma...@denx.de>> wrote:
> >> On 11/02/2016 04:24 PM, Phil Edworthy wrote:
> Please no c-structure register
Hi Vignesh,
On 04 November 2016 05:57, Vignesh R wrote:
> On Wednesday 02 November 2016 08:45 PM, Phil Edworthy wrote:
> > The HW manual does not give details about what the register
> > value for this bit actually does, other than "Choose edge on
> > which data outputs
Whilst at it, move the code to read the "sram-size" property
into the other code that reads properties from the node, rather
than the SF subnode.
Also change the code to use a bool for the bypass arg.
Signed-off-by: Phil Edworthy
---
v2:
Change name of DT prop and provide details
The offset was applied to write, but not read, now its applied to
both.
Signed-off-by: Phil Edworthy
---
drivers/dfu/dfu_sf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c
index 9702eee..b6d5fe2 100644
--- a/drivers/dfu
.
This change accurately calculates the additional delays in Ref clocks.
Signed-off-by: Phil Edworthy
---
v2:
Was "spi: cadence_qspi: Fix CQSPI_CAL_DELAY calculation"
Note only did the existing code not cope with the delay less than
an SCLK period, but the calculation didn't roun
Hi Jagan,
On 02 November 2016 15:16, Phil wrote:
> This series has fixes, patches to clean the code up, and add support for
> specifying the sampling edge.
>
> Phil Edworthy (7):
> spi: cadence_qspi: Fix clearing of pol/pha bits
> spi: cadence_qspi: Fix baud rate c
ample edge used
Added in v2:
spi: cadence_qspi: Better debug information on the SPI clock rate
Phil Edworthy (8):
spi: cadence_qspi: Fix clearing of pol/pha bits
spi: cadence_qspi: Fix baud rate calculation
spi: cadence_qspi: Better debug information on the SPI clock rate
spi: cadence
Or'ing together bit positions is clearly wrong.
Signed-off-by: Phil Edworthy
---
drivers/spi/cadence_qspi_apb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e285d3c..2403e71 100644
--- a/driver
Most of the code already uses #defines for the bit value, rather
than the shift required to get the value. This changes the remaining
code over.
Whislt at it, fix the names of the "Rd Data Capture" register defs.
Signed-off-by: Phil Edworthy
---
drivers/spi/cadence_qspi_
Show what the output clock rate actually is.
Signed-off-by: Phil Edworthy
---
drivers/spi/cadence_qspi_apb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index b9e0df7..3ae4b5a 100644
--- a/drivers/spi
the divider to generate
25MHz.
This change fixes the calculation.
Signed-off-by: Phil Edworthy
---
v2:
- Use the DIV_ROUND_UP macro
---
drivers/spi/cadence_qspi_apb.c | 23 +++
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b
A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remove _MASK from them.
Whilst doing so, also remove the unnecessary brackets around the
constants.
Signed-off-by: Phil Edworthy
---
drivers/spi
Signed-off-by: Phil Edworthy
---
drivers/spi/cadence_qspi_apb.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e7d8320..1cd636a 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
.
This change accurately calculates the additional delays in Ref clocks.
Signed-off-by: Phil Edworthy
---
v2:
Was "spi: cadence_qspi: Fix CQSPI_CAL_DELAY calculation"
Note only did the existing code not cope with the delay less than
an SCLK period, but the calculation didn't roun
Whilst at it, move the code to read the "sram-size" property
into the other code that reads properties from the node, rather
than the SF subnode.
Also change the code to use a bool for the bypass arg.
Signed-off-by: Phil Edworthy
---
v2:
Change name of DT prop and provide details
Hi Marek,
On 25 November 2016 14:58 Marek Vasut wrote:
> On 11/25/2016 03:38 PM, Phil Edworthy wrote:
> > With the existing code, when the requested SPI clock rate is near
> > to the lowest that can be achieved by the hardware (max divider
> > of the ref clock is 32), the ge
Hi Marek,
On 25 November 2016 15:00 Marek Vasut wrote:
> On 11/25/2016 03:38 PM, Phil Edworthy wrote:
> > Most of the code already uses #defines for the bit value, rather
> > than the shift required to get the value. This changes the remaining
> > code over.
> >
> &g
Hi Marek,
On 25 November 2016 15:06 Marek Vasut wrote:
> On 11/25/2016 03:38 PM, Phil Edworthy wrote:
> > Whilst at it, move the code to read the "sram-size" property
> > into the other code that reads properties from the node, rather
> > than the SF subnode.
&
Hi Jagan,
On 25 November 2016 15:29 Jagan Teki wrote:
> On Fri, Nov 25, 2016 at 8:08 PM, Phil Edworthy
> wrote:
> > Or'ing together bit positions is clearly wrong.
> >
> > Signed-off-by: Phil Edworthy
> > ---
> > drivers/spi/cadence_qspi_apb.c | 4 ++-
Hi Jagan,
On 25 November 2016 15:42 Jagan Teki wrote:
> On Fri, Nov 25, 2016 at 8:08 PM, Phil Edworthy
> wrote:
> > With the existing code, when the requested SPI clock rate is near
> > to the lowest that can be achieved by the hardware (max divider
> > of the ref clo
Hi Chin Liang,
On 28 November 2016 12:49 See, Chin Liang wrote:
> On Jum, 2016-11-25 at 14:38 +0000, Phil Edworthy wrote:
> >
> > The Cadence QSPI controller has specified overheads for the various
> > CS
> > times that are in addition to those programmed in to the Dev
Or'ing together bit positions is clearly wrong.
Signed-off-by: Phil Edworthy
Acked-by: Marek Vasut
---
v3:
- No change.
v2:
- No change.
---
drivers/spi/cadence_qspi_apb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/driver
ying the sample edge used" has been
split into 3 separate patches.
Phil Edworthy (11):
spi: cadence_qspi: Fix clearing of pol/pha bits
spi: cadence_qspi: Fix baud rate calculation
spi: cadence_qspi: Better debug information on the SPI clock rate
spi: cadence_qspi: Use #define for
the divider to generate
25MHz.
This change fixes the calculation.
Signed-off-by: Phil Edworthy
---
v3:
- Use single line DIV_ROUND_UP instead of two
v2:
- Use the DIV_ROUND_UP macro
---
drivers/spi/cadence_qspi_apb.c | 22 ++
1 file changed, 6 insertions(+), 16 deletions
Most of the code already uses #defines for the bit value, rather
than the shift required to get the value. This changes the remaining
code over.
Whislt at it, fix the names of the "Rd Data Capture" register defs.
Signed-off-by: Phil Edworthy
Acked-by: Marek Vasut
---
v3:
- Remov
A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remove _MASK from them.
Whilst doing so, also remove the unnecessary brackets around the
constants.
Signed-off-by: Phil Edworthy
Acked-by: Marek
Show what the output clock rate actually is.
Signed-off-by: Phil Edworthy
Acked-by: Marek Vasut
---
v3:
- No change.
v2:
- No change.
---
drivers/spi/cadence_qspi_apb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi
Instead of extracting mode settings and passing them as separate
args to another function, just pass the SPI mode as an arg.
Signed-off-by: Phil Edworthy
---
v3:
- New patch introduced to address comments.
---
drivers/spi/cadence_qspi.c | 4 +---
drivers/spi/cadence_qspi.h | 3
Signed-off-by: Phil Edworthy
Acked-by: Marek Vasut
---
v3:
- No change.
v2:
- No change.
---
drivers/spi/cadence_qspi_apb.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e81d678..39e31f6 100644
--- a
Move the code to read the "sram-size" property into the other code
that reads properties from the node, rather than the SF subnode.
Signed-off-by: Phil Edworthy
---
v3:
- New patch to split changes.
---
drivers/spi/cadence_qspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
This is in preparation for adding another arg.
Signed-off-by: Phil Edworthy
---
v3:
- New patch to split changes.
---
drivers/spi/cadence_qspi.c | 7 ---
drivers/spi/cadence_qspi.h | 2 +-
drivers/spi/cadence_qspi_apb.c | 2 +-
3 files changed, 6 insertions(+), 5 deletions
.
This change accurately calculates the additional delays in Ref clocks.
Signed-off-by: Phil Edworthy
---
v3:
- No change.
v2:
Was "spi: cadence_qspi: Fix CQSPI_CAL_DELAY calculation"
Note only did the existing code not cope with the delay less than
an SCLK period, but the calculat
Introduce a new DT property to specify whether the QSPI Controller
samples the data on a rising edge. The default is falling edge.
Some versions of the QSPI Controller do not implement this bit, in
which case the property should be omitted.
Signed-off-by: Phil Edworthy
---
v3:
- Patch split
Hi Jagan,
On 30 November 2016 04:59, Jagan Teki wrote:
> On Tue, Nov 29, 2016 at 6:28 PM, Phil Edworthy
> wrote:
> > Most of the code already uses #defines for the bit value, rather
> > than the shift required to get the value. This changes the remaining
> > code over.
&
Hi Jagan,
On 02 December 2016 14:20, Jagan Teki wrote:
> On Tue, Nov 29, 2016 at 6:28 PM, Phil Edworthy
> wrote:
> > This is in preparation for adding another arg.
>
> ?? proper reason for changing arg to bool.
Purely because the patch 11 adds another arg that is a bool (whi
Hi Jagan,
On 02 December 2016 14:23, Jagan Teki wrote:
> On Tue, Nov 29, 2016 at 6:28 PM, Phil Edworthy
> wrote:
> > Introduce a new DT property to specify whether the QSPI Controller
> > samples the data on a rising edge. The default is falling edge.
> > Some versions o
HI Jagan,
On 05 December 2016 10:26, Jagan Teki wrote:
> On Mon, Dec 5, 2016 at 11:09 AM, Phil Edworthy
> wrote:
> > Hi Jagan,
> >
> > On 02 December 2016 14:23, Jagan Teki wrote:
> >> On Tue, Nov 29, 2016 at 6:28 PM, Phil Edworthy
> >> wrote:
>
Hi Jagan,
On 05 December 2016 10:29, Jagan Teki wrote:
> On Mon, Dec 5, 2016 at 11:07 AM, Phil Edworthy
> wrote:
> > Hi Jagan,
> >
> > On 02 December 2016 14:20, Jagan Teki wrote:
> >> On Tue, Nov 29, 2016 at 6:28 PM, Phil Edworthy
> >> wrote:
> &
Hi Jagan,
On 05 December 2016 10:42, Jagan Teki wrote:
> On Mon, Dec 5, 2016 at 11:31 AM, Phil Edworthy
> wrote:
> > HI Jagan,
> >
> > On 05 December 2016 10:26, Jagan Teki wrote:
> >> On Mon, Dec 5, 2016 at 11:09 AM, Phil Edworthy
> >> wrote:
> >
Hi Marek,
On 05 December 2016 13:31, Marek Vasut wrote:
> On 12/05/2016 11:46 AM, Phil Edworthy wrote:
> > On 05 December 2016 10:42, Jagan Teki wrote:
> >> On Mon, Dec 5, 2016 at 11:31 AM, Phil Edworthy
> >> wrote:
> >>> On 05 December 2016 10:26, Jagan Te
Hi Jagan, Marek,
On 06 December 2016 12:39 Marek Vasut wrote:
> On 12/06/2016 11:25 AM, Phil Edworthy wrote:
> > On 05 December 2016 13:31, Marek Vasut wrote:
> >> On 12/05/2016 11:46 AM, Phil Edworthy wrote:
> >>> On 05 December 2016 10:42, Jagan Teki wrote:
>
Hi Jagan,
On 06 December 2016 17:24 Jagan Teki wrote:
> On Tue, Dec 6, 2016 at 6:00 PM, Phil Edworthy
> wrote:
> > Hi Jagan, Marek,
> >
> > On 06 December 2016 12:39 Marek Vasut wrote:
> >> On 12/06/2016 11:25 AM, Phil Edworthy wrote:
> >> >
Hi Jagan,
When using Micron devices, SPI flash with quad mode does not work since commit
c56ae7519f141523ba1248b22b5b5169b21772fe "sf: Fix quad bit set for micron
devices".
This has been pointed out before, details about why the patch does work are
here:
http://lists.denx.de/pipermail/u-boot/20
The mask for the 88E1510 meant that the 88E1518 code would never be
used.
Signed-off-by: Phil Edworthy
---
Note: This has only been tested on a board that uses a Marvell 88E1512
PHY, see subsequent patches.
---
drivers/net/phy/marvell.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
These patches add support for the Marvell M88E1512 PHY.
Phil Edworthy (5):
net: phy: Fix mask so that we can identify Marvell 88E1518
net: phy: Add support for Marvell M88E1512
net: phy: Marvell 88E151x: Add support for RGMII
net: phy: Marvell 88E151x: Increase delay after init
net: phy
Signed-off-by: Phil Edworthy
---
drivers/net/phy/marvell.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 06029c0..a7ea435 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -560,6 +560,16
Signed-off-by: Phil Edworthy
---
drivers/net/phy/marvell.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 48ebb50..dc1d25f 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -177,10 +177,7
On Marvell 88E1512, the delay is not enough when connected
to some external switches (e.g. Netgear GS108E).
Signed-off-by: Phil Edworthy
---
drivers/net/phy/marvell.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
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