[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)
preames wrote: All of the dependent pieces have landed. For ease of future reference: * https://github.com/llvm/llvm-project/pull/90266 is the attributes emission (off by default). * https://github.com/llvm/llvm-project/pull/97347 is the LLD change. * https://github.com/llvm/llvm-project/pull/87376 is the change to A67 by default The combination of the first and third mean that the emitted attributes now match our ztso lowering as well. Unfortunately, most binaries wont have the attributes at all (due to the LD crash on older versions), but that seems unavoidable at this point. I have re-landed the original change. https://github.com/llvm/llvm-project/pull/96465 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 90d79e2 - Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
Author: Philip Reames Date: 2024-07-09T10:45:56-07:00 New Revision: 90d79e258ee9c6935ffeac405b3e9b74542068aa URL: https://github.com/llvm/llvm-project/commit/90d79e258ee9c6935ffeac405b3e9b74542068aa DIFF: https://github.com/llvm/llvm-project/commit/90d79e258ee9c6935ffeac405b3e9b74542068aa.diff LOG: Reapply "[RISCV] Remove experimental from Ztso. (#96465)" This was reverted in f985a8826bfa4ca3d23e654185de35e30ea6dc79. Since that, the default WMO lowering has moved to A67 compatible, the ABI attribute emission has landed (off by default), and the LLD change to merge said attributes have landed. Our ztso lowering is believed to also be A67 compatible, and no known issues remain. Original commit message: Ztso 1.0 was ratified in January 2023. Documentation: https://github.com/riscv/riscv-isa-manual/blob/main/src/ztso-st-ext.adoc Added: Modified: clang/test/Driver/print-supported-extensions-riscv.c clang/test/Driver/riscv-arch.c clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/Target/RISCV/RISCVFeatures.td llvm/test/CodeGen/RISCV/GlobalISel/atomic-fence.ll llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll llvm/test/CodeGen/RISCV/atomic-fence.ll llvm/test/CodeGen/RISCV/atomic-load-store.ll llvm/test/CodeGen/RISCV/atomic-rmw.ll llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll llvm/test/CodeGen/RISCV/attributes.ll llvm/test/CodeGen/RISCV/module-elf-flags.ll llvm/test/MC/RISCV/Ztso.s llvm/test/MC/RISCV/attribute-arch.s llvm/test/MC/RISCV/elf-flags.s llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 36ace1e007c32..49bdb21ac59d6 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -70,6 +70,7 @@ // CHECK-NEXT: zksed1.0 'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions) // CHECK-NEXT: zksh 1.0 'Zksh' (ShangMi Suite: SM3 Hash Function Instructions) // CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency) +// CHECK-NEXT: ztso 1.0 'Ztso' (Memory Model - Total Store Order) // CHECK-NEXT: zvbb 1.0 'Zvbb' (Vector basic bit-manipulation instructions) // CHECK-NEXT: zvbc 1.0 'Zvbc' (Vector Carryless Multiplication) // CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension) @@ -170,7 +171,6 @@ // CHECK-NEXT: zicfilp 0.4 'Zicfilp' (Landing pad) // CHECK-NEXT: zicfiss 0.4 'Zicfiss' (Shadow stack) // CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) -// CHECK-NEXT: ztso 0.1 'Ztso' (Memory Model - Total Store Order) // CHECK-NEXT: smmpm1.0 'Smmpm' (Machine-level Pointer Masking for M-mode) // CHECK-NEXT: smnpm1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode) // CHECK-NEXT: ssnpm1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode) diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 0f285f7c0033c..018fa25218ea6 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -365,24 +365,30 @@ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s // RV32-ZFHMIN: "-target-feature" "+zfhmin" -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s -// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32iztso' +// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izalasr' // RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -menable-experimental-extensions -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s -// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32iztso' +// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izalasr' // RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso0p7 -menable-experimental-extensions -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf
[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
@@ -290,8 +290,24 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList
,
// 2. Get march (isa string) based on `-mcpu=`
if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "native") {
CPU = llvm::sys::getHostCPUName();
+ // If the target cpu is unrecognized, use target features.
+ if (CPU.empty() || CPU.starts_with("generic")) {
+llvm::StringMap HostFeatures;
+if (llvm::sys::getHostCPUFeatures(HostFeatures)) {
+ std::vector Features;
+ for (auto : HostFeatures)
+Features.push_back(
+Args.MakeArgString((F.second ? "+" : "-") + F.first()));
+
+ auto ParseResult = llvm::RISCVISAInfo::parseFeatures(
+ Triple.isRISCV32() ? 32 : 64, Features);
+ if (ParseResult)
+return (*ParseResult)->toString();
preames wrote:
Good catch. Returning std::string for now appears to be the path of least
resistance.
Glancing at the callers, I note that more than half immediately call
parseArchString. We could invert the API here, and return the parsed ISAInfo,
and then convert that back into string form on demand. I didn't see any cases
where we wanted the string form of an invalid architecture combination - that
would be the case which might prevent the API inversion.
https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
https://github.com/preames approved this pull request. LGTM w/minor comments https://github.com/llvm/llvm-project/pull/94352 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
@@ -83,8 +83,14 @@ void riscv::getRISCVTargetFeatures(const Driver , const
llvm::Triple ,
// and other features (ex. mirco architecture feature) from mcpu
if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "native") {
CPU = llvm::sys::getHostCPUName();
+ llvm::StringMap HostFeatures;
+ if (llvm::sys::getHostCPUFeatures(HostFeatures))
+for (auto : HostFeatures)
+ Features.push_back(
+ Args.MakeArgString((F.second ? "+" : "-") + F.first()));
+}
preames wrote:
Do we also need to update riscv::getRISCVArch? There's analogous logic there
for getting features from mcpu native.
https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap ) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap ) {
+ RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0},
+ {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0}};
+ int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query,
+/*pair_count=*/std::size(Query), /*cpu_count=*/0,
+/*cpus=*/0, /*flags=*/0);
+ if (Ret != 0)
+return false;
+
+ uint64_t BaseMask = Query[0].Value;
+ // Check whether RISCV_HWPROBE_BASE_BEHAVIOR_IMA is set.
+ if (BaseMask & 1) {
+Features["i"] = true;
+Features["m"] = true;
+Features["a"] = true;
+ }
+
+ uint64_t ExtMask = Query[1].Value;
+ Features["f"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD
+ Features["d"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD
+ Features["c"] = ExtMask & (1 << 1); // RISCV_HWPROBE_IMA_C
+ Features["v"] = ExtMask & (1 << 2); // RISCV_HWPROBE_IMA_V
+ Features["zba"] = ExtMask & (1 << 3); // RISCV_HWPROBE_EXT_ZBA
+ Features["zbb"] = ExtMask & (1 << 4); // RISCV_HWPROBE_EXT_ZBB
+ Features["zbs"] = ExtMask & (1 << 5); // RISCV_HWPROBE_EXT_ZBS
+ Features["zicboz"] = ExtMask & (1 << 6); // RISCV_HWPROBE_EXT_ZICBOZ
+ Features["zbc"] = ExtMask & (1 << 7); // RISCV_HWPROBE_EXT_ZBC
+ Features["zbkb"] = ExtMask & (1 << 8);// RISCV_HWPROBE_EXT_ZBKB
+ Features["zbkc"] = ExtMask & (1 << 9);// RISCV_HWPROBE_EXT_ZBKC
+ Features["zbkx"] = ExtMask & (1 << 10); // RISCV_HWPROBE_EXT_ZBKX
+ Features["zknd"] = ExtMask & (1 << 11); // RISCV_HWPROBE_EXT_ZKND
+ Features["zkne"] = ExtMask & (1 << 12); // RISCV_HWPROBE_EXT_ZKNE
+ Features["zknh"] = ExtMask & (1 << 13); // RISCV_HWPROBE_EXT_ZKNH
+ Features["zksed"] = ExtMask & (1 << 14); // RISCV_HWPROBE_EXT_ZKSED
+ Features["zksh"] = ExtMask & (1 << 15); // RISCV_HWPROBE_EXT_ZKSH
+ Features["zkt"] = ExtMask & (1 << 16);// RISCV_HWPROBE_EXT_ZKT
+ Features["zvbb"] = ExtMask & (1 << 17); // RISCV_HWPROBE_EXT_ZVBB
+ Features["zvbc"] = ExtMask & (1 << 18); // RISCV_HWPROBE_EXT_ZVBC
+ Features["zvkb"] = ExtMask & (1 << 19); // RISCV_HWPROBE_EXT_ZVKB
+ Features["zvkg"] = ExtMask & (1 << 20); // RISCV_HWPROBE_EXT_ZVKG
+ Features["zvkned"] = ExtMask & (1 << 21); // RISCV_HWPROBE_EXT_ZVKNED
+ Features["zvknha"] = ExtMask & (1 << 22); // RISCV_HWPROBE_EXT_ZVKNHA
+ Features["zvknhb"] = ExtMask & (1 << 23); // RISCV_HWPROBE_EXT_ZVKNHB
+ Features["zvksed"] = ExtMask & (1 << 24); // RISCV_HWPROBE_EXT_ZVKSED
+ Features["zvksh"] = ExtMask & (1 << 25); // RISCV_HWPROBE_EXT_ZVKSH
+ Features["zvkt"] = ExtMask & (1 << 26); // RISCV_HWPROBE_EXT_ZVKT
+ Features["zfh"] = ExtMask & (1 << 27);// RISCV_HWPROBE_EXT_ZFH
+ Features["zfhmin"] = ExtMask & (1 << 28); // RISCV_HWPROBE_EXT_ZFHMIN
+ Features["zihintntl"] = ExtMask & (1 << 29); // RISCV_HWPROBE_EXT_ZIHINTNTL
+ Features["zvfh"] = ExtMask & (1 << 30); // RISCV_HWPROBE_EXT_ZVFH
+ Features["zvfhmin"] = ExtMask & (1ULL << 31); // RISCV_HWPROBE_EXT_ZVFHMIN
+ Features["zfa"] = ExtMask & (1ULL << 32); // RISCV_HWPROBE_EXT_ZFA
+ // TODO: set ztso when it is no longer experimental.
+ // Features["ztso"] = ExtMask & (1ULL << 33);// RISCV_HWPROBE_EXT_ZTSO
preames wrote:
I agree that leaving this as a TODO is the right thing to do right now.
https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap ) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap ) {
+ RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0},
+ {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0}};
+ int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query,
preames wrote:
Consider this a purely stylistic comment.
We should probably be using either the vDSO symbol or the glibc shim. In
either case, we'd have a weak symbol which could possibly be nullptr, and need
to return early.
In this use case, the difference likely doesn't matter, but if we reuse this
code, the lack of caching provided by vDSO could be problematic.
https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap ) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap ) {
+ RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0},
+ {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0}};
+ int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query,
+/*pair_count=*/std::size(Query), /*cpu_count=*/0,
+/*cpus=*/0, /*flags=*/0);
+ if (Ret != 0)
+return false;
+
+ uint64_t BaseMask = Query[0].Value;
+ // Check whether RISCV_HWPROBE_BASE_BEHAVIOR_IMA is set.
+ if (BaseMask & 1) {
+Features["i"] = true;
+Features["m"] = true;
+Features["a"] = true;
+ }
+
+ uint64_t ExtMask = Query[1].Value;
preames wrote:
I think this is likely to be fine in practice.
>From https://docs.kernel.org/arch/riscv/hwprobe.html, I see "If a key is
>unknown to the kernel, its key field will be cleared to -1, and its value set
>to 0. " If I'm reading that properly, if RISCV_HWPROBE_KEY_IMA_EXT_0 isn't a
>valid key, it is the kernel's responsible for clearing all bits to zero, so
>this code should work.
https://github.com/llvm/llvm-project/pull/94352
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[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/94352 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)
preames wrote: Once https://github.com/llvm/llvm-project/pull/90266 lands with the attributes off by default, I think we should move forward with relanding this. We do need one change though - our TSO lowering unconditionally uses the A6S ABI variant - right? - so we need to adjust the attribute emission to generate A6S when compiling for TSO. This is pretty minor honestly, but we should do it. https://github.com/llvm/llvm-project/pull/96465 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)
preames wrote:
Chatted with @patrick-rivos on the status of TSO. The following is my summary:
* psABI changes have landed which change the default for WMO to what we used to
call the "A6/A7 compatibility table". The TSO change which landed to psABI
defines a mapping which is compatible with this table, but also cross
compatible with WMO A6 and WMO A7 independently.
* Patrick's change (https://reviews.llvm.org/D155517) changed LLVM to emitting
code which is believed to match the psABI for TSO. Note that this was done
before the psABI changes were accepted.
* Our WMO lowering is still the A6 variant. We have not moved to the A6/A7
compat mapping which is now mandated by psABI. (We probably should, just to
match gcc.)
* The psABI change included two set of ELF flags for managing TSO and the A6/A7
compat question. I know I implemented the former, but neither of us knew the
status of the compat flags.
* As a reminder, gcc originally implemented a buggy variant of the A6 table for
WMO. The first correct version was gcc 13 which went straight to the new psABI
mapping ("A6/A7 compat"). None of the available options give us cross
compatibility with binaries compiled with an old gcc.
Takeaway here is that we probably are fine to move ztso out of experimental
once someone reports back on the status of the elf flags for the a6/a7 compat
thing.
https://github.com/llvm/llvm-project/pull/96465
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[clang] f985a88 - Revert "[RISCV] Remove experimental from Ztso. (#96465)"
Author: Philip Reames
Date: 2024-06-24T08:32:28-07:00
New Revision: f985a8826bfa4ca3d23e654185de35e30ea6dc79
URL:
https://github.com/llvm/llvm-project/commit/f985a8826bfa4ca3d23e654185de35e30ea6dc79
DIFF:
https://github.com/llvm/llvm-project/commit/f985a8826bfa4ca3d23e654185de35e30ea6dc79.diff
LOG: Revert "[RISCV] Remove experimental from Ztso. (#96465)"
This reverts commit 9cd6ef4b8a5c843ef491437c765d4cb2ff2f8fe3. See
discussion on review thread.
Added:
Modified:
clang/test/Driver/riscv-arch.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/CodeGen/RISCV/GlobalISel/atomic-fence.ll
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
llvm/test/CodeGen/RISCV/atomic-fence.ll
llvm/test/CodeGen/RISCV/atomic-load-store.ll
llvm/test/CodeGen/RISCV/atomic-rmw.ll
llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/module-elf-flags.ll
llvm/test/MC/RISCV/Ztso.s
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/elf-flags.s
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index c3c471c4bc396..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -365,30 +365,24 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
// RV32-ZFHMIN: "-target-feature" "+zfhmin"
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG
%s
-// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izalasr'
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32iztso'
// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr
-menable-experimental-extensions -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS
%s
-// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izalasr'
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32iztso'
// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version
number
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr0p7
-menable-experimental-extensions -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso0p7
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS
%s
-// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izalasr0p7'
-// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental
extension 'zalasr' (this compiler supports 0.1)
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32iztso0p7'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental
extension 'ztso' (this compiler supports 0.1)
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr0p1
-menable-experimental-extensions -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso0p1
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck
-check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
-// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zalasr"
-
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso1p0 -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZTSO %s
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZTSO %s
-// RV32-ZTSO: "-target-feature" "+ztso"
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-ztso"
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 46a61e3c0afc7..d7935af532dfa 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1650,13 +1650,13 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
// CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}}
-// RUN: %clang --target=riscv32-unknown-linux-gnu \
-// RUN: -march=rv32iztso1p0 -E -dM %s \
+// RUN: %clang --target=riscv32-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv32iztso0p1 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
-// RUN: %clang --target=riscv64-unknown-linux-gnu \
-//
[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)
preames wrote: > I think @preames told me he was keeping this experimental for a reason. Yes, revert pending. The concern here is that there are multiple possible ABIs here, and at the point I implemented this, the ABI chosen in my initial set of patches was compatible with the then current WMO ABI, but is *incompatible* with the revised ABI for load acquire/store release. I know there has been some work on this since, but the prominent warning comment has not been removed, and there is not discussion in this review about status. I will note that simply deleting a comment from the docs *which directly explain why something is still experimental* without discussing exactly that issue in the review thread is, IMO, poor behavior on all parties involved. https://github.com/llvm/llvm-project/pull/96465 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lld] [llvm] [RISCV] Make M imply Zmmul (PR #95070)
preames wrote: Given the concern about breaking configurations w/no-integrated-as and older binutils, can someone summarize here which versions of binutils are known to work/not work after this change? This will likely become the key search result for such breakage, and having it well documented for users seems critical. https://github.com/llvm/llvm-project/pull/95070 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)
@@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max", FeatureStdExtC], [TuneNoDefaultUnroll]>; +def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32", + SyntacoreSCR3RV32Model, + [Feature32Bit, + FeatureStdExtI, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtC], + [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + +def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64", preames wrote: This part should really be a standalone change. Please separate the addition of the new processor as it's own PR. https://github.com/llvm/llvm-project/pull/95427 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
preames wrote: > Will this core have active support on the LLVM side? I can't speak for the vendor, but I'll say that I'm interested in having this supported upstream. This looks to be a reasonable rva22 dev board w/V1.0, and having in tree support seems worthwhile. I've ordered one of these myself, and plan on using it for ongoing RISC-V vector development. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", + NoSchedModel, + !listconcat(RVA22S64Features, + [FeatureStdExtV, +FeatureStdExtSvnapot, +FeatureStdExtZbc, +FeatureStdExtZbkc, +FeatureStdExtZfh, +FeatureStdExtZicond, preames wrote: > The supported extensions are listed in 2.1.2 of this > [document](https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb), > including zicond. I @sunshaoce We should adjust the patch description to reference this document. If you have anything you think is supported which is not on the documented list, please highlight it so that @zqb-all can clarify docs. @zqb-all Thanks! https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", + NoSchedModel, + !listconcat(RVA22S64Features, + [FeatureStdExtV, +FeatureStdExtSvnapot, +FeatureStdExtZbc, +FeatureStdExtZbkc, +FeatureStdExtZfh, +FeatureStdExtZicond, +FeatureStdExtZmmul, +FeatureStdExtZvfh, +FeatureStdExtZvfhmin, +FeatureStdExtZvl32b, +FeatureStdExtZvl64b, +FeatureStdExtZvl128b, +FeatureStdExtZvl256b])>; preames wrote: Zvl256 implies Zvl32 through Zvl128, so those don't need to be explicitly repeated. Per the docs, the actual execution width is 128 bit so we could add [TuneDLenFactor2] to the tuning list. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", + NoSchedModel, + !listconcat(RVA22S64Features, + [FeatureStdExtV, +FeatureStdExtSvnapot, +FeatureStdExtZbc, +FeatureStdExtZbkc, +FeatureStdExtZfh, +FeatureStdExtZicond, preames wrote: Looking at e.g. zicond, I don't see anything in the docs which claim support for this extension. ruapu appears to work via running an instruction and checking for faults - this could be a dangerous thing to rely on if the CPU e.g. incorrectly implements some extension, or doesn't implement the reserved opcodes the way the tool expects. I suggest that we cut down this list to include *only* those things which are specified. We can expand that list later based on changes to documentation and/or communication with vendor. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/preames requested changes to this pull request. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [IR] Avoid creating icmp/fcmp constant expressions (PR #92885)
@@ -8,7 +8,8 @@ // CHECK: entry: // CHECK-NEXT: %retval = alloca i32 // CHECK-NEXT: store i32 0, ptr %retval -// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 true to i32 +// CHECK-NEXT: [[CMP:%.*]] = icmp ne ptr @b, @a +// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 preames wrote: Oh, ignore me. I didn't realize this was specific testing unsimplified IR. https://github.com/llvm/llvm-project/pull/92885 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [IR] Avoid creating icmp/fcmp constant expressions (PR #92885)
@@ -8,7 +8,8 @@ // CHECK: entry: // CHECK-NEXT: %retval = alloca i32 // CHECK-NEXT: store i32 0, ptr %retval -// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 true to i32 +// CHECK-NEXT: [[CMP:%.*]] = icmp ne ptr @b, @a +// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 preames wrote: This looks to be a missing constant fold somewhere. The compare should be folded to true, not a constantexpr. https://github.com/llvm/llvm-project/pull/92885 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Don't enable -mrelax-all for -O0 on RISC-V (PR #88538)
https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/88538 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #88954)
https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/88954 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
preames wrote:
Please rename NewArch to ArchStorage. Specifically, we end up with a StringRef
bound to this storage, and having it go out of scope before that StringRef
would be a use-after-free.
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ if (IsProfile) {
+// A mapping from profile name to march string with all mandatory
+// extensions.
+static const std::map SupportedProfiles = {
preames wrote:
This may not be fully evaluated at compile time. I'd go back to the static
arrays personally.
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ if (IsProfile) {
+// A mapping from profile name to march string with all mandatory
+// extensions.
+static const std::map SupportedProfiles = {
+{"rvi20u32", "rv32i"},
+{"rvi20u64", "rv64i"},
+{"rva20u64",
+ "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"},
+{"rva20s64",
+ "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_"
+ "za128rs_ssccptr_sstvala_sstvecd_svade_svbare"},
+{"rva22u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
+ "zicclsm_ziccrse_"
+ "zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"},
+{"rva22s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_"
+ "ssccptr_"
+ "sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"},
+{"rva23u64",
+ "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_zfa_"
+ "zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"},
+{"rva23s64",
+ "rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_"
+ "zawrs_"
+ "zfa_zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_"
+ "shcounterenw_"
+ "shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_"
+ "sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_"
+ "svbare_svinval_svnapot_svpbmt"},
+{"rvb23u64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
+ "zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_"
+ "zimop0p1_za64rs_zawrs_zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt"},
+{"rvb23s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
preames wrote:
The formatting on this is very odd - please file each line to 76 characters for
the long sequences of extensions.
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ if (IsProfile) {
+// A mapping from profile name to march string with all mandatory
+// extensions.
+static const std::map SupportedProfiles = {
+{"rvi20u32", "rv32i"},
+{"rvi20u64", "rv64i"},
+{"rva20u64",
+ "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"},
+{"rva20s64",
+ "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_"
+ "za128rs_ssccptr_sstvala_sstvecd_svade_svbare"},
+{"rva22u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
+ "zicclsm_ziccrse_"
+ "zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"},
+{"rva22s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_"
+ "ssccptr_"
+ "sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"},
+{"rva23u64",
+ "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_zfa_"
+ "zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"},
+{"rva23s64",
+ "rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_"
+ "zawrs_"
+ "zfa_zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_"
+ "shcounterenw_"
+ "shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_"
+ "sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_"
+ "svbare_svinval_svnapot_svpbmt"},
+{"rvb23u64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
+ "zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_"
+ "zimop0p1_za64rs_zawrs_zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt"},
+{"rvb23s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_"
+ "zawrs_"
+ "zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_"
+ "sstvala_sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"},
+{"rvm23u32",
+ "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop0p1_"
+ "zca_zcb_zce_zcmop0p2_zcmp_zcmt_zba_zbb_zbs"},
+};
+
+auto FoundProfile = llvm::find_if(
+SupportedProfiles,
+[Arch](const std::pair ) {
+ return Arch.starts_with(Profile.first);
+});
+
+if (FoundProfile == SupportedProfiles.end())
+ return createStringError(errc::invalid_argument, "unsupported profile");
+
+NewArch = FoundProfile->second;
+StringRef ArchWithoutProfile = Arch.substr(FoundProfile->first.size());
+if (!ArchWithoutProfile.empty()) {
+ if (!ArchWithoutProfile.starts_with("_"))
+return createStringError(
+errc::invalid_argument,
+"additional extensions must be after separator '_'");
+ NewArch += ArchWithoutProfile.str();
+}
+Arch = NewArch;
preames wrote:
One idea to simplify this code - build the std::string NewArch, and then make a
recursive call to this routine and return the result. This would avoid all the
lifetime issues involved with the fallthrough.
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
preames wrote:
You don't need this variable, please sink it into the if-clause below.
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/preames commented: After this was discussed at the sync-up call today, I believe we're in agreement on direction here. This is close to being ready and is just pending some code cleanup. https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -36,6 +36,11 @@ struct RISCVSupportedExtension {
}
};
+struct RISCVProfile {
preames wrote:
Very minor, but I believe you can use std::pair here instead.
https://github.com/llvm/llvm-project/pull/76357
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[clang] 13ccaf9 - Revert "Reapply "[analyzer] Accept C library functions from the `std` namespace""
Author: Philip Reames
Date: 2024-03-13T10:19:42-07:00
New Revision: 13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c
URL:
https://github.com/llvm/llvm-project/commit/13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c
DIFF:
https://github.com/llvm/llvm-project/commit/13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c.diff
LOG: Revert "Reapply "[analyzer] Accept C library functions from the `std`
namespace""
This reverts commit e48d5a838f69e0a8e0ae95a8aed1a8809f45465a.
Fails to build on x86-64 w/gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)
with the following message:
../llvm-project/clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp:41:28:
error: declaration of ‘std::unique_ptr
IsCLibraryFunctionTest::ASTUnit’ changes meaning of ‘ASTUnit’ [-fpermissive]
41 | std::unique_ptr ASTUnit;
|^~~
In file included from
../llvm-project/clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp:4:
../llvm-project/clang/include/clang/Frontend/ASTUnit.h:89:7: note: ‘ASTUnit’
declared here as ‘class clang::ASTUnit’
89 | class ASTUnit {
| ^~~
Added:
Modified:
clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
clang/unittests/StaticAnalyzer/CMakeLists.txt
llvm/utils/gn/secondary/clang/unittests/StaticAnalyzer/BUILD.gn
Removed:
clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp
diff --git
a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
index b4e1636130ca7c..3432d2648633c2 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
@@ -41,8 +41,12 @@ class CallDescription {
/// - We also accept calls where the number of arguments or parameters is
///greater than the specified value.
/// For the exact heuristics, see CheckerContext::isCLibraryFunction().
-/// (This mode only matches functions that are declared either directly
-/// within a TU or in the namespace `std`.)
+/// Note that functions whose declaration context is not a TU (e.g.
+/// methods, functions in namespaces) are not accepted as C library
+/// functions.
+/// FIXME: If I understand it correctly, this discards calls where C++ code
+/// refers a C library function through the namespace `std::` via headers
+/// like .
CLibrary,
/// Matches "simple" functions that are not methods. (Static methods are
diff --git a/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
b/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
index 1a9bff529e9bb1..d6d4cec9dd3d4d 100644
--- a/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
+++ b/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
@@ -87,11 +87,9 @@ bool CheckerContext::isCLibraryFunction(const FunctionDecl
*FD,
if (!II)
return false;
- // C library functions are either declared directly within a TU (the common
- // case) or they are accessed through the namespace `std` (when they are used
- // in C++ via headers like ).
- const DeclContext *DC = FD->getDeclContext()->getRedeclContext();
- if (!(DC->isTranslationUnit() || DC->isStdNamespace()))
+ // Look through 'extern "C"' and anything similar invented in the future.
+ // If this function is not in TU directly, it is not a C library function.
+ if (!FD->getDeclContext()->getRedeclContext()->isTranslationUnit())
return false;
// If this function is not externally visible, it is not a C library
function.
diff --git a/clang/unittests/StaticAnalyzer/CMakeLists.txt
b/clang/unittests/StaticAnalyzer/CMakeLists.txt
index db56e77331b821..775f0f8486b8f9 100644
--- a/clang/unittests/StaticAnalyzer/CMakeLists.txt
+++ b/clang/unittests/StaticAnalyzer/CMakeLists.txt
@@ -11,7 +11,6 @@ add_clang_unittest(StaticAnalysisTests
CallEventTest.cpp
ConflictingEvalCallsTest.cpp
FalsePositiveRefutationBRVisitorTest.cpp
- IsCLibraryFunctionTest.cpp
NoStateChangeFuncVisitorTest.cpp
ParamRegionTest.cpp
RangeSetTest.cpp
diff --git a/clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp
b/clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp
deleted file mode 100644
index 31ff13f428da36..00
--- a/clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp
+++ /dev/null
@@ -1,84 +0,0 @@
-#include "clang/ASTMatchers/ASTMatchFinder.h"
-#include "clang/ASTMatchers/ASTMatchers.h"
-#include "clang/Analysis/AnalysisDeclContext.h"
-#include "clang/Frontend/ASTUnit.h"
-#include "clang/StaticAnalyzer/Core/PathSensitive/CheckerContext.h"
-#include "clang/Tooling/Tooling.h"
-#include "gtest/gtest.h"
-
-#include
-
-using namespace clang;
-using namespace ento;
-using namespace ast_matchers;
-
-class IsCLibraryFunctionTest : public
[clang] [RISCV] Add canonical ISA string as Module metadata in IR. (PR #80760)
preames wrote: I agree with @asb's framing above. Assuming this doesn't commit us to something which is hard to forward version for some reason, I support addressing this in a target specific manner for the moment. https://github.com/llvm/llvm-project/pull/80760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)
@@ -3878,6 +3883,130 @@ static Align computeCommonAlignment(ArrayRef
VL) {
return CommonAlignment;
}
+/// Check if \p Order represents reverse order.
+static bool isReverseOrder(ArrayRef Order) {
+ unsigned Sz = Order.size();
+ return !Order.empty() && all_of(enumerate(Order), [&](const auto ) {
+return Pair.value() == Sz || Sz - Pair.index() - 1 == Pair.value();
+ });
+}
+
+/// Checks if the provided list of pointers \p Pointers represents the strided
+/// pointers for type ElemTy. If they are not, std::nullopt is returned.
+/// Otherwise, if \p Inst is not specified, just initialized optional value is
+/// returned to show that the pointers represent strided pointers. If \p Inst
+/// specified, the runtime stride is materialized before the given \p Inst.
+/// \returns std::nullopt if the pointers are not pointers with the runtime
+/// stride, nullptr or actual stride value, otherwise.
+static std::optional
+calculateRtStride(ArrayRef PointerOps, Type *ElemTy,
+ const DataLayout , ScalarEvolution ,
+ SmallVectorImpl ,
+ Instruction *Inst = nullptr) {
+ SmallVector SCEVs;
preames wrote:
An alternate approach which might be simpler and yet cover many of the
interesting test cases might be:
* Loop over the pointers, check that getPointerBase matches.
* Loop again doing removePointerBase
* This gives a list of offsets from base, bail if any non-constant
* Sort the list of constant offsets
* Check if strided w/shuffle?
If you don't want a shuffle afterwards, you can check the delta without sorting.
This won't cover non-constant strides, but I'm not sure we really care about
those in practice.
https://github.com/llvm/llvm-project/pull/80310
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[openmp] [clang-tools-extra] [libcxx] [lld] [flang] [clang] [llvm] [lldb] [mlir] [libc] [SLP]Add support for strided loads. (PR #80310)
@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef
VL, const Value *VL0,
std::optional Diff =
getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE);
// Check that the sorted loads are consecutive.
- if (static_cast(*Diff) == VL.size() - 1)
+ if (static_cast(*Diff) == Sz - 1)
return LoadsState::Vectorize;
// Simple check if not a strided access - clear order.
- IsPossibleStrided = *Diff % (VL.size() - 1) == 0;
+ bool IsPossibleStrided = *Diff % (Sz - 1) == 0;
+ // Try to generate strided load node if:
+ // 1. Target with strided load support is detected.
+ // 2. The number of loads is greater than MinProfitableStridedLoads,
+ // or the potential stride <= MaxProfitableLoadStride and the
+ // potential stride is power-of-2 (to avoid perf regressions for the very
+ // small number of loads) and max distance > number of loads, or
potential
+ // stride is -1.
+ // 3. The loads are ordered, or number of unordered loads <=
+ // MaxProfitableUnorderedLoads, or loads are in reversed order.
+ // (this check is to avoid extra costs for very expensive shuffles).
+ if (IsPossibleStrided && (((Sz > MinProfitableStridedLoads ||
+ (static_cast(std::abs(*Diff)) <=
+ MaxProfitableLoadStride * Sz &&
+ isPowerOf2_32(std::abs(*Diff &&
+ static_cast(std::abs(*Diff)) > Sz)
||
+*Diff == -(static_cast(Sz) - 1))) {
+int Stride = *Diff / static_cast(Sz - 1);
preames wrote:
How is the diff-in-bytes divided by the number of elements the stride? Did you
maybe mean to use element size here?
It's also possible you have two Sz variables with different meaning. I did not
check for this.
https://github.com/llvm/llvm-project/pull/80310
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[libcxx] [flang] [mlir] [openmp] [llvm] [clang] [clang-tools-extra] [lldb] [lld] [libc] [SLP]Add support for strided loads. (PR #80310)
https://github.com/preames commented: These comments are trying to be helpful in pointing out bits which might be simplified or split off, but my track record with SLP reviews is not great. Feel free to ignore any or all of these. https://github.com/llvm/llvm-project/pull/80310 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [libcxx] [lldb] [lld] [mlir] [clang-tools-extra] [libc] [openmp] [llvm] [clang] [SLP]Add support for strided loads. (PR #80310)
@@ -30,7 +30,7 @@ define void @test() {
; CHECK-SLP-THRESHOLD: bb:
; CHECK-SLP-THRESHOLD-NEXT:[[TMP0:%.*]] = insertelement <4 x ptr> poison,
ptr [[COND_IN_V]], i32 0
; CHECK-SLP-THRESHOLD-NEXT:[[TMP1:%.*]] = shufflevector <4 x ptr>
[[TMP0]], <4 x ptr> poison, <4 x i32> zeroinitializer
-; CHECK-SLP-THRESHOLD-NEXT:[[TMP2:%.*]] = getelementptr i64, <4 x ptr>
[[TMP1]], <4 x i64>
+; CHECK-SLP-THRESHOLD-NEXT:[[TMP2:%.*]] = getelementptr i64, <4 x ptr>
[[TMP1]], <4 x i64>
preames wrote:
Shouldn't this be a strided load with a stride of -4*8?
If what you're aiming for is test stability, can you use a index which doesn't
look anything like a strided load?
https://github.com/llvm/llvm-project/pull/80310
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[clang] [libc] [lld] [llvm] [lldb] [libcxx] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)
@@ -17,7 +17,7 @@ define i16 @test() {
; CHECK-NEXT:[[TMP4:%.*]] = call <2 x i16>
@llvm.masked.gather.v2i16.v2p0(<2 x ptr> [[TMP3]], i32 2, <2 x i1> , <2 x i16> poison)
; CHECK-NEXT:[[TMP5:%.*]] = extractelement <2 x i16> [[TMP4]], i32 0
; CHECK-NEXT:[[TMP6:%.*]] = extractelement <2 x i16> [[TMP4]], i32 1
-; CHECK-NEXT:[[CMP_I178:%.*]] = icmp ult i16 [[TMP6]], [[TMP5]]
+; CHECK-NEXT:[[CMP_I178:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]]
; CHECK-NEXT:br label [[WHILE_BODY_I]]
;
entry:
preames wrote:
Unless this is specifically testing something about offsets from null, can you
update this test to pass in a pointer argument and index off that?
(Separate change, no review needed.)
https://github.com/llvm/llvm-project/pull/80310
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[flang] [libc] [mlir] [libcxx] [lldb] [lld] [clang] [openmp] [clang-tools-extra] [llvm] [SLP]Add support for strided loads. (PR #80310)
@@ -397,27 +241,12 @@ define void @test3([48 x float]* %p, float* noalias %s) {
; CHECK-NEXT: entry:
; CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds [48 x float], ptr
[[P:%.*]], i64 0, i64 0
; CHECK-NEXT:[[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr
[[S:%.*]], i64 0
-; CHECK-NEXT:[[ARRAYIDX4:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 4
-; CHECK-NEXT:[[ARRAYIDX11:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 8
-; CHECK-NEXT:[[ARRAYIDX18:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 12
-; CHECK-NEXT:[[ARRAYIDX25:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 16
-; CHECK-NEXT:[[ARRAYIDX32:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 20
-; CHECK-NEXT:[[ARRAYIDX39:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 24
-; CHECK-NEXT:[[ARRAYIDX46:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 28
; CHECK-NEXT:[[ARRAYIDX48:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 23
-; CHECK-NEXT:[[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr
[[ARRAYIDX]], i32 0
-; CHECK-NEXT:[[TMP1:%.*]] = insertelement <8 x ptr> [[TMP0]], ptr
[[ARRAYIDX4]], i32 1
-; CHECK-NEXT:[[TMP2:%.*]] = insertelement <8 x ptr> [[TMP1]], ptr
[[ARRAYIDX11]], i32 2
-; CHECK-NEXT:[[TMP3:%.*]] = insertelement <8 x ptr> [[TMP2]], ptr
[[ARRAYIDX18]], i32 3
-; CHECK-NEXT:[[TMP4:%.*]] = insertelement <8 x ptr> [[TMP3]], ptr
[[ARRAYIDX25]], i32 4
-; CHECK-NEXT:[[TMP5:%.*]] = insertelement <8 x ptr> [[TMP4]], ptr
[[ARRAYIDX32]], i32 5
-; CHECK-NEXT:[[TMP6:%.*]] = insertelement <8 x ptr> [[TMP5]], ptr
[[ARRAYIDX39]], i32 6
-; CHECK-NEXT:[[TMP7:%.*]] = insertelement <8 x ptr> [[TMP6]], ptr
[[ARRAYIDX46]], i32 7
-; CHECK-NEXT:[[TMP8:%.*]] = call <8 x float>
@llvm.masked.gather.v8f32.v8p0(<8 x ptr> [[TMP7]], i32 4, <8 x i1> , <8 x float> poison)
-; CHECK-NEXT:[[TMP9:%.*]] = load <8 x float>, ptr [[ARRAYIDX48]], align 4
-; CHECK-NEXT:[[TMP10:%.*]] = shufflevector <8 x float> [[TMP9]], <8 x
float> poison, <8 x i32>
-; CHECK-NEXT:[[TMP11:%.*]] = fsub fast <8 x float> [[TMP10]], [[TMP8]]
-; CHECK-NEXT:store <8 x float> [[TMP11]], ptr [[ARRAYIDX2]], align 4
+; CHECK-NEXT:[[TMP0:%.*]] = call <8 x float>
@llvm.experimental.vp.strided.load.v8f32.p0.i64(ptr align 4 [[ARRAYIDX]], i64
16, <8 x i1> , i32 8)
+; CHECK-NEXT:[[TMP1:%.*]] = load <8 x float>, ptr [[ARRAYIDX48]], align 4
+; CHECK-NEXT:[[TMP2:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x
float> poison, <8 x i32>
preames wrote:
Can't this reverse become a negative strided load?
https://github.com/llvm/llvm-project/pull/80310
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[flang] [clang] [openmp] [mlir] [libc] [lldb] [lld] [clang-tools-extra] [llvm] [libcxx] [SLP]Add support for strided loads. (PR #80310)
@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef
VL, const Value *VL0,
std::optional Diff =
getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE);
// Check that the sorted loads are consecutive.
- if (static_cast(*Diff) == VL.size() - 1)
+ if (static_cast(*Diff) == Sz - 1)
return LoadsState::Vectorize;
// Simple check if not a strided access - clear order.
- IsPossibleStrided = *Diff % (VL.size() - 1) == 0;
+ bool IsPossibleStrided = *Diff % (Sz - 1) == 0;
+ // Try to generate strided load node if:
+ // 1. Target with strided load support is detected.
+ // 2. The number of loads is greater than MinProfitableStridedLoads,
+ // or the potential stride <= MaxProfitableLoadStride and the
+ // potential stride is power-of-2 (to avoid perf regressions for the very
+ // small number of loads) and max distance > number of loads, or
potential
+ // stride is -1.
+ // 3. The loads are ordered, or number of unordered loads <=
+ // MaxProfitableUnorderedLoads, or loads are in reversed order.
+ // (this check is to avoid extra costs for very expensive shuffles).
+ if (IsPossibleStrided && (((Sz > MinProfitableStridedLoads ||
+ (static_cast(std::abs(*Diff)) <=
+ MaxProfitableLoadStride * Sz &&
+ isPowerOf2_32(std::abs(*Diff &&
+ static_cast(std::abs(*Diff)) > Sz)
||
+*Diff == -(static_cast(Sz) - 1))) {
+int Stride = *Diff / static_cast(Sz - 1);
+if (*Diff == Stride * static_cast(Sz - 1)) {
+ if (TTI.isTypeLegal(VecTy) &&
preames wrote:
The isTypeLegal check here should be redundant.
https://github.com/llvm/llvm-project/pull/80310
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[mlir] [clang] [libc] [lldb] [lld] [openmp] [flang] [libcxx] [clang-tools-extra] [llvm] [SLP]Add support for strided loads. (PR #80310)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/80310 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [libc] [mlir] [clang-tools-extra] [openmp] [llvm] [lldb] [clang] [flang] [lld] [SLP]Add support for strided loads. (PR #80310)
@@ -7,7 +7,7 @@ define i32 @test(ptr noalias %p, ptr noalias %addr) {
; CHECK-NEXT: entry:
; CHECK-NEXT:[[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr
[[ADDR:%.*]], i32 0
; CHECK-NEXT:[[TMP1:%.*]] = shufflevector <8 x ptr> [[TMP0]], <8 x ptr>
poison, <8 x i32> zeroinitializer
-; CHECK-NEXT:[[TMP2:%.*]] = getelementptr i32, <8 x ptr> [[TMP1]], <8 x
i32>
+; CHECK-NEXT:[[TMP2:%.*]] = getelementptr i32, <8 x ptr> [[TMP1]], <8 x
i32>
preames wrote:
Same as last.
https://github.com/llvm/llvm-project/pull/80310
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[libcxx] [libc] [mlir] [clang-tools-extra] [openmp] [llvm] [lldb] [clang] [flang] [lld] [SLP]Add support for strided loads. (PR #80310)
preames wrote: FYI - https://github.com/llvm/llvm-project/pull/80360 adds testing infrastructure to exercise the TTI hooks. https://github.com/llvm/llvm-project/pull/80310 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[compiler-rt] [llvm] [clang-tools-extra] [lld] [clang] [libc] [libcxx] [lldb] [flang] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
@@ -326,6 +326,50 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp)) {
+unsigned TpRegs = getRegUsageForType(Tp);
+unsigned NumElems =
+divideCeil(Tp->getElementCount().getFixedValue(), TpRegs);
+// Whole vector extract - just the vector itself + (possible) vsetvli.
+// TODO: consider adding the cost for vsetvli.
+if (Index == 0 || (ST->getRealMaxVLen() == ST->getRealMinVLen() &&
+ Index % NumElems == 0)) {
+ std::pair SubLT =
+ getTypeLegalizationCost(SubTp);
+ return Index == 0
+ ? TTI::TCC_Free
+ : SubLT.first * getRISCVInstructionCost(RISCV::VMV_V_V,
+ SubLT.second,
+ CostKind);
+}
+ }
+ break;
+case TTI::SK_InsertSubvector:
+ if (auto *FSubTy = dyn_cast(SubTp)) {
+unsigned TpRegs = getRegUsageForType(Tp);
preames wrote:
Same basic style comments as above.
https://github.com/llvm/llvm-project/pull/80164
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[clang-tools-extra] [clang] [libcxx] [compiler-rt] [lldb] [llvm] [flang] [lld] [libc] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
@@ -326,6 +326,50 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp)) {
+unsigned TpRegs = getRegUsageForType(Tp);
+unsigned NumElems =
+divideCeil(Tp->getElementCount().getFixedValue(), TpRegs);
+// Whole vector extract - just the vector itself + (possible) vsetvli.
+// TODO: consider adding the cost for vsetvli.
+if (Index == 0 || (ST->getRealMaxVLen() == ST->getRealMinVLen() &&
preames wrote:
I think this check would be more clearly expressed as an and of the following
clauses
a) ST->getRealMaxVLen() == ST->getRealMinVLen()
b) NumElems * ElementSizeInBits == VLEN
c) Index % NumElems == 0
Note that this only supports m1 full extracts. But starting there and
extending it to m2, and m4 later seems entirely reasonable.
https://github.com/llvm/llvm-project/pull/80164
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[lldb] [compiler-rt] [clang-tools-extra] [llvm] [flang] [clang] [libcxx] [libc] [lld] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
@@ -326,6 +326,50 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp)) {
+unsigned TpRegs = getRegUsageForType(Tp);
+unsigned NumElems =
+divideCeil(Tp->getElementCount().getFixedValue(), TpRegs);
+// Whole vector extract - just the vector itself + (possible) vsetvli.
+// TODO: consider adding the cost for vsetvli.
+if (Index == 0 || (ST->getRealMaxVLen() == ST->getRealMinVLen() &&
+ Index % NumElems == 0)) {
+ std::pair SubLT =
+ getTypeLegalizationCost(SubTp);
+ return Index == 0
+ ? TTI::TCC_Free
+ : SubLT.first * getRISCVInstructionCost(RISCV::VMV_V_V,
preames wrote:
For a full VREG case, you never need the VMV_V_V. You only need the VMV_V_V if
NumElems < VLMAX.
Extending this to sub-register extract with exact VLEN known would be
reasonable, but let's do that in a separate patch.
https://github.com/llvm/llvm-project/pull/80164
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[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", + "'Ssccptr' (Main memory supports page table reads)", []>; + +def FeatureStdExtShcounterenvw +: SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true", + "'Shcounterenw' (Support writeable enables for any supproted counter)", []>; +def FeatureStdExtSscounterenvw +: SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true", + "'Sscounterenw' (Support writeable enables for any supproted counter)", []>; preames wrote: I honestly neither understand this, nor particular care. I'm okay with any reasonable wording you want to use here - up to and including the previous identical wording for the two with the minor typo fix. If we find better wording later, we can just update it then. https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)
https://github.com/preames closed https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)
preames wrote: > It has been approved to be pursued as a fast track extension > (https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698). > It has not yet been approved by the chairs. Works for me. I've edited the PR description to include this information so that it ends up in the submit message. I'm about to land this change on @mehnadnerd behalf since he doesn't have commit access. This was requested out of band. https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", + "'Ssccptr' (Main memory supports page table reads)", []>; + +def FeatureStdExtShcounterenvw +: SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true", + "'Shcounterenw' (Support writeable enables for any supproted counter)", []>; +def FeatureStdExtSscounterenvw +: SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true", + "'Sscounterenw' (Support writeable enables for any supproted counter)", []>; preames wrote: The difference between the two appears to be which counter must be writeable. So maybe something like, "hcounter bits writeable for all non-zero hpmcounter bits" vs "scounter bits writeable for all non-zero hpmcounter bits"? This is the case where having an actual spec for this would be really useful. https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", + "'Ssccptr' (Main memory supports page table reads)", []>; + +def FeatureStdExtShcounterenvw +: SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true", + "'Shcounterenw' (Support writeable enables for any supproted counter)", []>; +def FeatureStdExtSscounterenvw +: SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true", + "'Sscounterenw' (Support writeable enables for any supproted counter)", []>; preames wrote: This description looks wrong. Document says "Sscounterenw For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable." Maybe: "Support writeable enables for any supproted counter (with exception of zero registers)" Also, typo: "supproted" should be "supported" https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
https://github.com/preames approved this pull request. LGTM w/comments addressed. https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)
preames wrote: I think we need some kind of official documentation to merge this. I went looking to see if I could find mention of this extension in e.g. ARC notes, and didn't find it. @mehnadnerd can you provide some kind of link or reference to some RVI source indicating the status of this proposal? It doesn't need to be near ratified, I'm just worried about the precedent we'd set by accepting an experimental extension with the only reference being an individual person's github. https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/79911
>From 3344e42d05875269b680b9626cd6cd093e88d81e Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH 1/2] [RISCV][MC] MC layer support for the experimental zalasr
extension
---
.../test/Preprocessor/riscv-target-features.c | 9 +++
llvm/docs/RISCVUsage.rst | 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td | 65
llvm/test/CodeGen/RISCV/attributes.ll | 4 +
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/rv32zalasr-invalid.s | 40 ++
llvm/test/MC/RISCV/rv32zalasr-valid.s | 78 +++
llvm/test/MC/RISCV/rv64zalasr-invalid.s | 28 +++
llvm/test/MC/RISCV/rv64zalasr-valid.s | 31
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
13 files changed, 271 insertions(+)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
create mode 100644 llvm/test/MC/RISCV/rv32zalasr-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zalasr-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zalasr-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zalasr-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 2361c83a5a610..35d112bcd070f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -144,6 +144,7 @@
// CHECK-NOT: __riscv_zaamo {{.*$}}
// CHECK-NOT: __riscv_zacas {{.*$}}
+// CHECK-NOT: __riscv_zalasr {{.*$}}
// CHECK-NOT: __riscv_zalrsc {{.*$}}
// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
@@ -1333,6 +1334,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
// CHECK-ZACAS-EXT: __riscv_zacas 100{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zalasr0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zalasr0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
+// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
+
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zalrsc0p2 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 5caf2fee197f2..a957a8dfba95b 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -232,6 +232,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zacas``
LLVM implements the `1.0-rc1 draft specification
`_.
+``experimental-zalasr``
+ LLVM implements the `0.0.5 draft specification
`_.
+
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
LLVM implements assembler support for the `1.0.0-rc2 specification
`_.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 0ae1fc01e4ffc..8f31b0f40d5c9 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -197,6 +197,7 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zaamo", {0, 2}},
{"zabha", {1, 0}},
{"zacas", {1, 0}},
+{"zalasr", {0, 1}},
{"zalrsc", {0, 2}},
{"zcmop", {0, 2}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 6b7bf4886c263..6f87eae101f04 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -192,6 +192,13 @@ def HasStdExtZacas :
Predicate<"Subtarget->hasStdExtZacas()">,
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
+def FeatureStdExtZalasr
+: SubtargetFeature<"experimental-zalasr", "HasStdExtZalasr", "true",
+ "'Zalasr' (Load-Acquire and Store-Release
Instructions)">;
+def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
+ AssemblerPredicate<(all_of FeatureStdExtZalasr),
+ "'Zalasr' (Load-Acquire and Store-Release
Instructions)">;
+
def FeatureStdExtZalrsc
: SubtargetFeature<"experimental-zalrsc", "HasStdExtZalrsc", "true",
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
[clang] [llvm] [RISCV] Graduate Zicond to non-experimental (PR #79811)
https://github.com/preames approved this pull request. LGTM as well. https://github.com/llvm/llvm-project/pull/79811 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [driver] Respect the mode the driver is in for autocomplete (PR #74770)
preames wrote: Not actively working on this. Anyone interested is welcome to pick up the patch. https://github.com/llvm/llvm-project/pull/74770 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [driver] Respect the mode the driver is in for autocomplete (PR #74770)
https://github.com/preames closed https://github.com/llvm/llvm-project/pull/74770 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][doc] Add blank line before lists (PR #77573)
https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77573 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
@@ -96,6 +96,8 @@ on support follow. ``Svnapot`` Assembly Support ``Svpbmt`` Supported ``V``Supported + ``Za128rs`` Supported preames wrote: I think these may warrant an explanatory note after the table. See what we do for e.g. zicntr. Something which says these are defined by the profile specification seems like a useful breadcrumb. https://github.com/llvm/llvm-project/pull/77458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC (PR #77645)
https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77645 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [clang] [Flang] Support -mrvv-vector-bits flag (PR #77588)
https://github.com/preames approved this pull request. LGTM We should explore options for merging the option processing code for options supported by both clang and flang, but that's explicitly future work. https://github.com/llvm/llvm-project/pull/77588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 0b7dda3 - Revert "[flang][nfc] Refactor linker invocation logic (#75534)"
Author: Philip Reames
Date: 2023-12-15T11:08:09-08:00
New Revision: 0b7dda3d4cbe6a4180fd80f91e9f29e474c1d896
URL:
https://github.com/llvm/llvm-project/commit/0b7dda3d4cbe6a4180fd80f91e9f29e474c1d896
DIFF:
https://github.com/llvm/llvm-project/commit/0b7dda3d4cbe6a4180fd80f91e9f29e474c1d896.diff
LOG: Revert "[flang][nfc] Refactor linker invocation logic (#75534)"
This reverts commit 71bbfabd08d90a3007f6034e420daa66c41027db. Breaks
check-flang on x86_64 host.
Added:
Modified:
clang/lib/Driver/ToolChains/CommonArgs.cpp
flang/test/Driver/linker-flags.f90
Removed:
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 6de41642a734a7..3d1df58190ce05 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -1116,87 +1116,73 @@ bool tools::addOpenMPRuntime(ArgStringList ,
const ToolChain ,
return true;
}
-/// Determines if --whole-archive is active in the list of arguments.
-static bool isWholeArchivePresent(const ArgList ) {
- bool WholeArchiveActive = false;
- for (auto *Arg : Args.filtered(options::OPT_Wl_COMMA)) {
-if (Arg) {
- for (StringRef ArgValue : Arg->getValues()) {
-if (ArgValue == "--whole-archive")
- WholeArchiveActive = true;
-if (ArgValue == "--no-whole-archive")
- WholeArchiveActive = false;
- }
-}
- }
-
- return WholeArchiveActive;
-}
-
-/// Add Fortran runtime libs for MSVC
-static void addFortranRuntimeLibsMSVC(const ArgList ,
- llvm::opt::ArgStringList ) {
- unsigned RTOptionID = options::OPT__SLASH_MT;
- if (auto *rtl = Args.getLastArg(options::OPT_fms_runtime_lib_EQ)) {
-RTOptionID = llvm::StringSwitch(rtl->getValue())
- .Case("static", options::OPT__SLASH_MT)
- .Case("static_dbg", options::OPT__SLASH_MTd)
- .Case("dll", options::OPT__SLASH_MD)
- .Case("dll_dbg", options::OPT__SLASH_MDd)
- .Default(options::OPT__SLASH_MT);
- }
- switch (RTOptionID) {
- case options::OPT__SLASH_MT:
-CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.static.lib");
-break;
- case options::OPT__SLASH_MTd:
-CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.static_dbg.lib");
-break;
- case options::OPT__SLASH_MD:
-CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.dynamic.lib");
-break;
- case options::OPT__SLASH_MDd:
-CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.dynamic_dbg.lib");
-break;
- }
-}
-
-/// Add Fortran runtime libs
void tools::addFortranRuntimeLibs(const ToolChain , const ArgList ,
llvm::opt::ArgStringList ) {
- // 1. Link FortranRuntime and FortranDecimal
- // These are handled earlier on Windows by telling the frontend driver to
- // add the correct libraries to link against as dependents in the object
- // file.
- if (!TC.getTriple().isKnownWindowsMSVCEnvironment()) {
-CmdArgs.push_back("-lFortranRuntime");
-CmdArgs.push_back("-lFortranDecimal");
- }
+ // These are handled earlier on Windows by telling the frontend driver to add
+ // the correct libraries to link against as dependents in the object file.
- // 2. Link FortranMain
- // If -fno-fortran-main has been passed, skip linking Fortran_main.a
- if (Args.hasArg(options::OPT_no_fortran_main))
-return;
+ // if -fno-fortran-main has been passed, skip linking Fortran_main.a
+ bool LinkFortranMain = !Args.hasArg(options::OPT_no_fortran_main);
+ if (!TC.getTriple().isKnownWindowsMSVCEnvironment()) {
+if (LinkFortranMain) {
+ // The --whole-archive option needs to be part of the link line to
+ // make sure that the main() function from Fortran_main.a is pulled
+ // in by the linker. Determine if --whole-archive is active when
+ // flang will try to link Fortran_main.a. If it is, don't add the
+ // --whole-archive flag to the link line. If it's not, add a proper
+ // --whole-archive/--no-whole-archive bracket to the link line.
+ bool WholeArchiveActive = false;
+ for (auto *Arg : Args.filtered(options::OPT_Wl_COMMA)) {
+if (Arg) {
+ for (StringRef ArgValue : Arg->getValues()) {
+if (ArgValue == "--whole-archive")
+ WholeArchiveActive = true;
+if (ArgValue == "--no-whole-archive")
+ WholeArchiveActive = false;
+ }
+}
+ }
- // 2.1. MSVC
- if (TC.getTriple().isKnownWindowsMSVCEnvironment()) {
-addFortranRuntimeLibsMSVC(Args, CmdArgs);
-return;
- }
+ // TODO: Find an equivalent of `--whole-archive` for Darwin.
+ if (!WholeArchiveActive && !TC.getTriple().isMacOSX()) {
+CmdArgs.push_back("--whole-archive");
+CmdArgs.push_back("-lFortran_main");
+
[llvm] [clang] [clang-tools-extra] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)
@@ -228,87 +228,86 @@ define void @widen_broadcast_unaligned(ptr %p0, i32 %v) {
}
define i128 @load_i128(ptr %ptr) {
-; CHECK-O0-LABEL: load_i128:
-; CHECK-O0: # %bb.0:
-; CHECK-O0-NEXT:pushq %rbx
-; CHECK-O0-NEXT:.cfi_def_cfa_offset 16
-; CHECK-O0-NEXT:.cfi_offset %rbx, -16
-; CHECK-O0-NEXT:xorl %eax, %eax
-; CHECK-O0-NEXT:movl %eax, %ebx
-; CHECK-O0-NEXT:movq %rbx, %rax
-; CHECK-O0-NEXT:movq %rbx, %rdx
-; CHECK-O0-NEXT:movq %rbx, %rcx
-; CHECK-O0-NEXT:lock cmpxchg16b (%rdi)
-; CHECK-O0-NEXT:popq %rbx
-; CHECK-O0-NEXT:.cfi_def_cfa_offset 8
-; CHECK-O0-NEXT:retq
-;
-; CHECK-O3-LABEL: load_i128:
-; CHECK-O3: # %bb.0:
-; CHECK-O3-NEXT:pushq %rbx
-; CHECK-O3-NEXT:.cfi_def_cfa_offset 16
-; CHECK-O3-NEXT:.cfi_offset %rbx, -16
-; CHECK-O3-NEXT:xorl %eax, %eax
-; CHECK-O3-NEXT:xorl %edx, %edx
-; CHECK-O3-NEXT:xorl %ecx, %ecx
-; CHECK-O3-NEXT:xorl %ebx, %ebx
-; CHECK-O3-NEXT:lock cmpxchg16b (%rdi)
-; CHECK-O3-NEXT:popq %rbx
-; CHECK-O3-NEXT:.cfi_def_cfa_offset 8
-; CHECK-O3-NEXT:retq
+; CHECK-O0-CUR-LABEL: load_i128:
preames wrote:
Your tests need updated, these check prefixes no longer exist.
https://github.com/llvm/llvm-project/pull/74275
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[llvm] [clang-tools-extra] [clang] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)
@@ -30095,12 +30102,16 @@ TargetLoweringBase::AtomicExpansionKind
X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
Type *MemType = SI->getValueOperand()->getType();
- bool NoImplicitFloatOps =
- SI->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat);
- if (MemType->getPrimitiveSizeInBits() == 64 && !Subtarget.is64Bit() &&
- !Subtarget.useSoftFloat() && !NoImplicitFloatOps &&
- (Subtarget.hasSSE1() || Subtarget.hasX87()))
-return AtomicExpansionKind::None;
+ if (!SI->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat) &&
+ !Subtarget.useSoftFloat()) {
+if (MemType->getPrimitiveSizeInBits() == 64 && !Subtarget.is64Bit() &&
+(Subtarget.hasSSE1() || Subtarget.hasX87()))
preames wrote:
Do we need to check the alignment here?
https://github.com/llvm/llvm-project/pull/74275
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[clang-tools-extra] [clang] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)
@@ -30115,12 +30126,16 @@
X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
// If this a 64 bit atomic load on a 32-bit target and SSE2 is enabled, we
// can use movq to do the load. If we have X87 we can load into an 80-bit
// X87 register and store it to a stack temporary.
preames wrote:
Can you move the comment down to the case it applies to (inside the outer if).
Currently, it binds to both cases which is misleading.
https://github.com/llvm/llvm-project/pull/74275
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[clang-tools-extra] [clang] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)
@@ -31259,14 +31274,23 @@ static SDValue LowerATOMIC_STORE(SDValue Op,
SelectionDAG ,
if (!IsSeqCst && IsTypeLegal)
return Op;
- if (VT == MVT::i64 && !IsTypeLegal) {
+ if (!IsTypeLegal && !Subtarget.useSoftFloat() &&
+ !DAG.getMachineFunction().getFunction().hasFnAttribute(
+ Attribute::NoImplicitFloat)) {
+SDValue Chain;
+// For illegal i128 atomic_store, when AVX is enabled, we can simply emit a
+// vector store.
+if (VT == MVT::i128) {
+ if (Subtarget.is64Bit() && Subtarget.hasAVX()) {
preames wrote:
Looks like you can collapse one level of if clause here.
https://github.com/llvm/llvm-project/pull/74275
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[clang] [clang-tools-extra] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)
@@ -31259,14 +31274,23 @@ static SDValue LowerATOMIC_STORE(SDValue Op,
SelectionDAG ,
if (!IsSeqCst && IsTypeLegal)
return Op;
- if (VT == MVT::i64 && !IsTypeLegal) {
+ if (!IsTypeLegal && !Subtarget.useSoftFloat() &&
+ !DAG.getMachineFunction().getFunction().hasFnAttribute(
+ Attribute::NoImplicitFloat)) {
+SDValue Chain;
+// For illegal i128 atomic_store, when AVX is enabled, we can simply emit a
+// vector store.
+if (VT == MVT::i128) {
+ if (Subtarget.is64Bit() && Subtarget.hasAVX()) {
+SDValue VecVal = DAG.getBitcast(MVT::v2i64, Node->getVal());
+Chain = DAG.getStore(Node->getChain(), dl, VecVal, Node->getBasePtr(),
+ Node->getMemOperand());
+ }
+}
+
// For illegal i64 atomic_stores, we can try to use MOVQ or MOVLPS if SSE
// is enabled.
-bool NoImplicitFloatOps =
-DAG.getMachineFunction().getFunction().hasFnAttribute(
-Attribute::NoImplicitFloat);
-if (!Subtarget.useSoftFloat() && !NoImplicitFloatOps) {
- SDValue Chain;
+if (VT == MVT::i64) {
if (Subtarget.hasSSE1()) {
preames wrote:
Same here.
https://github.com/llvm/llvm-project/pull/74275
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[clang] [RISCV] Reduce the size of the index used for RVV intrinsics. NFC (PR #74906)
preames wrote: > > LGTM - though maybe use uint32_t? > > Looking at this code, the whole Intrinsics map vs OverloadIntrinsic map > > structure loops to have heavy redundancy and could be greatly simplified. > > Maybe a follow up? > > Did you have a specific idea in mind? Maybe we could use a single map and use > the size of the vector being more than 1 to detect overloaded? > > I'm skeptical that the `8` is the correct inline space for the SmallVector in > OverloadedIntrinsicMap. That's basically where I was going. We track every name to index mapping twice, and we really only need to do so once. Maybe the cost of a SmallVector is high enough to be worth two structures, but then why not have a signal value in the primary map and a much smaller index keyed overload structure? https://github.com/llvm/llvm-project/pull/74906 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Reduce the size of the index used for RVV intrinsics. NFC (PR #74906)
https://github.com/preames approved this pull request. LGTM - though maybe use uint32_t? Looking at this code, the whole Intrinsics map vs OverloadIntrinsic map structure loops to have heavy redundancy and could be greatly simplified. Maybe a follow up? https://github.com/llvm/llvm-project/pull/74906 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Enable target attribute when invoked through clang driver (PR #74889)
https://github.com/preames closed https://github.com/llvm/llvm-project/pull/74889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Enable target attribute when invoked through clang driver (PR #74889)
preames wrote: > Related question. If there is an -mcpu on the command line and target > attribute changes the march, do we keep the original CPU in the -target-cpu > attribute or drop it. The reason for all those negative features from the > driver was to make the backend not infer any features from the CPU that > weren't in the provided march. So I'm wondering if we have that issue with > the target attribute now. It looks like the original -mcpu from the command line is passed through the to the function attributes unless the *cpu* is overridden via the target attribute. Doing a full replacement of the march does not appear to change or remove the target-cpu attribute on the result. One case I could see being problematic would be a CPU which enabled e.g. V, and a replacement march which didn't. Before this change, we'd end up with with an explicit target-feature for +v (coming from the original list passed into cc1), and that's clearly wrong. After this change, we end up with the explicit features being entirely missing (i.e. no explicit +v). I had to go run a test to see what happened from there. It does look like we re-infer from the cpu definition and proceed to generate vector code. Yeah, that's more than a bit suspect. This does fall into the "extension subtraction" case we'd tried to leave out of the specification. So I can see two fixes here: add back the explicit negative feature, or update the specification text to disallow this. https://github.com/llvm/llvm-project/pull/74889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Enable target attribute when invoked through clang driver (PR #74889)
https://github.com/preames created
https://github.com/llvm/llvm-project/pull/74889
d80e46d added support for the target function attribute. However, it turns out
that commit has a nasty bug/oversight. As the tests in that revision show,
everything works if clang -cc1 is directly invoked. I was suprised to learn
this morning that compiling with clang (i.e. the typical user workflow) did not
work.
The bug is that if a set of explicit negative extensions is passed to cc1 at
the command line (as the clang driver always does), we were copying these
negative extensions to the end of the rewritten extension list. When this was
later parsed, this had the effect of turning back off any extension that the
target attribute had enabled.
This patch updates the logic to only propagate the features from the input
which don't appear in the rewritten form in either positive or negative form.
Note that this code structure is still highly suspect. In particular I'm
fairly sure that mixing extension versions with this code will result in odd
results. However, I figure its better to have something which mostly works
than something which doesn't work at all.
>From 65707b837a8bb7283896d2c9d4933a17e02a20b9 Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Fri, 8 Dec 2023 12:49:58 -0800
Subject: [PATCH] [RISCV] Enable target attribute when invoked through clang
driver
d80e46d added support for the target function attribute. However,
it turns out that commit has a nasty bug/oversight. As the tests
in that revision show, everything works if clang -cc1 is directly
invoked. I was suprised to learn this morning that compiling with
clang (i.e. the typical user workflow) did not work.
The bug is that if a set of explicit negative extensions is passed
to cc1 at the command line (as the clang driver always does), we
were copying these negative extensions to the end of the rewritten
extension list. When this was later parsed, this had the effect of
turning back off any extension that the target attribute had enabled.
This patch updates the logic to only propagate the features from
the input which don't appear in the rewritten form in either
positive or negative form.
Note that this code structure is still highly suspect. In particular
I'm fairly sure that mixing extension versions with this code will
result in odd results. However, I figure its better to have something
which mostly works than something which doesn't work at all.
---
clang/lib/Basic/Targets/RISCV.cpp | 15 +
.../CodeGen/RISCV/riscv-func-attr-target.c| 21 ++-
2 files changed, 22 insertions(+), 14 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 13f934e9947212..184176c05da23b 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -304,11 +304,18 @@ bool RISCVTargetInfo::initFeatureMap(
// RISCVISAInfo makes implications for ISA features
std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
- // Add non-ISA features like `relax` and `save-restore` back
- for (const std::string : NewFeaturesVec)
-if (!llvm::is_contained(ImpliedFeatures, Feature))
- ImpliedFeatures.push_back(Feature);
+ // parseFeatures normalizes the feature set by dropping any explicit
+ // negatives, and non-extension features. We need to preserve the later
+ // for correctness and want to preserve the former for consistency.
+ for (auto : NewFeaturesVec) {
+ StringRef ExtName = Feature;
+ assert(ExtName.size() > 1 && (ExtName[0] == '+' || ExtName[0] == '-'));
+ ExtName = ExtName.drop_front(1); // Drop '+' or '-'
+ if (!llvm::is_contained(ImpliedFeatures, ("+" + ExtName).str()) &&
+ !llvm::is_contained(ImpliedFeatures, ("-" + ExtName).str()))
+ ImpliedFeatures.push_back(Feature);
+ }
return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
}
diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index 74bc5f2ac70492..506acaba687417 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -1,6 +1,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature
+m \
-// RUN: -target-feature +a -target-feature +save-restore \
+// RUN: -target-feature +a -target-feature +save-restore -target-feature -zbb
\
+// RUN: -target-feature -relax -target-feature -zfa \
// RUN: -emit-llvm %s -o - | FileCheck %s
// CHECK-LABEL: define dso_local void @testDefault
@@ -35,12 +36,12 @@ testAttrFullArchAndAttrCpu() {}
__attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
//.
-// CHECK: attributes #0 = {
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei" }
-// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64"
[clang] [driver] Respect the mode the driver is in for autocomplete (PR #74770)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/74770 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [driver] Respect the mode the driver is in for autocomplete (PR #74770)
https://github.com/preames created
https://github.com/llvm/llvm-project/pull/74770
The previous code was always auto-completing options for the clang mode. We'd
special cases flang to allow both clang and flang options, but this doesn't
match either the help output or the actual argument parsing. Seemingly, the
obvious thing to do is to auto-complete with the same options we'd accept?
Note: Advice on how to test this is very welcome. I don't see any testing in
tree for anything except clang, and I don't personally use this auto complete
feature at all.
>From 255c261df90bd15d3bcee7a212758c2de4c56e69 Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Thu, 7 Dec 2023 13:51:26 -0800
Subject: [PATCH] [driver] Respect the mode the driver is in for autocomplete
The previous code was always auto-completing options for the clang
mode. We'd special cases flang to allow both clang and flang options,
but this doesn't match either the help output or the actual argument
parsing. Seemingly, the obvious thing to do is to auto-complete with
the same options we'd accept?
Note: Advice on how to test this is very welcome. I don't see any testing
in tree for anything except clang, and I don't personally use this auto
complete feature at all.
---
clang/lib/Driver/Driver.cpp | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index e241706b9082ee..49e272f69d8130 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -1991,12 +1991,7 @@ void Driver::HandleAutocompletions(StringRef
PassedFlags) const {
std::vector SuggestedCompletions;
std::vector Flags;
- llvm::opt::Visibility VisibilityMask(options::ClangOption);
-
- // Make sure that Flang-only options don't pollute the Clang output
- // TODO: Make sure that Clang-only options don't pollute Flang output
- if (IsFlangMode())
-VisibilityMask = llvm::opt::Visibility(options::FlangOption);
+ llvm::opt::Visibility VisibilityMask = getOptionVisibilityMask();
// Distinguish "--autocomplete=-someflag" and "--autocomplete=-someflag,"
// because the latter indicates that the user put space before pushing tab
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[clang] a93cacf - [clang driver] Remove a bit of redundant flang specific code [nfc]
Author: Philip Reames
Date: 2023-12-06T14:20:36-08:00
New Revision: a93cacf9b08f0780f2ae2832da10a9a841ae7d03
URL:
https://github.com/llvm/llvm-project/commit/a93cacf9b08f0780f2ae2832da10a9a841ae7d03
DIFF:
https://github.com/llvm/llvm-project/commit/a93cacf9b08f0780f2ae2832da10a9a841ae7d03.diff
LOG: [clang driver] Remove a bit of redundant flang specific code [nfc]
getOptionVisibilityMask already returns options::FlangOption in FlangMode,
so this assignment is entirely pointless.
Added:
Modified:
clang/lib/Driver/Driver.cpp
Removed:
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 6f5ff81410326..e241706b9082e 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -1940,12 +1940,6 @@ int Driver::ExecuteCompilation(
void Driver::PrintHelp(bool ShowHidden) const {
llvm::opt::Visibility VisibilityMask = getOptionVisibilityMask();
- // TODO: We're overriding the mask for flang here to keep this NFC for the
- // option refactoring, but what we really need to do is annotate the flags
- // that Flang uses.
- if (IsFlangMode())
-VisibilityMask = llvm::opt::Visibility(options::FlangOption);
-
std::string Usage = llvm::formatv("{0} [options] file...", Name).str();
getOpts().printHelp(llvm::outs(), Usage.c_str(), DriverTitle.c_str(),
ShowHidden, /*ShowAllAliases=*/false,
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[llvm] [clang] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)
https://github.com/preames closed https://github.com/llvm/llvm-project/pull/73971 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/73971
>From 2f746ba1857d0d9f3dc20bbde499f2340735b05e Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Thu, 30 Nov 2023 10:34:22 -0800
Subject: [PATCH 1/2] [RISCV] Collapse fast unaligned access into a single
feature [nfc-ish]
When we'd originally added unaligned-scalar-mem and unaligned-vector-mem,
they were separated into two parts under the theory that some processor
might implement one, but not the other. At the moment, we don't have
evidence of such a processor. The C/C++ level interface, and the clang
driver command lines have settled on a single unaligned flag which
indicates both scalar and vector support unaligned. Given that, let's
remove the test matrix complexity for a set of configurations which
don't appear useful.
Given these are internal feature names, I don't think we need to
provide any forward compatibility. Anyone disagree?
Note: The immediate trigger for this patch was finding another case
where the unaligned-vector-mem wasn't being properly serialized to
IR from clang which resulted in problems reproducing assembly from
clang's -emit-llvm feature. Instead of fixing this, I decided getting
rid of the complexity was the better approach.
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
clang/lib/Driver/ToolChains/Arch/RISCV.cpp| 15 +-
clang/test/Driver/riscv-features.c| 20 +++
.../Target/RISCV/RISCVExpandPseudoInsts.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCVFeatures.td| 13
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 16 +++
.../Target/RISCV/RISCVTargetTransformInfo.h | 4 ++--
llvm/test/CodeGen/RISCV/memcpy-inline.ll | 4 ++--
llvm/test/CodeGen/RISCV/memcpy.ll | 4 ++--
llvm/test/CodeGen/RISCV/memset-inline.ll | 4 ++--
llvm/test/CodeGen/RISCV/pr56110.ll| 2 +-
.../RISCV/riscv-func-target-feature.ll| 2 +-
.../rvv/concat-vectors-constant-stride.ll | 4 ++--
.../rvv/fixed-vectors-strided-load-combine.ll | 2 +-
.../RISCV/rvv/fixed-vectors-unaligned.ll | 4 ++--
llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll | 4 ++--
llvm/test/CodeGen/RISCV/rvv/memset-inline.ll | 4 ++--
.../RISCV/rvv/unaligned-loads-stores.ll | 4 ++--
.../CodeGen/RISCV/unaligned-load-store.ll | 4 ++--
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 2 +-
20 files changed, 51 insertions(+), 67 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index d1d9cc1c770e361..6ee82d6665501b9 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -377,7 +377,7 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector ,
if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
HasLegalHalfType = true;
- FastUnalignedAccess = llvm::is_contained(Features, "+unaligned-scalar-mem");
+ FastUnalignedAccess = llvm::is_contained(Features, "+fast-unaligned-access");
return true;
}
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 346fb67ff277e9c..5db188fd7587daf 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -65,7 +65,7 @@ static void getRISCFeaturesFromMcpu(const Driver , const
Arg *A,
}
if (llvm::RISCV::hasFastUnalignedAccess(Mcpu))
-Features.push_back("+unaligned-scalar-mem");
+Features.push_back("+fast-unaligned-access");
}
void riscv::getRISCVTargetFeatures(const Driver , const llvm::Triple ,
@@ -174,15 +174,10 @@ void riscv::getRISCVTargetFeatures(const Driver , const
llvm::Triple ,
bool HasV = llvm::is_contained(Features, "+zve32x");
if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
options::OPT_mno_unaligned_access)) {
-if (A->getOption().matches(options::OPT_munaligned_access)) {
- Features.push_back("+unaligned-scalar-mem");
- if (HasV)
-Features.push_back("+unaligned-vector-mem");
-} else {
- Features.push_back("-unaligned-scalar-mem");
- if (HasV)
-Features.push_back("-unaligned-vector-mem");
-}
+if (A->getOption().matches(options::OPT_munaligned_access))
+ Features.push_back("+fast-unaligned-access");
+else
+ Features.push_back("-fast-unaligned-access");
}
// Now add any that the user explicitly requested on the command line,
diff --git a/clang/test/Driver/riscv-features.c
b/clang/test/Driver/riscv-features.c
index 851a7c0507eb3a3..716f3f6da57b889 100644
--- a/clang/test/Driver/riscv-features.c
+++ b/clang/test/Driver/riscv-features.c
@@ -27,19 +27,13 @@
// DEFAULT: "-target-feature" "-save-restore"
// DEFAULT-NOT: "-target-feature" "+save-restore"
-// RUN: %clang --target=riscv32-unknown-elf -### %s -munaligned-access 2>&1 |
FileCheck %s -check-prefix=UNALIGNED-SCALAR-MEM
-// RUN:
[clang] [llvm] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)
@@ -174,15 +174,10 @@ void riscv::getRISCVTargetFeatures(const Driver , const llvm::Triple , bool HasV = llvm::is_contained(Features, "+zve32x"); preames wrote: Yep, change pending. https://github.com/llvm/llvm-project/pull/73971 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)
https://github.com/preames created
https://github.com/llvm/llvm-project/pull/73971
When we'd originally added unaligned-scalar-mem and unaligned-vector-mem, they
were separated into two parts under the theory that some processor might
implement one, but not the other. At the moment, we don't have evidence of
such a processor. The C/C++ level interface, and the clang driver command
lines have settled on a single unaligned flag which indicates both scalar and
vector support unaligned. Given that, let's remove the test matrix complexity
for a set of configurations which don't appear useful.
Given these are internal feature names, I don't think we need to provide any
forward compatibility. Anyone disagree?
Note: The immediate trigger for this patch was finding another case where the
unaligned-vector-mem wasn't being properly serialized to IR from clang which
resulted in problems reproducing assembly from clang's -emit-llvm feature.
Instead of fixing this, I decided getting rid of the complexity was the better
approach.
>From 2f746ba1857d0d9f3dc20bbde499f2340735b05e Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Thu, 30 Nov 2023 10:34:22 -0800
Subject: [PATCH] [RISCV] Collapse fast unaligned access into a single feature
[nfc-ish]
When we'd originally added unaligned-scalar-mem and unaligned-vector-mem,
they were separated into two parts under the theory that some processor
might implement one, but not the other. At the moment, we don't have
evidence of such a processor. The C/C++ level interface, and the clang
driver command lines have settled on a single unaligned flag which
indicates both scalar and vector support unaligned. Given that, let's
remove the test matrix complexity for a set of configurations which
don't appear useful.
Given these are internal feature names, I don't think we need to
provide any forward compatibility. Anyone disagree?
Note: The immediate trigger for this patch was finding another case
where the unaligned-vector-mem wasn't being properly serialized to
IR from clang which resulted in problems reproducing assembly from
clang's -emit-llvm feature. Instead of fixing this, I decided getting
rid of the complexity was the better approach.
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
clang/lib/Driver/ToolChains/Arch/RISCV.cpp| 15 +-
clang/test/Driver/riscv-features.c| 20 +++
.../Target/RISCV/RISCVExpandPseudoInsts.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCVFeatures.td| 13
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 16 +++
.../Target/RISCV/RISCVTargetTransformInfo.h | 4 ++--
llvm/test/CodeGen/RISCV/memcpy-inline.ll | 4 ++--
llvm/test/CodeGen/RISCV/memcpy.ll | 4 ++--
llvm/test/CodeGen/RISCV/memset-inline.ll | 4 ++--
llvm/test/CodeGen/RISCV/pr56110.ll| 2 +-
.../RISCV/riscv-func-target-feature.ll| 2 +-
.../rvv/concat-vectors-constant-stride.ll | 4 ++--
.../rvv/fixed-vectors-strided-load-combine.ll | 2 +-
.../RISCV/rvv/fixed-vectors-unaligned.ll | 4 ++--
llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll | 4 ++--
llvm/test/CodeGen/RISCV/rvv/memset-inline.ll | 4 ++--
.../RISCV/rvv/unaligned-loads-stores.ll | 4 ++--
.../CodeGen/RISCV/unaligned-load-store.ll | 4 ++--
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 2 +-
20 files changed, 51 insertions(+), 67 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index d1d9cc1c770e361..6ee82d6665501b9 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -377,7 +377,7 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector ,
if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
HasLegalHalfType = true;
- FastUnalignedAccess = llvm::is_contained(Features, "+unaligned-scalar-mem");
+ FastUnalignedAccess = llvm::is_contained(Features, "+fast-unaligned-access");
return true;
}
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 346fb67ff277e9c..5db188fd7587daf 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -65,7 +65,7 @@ static void getRISCFeaturesFromMcpu(const Driver , const
Arg *A,
}
if (llvm::RISCV::hasFastUnalignedAccess(Mcpu))
-Features.push_back("+unaligned-scalar-mem");
+Features.push_back("+fast-unaligned-access");
}
void riscv::getRISCVTargetFeatures(const Driver , const llvm::Triple ,
@@ -174,15 +174,10 @@ void riscv::getRISCVTargetFeatures(const Driver , const
llvm::Triple ,
bool HasV = llvm::is_contained(Features, "+zve32x");
if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
options::OPT_mno_unaligned_access)) {
-if (A->getOption().matches(options::OPT_munaligned_access)) {
-
[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)
preames wrote: Can you separate out the basic processor definition (using NoSchedModel), and a patch which adds the scheduling model? We can at least get the processor definition landed while we iterate on the scheduling related pieces. https://github.com/llvm/llvm-project/pull/70232 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 495b653 - [RISCV] Add missing plumbing and tests for zfa
Author: Philip Reames
Date: 2023-02-17T17:56:30-08:00
New Revision: 495b653480238d692d814dde50469441b83adb4b
URL:
https://github.com/llvm/llvm-project/commit/495b653480238d692d814dde50469441b83adb4b
DIFF:
https://github.com/llvm/llvm-project/commit/495b653480238d692d814dde50469441b83adb4b.diff
LOG: [RISCV] Add missing plumbing and tests for zfa
Experimental support for the zfa extension was recently added in
https://reviews.llvm.org/D141984. A couple of the normal test changes and clang
plumbing got missed in that change. This commit updates the usual suspects.
Differential Revision: https://reviews.llvm.org/D144288
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Removed:
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index da87e6b112a6e..f965f1ee8748c 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -506,3 +506,11 @@
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64izifencei2p0 -x c
-E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIFENCEI-EXT %s
// CHECK-ZIFENCEI-EXT: __riscv_zifencei 200{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv32izfa0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv64izfa0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
+// CHECK-ZFA-EXT: __riscv_zfa 1000{{$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index b3f67f4748e39..0928ad51fb6bd 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -126,6 +126,7 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zcb", RISCVExtensionVersion{1, 0}},
{"zcd", RISCVExtensionVersion{1, 0}},
{"zcf", RISCVExtensionVersion{1, 0}},
+{"zfa", RISCVExtensionVersion{0, 1}},
{"zvfh", RISCVExtensionVersion{0, 1}},
{"zawrs", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
@@ -836,6 +837,7 @@ static const char *ImpliedExtsZks[] = {"zbkb", "zbkc",
"zbkx", "zksed", "zksh"};
static const char *ImpliedExtsZvfh[] = {"zve32f"};
static const char *ImpliedExtsXTHeadVdot[] = {"v"};
static const char *ImpliedExtsZcb[] = {"zca"};
+static const char *ImpliedExtsZfa[] = {"f"};
struct ImpliedExtsEntry {
StringLiteral Name;
@@ -854,6 +856,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
{{"zcb"}, {ImpliedExtsZcb}},
{{"zdinx"}, {ImpliedExtsZdinx}},
+{{"zfa"}, {ImpliedExtsZfa}},
{{"zfh"}, {ImpliedExtsZfh}},
{{"zfhmin"}, {ImpliedExtsZfhmin}},
{{"zhinx"}, {ImpliedExtsZhinx}},
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 24c74097483fd..23a8fd46c5b6c 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -48,6 +48,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZCF %s
; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZICSR %s
; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZIFENCEI %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFA %s
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck
--check-prefixes=CHECK,RV64M %s
@@ -103,6 +104,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZCD %s
; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZICSR %s
; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZIFENCEI %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZFA %s
; CHECK: .attribute 4, 16
@@ -153,6 +155,7 @@
; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0"
; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0"
+; RV32ZFA: .attribute 5, "rv32i2p0_f2p0_zfa0p1"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -207,6 +210,7 @@
; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0"
; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0"
+; RV64ZFA: .attribute 5, "rv64i2p0_f2p0_zfa0p1"
define i32 @addi(i32 %a) {
%1 = add i32
[clang] 22e199e - [RISCV] Accept zicsr and zifencei command line options
Author: Philip Reames
Date: 2023-02-16T10:41:41-08:00
New Revision: 22e199e6afb1263c943c0c0d4498694e15bf8a16
URL:
https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16
DIFF:
https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16.diff
LOG: [RISCV] Accept zicsr and zifencei command line options
This change adds the definition of the two extensions, but does not either a)
make any instruction conditional on them or b) enabled the extensions by
default. (The *instructions* do remain enabled by default per ISA version 2.0
which is our current default.)
This is meant to be a building block towards something like
https://reviews.llvm.org/D141666, and in the meantime, address one of the most
surprising of the current user experience warts. The current behavior of
rejecting the extensions at the command line despite emitting code which
appears to use them is surprising to anyone not deeply versed in the details of
this situation.
Between versions 2.0 and 2.1 of the base I specification, a backwards
incompatible change was made to remove selected instructions and CSRs from the
base ISA. These instructions were grouped into a set of new extensions (these),
but were no longer required by the base ISA. This change is described in
“Preface to Document Version 20190608-Base-Ratified” from the specification
document.
As LLVM currently implements only version 2.0 of the base specification,
accepting these extensions at the command line introduces a configuration which
doesn't actually match any spec version. It's a pretty harmless variant since
the 2.0 extension definitions, to my knowledge, exactly match the text from the
2.0 I text before they were moved into standalone extensions in 2.1 of I. (The
version numbering in that sentence is a tad confusing to say the least.
Hopefully I got it right.)
It is worth noting that we already have numerous examples of accepting
extensions in the march string which didn't exist in version of the spec
document corresponding to our current base I version, so this doesn't set any
new precedent.
Differential Revision: https://reviews.llvm.org/D143953
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Removed:
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 31bddb97d7fbf..da87e6b112a6e 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -494,3 +494,15 @@
// RUN: %clang -target riscv32 -march=rv32izcf1p0
-menable-experimental-extensions \
// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s
// CHECK-ZCF-EXT: __riscv_zcf 100{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32izicsr2p0 -x c -E
-dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICSR-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64izicsr2p0 -x c -E
-dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICSR-EXT %s
+// CHECK-ZICSR-EXT: __riscv_zicsr 200{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32izifencei2p0 -x c
-E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIFENCEI-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64izifencei2p0 -x c
-E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIFENCEI-EXT %s
+// CHECK-ZIFENCEI-EXT: __riscv_zifencei 200{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8242707348385..5932523df391e 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -130,7 +130,7 @@ Supported
.. _riscv-i2p1-note:
``zicsr``, ``zifencei``
- Between versions 2.0 and 2.1 of the base I specification, a backwards
incompatible change was made to remove selected instructions and CSRs from the
base ISA. These instructions were grouped into a set of new extensions, but
were no longer required by the base ISA. This change is described in "Preface
to Document Version 20190608-Base-Ratified" from the specification document.
LLVM currently implements version 2.0 of the base specification. Thus,
instructions from these extensions are accepted as part of the base ISA, but
attempts to explicitly enable the extensions will error.
+ Between versions 2.0 and 2.1 of the base I specification, a backwards
incompatible change was made to remove selected instructions and CSRs from the
base ISA. These instructions were grouped into a set of new extensions, but
were no longer required by the base ISA. This change is described in "Preface
to Document Version 20190608-Base-Ratified" from the specification
[clang] 780c539 - [RISCV] Implement assembler support for XVentanaCondOps
Author: Philip Reames
Date: 2022-11-14T09:01:54-08:00
New Revision: 780c53984449e14f50e2418de993bbf560f54bfc
URL:
https://github.com/llvm/llvm-project/commit/780c53984449e14f50e2418de993bbf560f54bfc
DIFF:
https://github.com/llvm/llvm-project/commit/780c53984449e14f50e2418de993bbf560f54bfc.diff
LOG: [RISCV] Implement assembler support for XVentanaCondOps
This change provides an implementation of the XVentanaCondOps vendor extension.
This extension is defined in version 1.0.0 of the VTx-family custom
instructions specification
(https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf)
by Ventana Micro Systems.
In addition to the technical contribution, this change is intended to be a test
case for our vendor extension policy.
Once this lands, I plan to use this extension to prototype selection lowering
to conditional moves. There's an RVI proposal in flight, and the expectation is
that lowering to these and the new RVI instructions is likely to be
substantially similar.
Differential Revision: https://reviews.llvm.org/D137350
Added:
llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
llvm/test/MC/RISCV/XVentanaCondOps-valid.s
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
Removed:
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 2d4aed24002e0..5d43b3f520ba9 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -41,6 +41,7 @@
// CHECK-NOT: __riscv_zicboz
// CHECK-NOT: __riscv_svnapot
// CHECK-NOT: __riscv_svinval
+// CHECK-NOT: __riscv_xventanacondops
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -432,3 +433,7 @@
// RUN: %clang -target riscv64 -march=rv64isvinval -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
// CHECK-SVINVAL-EXT: __riscv_svinval 100{{$}}
+
+// RUN: %clang -target riscv64 -march=rv64ixventanacondops -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
+// CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 100{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 6506d750b8748..aa39935153973 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -149,14 +149,17 @@ To use an experimental extension from `clang`, you must
add `-menable-experiment
Vendor Extensions
=
-Vendor extensions are extensions which are not standardized by RISC-V
International, and are instead defined by a hardware vendor. At the moment,
LLVM does not support any vendor extensions for RISC-V, but we expect this to
change in the future.
-
-The term vendor extension roughly parallels the definition of a `non-standard`
extension from Section 1.3 of the Volume I: RISC-V Unprivileged ISA
specification. In particular, we expect to eventually accept both `custom`
extensions and `non-conforming` extensions.
+Vendor extensions are extensions which are not standardized by RISC-V
International, and are instead defined by a hardware vendor. The term vendor
extension roughly parallels the definition of a `non-standard` extension from
Section 1.3 of the Volume I: RISC-V Unprivileged ISA specification. In
particular, we expect to eventually accept both `custom` extensions and
`non-conforming` extensions.
Inclusion of a vendor extension will be considered on a case by case basis.
All proposals should be brought to the bi-weekly RISCV sync calls for
discussion. For a general idea of the factors likely to be considered, please
see the `Clang documentation `_.
It is our intention to follow the naming conventions described in
`riscv-non-isa/riscv-toolchain-conventions
`_.
Exceptions to this naming will need to be strongly motivated.
+The current vendor extensions supported are:
+
+``XVentanaCondOps``
+ LLVM implements `version 1.0.0 of the VTx-family custom instructions
specification
`_
by Ventana Micro Systems. All instructions are prefixed with `vt.` as
described in the specification, and the riscv-toolchai-convention document
linked above. These instructions are only available for riscv64 at this time.
+
[clang] 9a8f3b1 - [clang][RISCV] Set vscale_range attribute based on VLEN
Author: Philip Reames
Date: 2022-10-19T16:14:33-07:00
New Revision: 9a8f3b113d05d94d9aaacdf511365dde4e35ce4f
URL:
https://github.com/llvm/llvm-project/commit/9a8f3b113d05d94d9aaacdf511365dde4e35ce4f
DIFF:
https://github.com/llvm/llvm-project/commit/9a8f3b113d05d94d9aaacdf511365dde4e35ce4f.diff
LOG: [clang][RISCV] Set vscale_range attribute based on VLEN
Follow up on D135894, restructure code to work in terms of minimum and maximum
VLEN coming from RISCVISAInfo.cpp. In the original review, I'd mentioned that
MinVLEN was sometimes zero. This turns out to be a case of human error,
combined with really bad (lack of) error reporting.
This patch adds appropriate tests for various vector extension combinations to
show the mechanism works, but doesn't try to provide exhaustive coverage of the
extension interactions. Presumably, that is already covered in existing tests
elsewhere.
Differential Revision: https://reviews.llvm.org/D136106
Added:
Modified:
clang/lib/Basic/Targets/RISCV.cpp
clang/test/CodeGen/riscv-vector-bits-vscale-range.c
llvm/include/llvm/Support/RISCVISAInfo.h
Removed:
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index b94187f939f27..08da01602599f 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -252,9 +252,11 @@ RISCVTargetInfo::getVScaleRange(const LangOptions
) const {
return std::pair(
LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
- if (hasFeature("v"))
-// Minimum VLEN=128, Maximum VLEN=64k, and RISCV::RVVBitsPerBlock is 64.
-return std::pair(2, 1024);
+ if (unsigned MinVLen = ISAInfo->getMinVLen()) {
+unsigned MaxVLen = ISAInfo->getMaxVLen();
+// RISCV::RVVBitsPerBlock is 64.
+return std::pair(MinVLen/64, MaxVLen/64);
+ }
return None;
}
diff --git a/clang/test/CodeGen/riscv-vector-bits-vscale-range.c
b/clang/test/CodeGen/riscv-vector-bits-vscale-range.c
index 067669fa289d2..9fbb9795657b3 100644
--- a/clang/test/CodeGen/riscv-vector-bits-vscale-range.c
+++ b/clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -9,11 +9,17 @@
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8
--check-prefix=CHECK-NOMAX
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16
--check-prefix=CHECK-NOMAX
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=1 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s
--check-prefix=CHECK-UNBOUNDED
-// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-V
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-target-feature +zvl512b -S -emit-llvm -o - %s | FileCheck %s
--check-prefix=CHECK-ZVL
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64x -S
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ZVE64
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64f
-target-feature +f -S -emit-llvm -o - %s | FileCheck %s
--check-prefix=CHECK-ZVE64
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d
-target-feature +f -target-feature +d -S -emit-llvm -o - %s | FileCheck %s
--check-prefix=CHECK-ZVE64
// CHECK-LABEL: @func() #0
// CHECK: attributes #0 = { {{.*}} vscale_range([[#VBITS]],[[#VBITS]]) {{.*}} }
// CHECK-NOMAX: attributes #0 = { {{.*}} vscale_range([[#VBITS]],0) {{.*}} }
// CHECK-UNBOUNDED: attributes #0 = { {{.*}} vscale_range(1,0) {{.*}} }
-// CHECK-NONE: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} }
+// CHECK-V: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} }
+// CHECK-ZVL: attributes #0 = { {{.*}} vscale_range(8,1024) {{.*}} }
+// CHECK-ZVE64: attributes #0 = { {{.*}} vscale_range(1,1024) {{.*}} }
void func(void) {}
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h
b/llvm/include/llvm/Support/RISCVISAInfo.h
index eac6cc0925fb3..ced3baf416fcb 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -60,6 +60,7 @@ class RISCVISAInfo {
unsigned getXLen() const { return XLen; };
unsigned getFLen() const { return FLen; };
unsigned getMinVLen() const { return MinVLen; }
+ unsigned getMaxVLen() const { return 65536; }
unsigned getMaxELen() const { return MaxELen; }
unsigned getMaxELenFp() const { return MaxELenFp; }
___
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[clang] 4467c78 - [clang][RISCV] Set vscale_range attribute based on presence of "v" extension
Author: Philip Reames
Date: 2022-10-17T11:33:03-07:00
New Revision: 4467c781d7bbf25a3b89a25ccbc0382731f51322
URL:
https://github.com/llvm/llvm-project/commit/4467c781d7bbf25a3b89a25ccbc0382731f51322
DIFF:
https://github.com/llvm/llvm-project/commit/4467c781d7bbf25a3b89a25ccbc0382731f51322.diff
LOG: [clang][RISCV] Set vscale_range attribute based on presence of "v"
extension
This follows the path that AArch64 SVE has taken. Doing this via a function
attribute set in the frontend is basically a workaround for the fact that
several analyzes which need the information (i.e. known bits, lvi, scev) can't
easily use TTI without significant amounts of plumbing changes.
This patch hard codes "v" numbers, and directly follows the SVE precedent as a
result. In a follow up, I hope to drive this from RISCVISAInfo.h/cpp instead,
but the MinVLen number being returned from that interface seemed to always be 0
(which is wrong), and I haven't figured out what's going wrong there.
Differential Revision: https://reviews.llvm.org/D135894
Added:
clang/test/CodeGen/riscv-vector-bits-vscale-range.c
Modified:
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Basic/Targets/RISCV.h
Removed:
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index cb0d10abc7e35..b94187f939f27 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -246,6 +246,19 @@ bool RISCVTargetInfo::initFeatureMap(
return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
}
+Optional>
+RISCVTargetInfo::getVScaleRange(const LangOptions ) const {
+ if (LangOpts.VScaleMin || LangOpts.VScaleMax)
+return std::pair(
+LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
+
+ if (hasFeature("v"))
+// Minimum VLEN=128, Maximum VLEN=64k, and RISCV::RVVBitsPerBlock is 64.
+return std::pair(2, 1024);
+
+ return None;
+}
+
/// Return true if has this feature, need to sync with handleTargetFeatures.
bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 21c5e7ab795b2..868b1bd5ad041 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -90,6 +90,9 @@ class RISCVTargetInfo : public TargetInfo {
StringRef CPU,
const std::vector ) const override;
+ Optional>
+ getVScaleRange(const LangOptions ) const override;
+
bool hasFeature(StringRef Feature) const override;
bool handleTargetFeatures(std::vector ,
diff --git a/clang/test/CodeGen/riscv-vector-bits-vscale-range.c
b/clang/test/CodeGen/riscv-vector-bits-vscale-range.c
new file mode 100644
index 0..067669fa289d2
--- /dev/null
+++ b/clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=1 -mvscale-max=1 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=1
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=2 -mvscale-max=2 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=2
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=4 -mvscale-max=4 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=4
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=8 -mvscale-max=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=16 -mvscale-max=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=1 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=1
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=2 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=2
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=4 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=4
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v
-mvscale-min=1 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s
--check-prefix=CHECK-UNBOUNDED
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
+
+// CHECK-LABEL: @func() #0
+// CHECK: attributes #0 = { {{.*}} vscale_range([[#VBITS]],[[#VBITS]]) {{.*}} }
+//
[clang] eda2af5 - [RISCV][MC] Add support for experimental Zawrs extension
Author: Philip Reames
Date: 2022-09-20T10:15:11-07:00
New Revision: eda2af575fdf038f3508112b42845516e7cb6192
URL:
https://github.com/llvm/llvm-project/commit/eda2af575fdf038f3508112b42845516e7cb6192
DIFF:
https://github.com/llvm/llvm-project/commit/eda2af575fdf038f3508112b42845516e7cb6192.diff
LOG: [RISCV][MC] Add support for experimental Zawrs extension
This implements experimental support for the Zawrs extension as specified here:
https://github.com/riscv/riscv-zawrs/releases/download/V1.0-rc3/Zawrs.pdf.
Despite the 1.0 version name, this has not been ratified and there was a major
change to proposed specification between rc2 and rc3. Once this is ratified,
it'll move out of experimental status.
This change adds assembly support, but does not include C language or IR
intrinsics. We can decide if we want them, and handle that in a separate patch.
Differential Revision: https://reviews.llvm.org/D133443
Added:
llvm/test/MC/RISCV/Zawrs-valid.s
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Removed:
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 9ec91171e8f05..39ab684e575b0 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -463,6 +463,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOP-EXT %s
// CHECK-ZICBOP-EXT: __riscv_zicbop 100{{$}}
+// RUN: %clang -target riscv32-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv32izawrs1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZAWRS-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv64izawrs1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZAWRS-EXT %s
+// CHECK-ZAWRS-EXT: __riscv_zawrs 100{{$}}
+
// RUN: %clang -target riscv32-unknown-linux-gnu
-menable-experimental-extensions \
// RUN: -march=rv32iztso0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index ddfea5b99117a..5db374c24f0d6 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -128,6 +128,9 @@ LLVM supports (to various degrees) a number of experimental
extensions. All exp
The primary goal of experimental support is to assist in the process of
ratification by providing an existence proof of an implementation, and
simplifying efforts to validate the value of a proposed extension against large
code bases. Experimental extensions are expected to either transition to
ratified status, or be eventually removed. The decision on whether to accept
an experimental extension is currently done on an entirely case by case basis;
if you want to propose one, attending the bi-weekly RISC-V sync-up call is
strongly advised.
+``experimental-zawrs``
+ LLVM implements the `1.0-rc3 draft specification
`_.
Note that have been backwards incompatible changes made between release
candidates for the 1.0 draft.
+
``experimental-zbe``, ``experimental-zbf``, ``experimental-zbm``,
``experimental-zbp``, ``experimental-zbr``, ``experimental-zbt``
LLVM implements the `latest state of the bitmanip working branch
`_, which is largely
similar to the 0.93 draft specification but with some instruction naming
changes. These are individual portions of the bitmanip efforts which did *not*
get ratified. Given ratification for these sub-extensions appears stalled;
they are a likely candidate for removal in the future.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 8deedfb8c8fd7..a9ae60746ad10 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -114,6 +114,7 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zbt", RISCVExtensionVersion{0, 93}},
{"zca", RISCVExtensionVersion{0, 70}},
{"zvfh", RISCVExtensionVersion{0, 1}},
+{"zawrs", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
};
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index b4f3416857749..5ce40e0dcbff7 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -461,6 +461,13 @@ def HasStdExtZtso :
Predicate<"Subtarget->hasStdExtZTso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
[clang] a4a2943 - [RISCV][MC] Add minimal support for Ztso extension
Author: Philip Reames
Date: 2022-09-07T09:30:57-07:00
New Revision: a4a29438f451370ed241dde30bfcaab0fdf2ab71
URL:
https://github.com/llvm/llvm-project/commit/a4a29438f451370ed241dde30bfcaab0fdf2ab71
DIFF:
https://github.com/llvm/llvm-project/commit/a4a29438f451370ed241dde30bfcaab0fdf2ab71.diff
LOG: [RISCV][MC] Add minimal support for Ztso extension
This is a minimalist implementation which simply adds the extension (in the
experimental namespace since its not ratified), and wires up the setting of the
required ELF header flag. Future changes will include codegen changes to
exploit the stronger memory model.
This is intended to implement v0.1 of the proposed specification which can be
found in Chapter 25 of
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf.
Differential Revision: https://reviews.llvm.org/D133239
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/elf-flags.s
Removed:
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index deb333c46dedd..9ec91171e8f05 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -462,3 +462,11 @@
// RUN: %clang -target riscv64 -march=rv64izicbop -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOP-EXT %s
// CHECK-ZICBOP-EXT: __riscv_zicbop 100{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv32iztso0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv64iztso0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
+// CHECK-ZTSO-EXT: __riscv_ztso 1000{{$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a666337ee5619..8deedfb8c8fd7 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -114,6 +114,7 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zbt", RISCVExtensionVersion{0, 93}},
{"zca", RISCVExtensionVersion{0, 70}},
{"zvfh", RISCVExtensionVersion{0, 1}},
+{"ztso", RISCVExtensionVersion{0, 1}},
};
static bool stripExperimentalPrefix(StringRef ) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index c5f8a42bab6a5..fef8cb2798a39 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -157,6 +157,8 @@ void RISCVTargetELFStreamer::finish() {
if (Features[RISCV::FeatureStdExtC])
EFlags |= ELF::EF_RISCV_RVC;
+ if (Features[RISCV::FeatureStdExtZtso])
+EFlags |= ELF::EF_RISCV_TSO;
switch (ABI) {
case RISCVABI::ABI_ILP32:
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 6d9836f28a1bd..b4f3416857749 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -454,6 +454,13 @@ def HasStdExtZicbop :
Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of
FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch
Instructions)">;
+def FeatureStdExtZtso
+: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
+ "'Ztso' (Memory Model - Total Store Order)">;
+def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">,
+ AssemblerPredicate<(all_of FeatureStdExtZtso),
+ "'Ztso' (Memory Model - Total Store Order)">;
+
// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
// tuning CPU names.
def Feature32Bit
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h
b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 461968d40311f..3c95e062a13d5 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -92,6 +92,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtZicboz = false;
bool HasStdExtZicbop = false;
bool HasStdExtZmmul = false;
+ bool HasStdExtZtso = false;
bool HasRV32 = false;
bool HasRV64 = false;
bool IsRV32E = false;
@@ -192,6 +193,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasStdExtZicboz() const { return HasStdExtZicboz; }
bool hasStdExtZicbop() const { return HasStdExtZicbop; }
bool
[clang] 0b09313 - [funcattrs] Infer writeonly argument attribute [part 2]
Author: Philip Reames
Date: 2022-01-04T09:07:54-08:00
New Revision: 0b09313cd53316eacbdc5e98d4ef00bef2c41d02
URL:
https://github.com/llvm/llvm-project/commit/0b09313cd53316eacbdc5e98d4ef00bef2c41d02
DIFF:
https://github.com/llvm/llvm-project/commit/0b09313cd53316eacbdc5e98d4ef00bef2c41d02.diff
LOG: [funcattrs] Infer writeonly argument attribute [part 2]
This builds on the code from D114963, and extends it to handle calls both
direct and indirect. With the revised code structure (from series of previously
landed NFCs), this is pretty straight forward.
One thing to note is that we can not infer writeonly for arguments which might
be captured. If the pointer can be read back by the caller, and then read
through, we have no way to track that. This is the same restriction we have for
readonly, except that we get no mileage out of the "callee can be readonly"
exception since a writeonly param on a readonly function is either a) readnone
or b) UB. This means we can't actually infer much unless nocapture has already
been inferred.
Differential Revision: https://reviews.llvm.org/D115003
Added:
Modified:
clang/test/CodeGen/arm-vfp16-arguments.c
clang/test/CodeGenCXX/wasm-args-returns.cpp
clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
llvm/lib/Transforms/IPO/FunctionAttrs.cpp
llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
llvm/test/Other/cgscc-devirt-iteration.ll
llvm/test/Transforms/FunctionAttrs/norecurse.ll
llvm/test/Transforms/FunctionAttrs/writeonly.ll
Removed:
diff --git a/clang/test/CodeGen/arm-vfp16-arguments.c
b/clang/test/CodeGen/arm-vfp16-arguments.c
index e11ec1508bbf..0ad099092a9a 100644
--- a/clang/test/CodeGen/arm-vfp16-arguments.c
+++ b/clang/test/CodeGen/arm-vfp16-arguments.c
@@ -71,6 +71,6 @@ void test_hfa(hfa_t a) {}
hfa_t ghfa;
hfa_t test_ret_hfa(void) { return ghfa; }
-// CHECK-SOFT: define{{.*}} void @test_ret_hfa(%struct.hfa_t* noalias
nocapture sret(%struct.hfa_t) align 8 %agg.result)
+// CHECK-SOFT: define{{.*}} void @test_ret_hfa(%struct.hfa_t* noalias
nocapture writeonly sret(%struct.hfa_t) align 8 %agg.result)
// CHECK-HARD: define{{.*}} arm_aapcs_vfpcc [2 x <2 x i32>] @test_ret_hfa()
// CHECK-FULL: define{{.*}} arm_aapcs_vfpcc %struct.hfa_t @test_ret_hfa()
diff --git a/clang/test/CodeGenCXX/wasm-args-returns.cpp
b/clang/test/CodeGenCXX/wasm-args-returns.cpp
index c05bb44c05a3..d71bb28eabcc 100644
--- a/clang/test/CodeGenCXX/wasm-args-returns.cpp
+++ b/clang/test/CodeGenCXX/wasm-args-returns.cpp
@@ -30,7 +30,7 @@ struct two_fields {
double d, e;
};
test(two_fields);
-// CHECK: define void @_Z7forward10two_fields(%struct.two_fields* noalias
nocapture sret(%struct.two_fields) align 8 %{{.*}}, %struct.two_fields*
nocapture readonly byval(%struct.two_fields) align 8 %{{.*}})
+// CHECK: define void @_Z7forward10two_fields(%struct.two_fields* noalias
nocapture writeonly sret(%struct.two_fields) align 8 %{{.*}},
%struct.two_fields* nocapture readonly byval(%struct.two_fields) align 8
%{{.*}})
//
// CHECK: define void @_Z15test_two_fieldsv()
// CHECK: %[[tmp:.*]] = alloca %struct.two_fields, align 8
diff --git a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
index 17333cc80e14..350bb3c69366 100644
--- a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
+++ b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
@@ -403,14 +403,14 @@ struct_arr16 func_ret_struct_arr16()
return s;
}
-// CHECK: define{{.*}} void @func_ret_struct_arr32(%struct.struct_arr32
addrspace(5)* noalias nocapture sret(%struct.struct_arr32) align 4 %agg.result)
+// CHECK: define{{.*}} void @func_ret_struct_arr32(%struct.struct_arr32
addrspace(5)* noalias nocapture writeonly sret(%struct.struct_arr32) align 4
%agg.result)
struct_arr32 func_ret_struct_arr32()
{
struct_arr32 s = { 0 };
return s;
}
-// CHECK: define{{.*}} void @func_ret_struct_arr33(%struct.struct_arr33
addrspace(5)* noalias nocapture sret(%struct.struct_arr33) align 4 %agg.result)
+// CHECK: define{{.*}} void @func_ret_struct_arr33(%struct.struct_arr33
addrspace(5)* noalias nocapture writeonly sret(%struct.struct_arr33) align 4
%agg.result)
struct_arr33 func_ret_struct_arr33()
{
struct_arr33 s = { 0 };
@@ -468,7 +468,7 @@ double_nested_struct func_double_nested_struct_ret(int4
arg0, int arg1) {
// CHECK: define{{.*}} void @func_large_struct_padding_arg_direct(i8
%arg.coerce0, i32 %arg.coerce1, i8 %arg.coerce2, i32 %arg.coerce3, i8
%arg.coerce4, i8 %arg.coerce5, i16 %arg.coerce6, i16 %arg.coerce7, [3 x i8]
%arg.coerce8, i64 %arg.coerce9, i32 %arg.coerce10, i8 %arg.coerce11, i32
%arg.coerce12, i16 %arg.coerce13, i8 %arg.coerce14)
void func_large_struct_padding_arg_direct(large_struct_padding arg) { }
-// CHECK: define{{.*}} void
[clang] 33cbaab - [funcattrs] Consistently treat calling a function pointer as a non-capturing read
Author: Philip Reames
Date: 2021-12-17T09:02:03-08:00
New Revision: 33cbaab1416b234d5a08b41e3110d64a00b0651c
URL:
https://github.com/llvm/llvm-project/commit/33cbaab1416b234d5a08b41e3110d64a00b0651c
DIFF:
https://github.com/llvm/llvm-project/commit/33cbaab1416b234d5a08b41e3110d64a00b0651c.diff
LOG: [funcattrs] Consistently treat calling a function pointer as a
non-capturing read
We were being wildly inconsistent about what memory access was implied by an
indirect function call. Depending on the call site attributes, you could get
anything from a read, to unknown, to none at all. (The last was a miscompile.)
We were also always traversing the uses of a readonly indirect call. This is
entirely unneeded as the indirect call does not capture. The callee might
capture itself internally, but that has no implications for this caller. (See
the nice explanation in the CaptureTracking comments if that case is confusing.)
Note that elsewhere in the same file, we were correctly computing the nocapture
attribute for indirect calls. The changed case only resulted in conservatism
when computing memory attributes if say the return value was written to.
Differential Revision: https://reviews.llvm.org/D115916
Added:
Modified:
clang/test/CodeGen/arm-cmse-attr.c
llvm/lib/Transforms/IPO/FunctionAttrs.cpp
llvm/test/Transforms/FunctionAttrs/nocapture.ll
llvm/test/Transforms/FunctionAttrs/writeonly.ll
Removed:
diff --git a/clang/test/CodeGen/arm-cmse-attr.c
b/clang/test/CodeGen/arm-cmse-attr.c
index 5cfadfd3828a1..ae0b606a0bb21 100644
--- a/clang/test/CodeGen/arm-cmse-attr.c
+++ b/clang/test/CodeGen/arm-cmse-attr.c
@@ -29,9 +29,9 @@ void f4() __attribute__((cmse_nonsecure_entry))
{
}
-// CHECK: define{{.*}} void @f1(void ()* nocapture %fptr) {{[^#]*}}#0 {
+// CHECK: define{{.*}} void @f1(void ()* nocapture readonly %fptr) {{[^#]*}}#0
{
// CHECK: call void %fptr() #2
-// CHECK: define{{.*}} void @f2(void ()* nocapture %fptr) {{[^#]*}}#0 {
+// CHECK: define{{.*}} void @f2(void ()* nocapture readonly %fptr) {{[^#]*}}#0
{
// CHECK: call void %fptr() #2
// CHECK: define{{.*}} void @f3() {{[^#]*}}#1 {
// CHECK: define{{.*}} void @f4() {{[^#]*}}#1 {
diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
index 2cee9c0b4766a..8c8aea465c490 100644
--- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++ b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
@@ -702,6 +702,11 @@ determinePointerAccessAttrs(Argument *A,
};
CallBase = cast(*I);
+ if (CB.isCallee(U)) {
+IsRead = true;
+Captures = false; // See comment in CaptureTracking for context
+continue;
+ }
if (CB.doesNotAccessMemory()) {
AddUsersToWorklistIfCapturing();
continue;
diff --git a/llvm/test/Transforms/FunctionAttrs/nocapture.ll
b/llvm/test/Transforms/FunctionAttrs/nocapture.ll
index 3c699de9df6c9..ab84a0cece52e 100644
--- a/llvm/test/Transforms/FunctionAttrs/nocapture.ll
+++ b/llvm/test/Transforms/FunctionAttrs/nocapture.ll
@@ -128,7 +128,7 @@ define void @nc2(i32* %p, i32* %q) {
}
-; FNATTR: define void @nc3(void ()* nocapture %p)
+; FNATTR: define void @nc3(void ()* nocapture readonly %p)
define void @nc3(void ()* %p) {
call void %p()
ret void
@@ -141,7 +141,7 @@ define void @nc4(i8* %p) {
ret void
}
-; FNATTR: define void @nc5(void (i8*)* nocapture %f, i8* nocapture %p)
+; FNATTR: define void @nc5(void (i8*)* nocapture readonly %f, i8* nocapture %p)
define void @nc5(void (i8*)* %f, i8* %p) {
call void %f(i8* %p) readonly nounwind
call void %f(i8* nocapture %p)
@@ -319,21 +319,21 @@ define i1 @captureDereferenceableOrNullICmp(i32*
dereferenceable_or_null(4) %x)
declare void @capture(i8*)
-; FNATTR: define void @nocapture_fptr(i8* (i8*)* nocapture %f, i8* %p)
+; FNATTR: define void @nocapture_fptr(i8* (i8*)* nocapture readonly %f, i8* %p)
define void @nocapture_fptr(i8* (i8*)* %f, i8* %p) {
%res = call i8* %f(i8* %p)
call void @capture(i8* %res)
ret void
}
-; FNATTR: define void @recurse_fptr(i8* (i8*)* nocapture %f, i8* %p)
+; FNATTR: define void @recurse_fptr(i8* (i8*)* nocapture readonly %f, i8* %p)
define void @recurse_fptr(i8* (i8*)* %f, i8* %p) {
%res = call i8* %f(i8* %p)
store i8 0, i8* %res
ret void
}
-; FNATTR: define void @readnone_indirec(void (i8*)* nocapture readnone %f, i8*
readnone %p)
+; FNATTR: define void @readnone_indirec(void (i8*)* nocapture readonly %f, i8*
readnone %p)
define void @readnone_indirec(void (i8*)* %f, i8* %p) {
call void %f(i8* %p) readnone
ret void
diff --git a/llvm/test/Transforms/FunctionAttrs/writeonly.ll
b/llvm/test/Transforms/FunctionAttrs/writeonly.ll
index fb39b301b..54d00d355f7af 100644
--- a/llvm/test/Transforms/FunctionAttrs/writeonly.ll
+++
[clang] 7b54de5 - [funcattrs] Fix a bug in recently introduced writeonly argument inference
Author: Philip Reames
Date: 2021-12-03T08:57:15-08:00
New Revision: 7b54de5feffedfc08e5a02d6c9e27c54e3b7f119
URL:
https://github.com/llvm/llvm-project/commit/7b54de5feffedfc08e5a02d6c9e27c54e3b7f119
DIFF:
https://github.com/llvm/llvm-project/commit/7b54de5feffedfc08e5a02d6c9e27c54e3b7f119.diff
LOG: [funcattrs] Fix a bug in recently introduced writeonly argument inference
This fixes a bug in 740057d. There's two ways to describe the issue:
* One caller hasn't yet proven nocapture on the argument. Given that, the
inference routine is responsible for bailing out on a potential capture.
* Even if we know the argument is nocapture, the access inference needs to
traverse the exact set of users the capture tracking would (or exit
conservatively). Even if capture tracking can prove a store is non-capturing
(e.g. to a local alloc which doesn't escape), we still need to track the copy
of the pointer to see if it's later reloaded and accessed again.
Note that all the test changes except the newly added ones appear to be false
negatives. That is, cases where we could prove writeonly, but the current code
isn't strong enough. That's why I didn't spot this originally.
Added:
Modified:
clang/test/CodeGen/ms-mixed-ptr-sizes.c
llvm/lib/Transforms/IPO/FunctionAttrs.cpp
llvm/test/Feature/OperandBundles/pr26510.ll
llvm/test/Transforms/Coroutines/coro-async.ll
llvm/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
llvm/test/Transforms/FunctionAttrs/nocapture.ll
llvm/test/Transforms/FunctionAttrs/readattrs.ll
llvm/test/Transforms/FunctionAttrs/writeonly.ll
Removed:
diff --git a/clang/test/CodeGen/ms-mixed-ptr-sizes.c
b/clang/test/CodeGen/ms-mixed-ptr-sizes.c
index 294a8910e13e3..ececa42a4c4dd 100644
--- a/clang/test/CodeGen/ms-mixed-ptr-sizes.c
+++ b/clang/test/CodeGen/ms-mixed-ptr-sizes.c
@@ -7,32 +7,32 @@ struct Foo {
};
void use_foo(struct Foo *f);
void test_sign_ext(struct Foo *f, int * __ptr32 __sptr i) {
-// X64-LABEL: define dso_local void @test_sign_ext({{.*}}i32 addrspace(270)*
writeonly %i)
-// X86-LABEL: define dso_local void @test_sign_ext(%struct.Foo* %f, i32*
writeonly %i)
+// X64-LABEL: define dso_local void @test_sign_ext({{.*}}i32 addrspace(270)*
%i)
+// X86-LABEL: define dso_local void @test_sign_ext(%struct.Foo* %f, i32* %i)
// X64: %{{.+}} = addrspacecast i32 addrspace(270)* %i to i32*
// X86: %{{.+}} = addrspacecast i32* %i to i32 addrspace(272)*
f->p64 = i;
use_foo(f);
}
void test_zero_ext(struct Foo *f, int * __ptr32 __uptr i) {
-// X64-LABEL: define dso_local void @test_zero_ext({{.*}}i32 addrspace(271)*
writeonly %i)
-// X86-LABEL: define dso_local void @test_zero_ext({{.*}}i32 addrspace(271)*
writeonly %i)
+// X64-LABEL: define dso_local void @test_zero_ext({{.*}}i32 addrspace(271)*
%i)
+// X86-LABEL: define dso_local void @test_zero_ext({{.*}}i32 addrspace(271)*
%i)
// X64: %{{.+}} = addrspacecast i32 addrspace(271)* %i to i32*
// X86: %{{.+}} = addrspacecast i32 addrspace(271)* %i to i32 addrspace(272)*
f->p64 = i;
use_foo(f);
}
void test_trunc(struct Foo *f, int * __ptr64 i) {
-// X64-LABEL: define dso_local void @test_trunc(%struct.Foo* %f, i32*
writeonly %i)
-// X86-LABEL: define dso_local void @test_trunc({{.*}}i32 addrspace(272)*
writeonly %i)
+// X64-LABEL: define dso_local void @test_trunc(%struct.Foo* %f, i32* %i)
+// X86-LABEL: define dso_local void @test_trunc({{.*}}i32 addrspace(272)* %i)
// X64: %{{.+}} = addrspacecast i32* %i to i32 addrspace(270)*
// X86: %{{.+}} = addrspacecast i32 addrspace(272)* %i to i32*
f->p32 = i;
use_foo(f);
}
void test_noop(struct Foo *f, int * __ptr32 i) {
-// X64-LABEL: define dso_local void @test_noop({{.*}}i32 addrspace(270)*
writeonly %i)
-// X86-LABEL: define dso_local void @test_noop({{.*}}i32* writeonly %i)
+// X64-LABEL: define dso_local void @test_noop({{.*}}i32 addrspace(270)* %i)
+// X86-LABEL: define dso_local void @test_noop({{.*}}i32* %i)
// X64-NOT: addrspacecast
// X86-NOT: addrspacecast
f->p32 = i;
@@ -40,8 +40,8 @@ void test_noop(struct Foo *f, int * __ptr32 i) {
}
void test_other(struct Foo *f, __attribute__((address_space(10))) int *i) {
-// X64-LABEL: define dso_local void @test_other({{.*}}i32 addrspace(10)*
writeonly %i)
-// X86-LABEL: define dso_local void @test_other({{.*}}i32 addrspace(10)*
writeonly %i)
+// X64-LABEL: define dso_local void @test_other({{.*}}i32 addrspace(10)* %i)
+// X86-LABEL: define dso_local void @test_other({{.*}}i32 addrspace(10)* %i)
// X64: %{{.+}} = addrspacecast i32 addrspace(10)* %i to i32 addrspace(270)*
// X86: %{{.+}} = addrspacecast i32 addrspace(10)* %i to i32*
f->p32 = (int * __ptr32)i;
diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
index 1ad0055b56382..2cee9c0b4766a 100644
--- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++
[clang] 740057d - [funcattrs] Infer writeonly argument attribute
Author: Philip Reames
Date: 2021-12-02T13:04:09-08:00
New Revision: 740057d185ea0e8b5a4f8b7c78fdf38ae7a66f76
URL:
https://github.com/llvm/llvm-project/commit/740057d185ea0e8b5a4f8b7c78fdf38ae7a66f76
DIFF:
https://github.com/llvm/llvm-project/commit/740057d185ea0e8b5a4f8b7c78fdf38ae7a66f76.diff
LOG: [funcattrs] Infer writeonly argument attribute
This change extends the current logic for inferring readonly and readnone
argument attributes to also infer writeonly.
This change is deliberately minimal; there's a couple of areas for follow up.
* I left out all call handling and thus any benefit from the SCC walk. When
examining the test changes, I realized the existing code is imprecise, and am
going to fix that in it's own revision before adding in the writeonly handling.
(Mostly because updating the tests is hard when I, the human, can't figure out
whether the result is correct.)
* I left out handling for storing a value (as opposed to storing to a pointer).
This should benefit readonly/readnone as well, and applies to a bunch of other
instructions. Seemed worth having as a separate review.
Differential Revision: https://reviews.llvm.org/D114963
Added:
Modified:
clang/test/CodeGen/SystemZ/systemz-inline-asm.c
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
clang/test/CodeGen/arm-vfp16-arguments2.cpp
clang/test/CodeGen/mips-vector-return.c
clang/test/CodeGen/mips64-nontrivial-return.cpp
clang/test/CodeGen/ms-mixed-ptr-sizes.c
clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
clang/test/CodeGenOpenCL/amdgpu-call-kernel.cl
clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl
llvm/lib/Transforms/IPO/FunctionAttrs.cpp
llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
llvm/test/Feature/OperandBundles/pr26510.ll
llvm/test/Transforms/Coroutines/coro-async.ll
llvm/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
llvm/test/Transforms/FunctionAttrs/nocapture.ll
llvm/test/Transforms/FunctionAttrs/readattrs.ll
llvm/test/Transforms/FunctionAttrs/writeonly.ll
Removed:
diff --git a/clang/test/CodeGen/SystemZ/systemz-inline-asm.c
b/clang/test/CodeGen/SystemZ/systemz-inline-asm.c
index 0994b11825fe8..2a656eaf4a2a8 100644
--- a/clang/test/CodeGen/SystemZ/systemz-inline-asm.c
+++ b/clang/test/CodeGen/SystemZ/systemz-inline-asm.c
@@ -123,7 +123,7 @@ double test_f64(double f, double g) {
long double test_f128(long double f, long double g) {
asm("axbr %0, %2" : "=f" (f) : "0" (f), "f" (g));
return f;
-// CHECK: define{{.*}} void @test_f128(fp128* noalias nocapture sret(fp128)
align 8 [[DEST:%.*]], fp128* nocapture readonly %0, fp128* nocapture readonly
%1)
+// CHECK: define{{.*}} void @test_f128(fp128* noalias nocapture writeonly
sret(fp128) align 8 [[DEST:%.*]], fp128* nocapture readonly %0, fp128*
nocapture readonly %1)
// CHECK: %f = load fp128, fp128* %0
// CHECK: %g = load fp128, fp128* %1
// CHECK: [[RESULT:%.*]] = tail call fp128 asm "axbr $0, $2", "=f,0,f"(fp128
%f, fp128 %g)
diff --git
a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
index 071932a27a97b..4fa72c666bf98 100644
--- a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
+++ b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
@@ -59,7 +59,7 @@ typedef int8_t vec_int8 __attribute__((vector_size(N / 8)));
// CHECK128-NEXT:ret <16 x i8> [[CASTFIXEDSVE]]
// CHECK-LABEL: define{{.*}} void @f2(
-// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noalias nocapture
sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, <[[#div(VBITS,8)]] x i8>*
nocapture readonly %0)
+// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noalias nocapture writeonly
sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, <[[#div(VBITS,8)]] x i8>*
nocapture readonly %0)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X:%.*]] = load <[[#div(VBITS,8)]] x i8>, <[[#div(VBITS,8)]]
x i8>* [[TMP0:%.*]], align 16, [[TBAA6:!tbaa !.*]]
// CHECK-NEXT: [[TMP1:%.*]] = call
@llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
diff --git a/clang/test/CodeGen/arm-vfp16-arguments2.cpp
b/clang/test/CodeGen/arm-vfp16-arguments2.cpp
index 35b716230a096..b1b466c48dd31 100644
--- a/clang/test/CodeGen/arm-vfp16-arguments2.cpp
+++ b/clang/test/CodeGen/arm-vfp16-arguments2.cpp
@@ -37,27 +37,27 @@ struct S5 : B1 {
B1 M[1];
};
-// CHECK-SOFT: define{{.*}} void @_Z2f12S1(%struct.S1* noalias nocapture
sret(%struct.S1) align 8 %agg.result, [2 x i64] %s1.coerce)
+// CHECK-SOFT: define{{.*}} void @_Z2f12S1(%struct.S1* noalias nocapture
writeonly sret(%struct.S1) align 8 %agg.result, [2 x i64] %s1.coerce)
// CHECK-HARD: define{{.*}} arm_aapcs_vfpcc [2 x <2 x i32>] @_Z2f12S1([2 x <2
x i32>] returned %s1.coerce)
// CHECK-FULL: define{{.*}}
[clang] f549176 - [funcattrs] Add the maximal set of implied attributes to definitions
Author: Philip Reames
Date: 2021-04-16T14:22:19-07:00
New Revision: f549176ad976caa3e19edd036df9a7e12770af7c
URL:
https://github.com/llvm/llvm-project/commit/f549176ad976caa3e19edd036df9a7e12770af7c
DIFF:
https://github.com/llvm/llvm-project/commit/f549176ad976caa3e19edd036df9a7e12770af7c.diff
LOG: [funcattrs] Add the maximal set of implied attributes to definitions
Have funcattrs expand all implied attributes into the IR. This expands the
infrastructure from D100400, but for definitions not declarations this time.
Somewhat subtly, this mostly isn't semantic. Because the accessors did the
inference, any client which used the accessor was already getting the stronger
result. Clients that directly checked presence of attributes (there are some),
will see a stronger result now.
The old behavior can end up quite confusing for two reasons:
* Without this change, we have situations where function-attrs appears to fail
when inferring an attribute (as seen by a human reading IR), but that consuming
code will see that it should have been implied. As a human trying to sanity
check test results and study IR for optimization possibilities, this is
exceeding error prone and confusing. (I'll note that I wasted several hours
recently because of this.)
* We can have transforms which trigger without the IR appearing (on inspection)
to meet the preconditions. This change doesn't prevent this from happening (as
the accessors still involve multiple checks), but it should make it less
frequent.
I'd argue in favor of deleting the extra checks out of the accessors after this
lands, but I want that in it's own review as a) it's purely stylistic, and b) I
already know there's some disagreement.
Once this lands, I'm also going to do a cleanup change which will delete some
now redundant duplicate predicates in the inference code, but again, that
deserves to be a change of it's own.
Differential Revision: https://reviews.llvm.org/D100226
Added:
Modified:
clang/test/CodeGenOpenCL/convergent.cl
llvm/lib/Transforms/IPO/FunctionAttrs.cpp
llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
llvm/test/CodeGen/AMDGPU/inline-attr.ll
llvm/test/Other/cgscc-devirt-iteration.ll
llvm/test/Other/cgscc-iterate-function-mutation.ll
llvm/test/Other/cgscc-observe-devirt.ll
llvm/test/Transforms/FunctionAttrs/2008-09-03-ReadOnly.ll
llvm/test/Transforms/FunctionAttrs/atomic.ll
llvm/test/Transforms/FunctionAttrs/incompatible_fn_attrs.ll
llvm/test/Transforms/FunctionAttrs/nofree-attributor.ll
llvm/test/Transforms/FunctionAttrs/nofree.ll
llvm/test/Transforms/FunctionAttrs/nosync.ll
llvm/test/Transforms/FunctionAttrs/nounwind.ll
llvm/test/Transforms/FunctionAttrs/optnone.ll
llvm/test/Transforms/FunctionAttrs/willreturn-callsites.ll
llvm/test/Transforms/FunctionAttrs/writeonly.ll
llvm/test/Transforms/InferFunctionAttrs/norecurse_debug.ll
llvm/test/Transforms/Inline/cgscc-update.ll
Removed:
diff --git a/clang/test/CodeGenOpenCL/convergent.cl
b/clang/test/CodeGenOpenCL/convergent.cl
index 25951a64c1147..1905d7dd81aab 100644
--- a/clang/test/CodeGenOpenCL/convergent.cl
+++ b/clang/test/CodeGenOpenCL/convergent.cl
@@ -134,7 +134,7 @@ kernel void assume_convergent_asm()
__asm__ volatile("s_barrier");
}
-// CHECK: attributes #0 = { nofree noinline norecurse nounwind willreturn "
+// CHECK: attributes #0 = { nofree noinline norecurse nounwind willreturn
mustprogress "
// CHECK: attributes #1 = { {{[^}]*}}convergent{{[^}]*}} }
// CHECK: attributes #2 = { {{[^}]*}}convergent{{[^}]*}} }
// CHECK: attributes #3 = { {{[^}]*}}convergent noduplicate{{[^}]*}} }
diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
index cfd302a536c6f..0202046158b14 100644
--- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++ b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
@@ -57,6 +57,7 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/IPO.h"
+#include "llvm/Transforms/Utils/Local.h"
#include
#include
#include
@@ -1556,21 +1557,7 @@ static bool addNoSyncAttr(const SCCNodeSet ) {
++NumNoSync;
},
/* RequiresExactDefinition= */ true});
- bool Changed = AI.run(SCCNodes);
-
- // readnone + not convergent implies nosync
- // (This is here so that we don't have to duplicate the function local
- // memory reasoning of the readnone analysis.)
- for (Function *F : SCCNodes) {
-if (!F || F->hasNoSync())
- continue;
-if (!F->doesNotAccessMemory() || F->isConvergent())
- continue;
-F->setNoSync();
-NumNoSync++;
-Changed = true;
- }
- return Changed;
+ return AI.run(SCCNodes);
}
static SCCNodesResult createSCCNodeSet(ArrayRef Functions) {
@@ -1630,6 +1617,14 @@ static bool deriveAttrsInPostOrder(ArrayRef
Functions,
[clang] dd98555 - Reapply "[InferAttributes] Materialize all infered attributes for declaration"" and follow on patches.
Author: Philip Reames
Date: 2021-04-14T16:38:07-07:00
New Revision: dd985551c247752ee2be71f04a141225a40641ef
URL:
https://github.com/llvm/llvm-project/commit/dd985551c247752ee2be71f04a141225a40641ef
DIFF:
https://github.com/llvm/llvm-project/commit/dd985551c247752ee2be71f04a141225a40641ef.diff
LOG: Reapply "[InferAttributes] Materialize all infered attributes for
declaration"" and follow on patches.
This reverts commit ab98f2c7129a52e216fd7e088b964cf4af27b0f2 and
98eea392cdbcdb7360e58b46e9329573f092cd96.
It includes a fix for the clang test which triggered the revert. I failed to
notice this one because there was another AMDGPU llvm test with a similiar name
and the exact same text in the error message. Odd. Since only one build bot
reported the clang test, I didn't notice that one.
Added:
Modified:
clang/test/CodeGenOpenCL/builtins-amdgcn.cl
llvm/include/llvm/Transforms/Utils/Local.h
llvm/lib/Transforms/IPO/InferFunctionAttrs.cpp
llvm/lib/Transforms/Utils/Local.cpp
llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
llvm/test/Other/cgscc-devirt-iteration.ll
llvm/test/Transforms/InferFunctionAttrs/annotate.ll
llvm/test/Transforms/LICM/strlen.ll
Removed:
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl
index 3769149c8c6d..b02e6308c343 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl
@@ -748,7 +748,7 @@ kernel void test_s_setreg(uint val) {
// CHECK-DAG: [[$WI_RANGE]] = !{i32 0, i32 1024}
// CHECK-DAG: [[$WS_RANGE]] = !{i16 1, i16 1025}
-// CHECK-DAG: attributes #[[$NOUNWIND_READONLY:[0-9]+]] = { nounwind readonly }
+// CHECK-DAG: attributes #[[$NOUNWIND_READONLY:[0-9]+]] = { nofree nounwind
readonly }
// CHECK-DAG: attributes #[[$READ_EXEC_ATTRS]] = { convergent }
// CHECK-DAG: ![[$EXEC]] = !{!"exec"}
// CHECK-DAG: ![[$EXEC_LO]] = !{!"exec_lo"}
diff --git a/llvm/include/llvm/Transforms/Utils/Local.h
b/llvm/include/llvm/Transforms/Utils/Local.h
index f7efeeb56fd3..8ab066f0b6a3 100644
--- a/llvm/include/llvm/Transforms/Utils/Local.h
+++ b/llvm/include/llvm/Transforms/Utils/Local.h
@@ -488,6 +488,15 @@ bool canReplaceOperandWithVariable(const Instruction *I,
unsigned OpIdx);
/// Invert the given true/false value, possibly reusing an existing copy.
Value *invertCondition(Value *Condition);
+
+//===--===//
+// Assorted
+//
+
+/// If we can infer one attribute from another on the declaration of a
+/// function, explicitly materialize the maximal set in the IR.
+bool inferAttributesFromOthers(Function );
+
} // end namespace llvm
#endif // LLVM_TRANSFORMS_UTILS_LOCAL_H
diff --git a/llvm/lib/Transforms/IPO/InferFunctionAttrs.cpp
b/llvm/lib/Transforms/IPO/InferFunctionAttrs.cpp
index 685f8f7d7a00..30402f109f30 100644
--- a/llvm/lib/Transforms/IPO/InferFunctionAttrs.cpp
+++ b/llvm/lib/Transforms/IPO/InferFunctionAttrs.cpp
@@ -15,6 +15,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/Utils/BuildLibCalls.h"
+#include "llvm/Transforms/Utils/Local.h"
using namespace llvm;
#define DEBUG_TYPE "inferattrs"
@@ -25,9 +26,14 @@ static bool inferAllPrototypeAttributes(
for (Function : M.functions())
// We only infer things using the prototype and the name; we don't need
-// definitions.
-if (F.isDeclaration() && !F.hasOptNone())
+// definitions. This ensures libfuncs are annotated and also allows our
+// CGSCC inference to avoid needing to duplicate the inference from other
+// attribute logic on all calls to declarations (as declarations aren't
+// explicitly visited by CGSCC passes in the new pass manager.)
+if (F.isDeclaration() && !F.hasOptNone()) {
Changed |= inferLibFuncAttributes(F, GetTLI(F));
+ Changed |= inferAttributesFromOthers(F);
+}
return Changed;
}
diff --git a/llvm/lib/Transforms/Utils/Local.cpp
b/llvm/lib/Transforms/Utils/Local.cpp
index e285f8aa7a20..89e62fb94ec1 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -3392,3 +3392,33 @@ Value *llvm::invertCondition(Value *Condition) {
Inverted->insertBefore(&*Parent->getFirstInsertionPt());
return Inverted;
}
+
+bool llvm::inferAttributesFromOthers(Function ) {
+ // Note: We explicitly check for attributes rather than using cover functions
+ // because some of the cover functions include the logic being implemented.
+
+ bool Changed = false;
+ // readnone + not convergent implies nosync
+ if (!F.hasFnAttribute(Attribute::NoSync) &&
+ F.doesNotAccessMemory() && !F.isConvergent()) {
+F.setNoSync();
+Changed = true;
+ }
+
+ // readonly implies nofree
+ if (!F.hasFnAttribute(Attribute::NoFree) && F.onlyReadsMemory()) {
+
[clang] 3b3eb7f - Speculative fix for build bot failures
Author: Philip Reames Date: 2020-12-14T13:44:40-08:00 New Revision: 3b3eb7f07ff97feb64a1975587bb473f1f3efa6b URL: https://github.com/llvm/llvm-project/commit/3b3eb7f07ff97feb64a1975587bb473f1f3efa6b DIFF: https://github.com/llvm/llvm-project/commit/3b3eb7f07ff97feb64a1975587bb473f1f3efa6b.diff LOG: Speculative fix for build bot failures (The clang build fails for me locally, so this is based on built bot output and a guess as to root cause.) f5fe849 made the execution of LAA conditional, so I'm guessing that's the root cause. Added: Modified: clang/test/CodeGen/thinlto-distributed-newpm.ll Removed: diff --git a/clang/test/CodeGen/thinlto-distributed-newpm.ll b/clang/test/CodeGen/thinlto-distributed-newpm.ll index 75ea4064d6af..8fe53762837e 100644 --- a/clang/test/CodeGen/thinlto-distributed-newpm.ll +++ b/clang/test/CodeGen/thinlto-distributed-newpm.ll @@ -183,7 +183,6 @@ ; CHECK-O: Running analysis: PostDominatorTreeAnalysis on main ; CHECK-O: Running analysis: DemandedBitsAnalysis on main ; CHECK-O: Running pass: LoopLoadEliminationPass on main -; CHECK-O: Running analysis: LoopAccessAnalysis on Loop at depth 1 containing: %b ; CHECK-O: Running pass: InstCombinePass on main ; CHECK-O: Running pass: SimplifyCFGPass on main ; CHECK-O: Running pass: SLPVectorizerPass on main ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D22221: Decide whether to enable plugin tests based on cmake variables
reames resigned from this revision. reames removed a reviewer: reames. reames added a comment. I know very little about our cmake infrastructure. Repository: rL LLVM https://reviews.llvm.org/D1 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
