Re: [PATCH] drm/amd/display: Fix DCN build breakage

[Dieter Nützel]

Ups,

you were faster than ever - my 'double post' 
''CONFIG_DRM_AMD_DC_DCN1_0=y' mandatory, again'...;-)


Tested-by: Dieter Nützel 

Dieter

Fixes: 680acc64120c (drm/amd/display: Set disp clk in a safe way to 
avoid

over high dpp clk.)

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 76fc903515ba..78e6beb6cf26 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -623,6 +623,7 @@ static bool dce_apply_clock_voltage_request(
}
}
if (send_request) {
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (clk->ctx->dce_version >= DCN_VERSION_1_0) {
struct dc *core_dc = clk->ctx->dc;
/*use dcfclk request voltage*/
@@ -630,6 +631,7 @@ static bool dce_apply_clock_voltage_request(
clock_voltage_req.clocks_in_khz =
dcn_find_dcfclk_suits_all(core_dc, 
&clk->cur_clocks_value);
}
+#endif
dm_pp_apply_clock_for_voltage_request(
clk->ctx, &clock_voltage_req);
}
--
2.14.1

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Re: [PATCH 1/3] drm/amdgpu: remove trailing whitespace from soc15ip.h

[Christian König]

Am 14.03.2018 um 02:22 schrieb Alex Deucher:

no intended functional change.

Signed-off-by: Alex Deucher 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/include/vega10_ip_offset.h | 286 -
  1 file changed, 143 insertions(+), 143 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/vega10_ip_offset.h 
b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
index 4c78dba5cf25..976dd2d565ba 100644
--- a/drivers/gpu/drm/amd/include/vega10_ip_offset.h
+++ b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
@@ -24,191 +24,191 @@
  #define MAX_INSTANCE   5
  #define MAX_SEGMENT5
  
-struct IP_BASE_INSTANCE

+struct IP_BASE_INSTANCE
  {
  unsigned int segment[MAX_SEGMENT];
  };
-
-struct IP_BASE
+
+struct IP_BASE
  {
  struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
  };
  
  
-static const struct IP_BASE NBIF_BASE			= { { { { 0x, 0x0014, 0x0D20, 0x00010400, 0 } },

-   
{ { 0, 0, 0, 0, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE NBIF_BASE  = { { { { 0x, 
0x0014, 0x0D20, 0x00010400, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE NBIO_BASE  = { { { { 0x, 
0x0014, 0x0D20, 0x00010400, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE NBIO_BASE  = { { { { 0x, 
0x0014, 0x0D20, 0x00010400, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DCE_BASE   = { { { { 0x0012, 
0x00C0, 0x34C0, 0, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE DCE_BASE   = { { { { 0x0012, 
0x00C0, 0x34C0, 0, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DCN_BASE   = { { { { 0x0012, 
0x00C0, 0x34C0, 0, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE DCN_BASE   = { { { { 0x0012, 
0x00C0, 0x34C0, 0, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },
+   
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP0_BASE   = { { { { 0x00016000, 
0, 0, 0, 0 } },
-   
{ { 0, 0, 0, 0, 0 } },
-   

Re: [PATCH] drm/amdgpu/powerplay/vega10: fix memory leak in error path

[Zhu, Rex]

Reviewed-by: Rex Zhu 


Best Regards

Rex


From: amd-gfx  on behalf of Quan, Evan 

Sent: Wednesday, March 14, 2018 11:20 AM
To: Alex Deucher; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: RE: [PATCH] drm/amdgpu/powerplay/vega10: fix memory leak in error path

Reviewed-by: Evan Quan 

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Alex 
Deucher
Sent: Wednesday, March 14, 2018 9:46 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH] drm/amdgpu/powerplay/vega10: fix memory leak in error path

Free the backend structure if we fail to allocate device memory.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 15e1afa28018..219950882be9 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -406,9 +406,8 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
 &handle,
 &mc_addr,
 &kaddr);
-
 if (ret)
-   return -EINVAL;
+   goto free_backend;

 priv->smu_tables.entry[PPTABLE].version = 0x01;
 priv->smu_tables.entry[PPTABLE].size = sizeof(PPTable_t); @@ -511,6 
+510,9 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
 amdgpu_bo_free_kernel(&priv->smu_tables.entry[PPTABLE].handle,
 &priv->smu_tables.entry[PPTABLE].mc_addr,
 &priv->smu_tables.entry[PPTABLE].table);
+free_backend:
+   kfree(hwmgr->smu_backend);
+
 return -EINVAL;
 }

--
2.13.6

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[PATCH] drm/amd/pp: Fix memory leak in error path in smumgr

[Rex Zhu]

Free the backend structure if we fail to allocate device memory.

Change-Id: Ib5fbd507369575b90df57a55d3e7318c769b3e27
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c   | 35 +-
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c |  8 +++--
 .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c  |  8 +++--
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c|  8 +++--
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c   | 21 -
 .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c|  8 +++--
 6 files changed, 54 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 957739a..ee8968c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -746,8 +746,6 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
if (cz_smu == NULL)
return -ENOMEM;
 
-   hwmgr->smu_backend = cz_smu;
-
cz_smu->toc_buffer.data_size = 4096;
cz_smu->smu_buffer.data_size =
ALIGN(UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 32) +
@@ -764,7 +762,7 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
&cz_smu->toc_buffer.mc_addr,
&cz_smu->toc_buffer.kaddr);
if (ret)
-   return -EINVAL;
+   goto err2;
 
ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
cz_smu->smu_buffer.data_size,
@@ -773,19 +771,15 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
&cz_smu->smu_buffer.handle,
&cz_smu->smu_buffer.mc_addr,
&cz_smu->smu_buffer.kaddr);
-   if (ret) {
-   amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,
-   &cz_smu->toc_buffer.mc_addr,
-   &cz_smu->toc_buffer.kaddr);
-   return -EINVAL;
-   }
+   if (ret)
+   goto err1;
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -793,14 +787,14 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -808,7 +802,7 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
sizeof(struct SMU8_MultimediaPowerLogData),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -816,10 +810,23 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
sizeof(struct SMU8_Fusion_ClkTable),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
+   hwmgr->smu_backend = cz_smu;
return 0;
+
+err0:
+   amdgpu_bo_free_kernel(&cz_smu->smu_buffer.handle,
+   &cz_smu->smu_buffer.mc_addr,
+   &cz_smu->smu_buffer.kaddr);
+err1:
+   amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,
+   &cz_smu->toc_buffer.mc_addr,
+   &cz_smu->toc_buffer.kaddr);
+err2:
+   kfree(cz_smu);
+   return -EINVAL;
 }
 
 static int cz_smu_fini(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index ed2e2e9..ff9ba9d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -352,10 +352,12 @@ static int fiji_smu_init(struct pp_hwmgr *hwmgr)
if (fiji_priv == NULL)
return -ENOMEM;
 
-   hwmgr->

RE: [PATCH] drm/amd/pp: Fix memory leak in error path in smumgr

[Quan, Evan]

Reviewed-by: Evan Quan 

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Rex 
Zhu
Sent: Wednesday, March 14, 2018 4:17 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex 
Subject: [PATCH] drm/amd/pp: Fix memory leak in error path in smumgr

Free the backend structure if we fail to allocate device memory.

Change-Id: Ib5fbd507369575b90df57a55d3e7318c769b3e27
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c   | 35 +-
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c |  8 +++--  
.../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c  |  8 +++--
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c|  8 +++--
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c   | 21 -
 .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c|  8 +++--
 6 files changed, 54 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 957739a..ee8968c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -746,8 +746,6 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
if (cz_smu == NULL)
return -ENOMEM;
 
-   hwmgr->smu_backend = cz_smu;
-
cz_smu->toc_buffer.data_size = 4096;
cz_smu->smu_buffer.data_size =
ALIGN(UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 32) + @@ -764,7 +762,7 @@ 
static int cz_smu_init(struct pp_hwmgr *hwmgr)
&cz_smu->toc_buffer.mc_addr,
&cz_smu->toc_buffer.kaddr);
if (ret)
-   return -EINVAL;
+   goto err2;
 
ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
cz_smu->smu_buffer.data_size,
@@ -773,19 +771,15 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
&cz_smu->smu_buffer.handle,
&cz_smu->smu_buffer.mc_addr,
&cz_smu->smu_buffer.kaddr);
-   if (ret) {
-   amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,
-   &cz_smu->toc_buffer.mc_addr,
-   &cz_smu->toc_buffer.kaddr);
-   return -EINVAL;
-   }
+   if (ret)
+   goto err1;
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -793,14 +787,14 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -808,7 +802,7 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
sizeof(struct SMU8_MultimediaPowerLogData),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -816,10 +810,23 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
sizeof(struct SMU8_Fusion_ClkTable),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
+   hwmgr->smu_backend = cz_smu;
return 0;
+
+err0:
+   amdgpu_bo_free_kernel(&cz_smu->smu_buffer.handle,
+   &cz_smu->smu_buffer.mc_addr,
+   &cz_smu->smu_buffer.kaddr);
+err1:
+   amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,
+   &cz_smu->toc_buffer.mc_addr,
+   &cz_smu->toc_buffer.kaddr);
+err2:
+   kfree(cz_smu);
+   return -EINVAL;
 }
 
 static int cz_smu_fini(struct pp_hwmgr *hwmgr) diff --git 
a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c

[bug report] drm/amd/display: Handle HDR use cases.

[Dan Carpenter]

Hello Vitaly Prosyak,

The patch 44c6f2e59ee8: "drm/amd/display: Handle HDR use cases." from
Feb 13, 2018, leads to the following static checker warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_cm_common.c:543 
cm_helper_translate_curve_to_degamma_hw_format()
warn: potential off by one (named limit 'MAX_REGIONS_NUMBER') 
'seg_distr[k]'

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_cm_common.c
   530  lut_params->hw_points_num = hw_points;
   531  
   532  i = 1;
   533  for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; 
k++) {
^^
Imagine we hit this limit and k == MAX_REGIONS_NUMBER,

   534  if (seg_distr[k] != -1) {
   535  lut_params->arr_curve_points[k].segments_num =
   536  seg_distr[k];
   537  lut_params->arr_curve_points[i].offset =
   538  
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
   539  }
   540  i++;
   541  }
   542  
   543  if (seg_distr[k] != -1)
^^
then this would be a problem.

   544  lut_params->arr_curve_points[k].segments_num = 
seg_distr[k];
   545  

regards,
dan carpenter
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How to enable Radeon Pro Duo with mesa

[Lvzhihong (ReJohn)]

Hi All ,
Does mesa support Radeon Pro Duo? I don't know how to configure xorg.conf to 
use two WX7100 card of DUO , and now I can only use the first card of DUO.
Installed software packages: xserver-xorg  xfce4  xinit
Mesa version: 17.2.8  kernel version: 4.15

Pci information:
000d:31:00.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port PCI 
Express Gen 3 (8.0 GT/s) Switch (rev ca)
000d:32:08.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port PCI 
Express Gen 3 (8.0 GT/s) Switch (rev ca)
000d:32:10.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port PCI 
Express Gen 3 (8.0 GT/s) Switch (rev ca)
000d:33:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] 
Ellesmere [Radeon Pro WX 7100]
000d:33:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device aaf0
000d:34:00.0 Display controller: Advanced Micro Devices, Inc. [AMD/ATI] 
Ellesmere [Radeon Pro WX 7100]

My xorg.conf:
Section "Device"
   Identifier "AMD"
   Driver "amdgpu"
   BusID "pci:51@13:00:00"
EndSection
Section "Monitor"
Identifier "monitor0"
Option "enable" "true"
EndSection
Section "Screen"
Identifier "screen0"
Device "AMD"
Monitor "monitor0"
DefaultDepth 24
SubSection "Display"
Depth 24
EndSubSection
EndSection

I use "startx" to start desktop , and only the first WX7100(PCI Bus ID: 
000d:33:00.0) being used , the second WX7100(PCI Bus ID: 000d:34:00.0) has no 
load .
 Even if I set BusID as "pci:52@13:00:00" (the second WX7100), it still 
only the first WX7100 being used.

  So , How to enable Radeon Pro Duo with opensource driver , does my 
xorg.conf is wrong or mesa doesn't support Radeon Pro Duo?


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[PATCH v2] drm/amd/pp: Fix memory leak in error path in smumgr

[Rex Zhu]

v2: not change the sequence of smu backend assignment

Free the backend structure if we fail to allocate device memory.

Change-Id: Ib2007d83f3d99dcc6c4a0c9fe9a9f144bb7469e9
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c   | 32 ++
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c |  4 ++-
 .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c  |  4 ++-
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c|  4 ++-
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c   | 18 +++-
 .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c|  4 ++-
 6 files changed, 43 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 957739a..669c1be 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -764,7 +764,7 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
&cz_smu->toc_buffer.mc_addr,
&cz_smu->toc_buffer.kaddr);
if (ret)
-   return -EINVAL;
+   goto err2;
 
ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
cz_smu->smu_buffer.data_size,
@@ -773,19 +773,15 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
&cz_smu->smu_buffer.handle,
&cz_smu->smu_buffer.mc_addr,
&cz_smu->smu_buffer.kaddr);
-   if (ret) {
-   amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,
-   &cz_smu->toc_buffer.mc_addr,
-   &cz_smu->toc_buffer.kaddr);
-   return -EINVAL;
-   }
+   if (ret)
+   goto err1;
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -793,14 +789,14 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -808,7 +804,7 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
sizeof(struct SMU8_MultimediaPowerLogData),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -816,10 +812,22 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
sizeof(struct SMU8_Fusion_ClkTable),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
-   return -1;
+   goto err0;
}
 
return 0;
+
+err0:
+   amdgpu_bo_free_kernel(&cz_smu->smu_buffer.handle,
+   &cz_smu->smu_buffer.mc_addr,
+   &cz_smu->smu_buffer.kaddr);
+err1:
+   amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,
+   &cz_smu->toc_buffer.mc_addr,
+   &cz_smu->toc_buffer.kaddr);
+err2:
+   kfree(cz_smu);
+   return -EINVAL;
 }
 
 static int cz_smu_fini(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index ed2e2e9..95fcda3 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -354,8 +354,10 @@ static int fiji_smu_init(struct pp_hwmgr *hwmgr)
 
hwmgr->smu_backend = fiji_priv;
 
-   if (smu7_init(hwmgr))
+   if (smu7_init(hwmgr)) {
+   kfree(fiji_priv);
return -EINVAL;
+   }
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 6255edf..4e2f62e 100644
--- a/drivers/gpu/drm/amd

Re: [PATCH][next] drm/amd/pp: remove redundant pointer internal_buf

[Zhu, Rex]

Apply it and thanks.


Best Regards

Rex





From: Colin King 
Sent: Tuesday, March 13, 2018 9:22 PM
To: Deucher, Alexander; Koenig, Christian; Zhou, David(ChunMing); David Airlie; 
Zhu, Rex; amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: [PATCH][next] drm/amd/pp: remove redundant pointer internal_buf

From: Colin Ian King 

The pointer internal_buf is assigned a value but the pointer is never
read, hence it is redundant and can be removed.

Cleans up clang warning:
drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/smu7_smumgr.c:630:2:
warning: Value stored to 'internal_buf' is never read

Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 7394bb46b8b2..dcb151cabc00 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -585,7 +585,6 @@ int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr)
 int smu7_init(struct pp_hwmgr *hwmgr)
 {
 struct smu7_smumgr *smu_data;
-   uint8_t *internal_buf;
 uint64_t mc_addr = 0;
 int r;
 /* Allocate memory for backend private data */
@@ -627,7 +626,6 @@ int smu7_init(struct pp_hwmgr *hwmgr)
 &smu_data->header_buffer.kaddr);
 return -EINVAL;
 }
-   internal_buf = smu_data->smu_buffer.kaddr;
 smu_data->smu_buffer.mc_addr = mc_addr;

 if (smum_is_hw_avfs_present(hwmgr))
--
2.15.1

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Re: How to enable Radeon Pro Duo with mesa

[Alex Deucher]

On Wed, Mar 14, 2018 at 5:41 AM, Lvzhihong (ReJohn)
 wrote:
> Hi All ,
>
> Does mesa support Radeon Pro Duo? I don’t know how to configure xorg.conf to
> use two WX7100 card of DUO , and now I can only use the first card of DUO.

What are you trying to do?  A large desktop spread across both chips?
Use the chips independently?  There is no support for crossfire on
Linux.  If you want to use a desktop across multiple chips or select
which chip is used for rendering, you can use xrandr and the prime
support in X:
https://wiki.archlinux.org/index.php/PRIME

Alex


>
> Installed software packages: xserver-xorg  xfce4  xinit
>
> Mesa version: 17.2.8  kernel version: 4.15
>
>
>
> Pci information:
>
> 000d:31:00.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port PCI
> Express Gen 3 (8.0 GT/s) Switch (rev ca)
>
> 000d:32:08.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port PCI
> Express Gen 3 (8.0 GT/s) Switch (rev ca)
>
> 000d:32:10.0 PCI bridge: PLX Technology, Inc. PEX 8747 48-Lane, 5-Port PCI
> Express Gen 3 (8.0 GT/s) Switch (rev ca)
>
> 000d:33:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
> [AMD/ATI] Ellesmere [Radeon Pro WX 7100]
>
> 000d:33:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device
> aaf0
>
> 000d:34:00.0 Display controller: Advanced Micro Devices, Inc. [AMD/ATI]
> Ellesmere [Radeon Pro WX 7100]
>
>
>
> My xorg.conf:
>
> Section "Device"
>
>Identifier "AMD"
>
>Driver "amdgpu"
>
>BusID "pci:51@13:00:00"
>
> EndSection
>
> Section "Monitor"
>
> Identifier "monitor0"
>
> Option "enable" "true"
>
> EndSection
>
> Section "Screen"
>
> Identifier "screen0"
>
> Device "AMD"
>
> Monitor "monitor0"
>
> DefaultDepth 24
>
> SubSection "Display"
>
> Depth 24
>
> EndSubSection
>
> EndSection
>
>
>
> I use “startx” to start desktop , and only the first WX7100(PCI Bus ID:
> 000d:33:00.0) being used , the second WX7100(PCI Bus ID: 000d:34:00.0) has
> no load .
>
>  Even if I set BusID as "pci:52@13:00:00" (the second WX7100), it
> still only the first WX7100 being used.
>
>
>
>   So , How to enable Radeon Pro Duo with opensource driver , does my
> xorg.conf is wrong or mesa doesn’t support Radeon Pro Duo?
>
>
>
>
>
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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Re: [PATCH 1/3] drm/amdgpu: remove trailing whitespace from soc15ip.h

[Christian König]

Am 14.03.2018 um 14:42 schrieb Alex Deucher:

On Wed, Mar 14, 2018 at 4:01 AM, Christian König
 wrote:

Am 14.03.2018 um 02:22 schrieb Alex Deucher:

no intended functional change.

Signed-off-by: Alex Deucher 


Reviewed-by: Christian König 

Is this for the series or just this patch?


For the series. Well actually for patch #1 and #2, #3 already had my rb.

Christian.



Alex




---
   drivers/gpu/drm/amd/include/vega10_ip_offset.h | 286
-
   1 file changed, 143 insertions(+), 143 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/vega10_ip_offset.h
b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
index 4c78dba5cf25..976dd2d565ba 100644
--- a/drivers/gpu/drm/amd/include/vega10_ip_offset.h
+++ b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
@@ -24,191 +24,191 @@
   #define MAX_INSTANCE   5
   #define MAX_SEGMENT5
   -struct IP_BASE_INSTANCE
+struct IP_BASE_INSTANCE
   {
   unsigned int segment[MAX_SEGMENT];
   };
-
-struct IP_BASE
+
+struct IP_BASE
   {
   struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
   };
 -static const struct IP_BASE NBIF_BASE  = { { { {
0x, 0x0014, 0x0D20, 0x00010400, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE NBIF_BASE  = { { { {
0x, 0x0014, 0x0D20, 0x00010400, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE NBIO_BASE  = { { { {
0x, 0x0014, 0x0D20, 0x00010400, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE NBIO_BASE  = { { { {
0x, 0x0014, 0x0D20, 0x00010400, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DCE_BASE   = { { { {
0x0012, 0x00C0, 0x34C0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE DCE_BASE   = { { { {
0x0012, 0x00C0, 0x34C0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DCN_BASE   = { { { {
0x0012, 0x00C0, 0x34C0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE DCN_BASE   = { { { {
0x0012, 0x00C0, 0x34C0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP0_BASE   = { { { {
0x00016000, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE MP0_BASE   = { { { {
0x00016000, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP1_BASE   = { { { {
0x00016000, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE MP1_BASE   = { { { {
0x00016000, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP2_BASE   = { { { {
0x00016000, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE MP2_BASE   = { { { {
0x00016000, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DF_BASE= { { { {
0x7000, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE DF_BASE= { { { {
0x7000, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE UVD_BASE   = { { { {
0x7800, 0x7E00, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE UVD_BASE   = { { { {
0x7800, 0x7E00, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },

{ { 0, 0, 0, 0, 0 } } } };  //note: GLN does not use the first segment
-static const struct IP_BASE VCN_BASE   = { { { {
0x7800, 0x7E00, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
-
{ { 0, 0, 0, 0, 0 } },
+static const struct IP_BASE VCN_BASE   = { { { {
0x7800, 0x7E00, 0, 0, 0 } },
+
{ { 0, 0, 0, 0, 0 } },
+
{ { 

Re: [PATCH 1/3] drm/amdgpu: remove trailing whitespace from soc15ip.h

[Alex Deucher]

On Wed, Mar 14, 2018 at 4:01 AM, Christian König
 wrote:
> Am 14.03.2018 um 02:22 schrieb Alex Deucher:
>>
>> no intended functional change.
>>
>> Signed-off-by: Alex Deucher 
>
>
> Reviewed-by: Christian König 

Is this for the series or just this patch?

Alex

>
>
>> ---
>>   drivers/gpu/drm/amd/include/vega10_ip_offset.h | 286
>> -
>>   1 file changed, 143 insertions(+), 143 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/include/vega10_ip_offset.h
>> b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
>> index 4c78dba5cf25..976dd2d565ba 100644
>> --- a/drivers/gpu/drm/amd/include/vega10_ip_offset.h
>> +++ b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
>> @@ -24,191 +24,191 @@
>>   #define MAX_INSTANCE   5
>>   #define MAX_SEGMENT5
>>   -struct IP_BASE_INSTANCE
>> +struct IP_BASE_INSTANCE
>>   {
>>   unsigned int segment[MAX_SEGMENT];
>>   };
>> -
>> -struct IP_BASE
>> +
>> +struct IP_BASE
>>   {
>>   struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
>>   };
>> -static const struct IP_BASE NBIF_BASE  = { { { {
>> 0x, 0x0014, 0x0D20, 0x00010400, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> +static const struct IP_BASE NBIF_BASE  = { { { {
>> 0x, 0x0014, 0x0D20, 0x00010400, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>>
>> { { 0, 0, 0, 0, 0 } } } };
>> -static const struct IP_BASE NBIO_BASE  = { { { {
>> 0x, 0x0014, 0x0D20, 0x00010400, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> +static const struct IP_BASE NBIO_BASE  = { { { {
>> 0x, 0x0014, 0x0D20, 0x00010400, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>>
>> { { 0, 0, 0, 0, 0 } } } };
>> -static const struct IP_BASE DCE_BASE   = { { { {
>> 0x0012, 0x00C0, 0x34C0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> +static const struct IP_BASE DCE_BASE   = { { { {
>> 0x0012, 0x00C0, 0x34C0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>>
>> { { 0, 0, 0, 0, 0 } } } };
>> -static const struct IP_BASE DCN_BASE   = { { { {
>> 0x0012, 0x00C0, 0x34C0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> +static const struct IP_BASE DCN_BASE   = { { { {
>> 0x0012, 0x00C0, 0x34C0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>>
>> { { 0, 0, 0, 0, 0 } } } };
>> -static const struct IP_BASE MP0_BASE   = { { { {
>> 0x00016000, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> +static const struct IP_BASE MP0_BASE   = { { { {
>> 0x00016000, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>>
>> { { 0, 0, 0, 0, 0 } } } };
>> -static const struct IP_BASE MP1_BASE   = { { { {
>> 0x00016000, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> +static const struct IP_BASE MP1_BASE   = { { { {
>> 0x00016000, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>>
>> { { 0, 0, 0, 0, 0 } } } };
>> -static const struct IP_BASE MP2_BASE   = { { { {
>> 0x00016000, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> +static const struct IP_BASE MP2_BASE   = { { { {
>> 0x00016000, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>>
>> { { 0, 0, 0, 0, 0 } } } };
>> -static const struct IP_BASE DF_BASE= { { { {
>> 0x7000, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> +static const struct IP_BASE DF_BASE= { { { {
>> 0x7000, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>>
>> { { 0, 0, 0, 0, 0 } } } };
>> -static const struct IP_BASE UVD_BASE   = { { { {
>> 0x7800, 0x7E00, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> -
>> { { 0, 0, 0, 0, 0 } },
>> +static const struct IP_BASE UVD_BASE   = { { { {
>> 0x7800, 0x7E00, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>> +
>> { { 0, 0, 0, 0, 0 } },
>

vga handover for raven

[Tom St Denis]

Hi,

In the original version of the patch we had:

@@ -358,7 +360,9 @@ struct dce_hwseq_registers { 



HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, 
PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, 
DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
-   HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh) 



+   HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh),\ 



+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 



+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) 





Which somehow changed into

@@ -404,7 +406,9 @@ struct dce_hwseq_registers { 


HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, 
mask_sh)
+   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, 
mask_sh), \
+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 

+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) 



And the net result is the display doesn't work (same glitches as before) 
on a raven1 device.


Tom
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[PATCH] drm/amd/display: Fix null pointer when setting backlight

[Harry Wentland]

Fixes: c894d9f208f9 (drm/amd/display: Fixed dim around 1sec when resume
from S3)

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index e6d5dcb35e96..eeb04471b2f5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1960,10 +1960,12 @@ bool dc_link_set_backlight_level(const struct dc_link 
*link, uint32_t level,
(abm->funcs->set_backlight_level == NULL))
return false;
 
-   if (stream->bl_pwm_level == 0)
-   frame_ramp = 0;
+   if (stream) {
+   if (stream->bl_pwm_level == 0)
+   frame_ramp = 0;
 
-   ((struct dc_stream_state *)stream)->bl_pwm_level = level;
+   ((struct dc_stream_state *)stream)->bl_pwm_level = level;
+   }
 
use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
 
-- 
2.14.1

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Re: [PATCH] drm/amd/display: Fix null pointer when setting backlight

[Alex Deucher]

On Wed, Mar 14, 2018 at 9:55 AM, Harry Wentland  wrote:
> Fixes: c894d9f208f9 (drm/amd/display: Fixed dim around 1sec when resume
> from S3)
>
> Signed-off-by: Harry Wentland 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index e6d5dcb35e96..eeb04471b2f5 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -1960,10 +1960,12 @@ bool dc_link_set_backlight_level(const struct dc_link 
> *link, uint32_t level,
> (abm->funcs->set_backlight_level == NULL))
> return false;
>
> -   if (stream->bl_pwm_level == 0)
> -   frame_ramp = 0;
> +   if (stream) {
> +   if (stream->bl_pwm_level == 0)
> +   frame_ramp = 0;
>
> -   ((struct dc_stream_state *)stream)->bl_pwm_level = level;
> +   ((struct dc_stream_state *)stream)->bl_pwm_level = level;
> +   }
>
> use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
>
> --
> 2.14.1
>
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Re: vga handover for raven

[Harry Wentland]

On 2018-03-14 09:54 AM, Tom St Denis wrote:
> Hi,
> 
> In the original version of the patch we had:
> 
> @@ -358,7 +360,9 @@ struct dce_hwseq_registers {
> 
>     HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
>     HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, 
> mask_sh), \
>     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 
> mask_sh), \
> -   HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
> 
> +   HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh),\
> 
> +   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
> 
> +   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
> 
> 
> 
> Which somehow changed into
> 
> @@ -404,7 +406,9 @@ struct dce_hwseq_registers {
>     HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
>     HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
>     HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
> -   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
> +   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \
> +   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
> +   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
> 

This is just defining the VGA_TEST registers for use by DC. It shouldn't have 
an impact on that patch.

> And the net result is the display doesn't work (same glitches as before) on a 
> raven1 device.
> 

Can you see if reverting this commit fixes it?
1b0ff66bc0bf drm/amd/display: early return if not in vga mode in 
disable_vga

If introduced a check to see if we're actually in VGA mode and only then 
applied the workaround. I believe it's to avoid problems resuming from S3.

Harry

> Tom
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Re: vga handover for raven

[Tom St Denis]

Hi Harry,

Reverting that on top of the current amd-staging-drm-next seems to have 
fixed the issue.


Thanks,
Tom

On 03/14/2018 10:08 AM, Harry Wentland wrote:

On 2018-03-14 09:54 AM, Tom St Denis wrote:

Hi,

In the original version of the patch we had:

@@ -358,7 +360,9 @@ struct dce_hwseq_registers {

     HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
     HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, 
mask_sh), \
     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 
mask_sh), \
-   HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)

+   HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh),\

+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\

+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)



Which somehow changed into

@@ -404,7 +406,9 @@ struct dce_hwseq_registers {
     HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
     HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
     HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \
+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)



This is just defining the VGA_TEST registers for use by DC. It shouldn't have 
an impact on that patch.


And the net result is the display doesn't work (same glitches as before) on a 
raven1 device.



Can you see if reverting this commit fixes it?
1b0ff66bc0bf drm/amd/display: early return if not in vga mode in 
disable_vga

If introduced a check to see if we're actually in VGA mode and only then 
applied the workaround. I believe it's to avoid problems resuming from S3.

Harry


Tom

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RE: vga handover for raven

[Yang, Eric]

If there is no VGA hand over, the change should make no difference. In the VGA 
hand over case, the difference introduced is the following, we can try to 
revert this part of the commit, which should not break S3.

REG_WRITE(D1VGA_CONTROL, 0);
-   REG_WRITE(D2VGA_CONTROL, 0);
-   REG_WRITE(D3VGA_CONTROL, 0);
-   REG_WRITE(D4VGA_CONTROL, 0);

-Original Message-
From: StDenis, Tom 
Sent: Wednesday, March 14, 2018 10:12 AM
To: Wentland, Harry ; Lakha, Bhawanpreet 

Cc: amd-gfx@lists.freedesktop.org; Cheng, Tony ; Yang, Eric 

Subject: Re: vga handover for raven

Hi Harry,

Reverting that on top of the current amd-staging-drm-next seems to have fixed 
the issue.

Thanks,
Tom

On 03/14/2018 10:08 AM, Harry Wentland wrote:
> On 2018-03-14 09:54 AM, Tom St Denis wrote:
>> Hi,
>>
>> In the original version of the patch we had:
>>
>> @@ -358,7 +360,9 @@ struct dce_hwseq_registers {
>>
>>      HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
>>      HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, 
>> PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
>>      HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, 
>> DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
>> -   HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
>>
>> +   HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh),\
>>
>> +   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
>>
>> +   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
>>
>>
>>
>> Which somehow changed into
>>
>> @@ -404,7 +406,9 @@ struct dce_hwseq_registers {
>>      HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, 
>> mask_sh), \
>>      HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
>>      HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
>> -   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, 
>> mask_sh)
>> +   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, 
>> +mask_sh), \
>> +   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
>> +   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
>>
> 
> This is just defining the VGA_TEST registers for use by DC. It shouldn't have 
> an impact on that patch.
> 
>> And the net result is the display doesn't work (same glitches as before) on 
>> a raven1 device.
>>
> 
> Can you see if reverting this commit fixes it?
>   1b0ff66bc0bf drm/amd/display: early return if not in vga mode in 
> disable_vga
> 
> If introduced a check to see if we're actually in VGA mode and only then 
> applied the workaround. I believe it's to avoid problems resuming from S3.
> 
> Harry
> 
>> Tom
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[PATCH xf86-video-ati] Pass extents to amdgpu_scanout_do_update by value

[Michel Dänzer]

From: Michel Dänzer 

amdgpu_scanout_extents_intersect could leave the scanout damage region
in an invalid state, triggering debugging checks in pixman:

*** BUG ***
In pixman_region_append_non_o: The expression r->x1 < r->x2 was false
Set a breakpoint on '_pixman_log_error' to debug

(Ported from amdgpu commit 8af989546907ad9fb491d940e1936d3bfc89276b)

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c |  4 ++--
 src/radeon.h  |  2 +-
 src/radeon_kms.c  | 24 
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 93261dc8d..f056bf3b4 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -817,7 +817,7 @@ drmmode_crtc_scanout_update(xf86CrtcPtr crtc, 
DisplayModePtr mode,
 
radeon_scanout_do_update(crtc, scanout_id,
 screen->GetWindowPixmap(screen->root),
-box);
+*box);
radeon_bo_wait(drmmode_crtc->scanout[scanout_id].bo);
}
 }
@@ -3282,7 +3282,7 @@ Bool radeon_do_pageflip(ScrnInfoPtr scrn, ClientPtr 
client,
}
 
radeon_scanout_do_update(crtc, scanout_id, new_front,
-&extents);
+extents);
 
drmmode_crtc_wait_pending_event(drmmode_crtc, 
pRADEONEnt->fd,

drmmode_crtc->scanout_update_pending);
diff --git a/src/radeon.h b/src/radeon.h
index 0815cd984..598a83c17 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -672,7 +672,7 @@ Bool radeon_dri3_screen_init(ScreenPtr screen);
 
 /* radeon_kms.c */
 Bool radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id,
- PixmapPtr src_pix, BoxPtr extents);
+ PixmapPtr src_pix, BoxRec extents);
 void RADEONWindowExposures_oneshot(WindowPtr pWin, RegionPtr pRegion
 #if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0)
   , RegionPtr pBSRegion
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 8c3d15eb0..26810e084 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -903,10 +903,10 @@ radeon_dirty_update(ScrnInfoPtr scrn)
 
 Bool
 radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id,
-PixmapPtr src_pix, BoxPtr extents)
+PixmapPtr src_pix, BoxRec extents)
 {
 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
-RegionRec region = { .extents = *extents, .data = NULL };
+RegionRec region = { .extents = extents, .data = NULL };
 ScrnInfoPtr scrn = xf86_crtc->scrn;
 ScreenPtr pScreen = scrn->pScreen;
 RADEONInfoPtr info = RADEONPTR(scrn);
@@ -915,11 +915,11 @@ radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int 
scanout_id,
 
 if (!xf86_crtc->enabled ||
!drmmode_crtc->scanout[scanout_id].pixmap ||
-   extents->x1 >= extents->x2 || extents->y1 >= extents->y2)
+   extents.x1 >= extents.x2 || extents.y1 >= extents.y2)
return FALSE;
 
 pDraw = &drmmode_crtc->scanout[scanout_id].pixmap->drawable;
-if (!radeon_scanout_extents_intersect(xf86_crtc, extents))
+if (!radeon_scanout_extents_intersect(xf86_crtc, &extents))
return FALSE;
 
 if (drmmode_crtc->tear_free) {
@@ -965,9 +965,9 @@ radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int 
scanout_id,
pScreen->SourceValidate = NULL;
CompositePicture(PictOpSrc,
 src, NULL, dst,
-extents->x1, extents->y1, 0, 0, extents->x1,
-extents->y1, extents->x2 - extents->x1,
-extents->y2 - extents->y1);
+extents.x1, extents.y1, 0, 0, extents.x1,
+extents.y1, extents.x2 - extents.x1,
+extents.y2 - extents.y1);
pScreen->SourceValidate = SourceValidate;
 
  free_dst:
@@ -981,9 +981,9 @@ radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int 
scanout_id,
 
ValidateGC(pDraw, gc);
(*gc->ops->CopyArea)(&src_pix->drawable, pDraw, gc,
-xf86_crtc->x + extents->x1, xf86_crtc->y + 
extents->y1,
-extents->x2 - extents->x1, extents->y2 - 
extents->y1,
-extents->x1, extents->y1);
+xf86_crtc->x + extents.x1, xf86_crtc->y + 
extents.y1,
+extents.x2 - extents.x1, extents.y2 - extents.y1,
+extents.x1, extents.y1);
FreeScratchGC(gc);
 }
 
@@ -1015,7 +1015,7 @@ radeon_scanout_update_handler(xf86CrtcPtr crtc, uint32_t 
frame, uint64_t usec,
drmmode_crtc->dpms_mode == DPMSModeOn) {
if (radeon_scanout_do_update(crtc, drmmode_crtc->scanout_

Re: AMD E8860 on PowerPC with u-boot (T2080)

[Bas Vermeulen]

I have the radeon driver working on the T2080, and am currently running
into a problem with gallium/mesa. My problem was a mismatch
between u-boot and my device-tree that caused PCI Express to misbehave.

When I run a program calling OpenCL, I get a segfault. The cause for this
particular crash in src/gallium/drivers/radeonsi/si_state_draw.c:474
is the use of bit fields in union si_vgt_param_key
(from src/gallium/drivers/radeonsi/si_pipe.h:310). I'm fairly sure there
will be other instances.

Is there a best practice on resolving this? Point me in the right direction
and I'll create some patches to get this fixed.

Bas Vermeulen

On Thu, Feb 22, 2018 at 9:51 AM, Christian König 
wrote:

> Am 22.02.2018 um 09:37 schrieb Bas Vermeulen:
>
> On Wed, Feb 21, 2018 at 6:22 PM, Alex Deucher 
> wrote:
>
>> On Wed, Feb 21, 2018 at 7:43 AM, Christian König
>> [SNIP]
>> > Apart from that I don't have any good idea any more why that shouldn't
>> work.
>>
>> Does your platform properly handle DMA masks?  Most radeon hw only
>> supports a 40 bit DMA mask.  If there are relevant bits in the upper
>> bits of the address, they will be lost when the hw tries to use the
>> address.  On at least some powerpc hw, I believe there is some memory
>> routing related info in the high bits.
>>
>
> On 4.1 (without the hashing algorithm when printing pointers), The rings
> are placed thus:
>
> [   11.002673] radeon 0002:01:00.0: fence driver on ring 0 use gpu addr
> 0x8c00 and cpu addr 0xc0007c0c8c00
> [   11.012165] radeon 0002:01:00.0: fence driver on ring 1 use gpu addr
> 0x8c04 and cpu addr 0xc0007c0c8c04
> [   11.021657] radeon 0002:01:00.0: fence driver on ring 2 use gpu addr
> 0x8c08 and cpu addr 0xc0007c0c8c08
> [   11.031152] radeon 0002:01:00.0: fence driver on ring 3 use gpu addr
> 0x8c0c and cpu addr 0xc0007c0c8c0c
> [   11.040644] radeon 0002:01:00.0: fence driver on ring 4 use gpu addr
> 0x8c10 and cpu addr 0xc0007c0c8c10
> [   11.051919] radeon 0002:01:00.0: fence driver on ring 5 use gpu addr
> 0x00075a18 and cpu addr 0x880088db5a18
>
> It's also using bit 63 & 62. So this might be something to look into.
>
>
> No, that is just the virtual address of the buffer in kernel space and
> perfectly ok.
>
> What you could try is to force the need_dma32 flag to true, see
> drivers/gpu/drm/radeon/radeon_ttm.c and search for need_dma32.
>
> Regards,
> Christian.
>
>
> Bas Vermeulen
>
>
>
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Re: vga handover for raven

[Tom St Denis]

This diff on top of drm-next works fine

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

index 4365906b14ee..7688ed5724b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -228,6 +228,9 @@ static void disable_vga(
return;

REG_WRITE(D1VGA_CONTROL, 0);
+   REG_WRITE(D2VGA_CONTROL, 0);
+   REG_WRITE(D3VGA_CONTROL, 0);
+   REG_WRITE(D4VGA_CONTROL, 0);

/* HW Engineer's Notes:
 *  During switch from vga->extended, if we set the 
VGA_TEST_ENABLE and



I can't test suspend/resume right now since I don't have the gfxoff 
branch handy.


Tom

On 03/14/2018 10:55 AM, Yang, Eric wrote:

If there is no VGA hand over, the change should make no difference. In the VGA 
hand over case, the difference introduced is the following, we can try to 
revert this part of the commit, which should not break S3.

 REG_WRITE(D1VGA_CONTROL, 0);
-   REG_WRITE(D2VGA_CONTROL, 0);
-   REG_WRITE(D3VGA_CONTROL, 0);
-   REG_WRITE(D4VGA_CONTROL, 0);

-Original Message-
From: StDenis, Tom
Sent: Wednesday, March 14, 2018 10:12 AM
To: Wentland, Harry ; Lakha, Bhawanpreet 

Cc: amd-gfx@lists.freedesktop.org; Cheng, Tony ; Yang, Eric 

Subject: Re: vga handover for raven

Hi Harry,

Reverting that on top of the current amd-staging-drm-next seems to have fixed 
the issue.

Thanks,
Tom

On 03/14/2018 10:08 AM, Harry Wentland wrote:

On 2018-03-14 09:54 AM, Tom St Denis wrote:

Hi,

In the original version of the patch we had:

@@ -358,7 +360,9 @@ struct dce_hwseq_registers {

      HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
      HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL,
PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
      HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL,
DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
-   HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)

+   HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh),\

+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\

+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)



Which somehow changed into

@@ -404,7 +406,9 @@ struct dce_hwseq_registers {
      HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS,
mask_sh), \
      HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
      HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R,
mask_sh)
+   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R,
+mask_sh), \
+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)



This is just defining the VGA_TEST registers for use by DC. It shouldn't have 
an impact on that patch.


And the net result is the display doesn't work (same glitches as before) on a 
raven1 device.



Can you see if reverting this commit fixes it?
1b0ff66bc0bf drm/amd/display: early return if not in vga mode in
disable_vga

If introduced a check to see if we're actually in VGA mode and only then 
applied the workaround. I believe it's to avoid problems resuming from S3.

Harry


Tom

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[PATCH] drm/radeon: Don't turn off DP sink when disconnected

[Michel Dänzer]

From: Michel Dänzer 

Turning off the sink in this case causes various issues, because
userspace expects it to stay on until it turns it off explicitly.

Instead, turn the sink off and back on when a display is connected
again. This dance seems necessary for link training to work correctly.

Bugzilla: https://bugs.freedesktop.org/105308
Cc: sta...@vger.kernel.org
Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 31 --
 1 file changed, 12 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 5012f5e47a1e..b108eaabb6df 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -90,25 +90,18 @@ void radeon_connector_hotplug(struct drm_connector 
*connector)
/* don't do anything if sink is not display port, i.e.,
 * passive dp->(dvi|hdmi) adaptor
 */
-   if (dig_connector->dp_sink_type == 
CONNECTOR_OBJECT_ID_DISPLAYPORT) {
-   int saved_dpms = connector->dpms;
-   /* Only turn off the display if it's physically 
disconnected */
-   if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 
{
-   drm_helper_connector_dpms(connector, 
DRM_MODE_DPMS_OFF);
-   } else if 
(radeon_dp_needs_link_train(radeon_connector)) {
-   /* Don't try to start link training before we
-* have the dpcd */
-   if (!radeon_dp_getdpcd(radeon_connector))
-   return;
-
-   /* set it to OFF so that 
drm_helper_connector_dpms()
-* won't return immediately since the current 
state
-* is ON at this point.
-*/
-   connector->dpms = DRM_MODE_DPMS_OFF;
-   drm_helper_connector_dpms(connector, 
DRM_MODE_DPMS_ON);
-   }
-   connector->dpms = saved_dpms;
+   if (dig_connector->dp_sink_type == 
CONNECTOR_OBJECT_ID_DISPLAYPORT &&
+   radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&
+   radeon_dp_needs_link_train(radeon_connector)) {
+   /* Don't start link training before we have the DPCD */
+   if (!radeon_dp_getdpcd(radeon_connector))
+   return;
+
+   /* Turn the connector off and back on immediately, which
+* will trigger link training
+*/
+   drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
+   drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
}
}
 }
-- 
2.16.2

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[PATCH] drm/amdgpu: Use atomic function to disable crtcs with dc enabled

[mikita.lipski]

From: Mikita Lipski 

This change fixes the deadlock when unloading the driver with displays
connected.

Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 65584f6..b4911911 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2081,9 +2081,12 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
 
DRM_INFO("amdgpu: finishing device.\n");
adev->shutdown = true;
-   if (adev->mode_info.mode_config_initialized)
-   drm_crtc_force_disable_all(adev->ddev);
-
+   if (adev->mode_info.mode_config_initialized){
+   if (!amdgpu_device_has_dc_support(adev))
+   drm_crtc_force_disable_all(adev->ddev);
+   else
+   drm_atomic_helper_shutdown(adev->ddev);
+   }
amdgpu_ib_pool_fini(adev);
amdgpu_fence_driver_fini(adev);
amdgpu_fbdev_fini(adev);
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: Use atomic function to disable crtcs with dc enabled

[Andrey Grodzovsky]

Reviewed-by: Andrey Grodzovsky 

Andrey


On 03/14/2018 01:51 PM, mikita.lip...@amd.com wrote:

From: Mikita Lipski 

This change fixes the deadlock when unloading the driver with displays
connected.

Signed-off-by: Mikita Lipski 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++---
  1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 65584f6..b4911911 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2081,9 +2081,12 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
  
  	DRM_INFO("amdgpu: finishing device.\n");

adev->shutdown = true;
-   if (adev->mode_info.mode_config_initialized)
-   drm_crtc_force_disable_all(adev->ddev);
-
+   if (adev->mode_info.mode_config_initialized){
+   if (!amdgpu_device_has_dc_support(adev))
+   drm_crtc_force_disable_all(adev->ddev);
+   else
+   drm_atomic_helper_shutdown(adev->ddev);
+   }
amdgpu_ib_pool_fini(adev);
amdgpu_fence_driver_fini(adev);
amdgpu_fbdev_fini(adev);


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[PATCH 1/2] drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel

[Andrey Grodzovsky]

and amdgpu_bo_create_reserved.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 48e0115..11673c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -171,7 +171,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo 
*abo, u32 domain)
  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr: resulting BO (new BO is created if bo_ptr is NULL)
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
@@ -240,7 +240,7 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
  * @size: size for the new BO
  * @align: alignment for the new BO
  * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr: resulting BO (new BO is created if bo_ptr is NULL)
  * @gpu_addr: GPU addr of the pinned BO
  * @cpu_addr: optional CPU address mapping
  *
-- 
2.7.4

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[PATCH 2/2] drm/amd/powerplay: Fix KASAN user after free on driver unload.

[Andrey Grodzovsky]

Reusing local handle to initialize BO without resetting it to
NULL is wrong since it causes amdgpu_bo_create_reserved to skip
new BO creation and just reuse the given pointer for pinning.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c |  7 ++-
 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 16 +---
 2 files changed, 7 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index e2ee23a..65c6ca7 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -327,7 +327,6 @@ static int rv_start_smu(struct pp_hwmgr *hwmgr)
 
 static int rv_smu_init(struct pp_hwmgr *hwmgr)
 {
-   struct amdgpu_bo *handle = NULL;
struct rv_smumgr *priv;
uint64_t mc_addr;
void *kaddr = NULL;
@@ -345,7 +344,7 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
sizeof(Watermarks_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
+   &priv->smu_tables.entry[WMTABLE].handle,
&mc_addr,
&kaddr);
 
@@ -357,14 +356,13 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
priv->smu_tables.entry[WMTABLE].mc_addr = mc_addr;
priv->smu_tables.entry[WMTABLE].table = kaddr;
-   priv->smu_tables.entry[WMTABLE].handle = handle;
 
/* allocate space for watermarks table */
r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
sizeof(DpmClocks_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
+   &priv->smu_tables.entry[CLOCKTABLE].handle,
&mc_addr,
&kaddr);
 
@@ -380,7 +378,6 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
priv->smu_tables.entry[CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
priv->smu_tables.entry[CLOCKTABLE].mc_addr = mc_addr;
priv->smu_tables.entry[CLOCKTABLE].table = kaddr;
-   priv->smu_tables.entry[CLOCKTABLE].handle = handle;
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 15e1afa..c8b326e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -377,7 +377,6 @@ static int vega10_verify_smc_interface(struct pp_hwmgr 
*hwmgr)
 
 static int vega10_smu_init(struct pp_hwmgr *hwmgr)
 {
-   struct amdgpu_bo *handle = NULL;
struct vega10_smumgr *priv;
uint64_t mc_addr;
void *kaddr = NULL;
@@ -403,7 +402,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
sizeof(PPTable_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
+   &priv->smu_tables.entry[PPTABLE].handle,
&mc_addr,
&kaddr);
 
@@ -415,14 +414,13 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
priv->smu_tables.entry[PPTABLE].table_id = TABLE_PPTABLE;
priv->smu_tables.entry[PPTABLE].mc_addr = mc_addr;
priv->smu_tables.entry[PPTABLE].table = kaddr;
-   priv->smu_tables.entry[PPTABLE].handle = handle;
 
/* allocate space for watermarks table */
ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
sizeof(Watermarks_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
+   &priv->smu_tables.entry[WMTABLE].handle,
&mc_addr,
&kaddr);
 
@@ -434,14 +432,13 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
priv->smu_tables.entry[WMTABLE].mc_addr = mc_addr;
priv->smu_tables.entry[WMTABLE].table = kaddr;
-   priv->smu_tables.entry[WMTABLE].handle = handle;
 
/* allocate space for AVFS table */
ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
sizeof(AvfsTable_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
+   &priv->smu_tables.entry[AVFSTABLE].handle,
&mc_addr,
&kaddr);
 
@@ -453,7 +450,6 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
priv->smu_tables.entry[AVFSTABLE].table_id = TABLE_AVFS;
priv->smu_tables.entry[AVFSTABLE].mc_addr = mc_addr;
priv->smu_tables.entry[AVFSTABLE].table = kaddr;
-   priv->s

Re: [PATCH 1/2] drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel

[Christian König]

Am 14.03.2018 um 19:07 schrieb Andrey Grodzovsky:

and amdgpu_bo_create_reserved.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 48e0115..11673c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -171,7 +171,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo 
*abo, u32 domain)
   * @size: size for the new BO
   * @align: alignment for the new BO
   * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr: resulting BO (new BO is created if bo_ptr is NULL)


Maybe add "only" here, e.g. new BO is only created if bo_ptr points to NULL.

And add something like "used to initialize BOs in structures".

Either way the patch is Reviewed-by: Christian König 
.


Christian.


   * @gpu_addr: GPU addr of the pinned BO
   * @cpu_addr: optional CPU address mapping
   *
@@ -240,7 +240,7 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
   * @size: size for the new BO
   * @align: alignment for the new BO
   * @domain: where to place it
- * @bo_ptr: resulting BO
+ * @bo_ptr: resulting BO (new BO is created if bo_ptr is NULL)
   * @gpu_addr: GPU addr of the pinned BO
   * @cpu_addr: optional CPU address mapping
   *


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Re: [PATCH 2/2] drm/amd/powerplay: Fix KASAN user after free on driver unload.

[Christian König]

Am 14.03.2018 um 19:07 schrieb Andrey Grodzovsky:

Reusing local handle to initialize BO without resetting it to
NULL is wrong since it causes amdgpu_bo_create_reserved to skip
new BO creation and just reuse the given pointer for pinning.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c |  7 ++-
  drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 16 +---
  2 files changed, 7 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index e2ee23a..65c6ca7 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -327,7 +327,6 @@ static int rv_start_smu(struct pp_hwmgr *hwmgr)
  
  static int rv_smu_init(struct pp_hwmgr *hwmgr)

  {
-   struct amdgpu_bo *handle = NULL;
struct rv_smumgr *priv;
uint64_t mc_addr;
void *kaddr = NULL;
@@ -345,7 +344,7 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
sizeof(Watermarks_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
+   &priv->smu_tables.entry[WMTABLE].handle,
&mc_addr,
&kaddr);
  
@@ -357,14 +356,13 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)

priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
priv->smu_tables.entry[WMTABLE].mc_addr = mc_addr;
priv->smu_tables.entry[WMTABLE].table = kaddr;
-   priv->smu_tables.entry[WMTABLE].handle = handle;
  
  	/* allocate space for watermarks table */

r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
sizeof(DpmClocks_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
+   &priv->smu_tables.entry[CLOCKTABLE].handle,
&mc_addr,
&kaddr);
  
@@ -380,7 +378,6 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)

priv->smu_tables.entry[CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
priv->smu_tables.entry[CLOCKTABLE].mc_addr = mc_addr;
priv->smu_tables.entry[CLOCKTABLE].table = kaddr;
-   priv->smu_tables.entry[CLOCKTABLE].handle = handle;
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 15e1afa..c8b326e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -377,7 +377,6 @@ static int vega10_verify_smc_interface(struct pp_hwmgr 
*hwmgr)
  
  static int vega10_smu_init(struct pp_hwmgr *hwmgr)

  {
-   struct amdgpu_bo *handle = NULL;
struct vega10_smumgr *priv;
uint64_t mc_addr;
void *kaddr = NULL;
@@ -403,7 +402,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
sizeof(PPTable_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
+   &priv->smu_tables.entry[PPTABLE].handle,
&mc_addr,
&kaddr);
  
@@ -415,14 +414,13 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)

priv->smu_tables.entry[PPTABLE].table_id = TABLE_PPTABLE;
priv->smu_tables.entry[PPTABLE].mc_addr = mc_addr;
priv->smu_tables.entry[PPTABLE].table = kaddr;
-   priv->smu_tables.entry[PPTABLE].handle = handle;
  
  	/* allocate space for watermarks table */

ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
sizeof(Watermarks_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
+   &priv->smu_tables.entry[WMTABLE].handle,
&mc_addr,
&kaddr);
  
@@ -434,14 +432,13 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)

priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
priv->smu_tables.entry[WMTABLE].mc_addr = mc_addr;
priv->smu_tables.entry[WMTABLE].table = kaddr;
-   priv->smu_tables.entry[WMTABLE].handle = handle;
  
  	/* allocate space for AVFS table */

ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
sizeof(AvfsTable_t),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
-   &handle,
+   &priv->smu_tables.entry[AVFSTABLE].handle,
&mc_addr,
&kaddr);
  
@@ -453,7 +450,6 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)

priv->smu_tables.entry[AVFSTABLE].table_id = TABLE_AVFS;
priv->smu_tables.entry[AVFSTABLE].mc_addr = mc_addr;
pr

Re: [PATCH] drm/radeon: Don't turn off DP sink when disconnected

[Alex Deucher]

On Wed, Mar 14, 2018 at 1:15 PM, Michel Dänzer  wrote:
> From: Michel Dänzer 
>
> Turning off the sink in this case causes various issues, because
> userspace expects it to stay on until it turns it off explicitly.
>
> Instead, turn the sink off and back on when a display is connected
> again. This dance seems necessary for link training to work correctly.
>
> Bugzilla: https://bugs.freedesktop.org/105308
> Cc: sta...@vger.kernel.org
> Signed-off-by: Michel Dänzer 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/radeon/radeon_connectors.c | 31 
> --
>  1 file changed, 12 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
> b/drivers/gpu/drm/radeon/radeon_connectors.c
> index 5012f5e47a1e..b108eaabb6df 100644
> --- a/drivers/gpu/drm/radeon/radeon_connectors.c
> +++ b/drivers/gpu/drm/radeon/radeon_connectors.c
> @@ -90,25 +90,18 @@ void radeon_connector_hotplug(struct drm_connector 
> *connector)
> /* don't do anything if sink is not display port, i.e.,
>  * passive dp->(dvi|hdmi) adaptor
>  */
> -   if (dig_connector->dp_sink_type == 
> CONNECTOR_OBJECT_ID_DISPLAYPORT) {
> -   int saved_dpms = connector->dpms;
> -   /* Only turn off the display if it's physically 
> disconnected */
> -   if (!radeon_hpd_sense(rdev, 
> radeon_connector->hpd.hpd)) {
> -   drm_helper_connector_dpms(connector, 
> DRM_MODE_DPMS_OFF);
> -   } else if 
> (radeon_dp_needs_link_train(radeon_connector)) {
> -   /* Don't try to start link training before we
> -* have the dpcd */
> -   if (!radeon_dp_getdpcd(radeon_connector))
> -   return;
> -
> -   /* set it to OFF so that 
> drm_helper_connector_dpms()
> -* won't return immediately since the current 
> state
> -* is ON at this point.
> -*/
> -   connector->dpms = DRM_MODE_DPMS_OFF;
> -   drm_helper_connector_dpms(connector, 
> DRM_MODE_DPMS_ON);
> -   }
> -   connector->dpms = saved_dpms;
> +   if (dig_connector->dp_sink_type == 
> CONNECTOR_OBJECT_ID_DISPLAYPORT &&
> +   radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&
> +   radeon_dp_needs_link_train(radeon_connector)) {
> +   /* Don't start link training before we have the DPCD 
> */
> +   if (!radeon_dp_getdpcd(radeon_connector))
> +   return;
> +
> +   /* Turn the connector off and back on immediately, 
> which
> +* will trigger link training
> +*/
> +   drm_helper_connector_dpms(connector, 
> DRM_MODE_DPMS_OFF);
> +   drm_helper_connector_dpms(connector, 
> DRM_MODE_DPMS_ON);
> }
> }
>  }
> --
> 2.16.2
>
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[pull] radeon and amdgpu drm-fixes-4.16

[Alex Deucher]

Hi Dave,

A few fixes for 4.16:
- Fix a backlight S/R regression on amdgpu
- Fix prime teardown on radeon and amdgpu
- DP fix for amdgpu

The following changes since commit b0655d668fc4faf0c1985e828820f9b9ca13abe6:

  Merge branch 'drm-fixes-4.16' of git://people.freedesktop.org/~agd5f/linux 
into drm-fixes (2018-03-09 09:23:02 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.16

for you to fetch changes up to 7d617264eb22b18d979eac6e85877a141253034e:

  drm/amdgpu/dce: Don't turn off DP sink when disconnected (2018-03-14 15:40:00 
-0500)


Alex Deucher (1):
  drm/amdgpu: save/restore backlight level in legacy dce code

Christian König (2):
  drm/amdgpu: fix prime teardown order
  drm/radeon: fix prime teardown order

Michel Dänzer (1):
  drm/amdgpu/dce: Don't turn off DP sink when disconnected

 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 31 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c|  2 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  2 ++
 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/atombios_encoders.h |  5 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c |  8 +++
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c |  8 +++
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  |  8 +++
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c  |  8 +++
 drivers/gpu/drm/radeon/radeon_gem.c|  2 --
 drivers/gpu/drm/radeon/radeon_object.c |  2 ++
 12 files changed, 56 insertions(+), 25 deletions(-)
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Debugging modesetting problem

[Jona Stubbe]

Hi AMD graphics developers,

I've recently hit a modesetting problem: when I used the DisplayPort KVM 
switch that I got yesterday to connect my PC (running Arch Linux) to my 4K 
monitor, it only worked in 3 out of about 60 times of switching/replugging the 
cable (the BIOS always manages to put something onscreen, though).
I've tried both graphics cards available to me right now: a Polaris (RX 480) 
and a Cayman (HD 6950/6970) and neither of them modesets properly and 
reliably.
I wouldn't be opposed to doing some work to fix this myself, as this is a good 
opportunity for me to get into system development, however I don't know where 
to start.
I have full (root if required) access to the system, so building/running 
custom kernels or whatever is necessary is not a big problem. However, logic 
analysers (or whatever you may need to find out what actually goes over the 
wire) are out of my reach. Is this something I can tackle?

Yours faithfully
Jona Stubbe

PS: if there is a shorter-latency way of asking this kind of question (like an 
IRC channel), I'd be interested too :)

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[PATCH 1/8] drm/amdgpu: Fix hardcoded base offset of vram pages

[Feifei Xu]

In gmc_v9_0_vram_gtt_location(),the vram_base_offset is hardcoded
to 0 in dGPU. Fix it by reading mmMC_VM_FB_OFFSET or return
zfb_phys_addr if ZFB is enabled.

Change-Id: I585b7d4d96ebab2a5d7178fe8d1d6a746ef0c72a
Signed-off-by: Feifei Xu 
Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a70cbc4..0f61e05 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -697,10 +697,7 @@ static void gmc_v9_0_vram_gtt_location(struct 
amdgpu_device *adev,
amdgpu_device_vram_location(adev, &adev->gmc, base);
amdgpu_device_gart_location(adev, mc);
/* base offset of vram pages */
-   if (adev->flags & AMD_IS_APU)
-   adev->vm_manager.vram_base_offset = 
gfxhub_v1_0_get_mc_fb_offset(adev);
-   else
-   adev->vm_manager.vram_base_offset = 0;
+   adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 }
 
 /**
-- 
2.7.4

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[PATCH 2/8] drm/amdgpu: add new member in amdgpu_mc for zfb support

[Feifei Xu]

Change-Id: I8253c8ff80e0cbd1f12e5ee801600e7619e6718f
Signed-off-by: Hawking Zhang 
Signed-off-by: Feifei Xu 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 893c249..8f35f7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -107,6 +107,9 @@ struct amdgpu_gmc {
booltranslate_further;
 
const struct amdgpu_gmc_funcs   *gmc_funcs;
+/* zero frame buffer */
+u64 zfb_phys_addr;
+u64 zfb_size;
 };
 
 #endif
-- 
2.7.4

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[PATCH 3/8] drm/amdgpu: add amdgpu module parameter for zfb

[Feifei Xu]

Users can pass in an array to decide enable/disable Zero Frame Buffer.
zfb[0] = zfb_size(MB), zfb[1] = zfb_phys_addr(MB).
If zbf_size > 0, zfb is enabled. Otherwise disabled.
Usage for example:
modprobe amdgpu zfb=256,8192

Change-Id: I711062eb86b6cdff74572cabb3df250c6708e473
Signed-off-by: Feifei Xu 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2e6d986..949b451 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -129,6 +129,7 @@ extern int amdgpu_lbpw;
 extern int amdgpu_compute_multipipe;
 extern int amdgpu_gpu_recovery;
 extern int amdgpu_emu_mode;
+extern ulong amdgpu_zfb[];
 
 #ifdef CONFIG_DRM_AMDGPU_SI
 extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e670936..53ba4ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -132,6 +132,7 @@ int amdgpu_lbpw = -1;
 int amdgpu_compute_multipipe = -1;
 int amdgpu_gpu_recovery = -1; /* auto */
 int amdgpu_emu_mode = 0;
+ulong amdgpu_zfb[2] = {0,4096UL}; /* {0,0x1} */
 
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -290,6 +291,10 @@ module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 
0444);
 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
 
+MODULE_PARM_DESC(zfb,
+"Enable Zero Frame Buffer feature (zfb will be set like 
,(zfb_size MB,zfb_phys_addr MB),default disabled)");
+module_param_array_named(zfb, amdgpu_zfb, ulong, NULL, 0444);
+
 #ifdef CONFIG_DRM_AMDGPU_SI
 
 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
-- 
2.7.4

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[PATCH 4/8] drm/amdgpu: init zfb start address and size

[Feifei Xu]

Use module parameter passed from user to initialize zfb start address
and size.

Change-Id: I3d786e863114a217f89ff7c3d4ffdabf000f31a4
Signed-off-by: Feifei Xu 
Signed-off-by: Hawking Zhang 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2188763..b88cb4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -859,6 +859,16 @@ static void amdgpu_device_check_arguments(struct 
amdgpu_device *adev)
amdgpu_lockup_timeout = 1;
}
 
+   if (amdgpu_zfb[0] > 0) {
+   dev_warn(adev->dev,
+"Zero Frame Buffer is enabled.\n");
+   adev->gmc.zfb_phys_addr = amdgpu_zfb[1] << 20;
+   adev->gmc.zfb_size = amdgpu_zfb[0] << 20;
+   } else {
+   adev->gmc.zfb_phys_addr = 0;
+   adev->gmc.zfb_size = 0;
+   }
+
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, 
amdgpu_fw_load_type);
 }
 
-- 
2.7.4

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[PATCH 5/8] drm/amdgpu: user reserved zfb to init vram base offset and size

[Feifei Xu]

Change-Id: I866dd16548304a42298b0cb28741f27cba3a76ca
Signed-off-by: Feifei Xu 
Signed-off-by: Hawking Zhang 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26 --
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 0f61e05..94e13c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -697,7 +697,10 @@ static void gmc_v9_0_vram_gtt_location(struct 
amdgpu_device *adev,
amdgpu_device_vram_location(adev, &adev->gmc, base);
amdgpu_device_gart_location(adev, mc);
/* base offset of vram pages */
-   adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
+   if (adev->gmc.zfb_size > 0)
+   adev->vm_manager.vram_base_offset = adev->gmc.zfb_phys_addr;
+   else
+   adev->vm_manager.vram_base_offset = 
gfxhub_v1_0_get_mc_fb_offset(adev);
 }
 
 /**
@@ -761,8 +764,11 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
}
 
/* size in MB on si */
-   adev->gmc.mc_vram_size =
-   adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
+   if (adev->gmc.zfb_size > 0)
+   adev->gmc.mc_vram_size = adev->gmc.zfb_size;
+   else
+   adev->gmc.mc_vram_size =
+   adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 
if (!(adev->flags & AMD_IS_APU)) {
@@ -770,12 +776,20 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
if (r)
return r;
}
-   adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
-   adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+   if (adev->gmc.zfb_size > 0) {
+   adev->gmc.aper_base = adev->gmc.zfb_phys_addr;
+   adev->gmc.aper_size = adev->gmc.zfb_size;
+   } else {
+   adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
+   adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+   }
 
 #ifdef CONFIG_X86_64
if (adev->flags & AMD_IS_APU) {
-   adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
+   if (adev->gmc.zfb_size > 0)
+   adev->gmc.aper_base = adev->gmc.zfb_phys_addr;
+   else
+   adev->gmc.aper_base = 
gfxhub_v1_0_get_mc_fb_offset(adev);
adev->gmc.aper_size = adev->gmc.real_vram_size;
}
 #endif
-- 
2.7.4

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[PATCH 6/8] drm/amdgpu: enable physical transaction for ptd/pde when ZFB is enabled

[Feifei Xu]

Change-Id: I2b45d765f1f60252fa1c02aced94f8100d575ddc
Signed-off-by: Hawking Zhang 
Signed-off-by: Feifei Xu 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 9 +++--
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 9 +++--
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index acfbd2d..0d72f52 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -155,8 +155,13 @@ static void gfxhub_v1_0_init_cache_regs(struct 
amdgpu_device *adev)
WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
 
tmp = mmVM_L2_CNTL4_DEFAULT;
-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+   if (adev->gmc.zfb_size > 0) {
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
+   } else {
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+   }
WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 3dd5816..bd3777a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -166,8 +166,13 @@ static void mmhub_v1_0_init_cache_regs(struct 
amdgpu_device *adev)
}
 
tmp = mmVM_L2_CNTL4_DEFAULT;
-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
-   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+   if (adev->gmc.zfb_size > 0) {
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
+   } else {
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+   tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, 
VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+   }
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
 }
 
-- 
2.7.4

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[PATCH 7/8] drm/amdgpu: program AGP aperture as frame buffer when ZFB is enabled

[Feifei Xu]

From: Hawking Zhang 

Change-Id: I09f9ddea0ad23af00fadd9af7aaccf7160e4e569
Signed-off-by: Hawking Zhang 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 19 +++
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 19 +++
 2 files changed, 30 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 0d72f52..3689f1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -71,10 +71,21 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
 {
uint64_t value;
 
-   /* Disable AGP. */
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0x);
+   if (adev->gmc.zfb_size > 0) {
+   /* Disable LFB */
+   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
+   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FF);
+
+   /* Enable AGP */
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, adev->gmc.zfb_phys_addr 
>> 24);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.vram_end >> 24);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.vram_start >> 
24);
+   } else {
+   /* Disable AGP. */
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0x);
+   }
 
/* Program the system aperture low logical page number. */
WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index bd3777a..ef79d49 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -82,10 +82,21 @@ static void mmhub_v1_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
uint64_t value;
uint32_t tmp;
 
-   /* Disable AGP. */
-   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
-   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
-   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FF);
+   if (adev->gmc.zfb_size > 0) {
+   /* Disable LFB */
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 0);
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FF);
+
+   /* Enable AGP */
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 
adev->gmc.zfb_phys_addr >> 24);
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.vram_end >> 
24);
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.vram_start >> 
24);
+   } else {
+   /* Disable AGP. */
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
+   WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FF);
+   }
 
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-- 
2.7.4

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[PATCH 8/8] drm/amdgpu: program system bit for pte/pde when ZFB is enabled

[Feifei Xu]

Change-Id: I9e4babf1e91855fb66e65cf2f82db64a1cd6fc97
Signed-off-by: Hawking Zhang 
Signed-off-by: Feifei Xu 
Acked-by: John Bridgman 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 6 ++
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 3689f1d..6b172ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -44,6 +44,8 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct 
amdgpu_device *adev)
+ adev->vm_manager.vram_base_offset;
value &= 0xF000ULL;
value |= 0x1; /*valid bit*/
+   if (adev->gmc.zfb_size > 0)
+   value |= 0x2; /*system bit*/
 
WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 lower_32_bits(value));
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 94e13c8..f3b6a5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -480,6 +480,9 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct 
amdgpu_device *adev,
if (flags & AMDGPU_VM_PAGE_WRITEABLE)
pte_flag |= AMDGPU_PTE_WRITEABLE;
 
+   if (adev->gmc.zfb_size > 0)
+   pte_flag |= AMDGPU_PTE_SYSTEM;
+
switch (flags & AMDGPU_VM_MTYPE_MASK) {
case AMDGPU_VM_MTYPE_DEFAULT:
pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
@@ -515,6 +518,9 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, 
int level,
adev->gmc.vram_start;
BUG_ON(*addr & 0x003FULL);
 
+   if (adev->gmc.zfb_size > 0)
+   *flags |= AMDGPU_PTE_SYSTEM;
+
if (!adev->gmc.translate_further)
return;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index ef79d49..471a59b 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -54,6 +54,8 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device 
*adev)
adev->vm_manager.vram_base_offset;
value &= 0xF000ULL;
value |= 0x1; /* valid bit */
+   if (adev->gmc.zfb_size > 0)
+   value |= 0x2; /* system bit*/
 
WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 lower_32_bits(value));
-- 
2.7.4

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