Re: [PATCH] drm/amd/powerplay: expose vega20 OD features

[Quan, Evan]

Hi @Deucher, Alexander & @Zhu, 
Rex,


I can remove the od setings for power limit and fan speed related since they 
seem redundant with other sysfs apis.

But for the clock/voltage related, i can not see how to reuse old 
pp_od_clk_voltage APIs.


For the old pp_od_clk_voltage APIs,

 1. they output/input the voltages in their exact values. E.g. "s 1 500 820" 
will update sclk level 1 to be 500 MHz at 820 mV

 But for vega20, we did not know its original voltage value. The 
output/input for voltage are just offest from its original value.

 So, if  to reuse these APIs, we will make them have two different 
explanations(

 on vega20 or later, the voltage is offset. On previous ASICs, the voltage 
is exact value). I think that will confuse the users.


 2. they support voltage set for each level. But for vega20, it supports only 
three pairs of clock/voltage set. And per suggestion,

 these three pairs should be: voltage offset of minimum clock level, 
voltage offset for middle clock level  and voltage offset

 for maximum clock level.


Also, i believe the future ASICs will also take the vega20 OD ways(that is we 
need the offset, not the exact value for voltage).


So, based on previous considerations, i decide to have new APIs instead of 
reusing existing ones.


Regards,

Evan


From: Zhu, Rex
Sent: Saturday, August 25, 2018 12:32 AM
To: Alex Deucher; Quan, Evan
Cc: amd-gfx list; Xu, Feifei; Kuehling, Felix; Deucher, Alexander; Zhang, 
Hawking
Subject: RE: [PATCH] drm/amd/powerplay: expose vega20 OD features



> -Original Message-
> From: Alex Deucher 
> Sent: Friday, August 24, 2018 11:48 PM
> To: Quan, Evan 
> Cc: amd-gfx list ; Xu, Feifei
> ; Kuehling, Felix ; Deucher,
> Alexander ; Zhu, Rex ;
> Zhang, Hawking 
> Subject: Re: [PATCH] drm/amd/powerplay: expose vega20 OD features
>
> On Fri, Aug 24, 2018 at 3:45 AM Evan Quan  wrote:
> >
> > Vega20 simplifies the OD logics and it can not fit old OD interfaces.
> > Thus we design new OD interfaces for vega20.
>
> Please split this into two patches, one to add the internal od8_settings API,
> and one to wire it up to sysfs.  A few more comments below.
>
> >
> > Change-Id: I888faec46a81287ae24f452ce16b42c1f6d06d7d
> > Signed-off-by: Evan Quan 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h   |   8 +
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 125 
> >  .../gpu/drm/amd/include/kgd_pp_interface.h|   2 +
> >  drivers/gpu/drm/amd/powerplay/amd_powerplay.c |  37 
> >  .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 191
> +-
> >  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   2 +
> >  6 files changed, 362 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> > index ff24e1cc5b65..84b3e6f87abf 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> > @@ -357,6 +357,14 @@ enum amdgpu_pcie_gen {
> > ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
> > (adev)->powerplay.pp_handle, type, parameter,
> > size))
> >
> > +#define amdgpu_dpm_get_od8_settings(adev, buf) \
> > +   ((adev)->powerplay.pp_funcs->get_od8_settings(\
> > +   (adev)->powerplay.pp_handle, buf))
> > +
> > +#define amdgpu_dpm_set_od8_settings(adev, parameter, size) \
> > +   ((adev)->powerplay.pp_funcs->set_od8_settings(\
> > +   (adev)->powerplay.pp_handle, parameter, size))
> > +
> >  struct amdgpu_dpm {
> > struct amdgpu_ps*ps;
> > /* number of valid power states */ diff --git
> > a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > index daa55fb06171..94cd7c503372 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > @@ -934,6 +934,121 @@ static ssize_t amdgpu_get_busy_percent(struct
> device *dev,
> > return snprintf(buf, PAGE_SIZE, "%d\n", value);  }
> >
> > +/**
> > + * DOC: pp_od8_settings
> > + *
> > + * The amdgpu driver provides a sysfs API for adjusting the clocks,
> > +voltages,
> > + * power limit, fan speed and temperature. The pp_od8_settings is
> > +used for
> > + * this.
> > + *
> > + * Reading the file will display:
> > + *
> > + * - a name list of the features that are able to be adjusted
> > + *
> > + * - the mininum and maximum allowed value for each supported
> > + *   feature labeled in format of "[mininum - maximum]"
> > + *
> > + * - the current value for each supported feature labeled after
> > + *   ":"
> > + *
> > + * To manually adjust these settings:
> > + *
> > + * - write a string that contains the new value for each supported
> > + *   feature. For those which do not need to be changed, just enter
> > + *   their old value
> > + *
> 

Re: [PATCH 1/2] drm/amdgpu: amdgpu_ctx_add_fence can't fail

[Zhang, Jerry (Junwei)]

On 08/24/2018 08:50 PM, Christian König wrote:

No more waiting for a fence done here.

Signed-off-by: Christian König 

Reviewed-by: Junwei Zhang 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 10 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c |  8 +++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h |  6 +++---
  3 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index fd3902983195..80ad23061f1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1217,15 +1217,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
job->owner = p->filp;
p->fence = dma_fence_get(>base.s_fence->finished);

-   r = amdgpu_ctx_add_fence(p->ctx, entity, p->fence, );
-   if (r) {
-   dma_fence_put(p->fence);
-   dma_fence_put(>base.s_fence->finished);
-   amdgpu_job_free(job);
-   amdgpu_mn_unlock(p->mn);
-   return r;
-   }
-
+   amdgpu_ctx_add_fence(p->ctx, entity, p->fence, );
amdgpu_cs_post_dependencies(p);

if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 987b7f256463..f9b54236102d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -434,9 +434,9 @@ int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
return 0;
  }

-int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
-struct drm_sched_entity *entity,
-struct dma_fence *fence, uint64_t* handle)
+void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
+ struct drm_sched_entity *entity,
+ struct dma_fence *fence, uint64_t* handle)
  {
struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity);
uint64_t seq = centity->sequence;
@@ -458,8 +458,6 @@ int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
dma_fence_put(other);
if (handle)
*handle = seq;
-
-   return 0;
  }

  struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index d67c1d285a4f..b3b012c0a7da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -65,9 +65,9 @@ int amdgpu_ctx_put(struct amdgpu_ctx *ctx);

  int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
  u32 ring, struct drm_sched_entity **entity);
-int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
-struct drm_sched_entity *entity,
-struct dma_fence *fence, uint64_t *seq);
+void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
+ struct drm_sched_entity *entity,
+ struct dma_fence *fence, uint64_t *seq);
  struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
   struct drm_sched_entity *entity,
   uint64_t seq);


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Re: [PATCH 4/5] drm/amdgpu: add amdgpu_gmc_get_pde_for_bo helper

[Zhang, Jerry (Junwei)]

On 08/24/2018 10:20 PM, Christian König wrote:

Helper to get the PDE for a PD/PT.

Signed-off-by: Christian König 

Reviewed-by: Junwei Zhang 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 37 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  2 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |  1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  |  4 +--
  5 files changed, 57 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 36058feac64f..6f79ce108728 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -26,6 +26,38 @@

  #include "amdgpu.h"

+/**
+ * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
+ *
+ * @bo: the BO to get the PDE for
+ * @level: the level in the PD hirarchy
+ * @addr: resulting addr
+ * @flags: resulting flags
+ *
+ * Get the address and flags to be used for a PDE.
+ */
+void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
+  uint64_t *addr, uint64_t *flags)
+{
+   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   struct ttm_dma_tt *ttm;
+
+   switch (bo->tbo.mem.mem_type) {
+   case TTM_PL_TT:
+   ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
+   *addr = ttm->dma_address[0];
+   break;
+   case TTM_PL_VRAM:
+   *addr = amdgpu_bo_gpu_offset(bo);
+   break;
+   default:
+   *addr = 0;
+   break;
+   }
+   *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, >tbo.mem);
+   amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
+}
+
  /**
   * amdgpu_gmc_pd_addr - return the address of the root directory
   *
@@ -35,13 +67,14 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
uint64_t pd_addr;

-   pd_addr = amdgpu_bo_gpu_offset(bo);
/* TODO: move that into ASIC specific code */
if (adev->asic_type >= CHIP_VEGA10) {
uint64_t flags = AMDGPU_PTE_VALID;

-   amdgpu_gmc_get_vm_pde(adev, -1, _addr, );
+   amdgpu_gmc_get_pde_for_bo(bo, -1, _addr, );
pd_addr |= flags;
+   } else {
+   pd_addr = amdgpu_bo_gpu_offset(bo);
}
return pd_addr;
  }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 7c469cce0498..0d2c9f65ca13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -131,6 +131,8 @@ static inline bool amdgpu_gmc_vram_full_visible(struct 
amdgpu_gmc *gmc)
return (gmc->real_vram_size == gmc->visible_vram_size);
  }

+void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
+  uint64_t *addr, uint64_t *flags);
  uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);

  #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index eb08a03b82a0..72366643e3c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1428,13 +1428,14 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
  }

  /**
- * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
+ * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
   *
   * @ttm: The ttm_tt object to compute the flags for
   * @mem: The memory registry backing this ttm_tt object
+ *
+ * Figure out the flags to use for a VM PDE.
   */
-uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt 
*ttm,
-struct ttm_mem_reg *mem)
+uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
  {
uint64_t flags = 0;

@@ -1448,6 +1449,20 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device 
*adev, struct ttm_tt *ttm,
flags |= AMDGPU_PTE_SNOOPED;
}

+   return flags;
+}
+
+/**
+ * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
+ *
+ * @ttm: The ttm_tt object to compute the flags for
+ * @mem: The memory registry backing this ttm_tt object
+ */
+uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt 
*ttm,
+struct ttm_mem_reg *mem)
+{
+   uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
+
flags |= adev->gart.gart_pte_flags;
flags |= AMDGPU_PTE_READABLE;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 8b3cc6687769..fe8f276e9811 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -116,6 +116,7 @@ bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
   int *last_invalidated);
  bool 

Re: [PATCH 3/5] drm/amdgpu: add GMC9 support for PDs/PTs in system memory

[Zhang, Jerry (Junwei)]

On 08/25/2018 12:09 AM, Alex Deucher wrote:

On Fri, Aug 24, 2018 at 10:21 AM Christian König
 wrote:


Add the necessary handling.

Signed-off-by: Christian König 


Reviewed-by: Alex Deucher 


Reviewed-by: Junwei Zhang 




---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a82b3eb429e8..453bd7ea50e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -560,7 +560,7 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct 
amdgpu_device *adev,
  static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 uint64_t *addr, uint64_t *flags)
  {
-   if (!(*flags & AMDGPU_PDE_PTE))
+   if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 *addr = adev->vm_manager.vram_base_offset + *addr -
 adev->gmc.vram_start;
 BUG_ON(*addr & 0x003FULL);
--
2.17.1

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Re: [PATCH 1/5] drm/amdgpu: remove extra root PD alignment

[Zhang, Jerry (Junwei)]

On 08/25/2018 12:09 AM, Alex Deucher wrote:

On Fri, Aug 24, 2018 at 10:20 AM Christian König
 wrote:


Just another leftover from radeon.

Signed-off-by: Christian König 


Reviewed-by: Alex Deucher 


Reviewed-by: Junwei Zhang 




---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ---
  2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a6b1126c61fd..53ce9982a5ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2566,8 +2566,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
  {
 struct amdgpu_bo_param bp;
 struct amdgpu_bo *root;
-   const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
-   AMDGPU_VM_PTE_COUNT(adev) * 8);
 unsigned long size;
 uint64_t flags;
 int r, i;
@@ -2615,7 +2613,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
 size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
 memset(, 0, sizeof(bp));
 bp.size = size;
-   bp.byte_align = align;
+   bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
 bp.flags = flags;
 bp.type = ttm_bo_type_kernel;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 1162c2bf3138..1c9049feaaea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -48,9 +48,6 @@ struct amdgpu_bo_list_entry;
  /* number of entries in page table */
  #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)

-/* PTBs (Page Table Blocks) need to be aligned to 32K */
-#define AMDGPU_VM_PTB_ALIGN_SIZE   32768
-
  #define AMDGPU_PTE_VALID   (1ULL << 0)
  #define AMDGPU_PTE_SYSTEM  (1ULL << 1)
  #define AMDGPU_PTE_SNOOPED (1ULL << 2)
--
2.17.1

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System freezes on Shutdown [amdgpu] [drm]

[John Smith]

Common shutdown seems to be ok. After any suspend (pressing stand-by button or 
close lit), I am not able to shutdown successful. The system hangs on shutdown.

First some hw-info, then the bad error log. Please let me know, if you need 
further infos.

Best, john.

> inxi -Fx
System:Host: bang Kernel: 4.18.0-ARCH+ x86_64 bits: 64 compiler: gcc v: 
8.2.0 Desktop: Gnome 3.28.3 
   Distro: Arch Linux 
Machine:   Type: Laptop System: HP product: HP ZBook 15u G5 v: N/A serial: N/A 
   Mobo: HP model: 83B2 v: KBC Version 04.45.00 serial: N/A UEFI: HP v: 
Q78 Ver. 01.00.05 
   date: 01/25/2018 
Battery:   ID-1: BAT0 charge: 46.3 Wh condition: 53.9/53.9 Wh (100%) model: 
Hewlett-Packard Primary 
   status: Discharging 
CPU:   Topology: Quad Core model: Intel Core i7-8550U bits: 64 type: MT MCP 
arch: Kaby Lake rev: 10 
   L2 cache: 8192 KiB 
   flags: lm nx pae sse sse2 sse3 sse4_1 sse4_2 ssse3 vmx bogomips: 
31880 
   Speed: 800 MHz min/max: 400/4000 MHz Core speeds (MHz): 1: 800 2: 
800 3: 800 4: 800 5: 800 6: 800 
   7: 800 8: 800 
Graphics:  Card-1: Intel UHD Graphics 620 driver: i915 v: kernel bus ID: 
00:02.0 
   Card-2: Advanced Micro Devices [AMD/ATI] Lexa XT [Radeon PRO WX 
3100] driver: amdgpu v: kernel 
   bus ID: 01:00.0 
   Display: wayland server: X.Org 1.20.1 driver: amdgpu resolution: 
1920x1080~60Hz 
   OpenGL: renderer: Mesa DRI Intel UHD Graphics 620 (Kabylake GT2) v: 
4.5 Mesa 18.1.6 
   direct render: Yes 
Audio: Card-1: Intel Sunrise Point-LP HD Audio driver: snd_hda_intel v: 
kernel bus ID: 00:1f.3 
   Sound Server: ALSA v: k4.18.0-ARCH+ 
Network:   Card-1: Intel Ethernet Connection I219-V driver: e1000e v: 3.2.6-k 
port: N/A bus ID: 00:1f.6 
   IF: enp0s31f6 state: down mac: b4:b6:86:1c:73:17 
   Card-2: Intel Wireless 8265 / 8275 driver: iwlwifi v: kernel bus ID: 
02:00.0 
   IF: wlp2s0 state: up mac: 00:1c:bf:fe:24:0f 
Drives:HDD Total Size: 476.94 GiB used: 41.80 GiB (8.8%) 
   ID-1: /dev/nvme0n1 model: KXG50ZNV512G_TOSHIBA size: 476.94 GiB 
Partition: ID-1: / size: 48.97 GiB used: 17.92 GiB (36.6%) fs: ext4 dev: 
/dev/nvme0n1p3 
   ID-2: /boot size: 2.00 GiB used: 130.6 MiB (6.4%) fs: vfat dev: 
/dev/nvme0n1p1 
   ID-3: /home size: 415.30 GiB used: 23.75 GiB (5.7%) fs: ext4 dev: 
/dev/nvme0n1p4 
   ID-4: swap-1 size: 2.00 GiB used: 0 KiB (0.0%) fs: swap dev: 
/dev/nvme0n1p2 
Sensors:   System Temperatures: cpu: 42.0 C mobo: N/A gpu: amdgpu temp: 37 C 
   Fan Speeds (RPM): N/A 
Info:  Processes: 259 Uptime: 15m Memory: 15.52 GiB used: 1.95 GiB (12.6%) 
Init: systemd Compilers: 
   gcc: 8.2.0 clang: 6.0.1 Shell: bash v: 4.4.23 inxi: 3.0.07 


> uname -a
Linux bang 4.18.0-ARCH+ #1 SMP PREEMPT Fri Aug 24 18:37:45 CEST 2018 x86_64 
GNU/Linux

> dmesg | grep amdgpu
[4.110050] [drm] amdgpu kernel modesetting enabled.
[4.125300] amdgpu :01:00.0: enabling device (0006 -> 0007)
[4.125687] amdgpu :01:00.0: kfd not supported on this ASIC
[4.155751] amdgpu :01:00.0: BAR 2: releasing [mem 0xd000-0xd01f 
64bit pref]
[4.155752] amdgpu :01:00.0: BAR 0: releasing [mem 0xc000-0xcfff 
64bit pref]
[4.155762] amdgpu :01:00.0: BAR 0: assigned [mem 0xc000-0xcfff 
64bit pref]
[4.155771] amdgpu :01:00.0: BAR 2: assigned [mem 0xd000-0xd01f 
64bit pref]
[4.155807] amdgpu :01:00.0: VRAM: 2048M 0x00F4 - 
0x00F47FFF (2048M used)
[4.155808] amdgpu :01:00.0: GART: 256M 0x - 
0x0FFF
[4.155925] [drm] amdgpu: 2048M of VRAM memory ready
[4.155926] [drm] amdgpu: 3072M of GTT memory ready.
[4.223253] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[4.224590] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[4.225873] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[4.226831] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[4.227538] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[4.228249] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[4.228950] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[4.249592] amdgpu: [powerplay] Failed to retrieve minimum clocks.
[4.249593] amdgpu: [powerplay] Error in phm_get_clock_info 
[4.249714] [drm:dc_create [amdgpu]] *ERROR* DC: Number of connectors is 
zero!
[4.405530] [drm] Initialized amdgpu 3.27.0 20150101 for :01:00.0 on 
minor 1
[   17.997201] amdgpu :01:00.0: GPU pci config reset

> dmesg | grep drm
[1.843759] fb: switching to inteldrmfb from EFI VGA
[1.843925] [drm] Replacing VGA console driver
[1.845633] [drm] Supports vblank timestamp