RE: [PATCH] drm/amdkfd: fix a minor typo on user queue init

[Huang, Ray]

Sorry, please ignore this patch. Just misunderstood before.

Thanks,
Ray

-Original Message-
From: Huang, Ray  
Sent: Wednesday, December 4, 2019 3:22 PM
To: amd-gfx@lists.freedesktop.org; Kuehling, Felix ; 
Zhao, Yong 
Cc: Deucher, Alexander ; Huang, Ray 

Subject: [PATCH] drm/amdkfd: fix a minor typo on user queue init

Fix PQM -> DQM.

Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index d3eacf7..b7db622 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -183,7 +183,7 @@ static int init_user_queue(struct process_queue_manager 
*pqm,
(*q)->device = dev;
(*q)->process = pqm->process;
 
-   pr_debug("PQM After init queue");
+   pr_debug("DQM After init queue");
 
return retval;
 }
-- 
2.7.4

___
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[PATCH] drm/amdkfd: fix a minor typo on user queue init

[Huang Rui]

Fix PQM -> DQM.

Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index d3eacf7..b7db622 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -183,7 +183,7 @@ static int init_user_queue(struct process_queue_manager 
*pqm,
(*q)->device = dev;
(*q)->process = pqm->process;
 
-   pr_debug("PQM After init queue");
+   pr_debug("DQM After init queue");
 
return retval;
 }
-- 
2.7.4

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RE: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for XGMI

[Ma, Le]

[AMD Official Use Only - Internal Distribution Only]


From: Grodzovsky, Andrey 
Sent: Wednesday, December 4, 2019 2:44 AM
To: Ma, Le ; amd-gfx@lists.freedesktop.org; Zhou1, Tao 
; Deucher, Alexander ; Li, Dennis 
; Zhang, Hawking 
Cc: Chen, Guchun 
Subject: Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for 
XGMI


Thanks Ma, this was very helpful as I am sill not able to setup XGMI hive with 
latest FW and VBIOS.

I traced the workqueue subsystem (full log attached). Specifically here is the 
life cycle of our 2 work items executing amdgpu_device_xgmi_reset_func bellow

[Le]: Thanks Andrey for the deep debug. Your feedback gave me a more profound 
understanding on this case. My comments split as below.

You were right to note they both run on came CPU (32) but they are executed by 
different threads. Also as you see by workqueue_execute_start/end timestamps 
they actually ran in parallel and not one after another even while being 
assigned to the same CPU and that because of thread preemption (there is at 
least psp_v11_0_mode1_reset->msleep(500)) which yields the CPU and hence allows 
the second work to run + I am sure that on preemptive kernel one reset work 
would be preempted at some point anyway  and let the other run.

[Le]: Yes, from the trace log, the xgmi_reset_func items are assigned to 
different work threads bound to one same CPU. And you are right that cpu 
preemption will happen when msleep called which yield the CPU to allow second 
work to run. That’s a great founding. But it’s not a real parallel run to me 
because second work can only preempt to run when first work go to sleep. I made 
an experiment here to change this unique msleep to udelay, then second work 
item will run after first item finished in a serial execuation.

Now you had issues with BACO reset while the test I ran on your system is mode1 
reset and so I assumed that maybe BACO has some non preempt-able busy wait 
which doesn't give a chance to second work item's thread to run on that CPU 
before the first finished - but from looking in the code I see 
smu_v11_0_baco_enter->msleep(10) so even in that case the first reset work item 
was supposed to yield CPU after BACO ENTER sent to SMU and let the other reset 
work do the same to the second card and so i don't see how even in this case 
there is a serial execution ?

[Le]: VG20 uses old powerplay framework (smu_v11_0_baco_enter->msleep(10) in 
swSMU framework), so no msleep and no CPU preemption. BACO reset has Enter/Exit 
2 phases. We expect all the XGMI nodes enter BACO simultaneously instead of one 
after one as a serial execution, then exit BACO simultaneously.

P.S How you solution solves the case where the XGMI hive is bigger then number 
of CPUs on the system ? Assuming that what you say is correct and there is a 
serial execution when on the same CPU, if they hive is bigger then number of 
CPUs you will eventually get back to sending reset work to a CPU already 
executing BACO ENTER (or EXIT) for another device and will get the 
serialization problem anyway.

[Le]: Yeah, I also considered the situation that XGMI hive bigger than CPU NR. 
I think it’s an extreme situation and should not exist. However, assuming it 
exists, many work items scatter in several CPUs will be executed faster than 
bound to one same CPU, isn’t it ?

 cat-3002  [032] d... 33153.791829: workqueue_queue_work: work 
struct=e43c1ebb function=amdgpu_device_xgmi_reset_func [amdgpu] 
workqueue=80331d91 req_cpu=8192 cpu=32
 cat-3002  [032] d... 33153.791829: workqueue_activate_work: work 
struct e43c1ebb
 cat-3002  [032] dN.. 33153.791831: workqueue_queue_work: work 
struct=e67113aa function=amdgpu_device_xgmi_reset_func [amdgpu] 
workqueue=80331d91 req_cpu=8192 cpu=32
 cat-3002  [032] dN.. 33153.791832: workqueue_activate_work: work 
struct e67113aa
   kworker/32:1H-551   [032]  33153.791834: workqueue_execute_start: work 
struct e43c1ebb: function amdgpu_device_xgmi_reset_func [amdgpu]
   kworker/32:0H-175   [032]  33153.792087: workqueue_execute_start: work 
struct e67113aa: function amdgpu_device_xgmi_reset_func [amdgpu]
   kworker/32:1H-551   [032]  33154.310948: workqueue_execute_end: work 
struct e43c1ebb
   kworker/32:0H-175   [032]  33154.311043: workqueue_execute_end: work 
struct e67113aa

Andrey




On 12/3/19 5:06 AM, Ma, Le wrote:

[AMD Official Use Only - Internal Distribution Only]

Hi Andrey,

You can try the XGMI system below:
  IP: 10.67.69.53
  U/P: jenkins/0

The original drm-next kernel is installed.

Regards,
Ma Le

From: Grodzovsky, Andrey 

Sent: Tuesday, December 3, 2019 6:05 AM
To: Ma, Le ; 
amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun ; Zhou1, Tao 

RE: [PATCH] drm/amdgpu/gfx: Improvement on EDC GPR workarounds

[Zhang, Hawking]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Zhu, James  
Sent: 2019年12月4日 4:45
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James ; Zhang, Hawking 
Subject: [PATCH] drm/amdgpu/gfx: Improvement on EDC GPR workarounds

SPI limits total CS waves in flight per SE to no more than 32 * num_cu and we 
need to stuff 40 waves on a CU to completely clean the SGPR. This is 
accomplished in the WR by cleaning the SE in two steps, half of the CU per step.

Signed-off-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 83 ++-
 1 file changed, 63 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6a251a3..147c08f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3938,24 +3938,37 @@ static const struct soc15_reg_entry vgpr_init_regs[] = {
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x },
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x },
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x100 }, /* 
CU_GROUP_COUNT=1 */
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x000 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x17f }, /* VGPRS=15 
(256 logical VGPRs, SGPRS=1 (16 SGPRs, BULKY=1 */
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f },
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x40 },  /* 64KB LDS */  
};
 
-static const struct soc15_reg_entry sgpr_init_regs[] = {
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x100 }, /* 
CU_GROUP_COUNT=1 */
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
+static const struct soc15_reg_entry sgpr1_init_regs[] = {
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x000 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, };
+
+static const struct soc15_reg_entry sgpr2_init_regs[] = {
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x000 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x340 }, /* SGPRS=13 (112 
GPRS) */
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) 
+ */
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },  };
 
@@ -4065,7 +4078,9 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct 
amdgpu_device *adev)
total_size =
((ARRAY_SIZE(vgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
total_size +=
-   ((ARRAY_SIZE(sgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
+   ((ARRAY_SIZE(sgpr1_init_regs) * 3) + 4 + 5 + 2) * 4;
+   total_size +=
+   ((ARRAY_SIZE(sgpr2_init_regs) * 3) + 4 + 5 + 2) * 4;
total_size = ALIGN(total_size, 256);
vgpr_offset = total_size;
total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256); @@ -4108,7 
+4123,35 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device 
*adev)
 
/* write dispatch packet */
ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
-   ib.ptr[ib.length_dw++] = 256; /* x */
+   ib.ptr[ib.length_dw++] = 0x40*2; /* x */
+   

Re: [PATCH v8 16/17] drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs

[kbuild test robot]

Hi,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20191203]
[cannot apply to drm-intel/for-linux-next linus/master v5.4-rc8 v5.4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:
https://github.com/0day-ci/linux/commits/mikita-lipski-amd-com/DSC-MST-support-for-DRM-and-AMDGPU/20191204-020604
base:1ab75b2e415a29dba9aec94f203c6f88dbfc0ba0
reproduce: make htmldocs

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot 

All warnings (new ones prefixed by >>):

   fs/posix_acl.c:647: warning: Function parameter or member 'mode_p' not 
described in 'posix_acl_update_mode'
   fs/posix_acl.c:647: warning: Function parameter or member 'acl' not 
described in 'posix_acl_update_mode'
   include/linux/regulator/machine.h:196: warning: Function parameter or member 
'max_uV_step' not described in 'regulation_constraints'
   include/linux/regulator/driver.h:223: warning: Function parameter or member 
'resume' not described in 'regulator_ops'
   sound/soc/soc-core.c:2509: warning: Function parameter or member 
'legacy_dai_naming' not described in 'snd_soc_register_dai'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'dev_scratch' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 'list' not 
described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'ip_defrag_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'skb_mstamp_ns' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'__cloned_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'head_frag' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'__pkt_type_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'encapsulation' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'encap_hdr_csum' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'csum_valid' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'__pkt_vlan_present_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'vlan_present' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'csum_complete_sw' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'csum_level' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'inner_protocol_type' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'remcsum_offload' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'sender_cpu' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'reserved_tailroom' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'inner_ipproto' not described in 'sk_buff'
   include/net/sock.h:232: warning: Function parameter or member 'skc_addrpair' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_portpair' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_ipv6only' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 
'skc_net_refcnt' not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_v6_daddr' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 
'skc_v6_rcv_saddr' not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_cookie' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_listener' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_tw_dr' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_rcv_wnd' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 
'skc_tw_rcv_nxt' not described in 'sock_common'
   include/net/sock.h:514: warning: Function parameter or member 
'sk_rx_skb_cache' not described in 'sock'
   include/net/sock.h:514: warning: Function parameter or member 'sk_wq_raw' 
not described in 'sock'
   include/net/sock.h:514: warning: Fu

Re: [PATCH v8 11/17] drm/dp_mst: Add DSC enablement helpers to DRM

[kbuild test robot]

Hi,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20191203]
[cannot apply to drm-intel/for-linux-next linus/master v5.4-rc8 v5.4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:
https://github.com/0day-ci/linux/commits/mikita-lipski-amd-com/DSC-MST-support-for-DRM-and-AMDGPU/20191204-020604
base:1ab75b2e415a29dba9aec94f203c6f88dbfc0ba0
reproduce: make htmldocs

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot 

All warnings (new ones prefixed by >>):

   drivers/usb/typec/class.c:1: warning: 'typec_altmode_register_notifier' not 
found
   fs/posix_acl.c:647: warning: Function parameter or member 'inode' not 
described in 'posix_acl_update_mode'
   fs/posix_acl.c:647: warning: Function parameter or member 'mode_p' not 
described in 'posix_acl_update_mode'
   fs/posix_acl.c:647: warning: Function parameter or member 'acl' not 
described in 'posix_acl_update_mode'
   include/linux/regulator/machine.h:196: warning: Function parameter or member 
'max_uV_step' not described in 'regulation_constraints'
   include/linux/regulator/driver.h:223: warning: Function parameter or member 
'resume' not described in 'regulator_ops'
   sound/soc/soc-core.c:2509: warning: Function parameter or member 
'legacy_dai_naming' not described in 'snd_soc_register_dai'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'dev_scratch' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 'list' not 
described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'ip_defrag_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'skb_mstamp_ns' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'__cloned_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'head_frag' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'__pkt_type_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'encapsulation' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'encap_hdr_csum' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'csum_valid' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'__pkt_vlan_present_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'vlan_present' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'csum_complete_sw' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'csum_level' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'inner_protocol_type' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'remcsum_offload' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'sender_cpu' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'reserved_tailroom' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'inner_ipproto' not described in 'sk_buff'
   include/net/sock.h:232: warning: Function parameter or member 'skc_addrpair' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_portpair' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_ipv6only' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 
'skc_net_refcnt' not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_v6_daddr' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 
'skc_v6_rcv_saddr' not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_cookie' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_listener' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_tw_dr' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_rcv_wnd' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 
'skc_tw_rcv_nxt' not described in 'sock_common'
   include/net/sock.h:514: warning: Function parameter or 

Re: [PATCH] drm/amdgpu/gfx: Improvement on EDC GPR workarounds

[Yong Zhao]

Not sure whether we should add the issue ticket info here.


Reviewed-by: Yong Zhao 



On 2019-12-03 3:45 p.m., James Zhu wrote:

SPI limits total CS waves in flight per SE to no more than 32 * num_cu and
we need to stuff 40 waves on a CU to completely clean the SGPR. This is
accomplished in the WR by cleaning the SE in two steps, half of the CU per
step.

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 83 ++-
  1 file changed, 63 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6a251a3..147c08f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3938,24 +3938,37 @@ static const struct soc15_reg_entry vgpr_init_regs[] = {
 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x },
 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x },
 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x100 }, /* 
CU_GROUP_COUNT=1 */
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x000 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x17f }, /* VGPRS=15 
(256 logical VGPRs, SGPRS=1 (16 SGPRs, BULKY=1 */
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f },
 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x40 },  /* 64KB LDS */
  };
  
-static const struct soc15_reg_entry sgpr_init_regs[] = {

-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x100 }, /* 
CU_GROUP_COUNT=1 */
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
+static const struct soc15_reg_entry sgpr1_init_regs[] = {
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x000 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
+};
+
+static const struct soc15_reg_entry sgpr2_init_regs[] = {
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x000 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x340 }, /* SGPRS=13 (112 
GPRS) */
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
  };
  
@@ -4065,7 +4078,9 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)

total_size =
((ARRAY_SIZE(vgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
total_size +=
-   ((ARRAY_SIZE(sgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
+   ((ARRAY_SIZE(sgpr1_init_regs) * 3) + 4 + 5 + 2) * 4;
+   total_size +=
+   ((ARRAY_SIZE(sgpr2_init_regs) * 3) + 4 + 5 + 2) * 4;
total_size = ALIGN(total_size, 256);
vgpr_offset = total_size;
total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
@@ -4108,7 +4123,35 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct 
amdgpu_device *adev)
  
  	/* write dispatch packet */

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
-   ib.ptr[ib.length_dw++] = 256; /* x */
+   ib.ptr[ib.length_dw++] = 0x40*2; /* x */
+   ib.ptr[ib.length_dw++] = 1; /* y */
+   ib.ptr[ib.length_dw++] = 1; /* z */
+   ib.ptr[ib.length_dw++] =
+

Re: [PATCH v8 02/17] drm/dp_mst: Parse FEC capability on MST ports

[kbuild test robot]

Hi,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20191203]
[cannot apply to drm-intel/for-linux-next linus/master v5.4-rc8 v5.4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:
https://github.com/0day-ci/linux/commits/mikita-lipski-amd-com/DSC-MST-support-for-DRM-and-AMDGPU/20191204-020604
base:1ab75b2e415a29dba9aec94f203c6f88dbfc0ba0
reproduce: make htmldocs

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot 

All warnings (new ones prefixed by >>):

   drivers/usb/typec/bus.c:1: warning: 'typec_altmode_unregister_driver' not 
found
   drivers/usb/typec/bus.c:1: warning: 'typec_altmode_register_driver' not found
   drivers/usb/typec/class.c:1: warning: 'typec_altmode_register_notifier' not 
found
   drivers/usb/typec/class.c:1: warning: 'typec_altmode_unregister_notifier' 
not found
   fs/posix_acl.c:647: warning: Function parameter or member 'inode' not 
described in 'posix_acl_update_mode'
   fs/posix_acl.c:647: warning: Function parameter or member 'mode_p' not 
described in 'posix_acl_update_mode'
   fs/posix_acl.c:647: warning: Function parameter or member 'acl' not 
described in 'posix_acl_update_mode'
   sound/soc/soc-core.c:2509: warning: Function parameter or member 
'legacy_dai_naming' not described in 'snd_soc_register_dai'
   include/linux/regulator/machine.h:196: warning: Function parameter or member 
'max_uV_step' not described in 'regulation_constraints'
   include/linux/regulator/driver.h:223: warning: Function parameter or member 
'resume' not described in 'regulator_ops'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'dev_scratch' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 'list' not 
described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'ip_defrag_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'skb_mstamp_ns' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'__cloned_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'head_frag' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'__pkt_type_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'encapsulation' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'encap_hdr_csum' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'csum_valid' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'__pkt_vlan_present_offset' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'vlan_present' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'csum_complete_sw' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'csum_level' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'inner_protocol_type' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'remcsum_offload' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'sender_cpu' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'reserved_tailroom' not described in 'sk_buff'
   include/linux/skbuff.h:888: warning: Function parameter or member 
'inner_ipproto' not described in 'sk_buff'
   include/net/sock.h:232: warning: Function parameter or member 'skc_addrpair' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_portpair' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_ipv6only' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 
'skc_net_refcnt' not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_v6_daddr' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 
'skc_v6_rcv_saddr' not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_cookie' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_listener' 
not described in 'sock_common'
   include/net/sock.h:232: warning: Function parameter or member 'skc_tw_dr' 
not described in 'sock_common'
   include/net/sock.h:232: w

RE: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[Deng, Emily]

[AMD Official Use Only - Internal Distribution Only]

Hi Andrey,
Thanks very much.

Best wishes
Emily Deng
From: Grodzovsky, Andrey 
Sent: Tuesday, December 3, 2019 12:33 PM
To: Deucher, Alexander ; Deng, Emily 

Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Koenig, 
Christian ; steven.pr...@arm.com
Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.


Turns out Steven's patch was already in so i just cherry-picked the change from 
drm-next-misc



Emily - it's in.



Andrey


On 12/3/19 2:59 PM, Deucher, Alexander wrote:

[AMD Official Use Only - Internal Distribution Only]

Cherry pick whatever dependencies you need or pick the older version of the 
patch.  Either way works.

Alex

From: Grodzovsky, Andrey 

Sent: Tuesday, December 3, 2019 2:57 PM
To: Deucher, Alexander 
; Deng, Emily 

Cc: dri-de...@lists.freedesktop.org 
; 
amd-gfx@lists.freedesktop.org 
; Koenig, 
Christian ; 
steven.pr...@arm.com 

Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.


I don't think i can apply this patch 'as is' as this has dependency on patch by 
Steven which also wasn't applied yet - 588b982 Steven Price6 weeks ago  
  drm: Don't free jobs in wait_event_interruptible()



Andrey


On 12/3/19 2:44 PM, Deucher, Alexander wrote:

[AMD Official Use Only - Internal Distribution Only]

Please go ahead an apply whatever version is necessary for amd-staging-drm-next.

Alex


From: Grodzovsky, Andrey 

Sent: Tuesday, December 3, 2019 2:10 PM
To: Deng, Emily ; Deucher, 
Alexander 
Cc: dri-de...@lists.freedesktop.org 
; 
amd-gfx@lists.freedesktop.org 
; Koenig, 
Christian ; 
steven.pr...@arm.com 

Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

Yes - Christian just pushed it to drm-next-misc - I guess Alex/Christian
didn't pull to amd-staging-drm-next yet.

Andrey

On 12/2/19 2:24 PM, Deng, Emily wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Andrey,
>  Seems this patch is still not in amd-staging-drm-next?
>
> Best wishes
> Emily Deng
>
>
>
>> -Original Message-
>> From: Deng, Emily
>> Sent: Tuesday, November 26, 2019 4:41 PM
>> To: Grodzovsky, Andrey 
>> 
>> Cc: dri-de...@lists.freedesktop.org; 
>> amd-gfx@lists.freedesktop.org; Koenig,
>> Christian ; 
>> steven.pr...@arm.com
>> Subject: RE: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>>
>> [AMD Official Use Only - Internal Distribution Only]
>>
>> Reviewed-by: Emily Deng 
>>
>>> -Original Message-
>>> From: Grodzovsky, Andrey 
>>> 
>>> Sent: Tuesday, November 26, 2019 7:37 AM
>>> Cc: 
>>> dri-de...@lists.freedesktop.org; 
>>> amd-gfx@lists.freedesktop.org;
>>> Koenig, Christian 
>>> ; Deng, Emily
>>> ; 
>>> steven.pr...@arm.com
>>> Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>>>
>>> Ping
>>>
>>> Andrey
>>>
>>> On 11/25/19 3:51 PM, Andrey Grodzovsky wrote:
 Problem:
 Due to a race between drm_sched_cleanup_jobs in sched thread and
 drm_sched_job_timedout in timeout work there is a possiblity that bad
 job was already freed while still being accessed from the timeout
 thread.

 Fix:
 Instead of just peeking at the bad job in the mirror list remove it
 from the list under lock and then put it back later when we are
 garanteed no race with main sched thread is possible which is after
 the thread is parked.

 v2: Lock around processing ring_mirror_list in drm_sched_cleanup_jobs.

 v3: Rebase on top of drm-misc-next. v2 is not needed anymore as
 drm_sched_get_cleanup_job already has a lock there.

 v4: Fix comments to relfect latest code in drm-misc.

 Signed-off-by: Andrey Grodzovsky 
 
 Reviewed-by: Christian König 
 

[PATCH] drm/amdgpu/gfx: Improvement on EDC GPR workarounds

[James Zhu]

SPI limits total CS waves in flight per SE to no more than 32 * num_cu and
we need to stuff 40 waves on a CU to completely clean the SGPR. This is
accomplished in the WR by cleaning the SE in two steps, half of the CU per
step.

Signed-off-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 83 ++-
 1 file changed, 63 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6a251a3..147c08f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3938,24 +3938,37 @@ static const struct soc15_reg_entry vgpr_init_regs[] = {
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x },
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x },
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x100 }, /* 
CU_GROUP_COUNT=1 */
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x000 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x17f }, /* VGPRS=15 
(256 logical VGPRs, SGPRS=1 (16 SGPRs, BULKY=1 */
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f },
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x40 },  /* 64KB LDS */
 };
 
-static const struct soc15_reg_entry sgpr_init_regs[] = {
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x100 }, /* 
CU_GROUP_COUNT=1 */
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
+static const struct soc15_reg_entry sgpr1_init_regs[] = {
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x00ff },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x000 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
+};
+
+static const struct soc15_reg_entry sgpr2_init_regs[] = {
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xff00 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x000 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x340 }, /* SGPRS=13 (112 
GPRS) */
+   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
 };
 
@@ -4065,7 +4078,9 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct 
amdgpu_device *adev)
total_size =
((ARRAY_SIZE(vgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
total_size +=
-   ((ARRAY_SIZE(sgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
+   ((ARRAY_SIZE(sgpr1_init_regs) * 3) + 4 + 5 + 2) * 4;
+   total_size +=
+   ((ARRAY_SIZE(sgpr2_init_regs) * 3) + 4 + 5 + 2) * 4;
total_size = ALIGN(total_size, 256);
vgpr_offset = total_size;
total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
@@ -4108,7 +4123,35 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct 
amdgpu_device *adev)
 
/* write dispatch packet */
ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
-   ib.ptr[ib.length_dw++] = 256; /* x */
+   ib.ptr[ib.length_dw++] = 0x40*2; /* x */
+   ib.ptr[ib.length_dw++] = 1; /* y */
+   ib.ptr[ib.length_dw++] = 1; /* z */
+   ib.ptr[ib.length_dw++] =
+   REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 
1);
+
+   /* write CS partial flush packet */
+   

[pull] amdgpu, amdkfd, radeon drm-next-5.5

[Alex Deucher]

Hi Dave, Daniel,

Fixes for 5.5.

The following changes since commit acc61b8929365e63a3e8c8c8913177795aa45594:

  Merge tag 'drm-next-5.5-2019-11-22' of 
git://people.freedesktop.org/~agd5f/linux into drm-next (2019-11-26 08:40:23 
+1000)

are available in the Git repository at:

  git://people.freedesktop.org/~agd5f/linux tags/drm-next-5.5-2019-12-03

for you to fetch changes up to 008037d4d972c9c47b273e40e52ae34f9d9e33e7:

  drm/radeon: fix r1xx/r2xx register checker for POT textures (2019-12-03 
15:06:11 -0500)


drm-next-5.5-2019-12-03:

amdgpu:
- Fix vram lost handling with BACO on VI/CI asics
- DC fixes for Navi14
- Misc gfx10 fixes
- SR-IOV fixes
- Fix driver unload
- Fix XGMI limits on Arcturus

amdkfd:
- Enable KFD on PPC
- Optimize KFD page table reservations

radeon:
- Fix register checker for r1xx/r2xx


Alex Deucher (5):
  drm/amd/display: add default clocks if not able to fetch them
  MAINTAINERS: Drop Rex Zhu for amdgpu powerplay
  drm/amdgpu: flag vram lost on baco reset for VI/CIK
  drm/amd/display: re-enable wait in pipelock, but add timeout
  drm/radeon: fix r1xx/r2xx register checker for POT textures

Felix Kuehling (1):
  drm/amdgpu: Optimize KFD page table reservation

John Clements (2):
  drm/amdgpu: Resolved offchip EEPROM I/O issue
  drm/amdgpu: Added ASIC specific checks in gfxhub V1.1 get XGMI info

Likun Gao (1):
  drm/amdgpu/powerplay: unify smu send message function

Monk Liu (6):
  drm/amdgpu: use CPU to flush vmhub if sched stopped
  drm/amdgpu: fix calltrace during kmd unload(v3)
  drm/amdgpu: skip rlc ucode loading for SRIOV gfx10
  drm/amdgpu: do autoload right after MEC loaded for SRIOV VF
  drm/amdgpu: should stop GFX ring in hw_fini
  drm/amdgpu: fix GFX10 missing CSIB set(v3)

Timothy Pearson (1):
  amdgpu: Enable KFD on POWER systems

Xiaojie Yuan (1):
  drm/amdgpu/gfx10: unlock srbm_mutex after queue programming finish

Zhan Liu (1):
  drm/amd/display: Include num_vmid and num_dsc within NV14's resource caps

Zhan liu (2):
  drm/amd/display: Adding NV14 IP Parameters
  drm/amd/display: Get NV14 specific ip params as needed

 MAINTAINERS|   1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c   |  15 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c|   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c |  17 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c|  10 +-
 drivers/gpu/drm/amd/amdgpu/cik.c   |   7 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 178 ++---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |  40 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  40 +
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c   |  19 ++-
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |   3 +-
 drivers/gpu/drm/amd/amdgpu/vi.c|   7 +-
 drivers/gpu/drm/amd/amdkfd/Kconfig |   2 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c   |   3 +-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c |  19 +++
 .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  |  74 +
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |   9 ++
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c   |   1 -
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |   4 +-
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h  |   5 +-
 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h  |   5 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c |   1 -
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c |   1 -
 drivers/gpu/drm/amd/powerplay/smu_internal.h   |   4 +-
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  |  29 +---
 drivers/gpu/drm/amd/powerplay/smu_v12_0.c  |  28 +---
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c |   1 -
 drivers/gpu/drm/radeon/r100.c  |   4 +-
 drivers/gpu/drm/radeon/r200.c  |   4 +-
 31 files changed, 235 insertions(+), 303 deletions(-)
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[Andrey Grodzovsky]

Turns out Steven's patch was already in so i just cherry-picked the 
change from drm-next-misc



Emily - it's in.


Andrey


On 12/3/19 2:59 PM, Deucher, Alexander wrote:


[AMD Official Use Only - Internal Distribution Only]


Cherry pick whatever dependencies you need or pick the older version 
of the patch.  Either way works.


Alex

*From:* Grodzovsky, Andrey 
*Sent:* Tuesday, December 3, 2019 2:57 PM
*To:* Deucher, Alexander ; Deng, Emily 

*Cc:* dri-de...@lists.freedesktop.org 
; amd-gfx@lists.freedesktop.org 
; Koenig, Christian 
; steven.pr...@arm.com 

*Subject:* Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

I don't think i can apply this patch 'as is' as this has dependency on 
patch by Steven which also wasn't applied yet - 588b982 Steven 
Price    6 weeks ago    drm: Don't free jobs in 
wait_event_interruptible()



Andrey


On 12/3/19 2:44 PM, Deucher, Alexander wrote:


[AMD Official Use Only - Internal Distribution Only]


Please go ahead an apply whatever version is necessary for 
amd-staging-drm-next.


Alex


*From:* Grodzovsky, Andrey  


*Sent:* Tuesday, December 3, 2019 2:10 PM
*To:* Deng, Emily  ; 
Deucher, Alexander  

*Cc:* dri-de...@lists.freedesktop.org 
 
 
; 
amd-gfx@lists.freedesktop.org  
 
; Koenig, Christian 
 ; 
steven.pr...@arm.com  
 

*Subject:* Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
Yes - Christian just pushed it to drm-next-misc - I guess Alex/Christian
didn't pull to amd-staging-drm-next yet.

Andrey

On 12/2/19 2:24 PM, Deng, Emily wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Andrey,
>  Seems this patch is still not in amd-staging-drm-next?
>
> Best wishes
> Emily Deng
>
>
>
>> -Original Message-
>> From: Deng, Emily
>> Sent: Tuesday, November 26, 2019 4:41 PM
>> To: Grodzovsky, Andrey  

>> Cc: dri-de...@lists.freedesktop.org 
; 
amd-gfx@lists.freedesktop.org ; 
Koenig,
>> Christian  
; steven.pr...@arm.com 


>> Subject: RE: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>>
>> [AMD Official Use Only - Internal Distribution Only]
>>
>> Reviewed-by: Emily Deng  


>>
>>> -Original Message-
>>> From: Grodzovsky, Andrey  


>>> Sent: Tuesday, November 26, 2019 7:37 AM
>>> Cc: dri-de...@lists.freedesktop.org 
; 
amd-gfx@lists.freedesktop.org ;
>>> Koenig, Christian  
; Deng, Emily
>>>  ; 
steven.pr...@arm.com 

>>> Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>>>
>>> Ping
>>>
>>> Andrey
>>>
>>> On 11/25/19 3:51 PM, Andrey Grodzovsky wrote:
 Problem:
 Due to a race between drm_sched_cleanup_jobs in sched thread and
 drm_sched_job_timedout in timeout work there is a possiblity 
that bad

 job was already freed while still being accessed from the timeout
 thread.

 Fix:
 Instead of just peeking at the bad job in the mirror list remove it
 from the list under lock and then put it back later when we are
 garanteed no race with main sched thread is possible which is after
 the thread is parked.

 v2: Lock around processing ring_mirror_list in 
drm_sched_cleanup_jobs.


 v3: Rebase on top of drm-misc-next. v2 is not needed anymore as
 drm_sched_get_cleanup_job already has a lock there.

 v4: Fix comments to relfect latest code in drm-misc.

 Signed-off-by: Andrey Grodzovsky  

 Reviewed-by: Christian König  

 Tested-by: Emily Deng  


 ---
 drivers/gpu/drm/scheduler/sched_main.c | 27
>>> +++
    1 file changed, 27 insertions(+)

 diff --git a/drivers/gpu/drm/scheduler/sched_main.c
 b/drivers/gpu/drm/scheduler/sched_main.c
 index 6774955..1bf9c40 100644
 --- a/drivers/gpu/drm/scheduler/sched_main.c
 +++ b/drivers/gpu/drm/scheduler/sched_main.c
 @@ -284,10 +284,21 @@ static void drm_sched_job_timedout(struct
>>> work_struct *work)
 unsigned long flags;

 sched = container_of(work, struct drm_gpu_scheduler,
 

Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

Cherry pick whatever dependencies you need or pick the older version of the 
patch.  Either way works.

Alex

From: Grodzovsky, Andrey 
Sent: Tuesday, December 3, 2019 2:57 PM
To: Deucher, Alexander ; Deng, Emily 

Cc: dri-de...@lists.freedesktop.org ; 
amd-gfx@lists.freedesktop.org ; Koenig, 
Christian ; steven.pr...@arm.com 

Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.


I don't think i can apply this patch 'as is' as this has dependency on patch by 
Steven which also wasn't applied yet - 588b982 Steven Price6 weeks ago  
  drm: Don't free jobs in wait_event_interruptible()


Andrey


On 12/3/19 2:44 PM, Deucher, Alexander wrote:

[AMD Official Use Only - Internal Distribution Only]

Please go ahead an apply whatever version is necessary for amd-staging-drm-next.

Alex


From: Grodzovsky, Andrey 

Sent: Tuesday, December 3, 2019 2:10 PM
To: Deng, Emily ; Deucher, 
Alexander 
Cc: dri-de...@lists.freedesktop.org 
; 
amd-gfx@lists.freedesktop.org 
; Koenig, 
Christian ; 
steven.pr...@arm.com 

Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

Yes - Christian just pushed it to drm-next-misc - I guess Alex/Christian
didn't pull to amd-staging-drm-next yet.

Andrey

On 12/2/19 2:24 PM, Deng, Emily wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Andrey,
>  Seems this patch is still not in amd-staging-drm-next?
>
> Best wishes
> Emily Deng
>
>
>
>> -Original Message-
>> From: Deng, Emily
>> Sent: Tuesday, November 26, 2019 4:41 PM
>> To: Grodzovsky, Andrey 
>> 
>> Cc: dri-de...@lists.freedesktop.org; 
>> amd-gfx@lists.freedesktop.org; Koenig,
>> Christian ; 
>> steven.pr...@arm.com
>> Subject: RE: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>>
>> [AMD Official Use Only - Internal Distribution Only]
>>
>> Reviewed-by: Emily Deng 
>>
>>> -Original Message-
>>> From: Grodzovsky, Andrey 
>>> 
>>> Sent: Tuesday, November 26, 2019 7:37 AM
>>> Cc: 
>>> dri-de...@lists.freedesktop.org; 
>>> amd-gfx@lists.freedesktop.org;
>>> Koenig, Christian 
>>> ; Deng, Emily
>>> ; 
>>> steven.pr...@arm.com
>>> Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>>>
>>> Ping
>>>
>>> Andrey
>>>
>>> On 11/25/19 3:51 PM, Andrey Grodzovsky wrote:
 Problem:
 Due to a race between drm_sched_cleanup_jobs in sched thread and
 drm_sched_job_timedout in timeout work there is a possiblity that bad
 job was already freed while still being accessed from the timeout
 thread.

 Fix:
 Instead of just peeking at the bad job in the mirror list remove it
 from the list under lock and then put it back later when we are
 garanteed no race with main sched thread is possible which is after
 the thread is parked.

 v2: Lock around processing ring_mirror_list in drm_sched_cleanup_jobs.

 v3: Rebase on top of drm-misc-next. v2 is not needed anymore as
 drm_sched_get_cleanup_job already has a lock there.

 v4: Fix comments to relfect latest code in drm-misc.

 Signed-off-by: Andrey Grodzovsky 
 
 Reviewed-by: Christian König 
 
 Tested-by: Emily Deng 
 ---
drivers/gpu/drm/scheduler/sched_main.c | 27
>>> +++
1 file changed, 27 insertions(+)

 diff --git a/drivers/gpu/drm/scheduler/sched_main.c
 b/drivers/gpu/drm/scheduler/sched_main.c
 index 6774955..1bf9c40 100644
 --- a/drivers/gpu/drm/scheduler/sched_main.c
 +++ b/drivers/gpu/drm/scheduler/sched_main.c
 @@ -284,10 +284,21 @@ static void drm_sched_job_timedout(struct
>>> work_struct *work)
 unsigned long flags;

 sched = container_of(work, struct drm_gpu_scheduler,
 work_tdr.work);
 +
 +  /* Protects against concurrent deletion in
>>> drm_sched_get_cleanup_job */
 +  spin_lock_irqsave(>job_list_lock, flags);
 job = list_first_entry_or_null(>ring_mirror_list,
struct drm_sched_job, node);

 

Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[Andrey Grodzovsky]

I don't think i can apply this patch 'as is' as this has dependency on 
patch by Steven which also wasn't applied yet - 588b982 Steven 
Price    6 weeks ago    drm: Don't free jobs in 
wait_event_interruptible()



Andrey


On 12/3/19 2:44 PM, Deucher, Alexander wrote:


[AMD Official Use Only - Internal Distribution Only]


Please go ahead an apply whatever version is necessary for 
amd-staging-drm-next.


Alex


*From:* Grodzovsky, Andrey 
*Sent:* Tuesday, December 3, 2019 2:10 PM
*To:* Deng, Emily ; Deucher, Alexander 

*Cc:* dri-de...@lists.freedesktop.org 
; amd-gfx@lists.freedesktop.org 
; Koenig, Christian 
; steven.pr...@arm.com 

*Subject:* Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
Yes - Christian just pushed it to drm-next-misc - I guess Alex/Christian
didn't pull to amd-staging-drm-next yet.

Andrey

On 12/2/19 2:24 PM, Deng, Emily wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Andrey,
>  Seems this patch is still not in amd-staging-drm-next?
>
> Best wishes
> Emily Deng
>
>
>
>> -Original Message-
>> From: Deng, Emily
>> Sent: Tuesday, November 26, 2019 4:41 PM
>> To: Grodzovsky, Andrey 
>> Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; 
Koenig,

>> Christian ; steven.pr...@arm.com
>> Subject: RE: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>>
>> [AMD Official Use Only - Internal Distribution Only]
>>
>> Reviewed-by: Emily Deng 
>>
>>> -Original Message-
>>> From: Grodzovsky, Andrey 
>>> Sent: Tuesday, November 26, 2019 7:37 AM
>>> Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
>>> Koenig, Christian ; Deng, Emily
>>> ; steven.pr...@arm.com
>>> Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>>>
>>> Ping
>>>
>>> Andrey
>>>
>>> On 11/25/19 3:51 PM, Andrey Grodzovsky wrote:
 Problem:
 Due to a race between drm_sched_cleanup_jobs in sched thread and
 drm_sched_job_timedout in timeout work there is a possiblity that bad
 job was already freed while still being accessed from the timeout
 thread.

 Fix:
 Instead of just peeking at the bad job in the mirror list remove it
 from the list under lock and then put it back later when we are
 garanteed no race with main sched thread is possible which is after
 the thread is parked.

 v2: Lock around processing ring_mirror_list in 
drm_sched_cleanup_jobs.


 v3: Rebase on top of drm-misc-next. v2 is not needed anymore as
 drm_sched_get_cleanup_job already has a lock there.

 v4: Fix comments to relfect latest code in drm-misc.

 Signed-off-by: Andrey Grodzovsky 
 Reviewed-by: Christian König 
 Tested-by: Emily Deng 
 ---
 drivers/gpu/drm/scheduler/sched_main.c | 27
>>> +++
    1 file changed, 27 insertions(+)

 diff --git a/drivers/gpu/drm/scheduler/sched_main.c
 b/drivers/gpu/drm/scheduler/sched_main.c
 index 6774955..1bf9c40 100644
 --- a/drivers/gpu/drm/scheduler/sched_main.c
 +++ b/drivers/gpu/drm/scheduler/sched_main.c
 @@ -284,10 +284,21 @@ static void drm_sched_job_timedout(struct
>>> work_struct *work)
 unsigned long flags;

 sched = container_of(work, struct drm_gpu_scheduler,
 work_tdr.work);
 +
 +  /* Protects against concurrent deletion in
>>> drm_sched_get_cleanup_job */
 + spin_lock_irqsave(>job_list_lock, flags);
 job = list_first_entry_or_null(>ring_mirror_list,
 struct drm_sched_job, node);

 if (job) {
 +  /*
 +   * Remove the bad job so it cannot be freed by concurrent
 +   * drm_sched_cleanup_jobs. It will be reinserted back 
after

>>> sched->thread
 +   * is parked at which point it's safe.
 +   */
 + list_del_init(>node);
 + spin_unlock_irqrestore(>job_list_lock, flags);
 +
 job->sched->ops->timedout_job(job);

 /*
 @@ -298,6 +309,8 @@ static void drm_sched_job_timedout(struct
>>> work_struct *work)
 job->sched->ops->free_job(job);
 sched->free_guilty = false;
 }
 +  } else {
 + spin_unlock_irqrestore(>job_list_lock, flags);
 }

 spin_lock_irqsave(>job_list_lock, flags); @@ -370,6 +383,20
 @@ void drm_sched_stop(struct drm_gpu_scheduler *sched, struct
>>> drm_sched_job *bad)
 kthread_park(sched->thread);

 /*
 +   * Reinsert back the bad job here - now it's safe as
 +   * drm_sched_get_cleanup_job cannot race against us and 
release the

 +   * bad job at this point - we parked (waited for) any in progress
 +   * (earlier) cleanups and drm_sched_get_cleanup_job will not be
>>> called
 +   * now until the scheduler thread is unparked.
 +   */
 +  if (bad && bad->sched == sched)
 +  /*
 +   * Add at 

RE: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[Deng, Emily]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
When we will cherry pick those patches to drm-next?

>-Original Message-
>From: Grodzovsky, Andrey 
>Sent: Tuesday, December 3, 2019 11:10 AM
>To: Deng, Emily ; Deucher, Alexander
>
>Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Koenig,
>Christian ; steven.pr...@arm.com
>Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>
>Yes - Christian just pushed it to drm-next-misc - I guess Alex/Christian 
>didn't pull
>to amd-staging-drm-next yet.
>
>Andrey
>
>On 12/2/19 2:24 PM, Deng, Emily wrote:
>> [AMD Official Use Only - Internal Distribution Only]
>>
>> Hi Andrey,
>>  Seems this patch is still not in amd-staging-drm-next?
>>
>> Best wishes
>> Emily Deng
>>
>>
>>
>>> -Original Message-
>>> From: Deng, Emily
>>> Sent: Tuesday, November 26, 2019 4:41 PM
>>> To: Grodzovsky, Andrey 
>>> Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
>>> Koenig, Christian ; steven.pr...@arm.com
>>> Subject: RE: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>>>
>>> [AMD Official Use Only - Internal Distribution Only]
>>>
>>> Reviewed-by: Emily Deng 
>>>
 -Original Message-
 From: Grodzovsky, Andrey 
 Sent: Tuesday, November 26, 2019 7:37 AM
 Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
 Koenig, Christian ; Deng, Emily
 ; steven.pr...@arm.com
 Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

 Ping

 Andrey

 On 11/25/19 3:51 PM, Andrey Grodzovsky wrote:
> Problem:
> Due to a race between drm_sched_cleanup_jobs in sched thread and
> drm_sched_job_timedout in timeout work there is a possiblity that
> bad job was already freed while still being accessed from the
> timeout thread.
>
> Fix:
> Instead of just peeking at the bad job in the mirror list remove it
> from the list under lock and then put it back later when we are
> garanteed no race with main sched thread is possible which is after
> the thread is parked.
>
> v2: Lock around processing ring_mirror_list in drm_sched_cleanup_jobs.
>
> v3: Rebase on top of drm-misc-next. v2 is not needed anymore as
> drm_sched_get_cleanup_job already has a lock there.
>
> v4: Fix comments to relfect latest code in drm-misc.
>
> Signed-off-by: Andrey Grodzovsky 
> Reviewed-by: Christian König 
> Tested-by: Emily Deng 
> ---
>drivers/gpu/drm/scheduler/sched_main.c | 27
 +++
>1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/scheduler/sched_main.c
> b/drivers/gpu/drm/scheduler/sched_main.c
> index 6774955..1bf9c40 100644
> --- a/drivers/gpu/drm/scheduler/sched_main.c
> +++ b/drivers/gpu/drm/scheduler/sched_main.c
> @@ -284,10 +284,21 @@ static void drm_sched_job_timedout(struct
 work_struct *work)
>   unsigned long flags;
>
>   sched = container_of(work, struct drm_gpu_scheduler,
> work_tdr.work);
> +
> + /* Protects against concurrent deletion in
 drm_sched_get_cleanup_job */
> + spin_lock_irqsave(>job_list_lock, flags);
>   job = list_first_entry_or_null(>ring_mirror_list,
>  struct drm_sched_job, node);
>
>   if (job) {
> + /*
> +  * Remove the bad job so it cannot be freed by concurrent
> +  * drm_sched_cleanup_jobs. It will be reinserted back after
 sched->thread
> +  * is parked at which point it's safe.
> +  */
> + list_del_init(>node);
> + spin_unlock_irqrestore(>job_list_lock, flags);
> +
>   job->sched->ops->timedout_job(job);
>
>   /*
> @@ -298,6 +309,8 @@ static void drm_sched_job_timedout(struct
 work_struct *work)
>   job->sched->ops->free_job(job);
>   sched->free_guilty = false;
>   }
> + } else {
> + spin_unlock_irqrestore(>job_list_lock, flags);
>   }
>
>   spin_lock_irqsave(>job_list_lock, flags); @@ -370,6
> +383,20 @@ void drm_sched_stop(struct drm_gpu_scheduler *sched,
> struct
 drm_sched_job *bad)
>   kthread_park(sched->thread);
>
>   /*
> +  * Reinsert back the bad job here - now it's safe as
> +  * drm_sched_get_cleanup_job cannot race against us and release the
> +  * bad job at this point - we parked (waited for) any in progress
> +  * (earlier) cleanups and drm_sched_get_cleanup_job will not be
 called
> +  * now until the scheduler thread is unparked.
> +  */
> + if (bad && bad->sched == sched)
> + /*
> +  * Add at the head of the queue to reflect it was the 

Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

Please go ahead an apply whatever version is necessary for amd-staging-drm-next.

Alex


From: Grodzovsky, Andrey 
Sent: Tuesday, December 3, 2019 2:10 PM
To: Deng, Emily ; Deucher, Alexander 

Cc: dri-de...@lists.freedesktop.org ; 
amd-gfx@lists.freedesktop.org ; Koenig, 
Christian ; steven.pr...@arm.com 

Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

Yes - Christian just pushed it to drm-next-misc - I guess Alex/Christian
didn't pull to amd-staging-drm-next yet.

Andrey

On 12/2/19 2:24 PM, Deng, Emily wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Andrey,
>  Seems this patch is still not in amd-staging-drm-next?
>
> Best wishes
> Emily Deng
>
>
>
>> -Original Message-
>> From: Deng, Emily
>> Sent: Tuesday, November 26, 2019 4:41 PM
>> To: Grodzovsky, Andrey 
>> Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Koenig,
>> Christian ; steven.pr...@arm.com
>> Subject: RE: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>>
>> [AMD Official Use Only - Internal Distribution Only]
>>
>> Reviewed-by: Emily Deng 
>>
>>> -Original Message-
>>> From: Grodzovsky, Andrey 
>>> Sent: Tuesday, November 26, 2019 7:37 AM
>>> Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
>>> Koenig, Christian ; Deng, Emily
>>> ; steven.pr...@arm.com
>>> Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.
>>>
>>> Ping
>>>
>>> Andrey
>>>
>>> On 11/25/19 3:51 PM, Andrey Grodzovsky wrote:
 Problem:
 Due to a race between drm_sched_cleanup_jobs in sched thread and
 drm_sched_job_timedout in timeout work there is a possiblity that bad
 job was already freed while still being accessed from the timeout
 thread.

 Fix:
 Instead of just peeking at the bad job in the mirror list remove it
 from the list under lock and then put it back later when we are
 garanteed no race with main sched thread is possible which is after
 the thread is parked.

 v2: Lock around processing ring_mirror_list in drm_sched_cleanup_jobs.

 v3: Rebase on top of drm-misc-next. v2 is not needed anymore as
 drm_sched_get_cleanup_job already has a lock there.

 v4: Fix comments to relfect latest code in drm-misc.

 Signed-off-by: Andrey Grodzovsky 
 Reviewed-by: Christian König 
 Tested-by: Emily Deng 
 ---
drivers/gpu/drm/scheduler/sched_main.c | 27
>>> +++
1 file changed, 27 insertions(+)

 diff --git a/drivers/gpu/drm/scheduler/sched_main.c
 b/drivers/gpu/drm/scheduler/sched_main.c
 index 6774955..1bf9c40 100644
 --- a/drivers/gpu/drm/scheduler/sched_main.c
 +++ b/drivers/gpu/drm/scheduler/sched_main.c
 @@ -284,10 +284,21 @@ static void drm_sched_job_timedout(struct
>>> work_struct *work)
 unsigned long flags;

 sched = container_of(work, struct drm_gpu_scheduler,
 work_tdr.work);
 +
 +  /* Protects against concurrent deletion in
>>> drm_sched_get_cleanup_job */
 +  spin_lock_irqsave(>job_list_lock, flags);
 job = list_first_entry_or_null(>ring_mirror_list,
struct drm_sched_job, node);

 if (job) {
 +  /*
 +   * Remove the bad job so it cannot be freed by concurrent
 +   * drm_sched_cleanup_jobs. It will be reinserted back after
>>> sched->thread
 +   * is parked at which point it's safe.
 +   */
 +  list_del_init(>node);
 +  spin_unlock_irqrestore(>job_list_lock, flags);
 +
 job->sched->ops->timedout_job(job);

 /*
 @@ -298,6 +309,8 @@ static void drm_sched_job_timedout(struct
>>> work_struct *work)
 job->sched->ops->free_job(job);
 sched->free_guilty = false;
 }
 +  } else {
 +  spin_unlock_irqrestore(>job_list_lock, flags);
 }

 spin_lock_irqsave(>job_list_lock, flags); @@ -370,6 +383,20
 @@ void drm_sched_stop(struct drm_gpu_scheduler *sched, struct
>>> drm_sched_job *bad)
 kthread_park(sched->thread);

 /*
 +   * Reinsert back the bad job here - now it's safe as
 +   * drm_sched_get_cleanup_job cannot race against us and release the
 +   * bad job at this point - we parked (waited for) any in progress
 +   * (earlier) cleanups and drm_sched_get_cleanup_job will not be
>>> called
 +   * now until the scheduler thread is unparked.
 +   */
 +  if (bad && bad->sched == sched)
 +  /*
 +   * Add at the head of the queue to reflect it was the earliest
 +   * job extracted.
 +   */
 +  list_add(>node, >ring_mirror_list);
 +
 +  /*
  * Iterate the job list from 

Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[Andrey Grodzovsky]

Yes - Christian just pushed it to drm-next-misc - I guess Alex/Christian 
didn't pull to amd-staging-drm-next yet.


Andrey

On 12/2/19 2:24 PM, Deng, Emily wrote:

[AMD Official Use Only - Internal Distribution Only]

Hi Andrey,
 Seems this patch is still not in amd-staging-drm-next?

Best wishes
Emily Deng




-Original Message-
From: Deng, Emily
Sent: Tuesday, November 26, 2019 4:41 PM
To: Grodzovsky, Andrey 
Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Koenig,
Christian ; steven.pr...@arm.com
Subject: RE: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Emily Deng 


-Original Message-
From: Grodzovsky, Andrey 
Sent: Tuesday, November 26, 2019 7:37 AM
Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
Koenig, Christian ; Deng, Emily
; steven.pr...@arm.com
Subject: Re: [PATCH v4] drm/scheduler: Avoid accessing freed bad job.

Ping

Andrey

On 11/25/19 3:51 PM, Andrey Grodzovsky wrote:

Problem:
Due to a race between drm_sched_cleanup_jobs in sched thread and
drm_sched_job_timedout in timeout work there is a possiblity that bad
job was already freed while still being accessed from the timeout
thread.

Fix:
Instead of just peeking at the bad job in the mirror list remove it
from the list under lock and then put it back later when we are
garanteed no race with main sched thread is possible which is after
the thread is parked.

v2: Lock around processing ring_mirror_list in drm_sched_cleanup_jobs.

v3: Rebase on top of drm-misc-next. v2 is not needed anymore as
drm_sched_get_cleanup_job already has a lock there.

v4: Fix comments to relfect latest code in drm-misc.

Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Christian König 
Tested-by: Emily Deng 
---
   drivers/gpu/drm/scheduler/sched_main.c | 27

+++

   1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/drm/scheduler/sched_main.c
index 6774955..1bf9c40 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -284,10 +284,21 @@ static void drm_sched_job_timedout(struct

work_struct *work)

unsigned long flags;

sched = container_of(work, struct drm_gpu_scheduler,
work_tdr.work);
+
+   /* Protects against concurrent deletion in

drm_sched_get_cleanup_job */

+   spin_lock_irqsave(>job_list_lock, flags);
job = list_first_entry_or_null(>ring_mirror_list,
   struct drm_sched_job, node);

if (job) {
+   /*
+* Remove the bad job so it cannot be freed by concurrent
+* drm_sched_cleanup_jobs. It will be reinserted back after

sched->thread

+* is parked at which point it's safe.
+*/
+   list_del_init(>node);
+   spin_unlock_irqrestore(>job_list_lock, flags);
+
job->sched->ops->timedout_job(job);

/*
@@ -298,6 +309,8 @@ static void drm_sched_job_timedout(struct

work_struct *work)

job->sched->ops->free_job(job);
sched->free_guilty = false;
}
+   } else {
+   spin_unlock_irqrestore(>job_list_lock, flags);
}

spin_lock_irqsave(>job_list_lock, flags); @@ -370,6 +383,20
@@ void drm_sched_stop(struct drm_gpu_scheduler *sched, struct

drm_sched_job *bad)

kthread_park(sched->thread);

/*
+* Reinsert back the bad job here - now it's safe as
+* drm_sched_get_cleanup_job cannot race against us and release the
+* bad job at this point - we parked (waited for) any in progress
+* (earlier) cleanups and drm_sched_get_cleanup_job will not be

called

+* now until the scheduler thread is unparked.
+*/
+   if (bad && bad->sched == sched)
+   /*
+* Add at the head of the queue to reflect it was the earliest
+* job extracted.
+*/
+   list_add(>node, >ring_mirror_list);
+
+   /*
 * Iterate the job list from later to  earlier one and either deactive
 * their HW callbacks or remove them from mirror list if they already
 * signaled.

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RE: [PATCH v2] drm/amd/display: Loading NV10/14 Bounding Box Data Directly from Code

[Wu, Hersen]

[AMD Official Use Only - Internal Distribution Only]


Reviewed-by: hersen wu < hersenxs...@amd.com>

-Original Message-
From: Liu, Zhan  
Sent: Tuesday, December 3, 2019 12:49 PM
To: amd-gfx@lists.freedesktop.org; Wu, Hersen ; 
Kazlauskas, Nicholas 
Cc: Liu, Zhan 
Subject: [PATCH v2] drm/amd/display: Loading NV10/14 Bounding Box Data Directly 
from Code

[Why]
NV10/14 has released. Its time to get NV10/14 bounding box directly from code.

[How]
Retrieve NV10/14 bounding box data directly from code.
Retrieve NV12 bounding box data from firmware.

Signed-off-by: Zhan Liu 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2ccfd84a7da4..2a158ff5f0a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -83,8 +83,6 @@
 
 #include "amdgpu_socbb.h"
 
-/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */ -#define 
SOC_BOUNDING_BOX_VALID false  #define DC_LOGGER_INIT(logger)
 
 struct _vcs_dpi_ip_params_st dcn2_0_ip = { @@ -3271,12 +3269,13 @@ static bool 
init_soc_bounding_box(struct dc *dc,
 
DC_LOGGER_INIT(dc->ctx->logger);
 
-   if (!bb && !SOC_BOUNDING_BOX_VALID) {
+   /* TODO: upstream NV12 bounding box when its launched */
+   if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
return false;
}
 
-   if (bb && !SOC_BOUNDING_BOX_VALID) {
+   if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
int i;
 
dcn2_0_nv12_soc.sr_exit_time_us =
--
2.17.1
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[PATCH v2] drm/amd/display: Loading NV10/14 Bounding Box Data Directly from Code

[Zhan Liu]

[Why]
NV10/14 has released. Its time to get NV10/14 bounding box
directly from code.

[How]
Retrieve NV10/14 bounding box data directly from code.
Retrieve NV12 bounding box data from firmware.

Signed-off-by: Zhan Liu 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2ccfd84a7da4..2a158ff5f0a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -83,8 +83,6 @@
 
 #include "amdgpu_socbb.h"
 
-/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */
-#define SOC_BOUNDING_BOX_VALID false
 #define DC_LOGGER_INIT(logger)
 
 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
@@ -3271,12 +3269,13 @@ static bool init_soc_bounding_box(struct dc *dc,
 
DC_LOGGER_INIT(dc->ctx->logger);
 
-   if (!bb && !SOC_BOUNDING_BOX_VALID) {
+   /* TODO: upstream NV12 bounding box when its launched */
+   if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
return false;
}
 
-   if (bb && !SOC_BOUNDING_BOX_VALID) {
+   if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
int i;
 
dcn2_0_nv12_soc.sr_exit_time_us =
-- 
2.17.1

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Re: [RFC PATCH] drm/amdgpu: allocate entities on demand

[Christian König]

Am 03.12.19 um 18:33 schrieb Christian König:

Am 03.12.19 um 16:02 schrieb Nirmoy:

Hi Christian,

On 12/2/19 3:59 PM, Christian König wrote:

Am 02.12.19 um 15:43 schrieb Nirmoy:


Do you mean something like

diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index 684692a8ed76..ac67f8f098fa 100644
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@ -81,7 +81,7 @@ enum drm_sched_priority {
 struct drm_sched_entity {
    struct list_head    list;
    struct drm_sched_rq *rq;
-   struct drm_sched_rq **rq_list;
+  struct drm_gpu_scheduler    **sched;
    unsigned int    num_rq_list;
    spinlock_t  rq_lock;


Yes, exactly. Problem is that I'm not 100% sure if that really works 
with all users of the rq_list.


currently rq_list users does two main tasks.

1  change rq priority for a context on user requests

2  helps drm scheduler to find rq  with least load.

Can you please check the bellow diff it doesn't really work because I 
get some kernel panic. But do you think


it is matching your idea ?


Yes, that looks exactly like what I had in mind.


BTW: What does the matching amdgpu change look like?

Keep in mind that you can't allocate the list of schedulers on the stack 
any more.


That might be the reason for you kernel panic.

Christian.



Christian.



test@install:~/linux> git diff 
drivers/gpu/drm/scheduler/sched_entity.c |tee
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c

index 1a5153197fe9..0bbd8ddd6c83 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -37,9 +37,9 @@
  * submit to HW ring.
  *
  * @entity: scheduler entity to init
- * @rq_list: the list of run queue on which jobs from this
+ * @sched_list: the list of drm scheds on which jobs from this
  *   entity can be submitted
- * @num_rq_list: number of run queue in rq_list
+ * @num_sched_list: number of drm sched in sched_list
  * @guilty: atomic_t set to 1 when a job on this queue
  *  is found to be guilty causing a timeout
  *
@@ -49,30 +49,24 @@
  * Returns 0 on success or a negative error code on failure.
  */
 int drm_sched_entity_init(struct drm_sched_entity *entity,
-              struct drm_sched_rq **rq_list,
-              unsigned int num_rq_list,
-              atomic_t *guilty)
+              struct drm_gpu_scheduler **sched_list,
+              unsigned int num_sched_list,
+              atomic_t *guilty, enum drm_sched_priority priority)
 {
-    int i;

-    if (!(entity && rq_list && (num_rq_list == 0 || rq_list[0])))
+    if (!(entity && sched_list && (num_sched_list == 0 || 
sched_list[0])))

         return -EINVAL;

     memset(entity, 0, sizeof(struct drm_sched_entity));
     INIT_LIST_HEAD(>list);
     entity->rq = NULL;
     entity->guilty = guilty;
-    entity->num_rq_list = num_rq_list;
-    entity->rq_list = kcalloc(num_rq_list, sizeof(struct 
drm_sched_rq *),

-                GFP_KERNEL);
-    if (!entity->rq_list)
-        return -ENOMEM;
-
-    for (i = 0; i < num_rq_list; ++i)
-        entity->rq_list[i] = rq_list[i];
+    entity->num_sched_list = num_sched_list;
+    entity->sched_list =  sched_list
+    entity->priority = priority;

-    if (num_rq_list)
-        entity->rq = rq_list[0];
+    if (num_sched_list)
+        entity->rq = 
>sched_list[0]->sched_rq[entity->priority];


     entity->last_scheduled = NULL;

@@ -136,10 +130,10 @@ drm_sched_entity_get_free_sched(struct 
drm_sched_entity *entity)

     unsigned int min_jobs = UINT_MAX, num_jobs;
     int i;

-    for (i = 0; i < entity->num_rq_list; ++i) {
-        struct drm_gpu_scheduler *sched = entity->rq_list[i]->sched;
+    for (i = 0; i < entity->num_sched_list; ++i) {
+        struct drm_gpu_scheduler *sched = entity->sched_list[i];

-        if (!entity->rq_list[i]->sched->ready) {
+        if (!entity->sched_list[i]->ready) {
             DRM_WARN("sched%s is not ready, skipping", sched->name);
             continue;
         }
@@ -147,7 +141,7 @@ drm_sched_entity_get_free_sched(struct 
drm_sched_entity *entity)

         num_jobs = atomic_read(>num_jobs);
         if (num_jobs < min_jobs) {
             min_jobs = num_jobs;
-            rq = entity->rq_list[i];
+            rq = >sched_list[i]->sched_rq[entity->priority];
         }
     }

@@ -304,7 +298,6 @@ void drm_sched_entity_fini(struct 
drm_sched_entity *entity)


     dma_fence_put(entity->last_scheduled);
     entity->last_scheduled = NULL;
-    kfree(entity->rq_list);
 }
 EXPORT_SYMBOL(drm_sched_entity_fini);

@@ -372,8 +365,9 @@ void drm_sched_entity_set_priority(struct 
drm_sched_entity *entity,

     unsigned int i;

     spin_lock(>rq_lock);
-
-    for (i = 0; i < entity->num_rq_list; ++i)
+//TODO
+/*
+    for (i = 0; i < entity->num_sched_list; ++i)
 drm_sched_entity_set_rq_priority(>rq_list[i], priority);

     

Re: [RFC PATCH] drm/amdgpu: allocate entities on demand

[Christian König]

Am 03.12.19 um 16:02 schrieb Nirmoy:

Hi Christian,

On 12/2/19 3:59 PM, Christian König wrote:

Am 02.12.19 um 15:43 schrieb Nirmoy:


Do you mean something like

diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index 684692a8ed76..ac67f8f098fa 100644
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@ -81,7 +81,7 @@ enum drm_sched_priority {
 struct drm_sched_entity {
    struct list_head    list;
    struct drm_sched_rq *rq;
-   struct drm_sched_rq **rq_list;
+  struct drm_gpu_scheduler    **sched;
    unsigned int    num_rq_list;
    spinlock_t  rq_lock;


Yes, exactly. Problem is that I'm not 100% sure if that really works 
with all users of the rq_list.


currently rq_list users does two main tasks.

1  change rq priority for a context on user requests

2  helps drm scheduler to find rq  with least load.

Can you please check the bellow diff it doesn't really work because I 
get some kernel panic. But do you think


it is matching your idea ?


Yes, that looks exactly like what I had in mind.

Christian.



test@install:~/linux> git diff 
drivers/gpu/drm/scheduler/sched_entity.c |tee
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c

index 1a5153197fe9..0bbd8ddd6c83 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -37,9 +37,9 @@
  * submit to HW ring.
  *
  * @entity: scheduler entity to init
- * @rq_list: the list of run queue on which jobs from this
+ * @sched_list: the list of drm scheds on which jobs from this
  *   entity can be submitted
- * @num_rq_list: number of run queue in rq_list
+ * @num_sched_list: number of drm sched in sched_list
  * @guilty: atomic_t set to 1 when a job on this queue
  *  is found to be guilty causing a timeout
  *
@@ -49,30 +49,24 @@
  * Returns 0 on success or a negative error code on failure.
  */
 int drm_sched_entity_init(struct drm_sched_entity *entity,
-              struct drm_sched_rq **rq_list,
-              unsigned int num_rq_list,
-              atomic_t *guilty)
+              struct drm_gpu_scheduler **sched_list,
+              unsigned int num_sched_list,
+              atomic_t *guilty, enum drm_sched_priority priority)
 {
-    int i;

-    if (!(entity && rq_list && (num_rq_list == 0 || rq_list[0])))
+    if (!(entity && sched_list && (num_sched_list == 0 || 
sched_list[0])))

         return -EINVAL;

     memset(entity, 0, sizeof(struct drm_sched_entity));
     INIT_LIST_HEAD(>list);
     entity->rq = NULL;
     entity->guilty = guilty;
-    entity->num_rq_list = num_rq_list;
-    entity->rq_list = kcalloc(num_rq_list, sizeof(struct drm_sched_rq 
*),

-                GFP_KERNEL);
-    if (!entity->rq_list)
-        return -ENOMEM;
-
-    for (i = 0; i < num_rq_list; ++i)
-        entity->rq_list[i] = rq_list[i];
+    entity->num_sched_list = num_sched_list;
+    entity->sched_list =  sched_list
+    entity->priority = priority;

-    if (num_rq_list)
-        entity->rq = rq_list[0];
+    if (num_sched_list)
+        entity->rq = >sched_list[0]->sched_rq[entity->priority];

     entity->last_scheduled = NULL;

@@ -136,10 +130,10 @@ drm_sched_entity_get_free_sched(struct 
drm_sched_entity *entity)

     unsigned int min_jobs = UINT_MAX, num_jobs;
     int i;

-    for (i = 0; i < entity->num_rq_list; ++i) {
-        struct drm_gpu_scheduler *sched = entity->rq_list[i]->sched;
+    for (i = 0; i < entity->num_sched_list; ++i) {
+        struct drm_gpu_scheduler *sched = entity->sched_list[i];

-        if (!entity->rq_list[i]->sched->ready) {
+        if (!entity->sched_list[i]->ready) {
             DRM_WARN("sched%s is not ready, skipping", sched->name);
             continue;
         }
@@ -147,7 +141,7 @@ drm_sched_entity_get_free_sched(struct 
drm_sched_entity *entity)

         num_jobs = atomic_read(>num_jobs);
         if (num_jobs < min_jobs) {
             min_jobs = num_jobs;
-            rq = entity->rq_list[i];
+            rq = >sched_list[i]->sched_rq[entity->priority];
         }
     }

@@ -304,7 +298,6 @@ void drm_sched_entity_fini(struct drm_sched_entity 
*entity)


     dma_fence_put(entity->last_scheduled);
     entity->last_scheduled = NULL;
-    kfree(entity->rq_list);
 }
 EXPORT_SYMBOL(drm_sched_entity_fini);

@@ -372,8 +365,9 @@ void drm_sched_entity_set_priority(struct 
drm_sched_entity *entity,

     unsigned int i;

     spin_lock(>rq_lock);
-
-    for (i = 0; i < entity->num_rq_list; ++i)
+//TODO
+/*
+    for (i = 0; i < entity->num_sched_list; ++i)
 drm_sched_entity_set_rq_priority(>rq_list[i], priority);

     if (entity->rq) {
@@ -381,7 +375,7 @@ void drm_sched_entity_set_priority(struct 
drm_sched_entity *entity,

         drm_sched_entity_set_rq_priority(>rq, priority);
         drm_sched_rq_add_entity(entity->rq, entity);
     }
-
+*/
     

Re: [error] Drm -> amdgpu Unrecoverable Machine Check

[Christian König]

Right now I am trying to increase MMIO size config to 512 MB
What you could try as well is to use the size 320MB for the MMIO. Those 
ranges usually don't need to be a power of two (only the BARs itself are 
a power of two) and this way it might even be easier to fit everything 
together.


By the way I wonder how can I get at least VGA output from GPU. Maybe 
I can get a text console on screen or something like X server? Do you 
have any recommendations?
What could maybe work is VGA emulation, which essentially means text 
only. But no guarantee for that this really works as expected.


I am just wondering, does modern gaming motherboards have more than 
4GB PCIe buffer for this job ?

They don't, resources are dynamically assigned instead.

See on x86 you usually have 1GB 32-bit address space where the BIOS 
shuffles all the mandatory devices it sees at boot time into.


Then when the motherboard has multiple PEG slots the BIOS also 
configures a 64-bit address space which is usually rather huge 
(256GB-1TB). Since the the VRAM and the doorbell BAR are 64bit BARs on 
the GPU they can be mapped into that as well.


This way you can easily have 10 GPUs connected to your CPU.

The problem you have here is that U-config doesn't do this resource 
assignment automatically and you need to configure it manually.


Regards,
Christian.

Am 03.12.19 um 13:50 schrieb Yusuf Altıparmak:


Hi Christian,


0001f000

Exactly as I thought. The hardware does support BAR resize, but
unfortunately 256MB is already the minimum.

Sorry, but there isn't anything I could do from the GPU drivers
point of view.


Yes unfortunately there is nothing remained to about GPU side.

The only good news I have is that 256M+2M+512K+128K=260M address
space should be enough for the GPU to work, maybe that makes
things a bit simpler.


Right now I am trying to increase MMIO size config to 512 MB, I hope 
that should help me. By the way I wonder how can I get at least VGA 
output from GPU. Maybe I can get a text console on screen or something 
like X server? Do you have any recommendations? I tried this GPU with 
my own Ubuntu 18.04 and its special driver. Everything worked fine.


But you definitely got an interesting use case here :)


This is the worlds the most interesting use case I think. I can't 
increase MMIO size because U-boot freezes. I can't decrease it to 256 
MB again because driver does not accept :D. I am just wondering, does 
modern gaming motherboards have more than 4GB PCIe buffer for this job 
? :D



Am 03.12.19 um 11:31 schrieb Yusuf Altıparmak:

Hello Christian,
My "setpci -s 0001:01:00.0 ECAP15+4.l ECAP15+8.l" output is;

0001f000
0820

Regards.



Yusuf Altıparmak mailto:yusufalti1...@gmail.com>>, 2 Ara 2019 Pzt, 19:31
tarihinde şunu yazdı:

Most likely not. There is support for resizing the VRAM
BAR, but usually you can only make it larger and not smaller.
Please give me the output of "sudo setpci -s 0001:01:00.0
ECAP15+4.l ECAP15+8.l" if you want to double check that.


Okay I'll try it tomorrow. What does the " sudo setpci -s
0001:01:00.0 ECAP15+4.l ECAP15+8.l" command exactly do ?

Well you rather need to ask if anybody has sample PCIe
configuration for GPUs in general. That problem is not
really E9171 related. You might want to ask NXP for that
maybe.
Sorry, no idea if that is correct or not. You need to ask
NXP for help with that.


Okay no problem. At least I know what is the missing point
now. The problem is probably because of the .dtsi and u-boot
config files. Memory ranges are overwriting like you said.
I'll ask nxp to take some sample PCIe configuration for GPUs.

Thank you for your interest Christian.
Regards .



Am 02.12.19 um 14:32 schrieb Yusuf Altıparmak:




I attached my dts file.

System is working fine when GPU is not plugged in.
*
*
*This is the last console log before freeze:*
[drm] amdgpu kernel modesetting enabled.
[drm] initializing kernel modesetting
(POLARIS12 0x1002:0x6987 0x1787:0x2389 0x80).
[drm] register mmio base: 0x2020
fsl-fman-port ffe488000.port fm1-gb0: renamed
from eth0
[drm] register mmio size: 262144
[drm] add ip block number 0 
[drm] add ip block number 1 
[drm] add ip block number 2 
[drm] add ip block number 3 
[drm] add ip block number 4 
[drm] add ip block number 5 
[drm] add ip block number 6 
[drm] add ip 

Re: [PATCH] drm/amd/display: Loading NV10/14 Bounding Box Data Directly From Code

[Kazlauskas, Nicholas]

On 2019-12-03 12:02 p.m., Zhan Liu wrote:

[Why]
NV10/14 has released. Its time to get NV10/14 bounding box
directly from code.

[How]
Retrieve NV10/14 bounding box data directly from code.

Signed-off-by: Zhan Liu 
---
  .../drm/amd/display/dc/dcn20/dcn20_resource.c | 199 +++---
  1 file changed, 121 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2ccfd84a7da4..4115b595e36e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -83,8 +83,6 @@
  
  #include "amdgpu_socbb.h"
  
-/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */

-#define SOC_BOUNDING_BOX_VALID false
  #define DC_LOGGER_INIT(logger)
  
  struct _vcs_dpi_ip_params_st dcn2_0_ip = {

@@ -3271,12 +3196,12 @@ static bool init_soc_bounding_box(struct dc *dc,
  
  	DC_LOGGER_INIT(dc->ctx->logger);
  
-	if (!bb && !SOC_BOUNDING_BOX_VALID) {

+   if (!bb) {


This will throw an error when we don't have firmware on disk (which now 
isn't required for Navi10 or Navi14).


Please replace SOC_BOUNDING_BOX_VALID with a function that has the logic 
to check whether the ASIC is Navi12 or not and use it below as well...



DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
return false;
}
  
-	if (bb && !SOC_BOUNDING_BOX_VALID) {

+   if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {


...here, eg.

static bool is_soc_bounding_box_valid(uint32_t hw_internal_rev)
{
if (ASICREV_IS_NAVI12_P(hw_internal_rev))
return false;

return true;
}



int i;
  
  		dcn2_0_nv12_soc.sr_exit_time_us =

@@ -3380,6 +3305,108 @@ static bool init_soc_bounding_box(struct dc *dc,
}
}
  
+	if (bb && (ASICREV_IS_NAVI14_M(dc->ctx->asic_id.hw_internal_rev) || ASICREV_IS_NAVI10_P(dc->ctx->asic_id.hw_internal_rev))) {


These constants are already in the table. We shouldn't need to be 
filling them in below.


Regards,
Nicholas Kazlauskas


+   dcn2_0_soc.sr_exit_time_us = 8.6;
+   dcn2_0_soc.sr_enter_plus_exit_time_us = 10.9;
+   dcn2_0_soc.urgent_latency_us = 4.0;
+   dcn2_0_soc.urgent_latency_pixel_data_only_us = 4.0;
+   dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us = 4.0;
+   dcn2_0_soc.urgent_latency_vm_data_only_us = 4.0;
+   
dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096;
+   
dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096;
+   dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes 
= 4096;
+   dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0;
+   dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 
40.0;
+   dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0;
+   dcn2_0_soc.max_avg_sdp_bw_use_normal_percent = 40.0;
+   dcn2_0_soc.max_avg_dram_bw_use_normal_percent = 40.0;
+   dcn2_0_soc.writeback_latency_us = 12.0;
+   dcn2_0_soc.ideal_dram_bw_after_urgent_percent = 40.0;
+   dcn2_0_soc.max_request_size_bytes = 256;
+   dcn2_0_soc.dram_channel_width_bytes = 2;
+   dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes = 64;
+   dcn2_0_soc.dcn_downspread_percent = 0.5;
+   dcn2_0_soc.downspread_percent = 0.38;
+   dcn2_0_soc.dram_page_open_time_ns = 50.0;
+   dcn2_0_soc.dram_rw_turnaround_time_ns = 17.5;
+   dcn2_0_soc.dram_return_buffer_per_channel_bytes = 8192;
+   dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles = 131;
+   dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes = 256;
+   dcn2_0_soc.channel_interleave_bytes = 256;
+   dcn2_0_soc.num_banks = 8;
+   dcn2_0_soc.num_chans = 16;
+   dcn2_0_soc.vmm_page_size_bytes = 4096;
+   dcn2_0_soc.dram_clock_change_latency_us = 404.0;
+   dcn2_0_soc.dummy_pstate_latency_us = 5.0;
+   dcn2_0_soc.writeback_dram_clock_change_latency_us = 23.0;
+   dcn2_0_soc.return_bus_width_bytes = 64;
+   dcn2_0_soc.dispclk_dppclk_vco_speed_mhz = 3850;
+   dcn2_0_soc.xfc_bus_transport_time_us = 20;
+   dcn2_0_soc.xfc_xbuf_latency_tolerance_us = 4;
+   dcn2_0_soc.use_urgent_burst_bw = 0;
+   dcn2_0_soc.num_states = 5;
+
+   dcn2_0_soc.clock_limits[0].state = 0;
+   dcn2_0_soc.clock_limits[0].dcfclk_mhz = 560.0;
+   dcn2_0_soc.clock_limits[0].fabricclk_mhz = 560.0;
+   dcn2_0_soc.clock_limits[0].dispclk_mhz = 513.0;
+   dcn2_0_soc.clock_limits[0].dppclk_mhz = 513.0;
+   

Re: [PATCH] drm/radeon: fix r1xx/r2xx register checker for POT textures

[Michel Dänzer]

On 2019-11-26 3:43 p.m., Alex Deucher wrote:
> Shift and mask were reversed.  Noticed by chance.
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/radeon/r100.c | 4 ++--
>  drivers/gpu/drm/radeon/r200.c | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
> index 7089dfc8c2a9..1ccee4e5880e 100644
> --- a/drivers/gpu/drm/radeon/r100.c
> +++ b/drivers/gpu/drm/radeon/r100.c
> @@ -1826,8 +1826,8 @@ static int r100_packet0_check(struct radeon_cs_parser 
> *p,
>   track->textures[i].use_pitch = 1;
>   } else {
>   track->textures[i].use_pitch = 0;
> - track->textures[i].width = 1 << ((idx_value >> 
> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
> - track->textures[i].height = 1 << ((idx_value >> 
> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
> + track->textures[i].width = 1 << 
> ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);

Indentation looks off for this line. With that fixed,

Reviewed-by: Michel Dänzer 


-- 
Earthling Michel Dänzer   |   https://redhat.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
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[PATCH] drm/amd/display: Loading NV10/14 Bounding Box Data Directly From Code

[Zhan Liu]

[Why]
NV10/14 has released. Its time to get NV10/14 bounding box
directly from code.

[How]
Retrieve NV10/14 bounding box data directly from code.

Signed-off-by: Zhan Liu 
---
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 199 +++---
 1 file changed, 121 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2ccfd84a7da4..4115b595e36e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -83,8 +83,6 @@
 
 #include "amdgpu_socbb.h"
 
-/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */
-#define SOC_BOUNDING_BOX_VALID false
 #define DC_LOGGER_INIT(logger)
 
 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
@@ -3271,12 +3196,12 @@ static bool init_soc_bounding_box(struct dc *dc,
 
DC_LOGGER_INIT(dc->ctx->logger);
 
-   if (!bb && !SOC_BOUNDING_BOX_VALID) {
+   if (!bb) {
DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
return false;
}
 
-   if (bb && !SOC_BOUNDING_BOX_VALID) {
+   if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
int i;
 
dcn2_0_nv12_soc.sr_exit_time_us =
@@ -3380,6 +3305,108 @@ static bool init_soc_bounding_box(struct dc *dc,
}
}
 
+   if (bb && (ASICREV_IS_NAVI14_M(dc->ctx->asic_id.hw_internal_rev) || 
ASICREV_IS_NAVI10_P(dc->ctx->asic_id.hw_internal_rev))) {
+   dcn2_0_soc.sr_exit_time_us = 8.6;
+   dcn2_0_soc.sr_enter_plus_exit_time_us = 10.9;
+   dcn2_0_soc.urgent_latency_us = 4.0;
+   dcn2_0_soc.urgent_latency_pixel_data_only_us = 4.0;
+   dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us = 4.0;
+   dcn2_0_soc.urgent_latency_vm_data_only_us = 4.0;
+   
dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096;
+   
dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096;
+   dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes 
= 4096;
+   dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0;
+   dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 
40.0;
+   dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0;
+   dcn2_0_soc.max_avg_sdp_bw_use_normal_percent = 40.0;
+   dcn2_0_soc.max_avg_dram_bw_use_normal_percent = 40.0;
+   dcn2_0_soc.writeback_latency_us = 12.0;
+   dcn2_0_soc.ideal_dram_bw_after_urgent_percent = 40.0;
+   dcn2_0_soc.max_request_size_bytes = 256;
+   dcn2_0_soc.dram_channel_width_bytes = 2;
+   dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes = 64;
+   dcn2_0_soc.dcn_downspread_percent = 0.5;
+   dcn2_0_soc.downspread_percent = 0.38;
+   dcn2_0_soc.dram_page_open_time_ns = 50.0;
+   dcn2_0_soc.dram_rw_turnaround_time_ns = 17.5;
+   dcn2_0_soc.dram_return_buffer_per_channel_bytes = 8192;
+   dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles = 131;
+   dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes = 256;
+   dcn2_0_soc.channel_interleave_bytes = 256;
+   dcn2_0_soc.num_banks = 8;
+   dcn2_0_soc.num_chans = 16;
+   dcn2_0_soc.vmm_page_size_bytes = 4096;
+   dcn2_0_soc.dram_clock_change_latency_us = 404.0;
+   dcn2_0_soc.dummy_pstate_latency_us = 5.0;
+   dcn2_0_soc.writeback_dram_clock_change_latency_us = 23.0;
+   dcn2_0_soc.return_bus_width_bytes = 64;
+   dcn2_0_soc.dispclk_dppclk_vco_speed_mhz = 3850;
+   dcn2_0_soc.xfc_bus_transport_time_us = 20;
+   dcn2_0_soc.xfc_xbuf_latency_tolerance_us = 4;
+   dcn2_0_soc.use_urgent_burst_bw = 0;
+   dcn2_0_soc.num_states = 5;
+
+   dcn2_0_soc.clock_limits[0].state = 0;
+   dcn2_0_soc.clock_limits[0].dcfclk_mhz = 560.0;
+   dcn2_0_soc.clock_limits[0].fabricclk_mhz = 560.0;
+   dcn2_0_soc.clock_limits[0].dispclk_mhz = 513.0;
+   dcn2_0_soc.clock_limits[0].dppclk_mhz = 513.0;
+   dcn2_0_soc.clock_limits[0].phyclk_mhz = 540.0;
+   dcn2_0_soc.clock_limits[0].socclk_mhz = 560.0;
+   dcn2_0_soc.clock_limits[0].dscclk_mhz = 171.0;
+   dcn2_0_soc.clock_limits[0].dram_speed_mts = 8960.0;
+
+   dcn2_0_soc.clock_limits[1].state = 1;
+   dcn2_0_soc.clock_limits[1].dcfclk_mhz = 694.0;
+   dcn2_0_soc.clock_limits[1].fabricclk_mhz = 694.0;
+   dcn2_0_soc.clock_limits[1].dispclk_mhz = 642.0;
+   dcn2_0_soc.clock_limits[1].dppclk_mhz = 642.0;
+   

Re: [PATCH RFC v4 16/16] drm/amdgpu: Integrate with DRM cgroup

[Kenny Ho]

Hey Joe,

I don't have all the answers right now but one thing I want to mention
is that, with cgroup, there's always a possibility for a user
configuration that lead to under resource for the application.  Your
comments certainly highlight the needs to make under-resource
situation obvious to debug.  (I want to write this down so I don't
forget also... :) I should probably have some dmesg for situation like
this.)  Thanks!

Regards,
Kenny

On Mon, Dec 2, 2019 at 5:05 PM Greathouse, Joseph
 wrote:
>
> > -Original Message-
> > From: Kenny Ho 
> > Sent: Friday, November 29, 2019 12:00 AM
> >
> > Reducing audience since this is AMD specific.
> >
> > On Tue, Oct 8, 2019 at 3:11 PM Kuehling, Felix  
> > wrote:
> > >
> > > On 2019-08-29 2:05 a.m., Kenny Ho wrote:
> > > > The number of logical gpu (lgpu) is defined to be the number of
> > > > compute unit (CU) for a device.  The lgpu allocation limit only
> > > > applies to compute workload for the moment (enforced via kfd queue
> > > > creation.)  Any cu_mask update is validated against the availability
> > > > of the compute unit as defined by the drmcg the kfd process belongs to.
> > >
> > > There is something missing here. There is an API for the application
> > > to specify a CU mask. Right now it looks like the
> > > application-specified and CGroup-specified CU masks would clobber each
> > > other. Instead the two should be merged.
> > >
> > > The CGroup-specified mask should specify a subset of CUs available for
> > > application-specified CU masks. When the cgroup CU mask changes, you'd
> > > need to take any application-specified CU masks into account before
> > > updating the hardware.
> > The idea behind the current implementation is to give sysadmin priority 
> > over user application (as that is the definition of control
> > group.)  Mask specified by applicatoin/user is validated by 
> > pqm_drmcg_lgpu_validate and rejected with EACCES if they are not
> > compatible.  The alternative is to ignore the difference and have the 
> > kernel guess/redistribute the assignment but I am not sure if this
> > is a good approach since there is not enough information to allow the 
> > kernel to guess the user's intention correctly consistently.  (This
> > is base on multiple conversations with you and Joe that, led me to believe, 
> > there are situation where spreading CU assignment across
> > multiple SE is a good thing but not always.)
> >
> > If the cgroup-specified mask is changed after the application has set the 
> > mask, the intersection of the two masks will be set instead.  It
> > is possible to have no intersection and in this case no CU is made 
> > available to the application (just like the possibility for memcgroup to
> > starve the amount of memory needed by an application.)
>
> I don't disagree with forcing a user to work within an lgpu's allocation. But 
> there's two minor problems here:
>
> 1) we will need a way for the process to query what the lgpu's bitmap looks 
> like. You and Felix are somewhat discussing this below, but I don't think the 
> KFD's "number of CUs" topology information is sufficient. I can know I have 
> 32 CUs, but I don't know which 32 bits in the bitmask are turned on. But your 
> code in pqm_drmcg_lgpu_validate() requires a subset when setting  CU mask on 
> an lgpu. A user needs to know what bits are on in the LGPU for this to work.
> 2) Even if we have a query API, do we have an easy way to prevent a data 
> race? Do we care? For instance, if I query the existing lgpu bitmap, then try 
> to set a CU mask on a subset of that, it's possible that the lgpu will change 
> between the query and set. That would make the setting fail, maybe that's 
> good enough (you can just try in a loop until it succeeds?)
>
> Do empty CU masks actually work? This seems like something we would want to 
> avoid. This could happen not infrequently if someone does something like:
> * lgpu with half the CUs enabled
> * User sets a mask to use half of those CUs
> * lgpu is changed to enable the other half of the CUS --> now the user's mask 
> is fully destroyed and everything dies. :\
>
> > > The KFD topology APIs report the number of available CUs to the
> > > application. CGroups would change that number at runtime and
> > > applications would not expect that. I think the best way to deal with
> > > that would be to have multiple bits in the application-specified CU
> > > mask map to the same CU. How to do that in a fair way is not obvious.
> > > I guess a more coarse-grain division of the GPU into LGPUs would make
> > > this somewhat easier.
> > Another possibility is to add namespace to the topology sysfs such that the 
> > correct number of CUs changes accordingly.  Although that
> > wouldn't give the user the available mask that is made available by this 
> > implementation via the cgroup sysfs.  Another possibility is to
> > modify the thunk similar to what was done for device cgroup (device
> > re-mapping.)
>
> I'd vote for 

Re: [RFC PATCH] drm/amdgpu: allocate entities on demand

[Nirmoy]

Hi Christian,

On 12/2/19 3:59 PM, Christian König wrote:

Am 02.12.19 um 15:43 schrieb Nirmoy:


Do you mean something like

diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index 684692a8ed76..ac67f8f098fa 100644
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@ -81,7 +81,7 @@ enum drm_sched_priority {
 struct drm_sched_entity {
    struct list_head    list;
    struct drm_sched_rq *rq;
-   struct drm_sched_rq **rq_list;
+  struct drm_gpu_scheduler    **sched;
    unsigned int    num_rq_list;
    spinlock_t  rq_lock;


Yes, exactly. Problem is that I'm not 100% sure if that really works 
with all users of the rq_list.


currently rq_list users does two main tasks.

1  change rq priority for a context on user requests

2  helps drm scheduler to find rq  with least load.

Can you please check the bellow diff it doesn't really work because I 
get some kernel panic. But do you think


it is matching your idea ?

test@install:~/linux> git diff drivers/gpu/drm/scheduler/sched_entity.c 
|tee
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c

index 1a5153197fe9..0bbd8ddd6c83 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -37,9 +37,9 @@
  * submit to HW ring.
  *
  * @entity: scheduler entity to init
- * @rq_list: the list of run queue on which jobs from this
+ * @sched_list: the list of drm scheds on which jobs from this
  *   entity can be submitted
- * @num_rq_list: number of run queue in rq_list
+ * @num_sched_list: number of drm sched in sched_list
  * @guilty: atomic_t set to 1 when a job on this queue
  *  is found to be guilty causing a timeout
  *
@@ -49,30 +49,24 @@
  * Returns 0 on success or a negative error code on failure.
  */
 int drm_sched_entity_init(struct drm_sched_entity *entity,
-              struct drm_sched_rq **rq_list,
-              unsigned int num_rq_list,
-              atomic_t *guilty)
+              struct drm_gpu_scheduler **sched_list,
+              unsigned int num_sched_list,
+              atomic_t *guilty, enum drm_sched_priority priority)
 {
-    int i;

-    if (!(entity && rq_list && (num_rq_list == 0 || rq_list[0])))
+    if (!(entity && sched_list && (num_sched_list == 0 || sched_list[0])))
         return -EINVAL;

     memset(entity, 0, sizeof(struct drm_sched_entity));
     INIT_LIST_HEAD(>list);
     entity->rq = NULL;
     entity->guilty = guilty;
-    entity->num_rq_list = num_rq_list;
-    entity->rq_list = kcalloc(num_rq_list, sizeof(struct drm_sched_rq *),
-                GFP_KERNEL);
-    if (!entity->rq_list)
-        return -ENOMEM;
-
-    for (i = 0; i < num_rq_list; ++i)
-        entity->rq_list[i] = rq_list[i];
+    entity->num_sched_list = num_sched_list;
+    entity->sched_list =  sched_list
+    entity->priority = priority;

-    if (num_rq_list)
-        entity->rq = rq_list[0];
+    if (num_sched_list)
+        entity->rq = >sched_list[0]->sched_rq[entity->priority];

     entity->last_scheduled = NULL;

@@ -136,10 +130,10 @@ drm_sched_entity_get_free_sched(struct 
drm_sched_entity *entity)

     unsigned int min_jobs = UINT_MAX, num_jobs;
     int i;

-    for (i = 0; i < entity->num_rq_list; ++i) {
-        struct drm_gpu_scheduler *sched = entity->rq_list[i]->sched;
+    for (i = 0; i < entity->num_sched_list; ++i) {
+        struct drm_gpu_scheduler *sched = entity->sched_list[i];

-        if (!entity->rq_list[i]->sched->ready) {
+        if (!entity->sched_list[i]->ready) {
             DRM_WARN("sched%s is not ready, skipping", sched->name);
             continue;
         }
@@ -147,7 +141,7 @@ drm_sched_entity_get_free_sched(struct 
drm_sched_entity *entity)

         num_jobs = atomic_read(>num_jobs);
         if (num_jobs < min_jobs) {
             min_jobs = num_jobs;
-            rq = entity->rq_list[i];
+            rq = >sched_list[i]->sched_rq[entity->priority];
         }
     }

@@ -304,7 +298,6 @@ void drm_sched_entity_fini(struct drm_sched_entity 
*entity)


     dma_fence_put(entity->last_scheduled);
     entity->last_scheduled = NULL;
-    kfree(entity->rq_list);
 }
 EXPORT_SYMBOL(drm_sched_entity_fini);

@@ -372,8 +365,9 @@ void drm_sched_entity_set_priority(struct 
drm_sched_entity *entity,

     unsigned int i;

     spin_lock(>rq_lock);
-
-    for (i = 0; i < entity->num_rq_list; ++i)
+//TODO
+/*
+    for (i = 0; i < entity->num_sched_list; ++i)
 drm_sched_entity_set_rq_priority(>rq_list[i], priority);

     if (entity->rq) {
@@ -381,7 +375,7 @@ void drm_sched_entity_set_priority(struct 
drm_sched_entity *entity,

         drm_sched_entity_set_rq_priority(>rq, priority);
         drm_sched_rq_add_entity(entity->rq, entity);
     }
-
+*/
     spin_unlock(>rq_lock);
 }
 EXPORT_SYMBOL(drm_sched_entity_set_priority);
@@ -486,7 +480,7 @@ void 

[PATCH] drm/amdkfd: Contain MMHUB number in mmhub_v9_4_setup_vm_pt_regs()

[Yong Zhao]

Adjust the exposed function prototype so that the caller does not need
to know the MMHUB number.

Change-Id: I4420d1715984f703954f074682b075fc59e2a330
Signed-off-by: Yong Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c |  6 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h |  8 
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c   | 14 --
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h   |  2 ++
 4 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 47c853ef1051..6f1a4676ddde 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -40,7 +40,7 @@
 #include "soc15d.h"
 #include "mmhub_v1_0.h"
 #include "gfxhub_v1_0.h"
-#include "gmc_v9_0.h"
+#include "mmhub_v9_4.h"
 
 
 enum hqd_dequeue_request_type {
@@ -774,9 +774,7 @@ void kgd_gfx_v9_set_vm_context_page_table_base(struct 
kgd_dev *kgd, uint32_t vmi
 * on GFX8 and older.
 */
if (adev->asic_type == CHIP_ARCTURUS) {
-   /* Two MMHUBs */
-   mmhub_v9_4_setup_vm_pt_regs(adev, 0, vmid, page_table_base);
-   mmhub_v9_4_setup_vm_pt_regs(adev, 1, vmid, page_table_base);
+   mmhub_v9_4_setup_vm_pt_regs(adev, vmid, page_table_base);
} else
mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
index 971c0840358f..49e8be761214 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
@@ -36,12 +36,4 @@
 
 extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
 extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
-
-/* amdgpu_amdkfd*.c */
-void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
-   uint64_t value);
-void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
-   uint64_t value);
-void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
-   uint32_t vmid, uint64_t value);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index 8599bfdb9a9e..d9301e80522a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -54,7 +54,7 @@ u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
return base;
 }
 
-void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
+static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int 
hubid,
uint32_t vmid, uint64_t value)
 {
/* two registers distance between mmVML2VC0_VM_CONTEXT0_* to
@@ -80,7 +80,7 @@ static void mmhub_v9_4_init_gart_aperture_regs(struct 
amdgpu_device *adev,
 {
uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 
-   mmhub_v9_4_setup_vm_pt_regs(adev, hubid, 0, pt_base);
+   mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base);
 
WREG32_SOC15_OFFSET(MMHUB, 0,
mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
@@ -101,6 +101,16 @@ static void mmhub_v9_4_init_gart_aperture_regs(struct 
amdgpu_device *adev,
(u32)(adev->gmc.gart_end >> 44));
 }
 
+void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
+   uint64_t page_table_base)
+{
+   int i;
+
+   for (i = 0; i < MMHUB_NUM_INSTANCES; i++)
+   mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid,
+   page_table_base);
+}
+
 static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
 int hubid)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
index 354a4b7e875b..1b979773776c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
@@ -34,5 +34,7 @@ void mmhub_v9_4_init(struct amdgpu_device *adev);
 int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
   enum amd_clockgating_state state);
 void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags);
+void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
+   uint64_t page_table_base);
 
 #endif
-- 
2.17.1

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[PATCH v8 17/17] drm/amd/display: Trigger modesets on MST DSC connectors

[mikita.lipski]

From: Mikita Lipski 

Whenever a connector on an MST network is attached, detached, or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stream did not change timing.

Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
for each crtc that shares a MST topology with that stream and
supports DSC, add that crtc (and all affected connectors and
planes) to the atomic state and set mode_changed on its state

v2: Do this check only on Navi and before adding connectors
and planes on modesetting crtcs

Cc: Leo Li 
Cc: Nicholas Kazlauskas 
Cc: Lyude Paul 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 +++
 1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2ac3a2f0b452..909665427110 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7930,6 +7930,29 @@ dm_determine_update_type_for_commit(struct 
amdgpu_display_manager *dm,
return ret;
 }
 
+static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct 
drm_crtc *crtc)
+{
+   struct drm_connector *connector;
+   struct drm_connector_state *conn_state;
+   struct amdgpu_dm_connector *aconnector = NULL;
+   int i;
+   for_each_new_connector_in_state(state, connector, conn_state, i) {
+   if (conn_state->crtc != crtc)
+   continue;
+
+   aconnector = to_amdgpu_dm_connector(connector);
+   if (!aconnector->port)
+   aconnector = NULL;
+   else
+   break;
+   }
+
+   if (!aconnector)
+   return 0;
+
+   return drm_dp_mst_add_affected_dsc_crtcs(state, >mst_mgr);
+}
+
 /**
  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
  * @dev: The DRM device
@@ -7982,6 +8005,16 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
 
+   if (adev->asic_type >= CHIP_NAVI10) {
+   for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 
new_crtc_state, i) {
+   if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
+   ret = add_affected_mst_dsc_crtcs(state, crtc);
+   if (ret)
+   goto fail;
+   }
+   }
+   }
+
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 
new_crtc_state, i) {
if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
!new_crtc_state->color_mgmt_changed &&
-- 
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[PATCH v8 15/17] drm/amd/display: Recalculate VCPI slots for new DSC connectors

[mikita.lipski]

From: Mikita Lipski 

[why]
Since for DSC MST connector's PBN is claculated differently
due to compression, we have to recalculate both PBN and
VCPI slots for that connector.

[how]
The function iterates through all the active streams to
find, which have DSC enabled, then recalculates PBN for
it and calls drm_dp_helper_update_vcpi_slots_for_dsc to
update connector's VCPI slots.

v2: - use drm_dp_mst_atomic_enable_dsc per port to
enable/disable DSC

v3: - Iterate through connector states from the state passed
- On each connector state get stream from dc_state,
instead CRTC state

Cc: Jerry Zuo 
Cc: Harry Wentland 
Cc: Lyude Paul 
Cc: Manasi Navare 
Signed-off-by: Mikita Lipski 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 76 +--
 1 file changed, 71 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 93a230d956ee..2ac3a2f0b452 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4986,6 +4986,69 @@ const struct drm_encoder_helper_funcs 
amdgpu_dm_encoder_helper_funcs = {
.atomic_check = dm_encoder_helper_atomic_check
 };
 
+static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
+   struct dc_state *dc_state)
+{
+   struct dc_stream_state *stream = NULL;
+   struct drm_connector *connector;
+   struct drm_connector_state *new_con_state, *old_con_state;
+   struct amdgpu_dm_connector *aconnector;
+   struct dm_connector_state *dm_conn_state;
+   int i, j, clock, bpp;
+   int vcpi, pbn_div, pbn = 0;
+
+   for_each_oldnew_connector_in_state(state, connector, old_con_state, 
new_con_state, i) {
+
+   aconnector = to_amdgpu_dm_connector(connector);
+
+   if (!aconnector->port)
+   continue;
+
+   if (!new_con_state || !new_con_state->crtc)
+   continue;
+
+   dm_conn_state = to_dm_connector_state(new_con_state);
+
+   for (j = 0; j < dc_state->stream_count; j++) {
+   stream = dc_state->streams[j];
+   if (!stream)
+   continue;
+
+   if ((struct 
amdgpu_dm_connector*)stream->dm_stream_context == aconnector)
+   break;
+
+   stream = NULL;
+   }
+
+   if (!stream)
+   continue;
+
+   if (stream->timing.flags.DSC != 1) {
+   drm_dp_mst_atomic_enable_dsc(state,
+aconnector->port,
+dm_conn_state->pbn,
+0,
+false);
+   continue;
+   }
+
+   pbn_div = dm_mst_get_pbn_divider(stream->link);
+   bpp = stream->timing.dsc_cfg.bits_per_pixel;
+   clock = stream->timing.pix_clk_100hz / 10;
+   pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
+   vcpi = drm_dp_mst_atomic_enable_dsc(state,
+   aconnector->port,
+   pbn, pbn_div,
+   true);
+   if (vcpi < 0)
+   return vcpi;
+
+   dm_conn_state->pbn = pbn;
+   dm_conn_state->vcpi_slots = vcpi;
+   }
+   return 0;
+}
+
 static void dm_drm_plane_reset(struct drm_plane *plane)
 {
struct dm_plane_state *amdgpu_state = NULL;
@@ -8022,11 +8085,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
 
-   /* Perform validation of MST topology in the state*/
-   ret = drm_dp_mst_atomic_check(state);
-   if (ret)
-   goto fail;
-
if (state->legacy_cursor_update) {
/*
 * This is a fast cursor update coming from the plane update
@@ -8098,6 +8156,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (!compute_mst_dsc_configs_for_state(state, 
dm_state->context))
goto fail;
 
+   ret = dm_update_mst_vcpi_slots_for_dsc(state, 
dm_state->context);
+   if (ret)
+   goto fail;
+
if (dc_validate_global_state(dc, dm_state->context, false) != 
DC_OK) {
ret = -EINVAL;
goto fail;
@@ -8126,6 +8188,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
dc_retain_state(old_dm_state->context);
}
}
+   /* Perform validation of MST topology in the state*/
+   

[PATCH v8 16/17] drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs

[mikita.lipski]

From: Mikita Lipski 

[why]
Whenever a connector on an MST network is changed or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stream did not change timing.

[how]
Adding helper to trigger modesets on MST DSC connectors
by setting mode_changed flag on CRTCs in the same topology
as affected connector

v2: use drm_dp_mst_dsc_aux_for_port function to verify
if the port is DSC capable

Cc: Manasi Navare 
Cc: Lyude Paul 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 62 +++
 include/drm/drm_dp_mst_helper.h   |  2 +
 2 files changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 76bcbb4cd8b4..fb3710b727cc 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4802,6 +4802,68 @@ drm_dp_mst_atomic_check_topology_state(struct 
drm_dp_mst_topology_mgr *mgr,
return 0;
 }
 
+/**
+ * drm_dp_mst_add_affected_dsc_crtcs
+ * @state: Pointer to the new  drm_dp_mst_topology_state
+ * @port: Pointer tothe port of connector with new state
+ *
+ * Whenever there is a change in mst topology
+ * DSC configuration would have to be recalculated
+ * therefore we need to trigger modeset on all affected
+ * CRTCs in that topology
+ *
+ * See also:
+ * drm_dp_mst_atomic_enable_dsc()
+ */
+int drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_state *state, struct 
drm_dp_mst_topology_mgr *mgr)
+{
+   struct drm_dp_mst_topology_state *mst_state;
+   struct drm_dp_vcpi_allocation *pos;
+   struct drm_connector *connector;
+   struct drm_connector_state *conn_state;
+   struct drm_crtc *crtc;
+   struct drm_crtc_state *crtc_state;
+
+   if (!mgr) {
+   DRM_DEBUG_ATOMIC("[MST MGR:%p] Passed Topology Manager pointer 
is pointing to NULL\n", mgr);
+   return -EINVAL;
+   }
+
+   mst_state = drm_atomic_get_mst_topology_state(state, mgr);
+
+   list_for_each_entry(pos, _state->vcpis, next) {
+
+   connector = pos->port->connector;
+
+   if (!connector)
+   return -EINVAL;
+
+   conn_state = drm_atomic_get_connector_state(state, connector);
+
+   if (IS_ERR(conn_state))
+   return PTR_ERR(conn_state);
+
+   crtc = conn_state->crtc;
+
+   if (!crtc)
+   return -EINVAL;
+
+   if (!drm_dp_mst_dsc_aux_for_port(pos->port))
+   continue;
+
+   crtc_state = drm_atomic_get_crtc_state(mst_state->base.state, 
crtc);
+
+   if (IS_ERR(crtc_state))
+   return PTR_ERR(crtc_state);
+
+   DRM_DEBUG_ATOMIC("[MST MGR:%p] Setting mode_changed flag on 
CRTC %p\n", mgr, crtc);
+
+   crtc_state->mode_changed = true;
+   }
+   return 0;
+}
+EXPORT_SYMBOL(drm_dp_mst_add_affected_dsc_crtcs);
+
 /**
  * drm_dp_mst_atomic_enable_dsc - Set DSC Enable Flag to On/Off
  * @state: Pointer to the new drm_atomic_state
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 2919d9776af3..10e9c7049061 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -779,6 +779,8 @@ int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state 
*state,
 struct drm_dp_mst_port *port,
 int pbn, int pbn_div,
 bool enable);
+int drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr);
 int __must_check
 drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state,
 struct drm_dp_mst_topology_mgr *mgr,
-- 
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[PATCH v8 10/17] drm/dp_mst: Manually overwrite PBN divider for calculating timeslots

[mikita.lipski]

From: Mikita Lipski 

[why]
For DSC case we cannot always use topology manager's PBN divider
variable. The default divider does not take FEC into account.
Therefore we should allow driver to calculate its own divider based
on the link rate and count its handling, as it is hw specific.
[how]
Pass pbn_div as an argument, which will be used if its more than
zero, otherwise default topology manager's pbn_div will be used.

Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
 drivers/gpu/drm/drm_dp_mst_topology.c | 9 +++--
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 2 +-
 drivers/gpu/drm/nouveau/dispnv50/disp.c   | 3 ++-
 include/drm/drm_dp_mst_helper.h   | 3 ++-
 5 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9fc03fc1017d..753a79734817 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4972,7 +4972,8 @@ static int dm_encoder_helper_atomic_check(struct 
drm_encoder *encoder,
dm_new_connector_state->vcpi_slots = 
drm_dp_atomic_find_vcpi_slots(state,
   
mst_mgr,
   
mst_port,
-  
dm_new_connector_state->pbn);
+  
dm_new_connector_state->pbn,
+  0);
if (dm_new_connector_state->vcpi_slots < 0) {
DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", 
(int)dm_new_connector_state->vcpi_slots);
return dm_new_connector_state->vcpi_slots;
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 018921c4ba98..f1d883960831 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4020,6 +4020,7 @@ static int drm_dp_init_vcpi(struct 
drm_dp_mst_topology_mgr *mgr,
  * @mgr: MST topology manager for the port
  * @port: port to find vcpi slots for
  * @pbn: bandwidth required for the mode in PBN
+ * @pbn_div: divider for DSC mode that takes FEC into account
  *
  * Allocates VCPI slots to @port, replacing any previous VCPI allocations it
  * may have had. Any atomic drivers which support MST must call this function
@@ -4046,7 +4047,8 @@ static int drm_dp_init_vcpi(struct 
drm_dp_mst_topology_mgr *mgr,
  */
 int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
  struct drm_dp_mst_topology_mgr *mgr,
- struct drm_dp_mst_port *port, int pbn)
+ struct drm_dp_mst_port *port, int pbn,
+ int pbn_div)
 {
struct drm_dp_mst_topology_state *topology_state;
struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
@@ -4079,7 +4081,10 @@ int drm_dp_atomic_find_vcpi_slots(struct 
drm_atomic_state *state,
if (!vcpi)
prev_slots = 0;
 
-   req_slots = DIV_ROUND_UP(pbn, mgr->pbn_div);
+   if (pbn_div <= 0)
+   pbn_div = mgr->pbn_div;
+
+   req_slots = DIV_ROUND_UP(pbn, pbn_div);
 
DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] VCPI %d -> %d\n",
 port->connector->base.id, port->connector->name,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 92be17711287..a068f54a6793 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -65,7 +65,7 @@ static int intel_dp_mst_compute_link_config(struct 
intel_encoder *encoder,
   false);
 
slots = drm_dp_atomic_find_vcpi_slots(state, _dp->mst_mgr,
- port, crtc_state->pbn);
+ port, crtc_state->pbn, 0);
if (slots == -EDEADLK)
return slots;
if (slots >= 0)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c 
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 1c9e23d5a6fd..edb78966c5b6 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -787,7 +787,8 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
 
slots = drm_dp_atomic_find_vcpi_slots(state, >mgr,
  mstc->port,
- asyh->dp.pbn);
+ asyh->dp.pbn,
+ 0);
 

[PATCH v8 12/17] drm/dp_mst: Add branch bandwidth validation to MST atomic check

[mikita.lipski]

From: Mikita Lipski 

Adding PBN attribute to drm_dp_vcpi_allocation structure to
keep track of how much bandwidth each Port requires.
Adding drm_dp_mst_atomic_check_bw_limit to verify that
state's bandwidth needs doesn't exceed available bandwidth.
The funtion is called in drm_dp_mst_atomic_check after
drm_dp_mst_atomic_check_topology_state to fully verify that
the proposed topology is supported.

Cc: Jerry Zuo 
Cc: Harry Wentland 
Cc: Lyude Paul 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 67 ++-
 include/drm/drm_dp_mst_helper.h   |  1 +
 2 files changed, 66 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 5e549f48ffb8..76bcbb4cd8b4 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4052,7 +4052,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state 
*state,
 {
struct drm_dp_mst_topology_state *topology_state;
struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
-   int prev_slots, req_slots;
+   int prev_slots, prev_bw, req_slots, ret;
 
topology_state = drm_atomic_get_mst_topology_state(state, mgr);
if (IS_ERR(topology_state))
@@ -4063,6 +4063,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state 
*state,
if (pos->port == port) {
vcpi = pos;
prev_slots = vcpi->vcpi;
+   prev_bw = vcpi->pbn;
 
/*
 * This should never happen, unless the driver tries
@@ -4078,8 +4079,10 @@ int drm_dp_atomic_find_vcpi_slots(struct 
drm_atomic_state *state,
break;
}
}
-   if (!vcpi)
+   if (!vcpi) {
prev_slots = 0;
+   prev_bw = 0;
+   }
 
if (pbn_div <= 0)
pbn_div = mgr->pbn_div;
@@ -4089,6 +4092,9 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state 
*state,
DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] VCPI %d -> %d\n",
 port->connector->base.id, port->connector->name,
 port, prev_slots, req_slots);
+   DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] PBN %d -> %d\n",
+port->connector->base.id, port->connector->name,
+port, prev_bw, pbn);
 
/* Add the new allocation to the state */
if (!vcpi) {
@@ -4101,6 +4107,7 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state 
*state,
list_add(>next, _state->vcpis);
}
vcpi->vcpi = req_slots;
+   vcpi->pbn = pbn;
 
return req_slots;
 }
@@ -4703,6 +4710,59 @@ static void drm_dp_mst_destroy_state(struct 
drm_private_obj *obj,
kfree(mst_state);
 }
 
+static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
+struct drm_dp_mst_branch 
*branch)
+{
+   while (port->parent) {
+   if (port->parent == branch)
+   return true;
+
+   if (port->parent->port_parent)
+   port = port->parent->port_parent;
+   else
+   break;
+   }
+   return false;
+}
+
+static inline
+int drm_dp_mst_atomic_check_bw_limit(struct drm_dp_mst_branch *branch,
+struct drm_dp_mst_topology_state 
*mst_state)
+{
+   struct drm_dp_mst_port *port;
+   struct drm_dp_vcpi_allocation *vcpi;
+   int pbn_limit = 0, pbn_used = 0;
+
+   list_for_each_entry(port, >ports, next) {
+   if (port->mstb) {
+   if (drm_dp_mst_atomic_check_bw_limit(port->mstb, 
mst_state))
+   return -EINVAL;
+   }
+   if (port->available_pbn > 0)
+   pbn_limit = port->available_pbn;
+   }
+   DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch has %d PBN available\n",
+branch,
+pbn_limit);
+
+   list_for_each_entry(vcpi, _state->vcpis, next) {
+   if (!vcpi->pbn)
+   continue;
+
+   if (drm_dp_mst_port_downstream_of_branch(vcpi->port, branch))
+   pbn_used += vcpi->pbn;
+   }
+   DRM_DEBUG_ATOMIC("[MST BRANCH:%p] branch used %d PBN\n",
+branch,
+pbn_used);
+   if (pbn_used > pbn_limit) {
+   DRM_DEBUG_ATOMIC("[MST BRANCH:%p] No available bandwidth\n",
+branch);
+   return -EINVAL;
+   }
+   return 0;
+}
+
 static inline int
 drm_dp_mst_atomic_check_topology_state(struct drm_dp_mst_topology_mgr *mgr,
   struct drm_dp_mst_topology_state 
*mst_state)
@@ -4834,6 

[PATCH v8 07/17] drm/amd/display: Initialize DSC PPS variables to 0

[mikita.lipski]

From: David Francis 

For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.

memset to 0 to avoid this

Reviewed-by: Nicholas Kazlauskas 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c   | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index bb1e8e5b5252..a7f3a9ecc626 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -526,6 +526,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool 
enable)
struct dsc_config dsc_cfg;
uint8_t dsc_packed_pps[128];
 
+   memset(_cfg, 0, sizeof(dsc_cfg));
+   memset(dsc_packed_pps, 0, 128);
+
/* Enable DSC hw block */
dsc_cfg.pic_width = stream->timing.h_addressable + 
stream->timing.h_border_left + stream->timing.h_border_right;
dsc_cfg.pic_height = stream->timing.v_addressable + 
stream->timing.v_border_top + stream->timing.v_border_bottom;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 0111545dac75..6bdfee20b6a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -206,6 +206,9 @@ static bool dsc2_get_packed_pps(struct 
display_stream_compressor *dsc, const str
struct dsc_reg_values dsc_reg_vals;
struct dsc_optc_config dsc_optc_cfg;
 
+   memset(_reg_vals, 0, sizeof(dsc_reg_vals));
+   memset(_optc_cfg, 0, sizeof(dsc_optc_cfg));
+
DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
dsc_config_log(dsc, dsc_cfg);
DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
-- 
2.17.1

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[PATCH v8 06/17] drm/dp_mst: Add new quirk for Synaptics MST hubs

[mikita.lipski]

From: Mikita Lipski 

Synaptics DP1.4 hubs (BRANCH_ID 0x90CC24) do not
support virtual DPCD registers, but do support DSC.
The DSC caps can be read from the physical aux,
like in SST DSC. These hubs have many different
DEVICE_IDs.  Add a new quirk to detect this case.

Reviewed-by: Wenjing Liu 
Reviewed-by: Lyude Paul 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/drm_dp_helper.c   |  2 ++
 drivers/gpu/drm/drm_dp_mst_topology.c | 27 +++
 include/drm/drm_dp_helper.h   |  7 +++
 3 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2faef8bd911f..374cedc6c2ac 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1165,6 +1165,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, 
BIT(DP_DPCD_QUIRK_NO_PSR) },
/* CH7511 seems to leave SINK_COUNT zeroed */
{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), 
false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
+   /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
+   { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, 
BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
 };
 
 #undef OUI
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 9df02090aa9f..018921c4ba98 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -5101,6 +5101,7 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct 
drm_dp_mst_port *port)
 {
struct drm_dp_mst_port *immediate_upstream_port;
struct drm_dp_mst_port *fec_port;
+   struct drm_dp_desc desc = { 0 };
 
if (!port)
return NULL;
@@ -5153,6 +5154,32 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct 
drm_dp_mst_port *port)
if (drm_dp_mst_is_virtual_dpcd(port))
return >aux;
 
+   /*
+* Synaptics quirk
+* Applies to ports for which:
+* - Physical aux has Synaptics OUI
+* - DPv1.4 or higher
+* - Port is on primary branch device
+* - Not a VGA adapter (DP_DWN_STRM_PORT_TYPE_ANALOG)
+*/
+   if (!drm_dp_read_desc(port->mgr->aux, , true))
+   return NULL;
+
+   if (drm_dp_has_quirk(, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&
+   port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
+   port->parent == port->mgr->mst_primary) {
+   u8 downstreamport;
+
+   if (drm_dp_dpcd_read(>aux, DP_DOWNSTREAMPORT_PRESENT,
+, 1) < 0)
+   return NULL;
+
+   if ((downstreamport & DP_DWN_STRM_PORT_PRESENT) &&
+  ((downstreamport & DP_DWN_STRM_PORT_TYPE_MASK)
+!= DP_DWN_STRM_PORT_TYPE_ANALOG))
+   return port->mgr->aux;
+   }
+
return NULL;
 }
 EXPORT_SYMBOL(drm_dp_mst_dsc_aux_for_port);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 51ecb5112ef8..e63cd508882b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1520,6 +1520,13 @@ enum drm_dp_quirk {
 * The driver should ignore SINK_COUNT during detection.
 */
DP_DPCD_QUIRK_NO_SINK_COUNT,
+   /**
+* @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
+*
+* The device supports MST DSC despite not supporting Virtual DPCD.
+* The DSC caps can be read from the physical aux instead.
+*/
+   DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
 };
 
 /**
-- 
2.17.1

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[PATCH v8 13/17] drm/amd/display: Add PBN per slot calculation for DSC

[mikita.lipski]

From: Mikita Lipski 

[why]
Need to calculate VCPI slots differently for DSC
to take in account current link rate, link count
and FEC.
[how]
Add helper to get pbn_div from dc_link

Signed-off-by: Mikita Lipski 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c   | 8 
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h   | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 7557edee7db0..c376c8ccd391 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -491,3 +491,11 @@ void amdgpu_dm_initialize_dp_connector(struct 
amdgpu_display_manager *dm,
aconnector->connector_id);
 }
 
+int dm_mst_get_pbn_divider(struct dc_link *link)
+{
+   if (!link)
+   return 0;
+
+   return dc_link_bandwidth_kbps(link,
+   dc_link_get_link_cap(link)) / (8 * 1000 * 54);
+}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 2da851b40042..a553ea046185 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -29,6 +29,8 @@
 struct amdgpu_display_manager;
 struct amdgpu_dm_connector;
 
+int dm_mst_get_pbn_divider(struct dc_link *link);
+
 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
   struct amdgpu_dm_connector *aconnector);
 
-- 
2.17.1

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[PATCH v8 11/17] drm/dp_mst: Add DSC enablement helpers to DRM

[mikita.lipski]

From: Mikita Lipski 

Adding a helper function to be called by
drivers outside of DRM to enable DSC on
the MST ports.

Function is called to recalculate VCPI allocation
if DSC is enabled and raise the DSC flag to enable.
In case of disabling DSC the flag is set to false
and recalculation of VCPI slots is expected to be done
in encoder's atomic_check.

v2: squash separate functions into one and call it per
port

Cc: Harry Wentland 
Cc: Lyude Paul 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 61 +++
 include/drm/drm_dp_mst_helper.h   |  5 +++
 2 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index f1d883960831..5e549f48ffb8 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4742,6 +4742,67 @@ drm_dp_mst_atomic_check_topology_state(struct 
drm_dp_mst_topology_mgr *mgr,
return 0;
 }
 
+/**
+ * drm_dp_mst_atomic_enable_dsc - Set DSC Enable Flag to On/Off
+ * @state: Pointer to the new drm_atomic_state
+ * @pointer: Pointer to the affected MST Port
+ * @pbn: Newly recalculated bw required for link with DSC enabled
+ * @pbn_div: Divider to calculate correct number of pbn per slot
+ * @enable: Boolean flag enabling or disabling DSC on the port
+ *
+ * This function enables DSC on the given Port
+ * by recalculating its vcpi from pbn provided
+ * and sets dsc_enable flag to keep track of which
+ * ports have DSC enabled
+ *
+ */
+int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state,
+struct drm_dp_mst_port *port,
+int pbn, int pbn_div,
+bool enable)
+{
+   struct drm_dp_mst_topology_state *mst_state;
+   struct drm_dp_vcpi_allocation *pos;
+   bool found = false;
+   int vcpi = 0;
+
+   mst_state = drm_atomic_get_mst_topology_state(state, port->mgr);
+
+   if (IS_ERR(mst_state))
+   return PTR_ERR(mst_state);
+
+   list_for_each_entry(pos, _state->vcpis, next) {
+   if (pos->port == port) {
+   found = true;
+   break;
+   }
+   }
+
+   if (!found) {
+   DRM_DEBUG_ATOMIC("[MST PORT:%p] Couldn't find VCPI allocation 
in mst state %p\n",
+port, mst_state);
+   return -EINVAL;
+   }
+
+   if (pos->dsc_enabled == enable) {
+   DRM_DEBUG_ATOMIC("[MST PORT:%p] DSC flag is already set to %d, 
returning %d VCPI slots\n",
+port, enable, pos->vcpi);
+   vcpi = pos->vcpi;
+   }
+
+   if (enable) {
+   vcpi = drm_dp_atomic_find_vcpi_slots(state, port->mgr, port, 
pbn, pbn_div);
+   DRM_DEBUG_ATOMIC("[MST PORT:%p] Enabling DSC flag, reallocating 
%d VCPI slots on the port\n",
+port, vcpi);
+   if (vcpi < 0)
+   return -EINVAL;
+   }
+
+   pos->dsc_enabled = enable;
+
+   return vcpi;
+}
+EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
 /**
  * drm_dp_mst_atomic_check - Check that the new state of an MST topology in an
  * atomic update is valid
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 0f813d6346aa..830c94b7f45d 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -502,6 +502,7 @@ struct drm_dp_payload {
 struct drm_dp_vcpi_allocation {
struct drm_dp_mst_port *port;
int vcpi;
+   bool dsc_enabled;
struct list_head next;
 };
 
@@ -773,6 +774,10 @@ drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state 
*state,
  struct drm_dp_mst_topology_mgr *mgr,
  struct drm_dp_mst_port *port, int pbn,
  int pbn_div);
+int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state,
+struct drm_dp_mst_port *port,
+int pbn, int pbn_div,
+bool enable);
 int __must_check
 drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state,
 struct drm_dp_mst_topology_mgr *mgr,
-- 
2.17.1

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[PATCH v8 03/17] drm/dp_mst: Add MST support to DP DPCD R/W functions

[mikita.lipski]

From: David Francis 

Instead of having drm_dp_dpcd_read/write and
drm_dp_mst_dpcd_read/write as entry points into the
aux code, have drm_dp_dpcd_read/write handle both.

This means that DRM drivers can make MST DPCD read/writes.

v2: Fix spacing
v3: Dump dpcd access on MST read/writes
v4: Fix calling wrong function on DPCD write
v5: delete deprecated include of drmP.h

Reviewed-by: Lyude Paul 
Reviewed-by: Harry Wentland 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/drm_dp_aux_dev.c | 12 ++--
 drivers/gpu/drm/drm_dp_helper.c  | 30 --
 2 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_aux_dev.c b/drivers/gpu/drm/drm_dp_aux_dev.c
index 0cfb386754c3..2510717d5a08 100644
--- a/drivers/gpu/drm/drm_dp_aux_dev.c
+++ b/drivers/gpu/drm/drm_dp_aux_dev.c
@@ -163,11 +163,7 @@ static ssize_t auxdev_read_iter(struct kiocb *iocb, struct 
iov_iter *to)
break;
}
 
-   if (aux_dev->aux->is_remote)
-   res = drm_dp_mst_dpcd_read(aux_dev->aux, pos, buf,
-  todo);
-   else
-   res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
+   res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
 
if (res <= 0)
break;
@@ -215,11 +211,7 @@ static ssize_t auxdev_write_iter(struct kiocb *iocb, 
struct iov_iter *from)
break;
}
 
-   if (aux_dev->aux->is_remote)
-   res = drm_dp_mst_dpcd_write(aux_dev->aux, pos, buf,
-   todo);
-   else
-   res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
+   res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
 
if (res <= 0)
break;
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2c7870aef469..2faef8bd911f 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -32,6 +32,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "drm_crtc_helper_internal.h"
 
@@ -266,7 +267,7 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 
request,
 
 /**
  * drm_dp_dpcd_read() - read a series of bytes from the DPCD
- * @aux: DisplayPort AUX channel
+ * @aux: DisplayPort AUX channel (SST or MST)
  * @offset: address of the (first) register to read
  * @buffer: buffer to store the register values
  * @size: number of bytes in @buffer
@@ -295,13 +296,18 @@ ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned 
int offset,
 * We just have to do it before any DPCD access and hope that the
 * monitor doesn't power down exactly after the throw away read.
 */
-   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer,
-1);
-   if (ret != 1)
-   goto out;
+   if (!aux->is_remote) {
+   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
+buffer, 1);
+   if (ret != 1)
+   goto out;
+   }
 
-   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
-size);
+   if (aux->is_remote)
+   ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
+   else
+   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
+buffer, size);
 
 out:
drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
@@ -311,7 +317,7 @@ EXPORT_SYMBOL(drm_dp_dpcd_read);
 
 /**
  * drm_dp_dpcd_write() - write a series of bytes to the DPCD
- * @aux: DisplayPort AUX channel
+ * @aux: DisplayPort AUX channel (SST or MST)
  * @offset: address of the (first) register to write
  * @buffer: buffer containing the values to write
  * @size: number of bytes in @buffer
@@ -328,8 +334,12 @@ ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned 
int offset,
 {
int ret;
 
-   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
-size);
+   if (aux->is_remote)
+   ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
+   else
+   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
+buffer, size);
+
drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
return ret;
 }
-- 
2.17.1

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[PATCH v8 14/17] drm/amd/display: MST DSC compute fair share

[mikita.lipski]

From: David Francis 

If there is limited link bandwidth on a MST network,
it must be divided fairly between the streams on that network

Implement an algorithm to determine the correct DSC config
for each stream

The algorithm:
This
 [   ]  ( )
represents the range of bandwidths possible for a given stream.
The [] area represents the range of DSC configs, and the ()
represents no DSC. The bandwidth used increases from left to right.

First, try disabling DSC on all streams
 [  ]  (|)
 [ ](|)
Check this against the bandwidth limits of the link and each branch
(including each endpoint). If it passes, the job is done

Second, try maximum DSC compression on all streams
that support DSC
 [| ]( )
 [|] ( )
If this does not pass, then enabling this combination of streams
is impossible

Otherwise, divide the remaining bandwidth evenly amongst the streams
 [|  ] ( )
 [|  ]( )

If one or more of the streams reach minimum compression, evenly
divide the reamining bandwidth amongst the remaining streams
 [|] ( )
 [   |]   ( )
 [ |   ]   ( )
 [ |  ]  ( )

If all streams can reach minimum compression, disable compression
greedily
 [  |]  ( )
 [|]( )
 [ ](|)

Perform this algorithm on each full update, on each MST link
with at least one DSC stream on it

After the configs are computed, call
dcn20_add_dsc_to_stream_resource on each stream with DSC enabled.
It is only after all streams are created that we can know which
of them will need DSC.

Do all of this at the end of amdgpu atomic check.  If it fails,
fail check; This combination of timings cannot be supported.

v2: Use drm_dp_mst_atomic_check to validate bw for certain dsc
configurations

v3: Use dc_dsc_policy structure to get min and max bpp rate
for DSC configuration

Cc: Lyude Paul 
Cc: Manasi Navare 
Reviewed-by: Wenjing Liu 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   3 +
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 364 ++
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   3 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
 5 files changed, 376 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 753a79734817..93a230d956ee 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8095,6 +8095,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
 
+   if (!compute_mst_dsc_configs_for_state(state, 
dm_state->context))
+   goto fail;
+
if (dc_validate_global_state(dc, dm_state->context, false) != 
DC_OK) {
ret = -EINVAL;
goto fail;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index c376c8ccd391..6d13d1c33530 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -40,6 +40,10 @@
 #if defined(CONFIG_DEBUG_FS)
 #include "amdgpu_dm_debugfs.h"
 #endif
+
+
+#include "dc/dcn20/dcn20_resource.h"
+
 /* #define TRACE_DPCD */
 
 #ifdef TRACE_DPCD
@@ -499,3 +503,363 @@ int dm_mst_get_pbn_divider(struct dc_link *link)
return dc_link_bandwidth_kbps(link,
dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 }
+
+struct dsc_mst_fairness_params {
+   struct dc_crtc_timing *timing;
+   struct dc_sink *sink;
+   struct dc_dsc_bw_range bw_range;
+   bool compression_possible;
+   struct drm_dp_mst_port *port;
+};
+
+struct dsc_mst_fairness_vars {
+   int pbn;
+   bool dsc_enabled;
+   int bpp_x16;
+};
+
+static int kbps_to_peak_pbn(int kbps)
+{
+   u64 peak_kbps = kbps;
+
+   peak_kbps *= 1006;
+   peak_kbps /= 1000;
+   return (int) DIV_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
+}
+
+static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params 
*params,
+   struct dsc_mst_fairness_vars *vars,
+   int count)
+{
+   int i;
+
+   for (i = 0; i < count; i++) {
+   memset([i].timing->dsc_cfg, 0, 
sizeof(params[i].timing->dsc_cfg));
+   if (vars[i].dsc_enabled && dc_dsc_compute_config(
+   
params[i].sink->ctx->dc->res_pool->dscs[0],
+   
[i].sink->sink_dsc_caps.dsc_dec_caps,
+

[PATCH v8 00/17] DSC MST support for DRM and AMDGPU

[mikita.lipski]

From: Mikita Lipski 

This set of patches is a continuation of DSC enablement
patches for AMDGPU. This set enables DSC on MST. It also
contains implementation of both encoder and connector
atomic check routines.

These patches have been introduced in multiple
iterations to the mailing list before. These patches were
developed by David Francis as part of his work on DSC.

v2: squashed previously 3 separate atomic check patches,
separate atomic check for dsc connectors, track vcpi and
pbn on connectors.

v3: Moved modeset trigger on affected MST displays to DRM

v4: Fix warnings, use current mode's bpc rather than display's
maximum capable one

v5: Moving branch's bandwidth validation to DRM,
Added function to enable DSC per port in DRM

v6: Compute fair share uses DRM helper for BW validation

v7: Add helper to overwrite PBN divider per slot,
Add helper function to trigger modeset on affected DSC connectors
in DRM

v8: Rebased on top of the MST refactor patches that were on DRM-tip
Some cosmetic and cleanup changes

David Francis (9):
  drm/dp_mst: Add PBN calculation for DSC modes
  drm/dp_mst: Parse FEC capability on MST ports
  drm/dp_mst: Add MST support to DP DPCD R/W functions
  drm/dp_mst: Fill branch->num_ports
  drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux
  drm/amd/display: Initialize DSC PPS variables to 0
  drm/amd/display: Validate DSC caps on MST endpoints
  drm/amd/display: Write DSC enable to MST DPCD
  drm/amd/display: MST DSC compute fair share

Mikita Lipski (8):
  drm/dp_mst: Add new quirk for Synaptics MST hubs
  drm/dp_mst: Manually overwrite PBN divider for calculating timeslots
  drm/dp_mst: Add DSC enablement helpers to DRM
  drm/dp_mst: Add branch bandwidth validation to MST atomic check
  drm/amd/display: Add PBN per slot calculation for DSC
  drm/amd/display: Recalculate VCPI slots for new DSC connectors
  drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs
  drm/amd/display: Trigger modesets on MST DSC connectors

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 117 -
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  19 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 399 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   5 +
 .../drm/amd/display/dc/core/dc_link_hwss.c|   3 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |   3 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
 drivers/gpu/drm/drm_dp_aux_dev.c  |  12 +-
 drivers/gpu/drm/drm_dp_helper.c   |  32 +-
 drivers/gpu/drm/drm_dp_mst_topology.c | 395 -
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   5 +-
 drivers/gpu/drm/nouveau/dispnv50/disp.c   |   5 +-
 drivers/gpu/drm/radeon/radeon_dp_mst.c|   2 +-
 include/drm/drm_dp_helper.h   |   7 +
 include/drm/drm_dp_mst_helper.h   |  19 +-
 17 files changed, 988 insertions(+), 44 deletions(-)

-- 
2.17.1

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[PATCH v8 05/17] drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux

[mikita.lipski]

From: David Francis 

Add drm_dp_mst_dsc_aux_for_port. To enable DSC, the DSC_ENABLED
register might have to be written on the leaf port's DPCD,
its parent's DPCD, or the MST manager's DPCD. This function
finds the correct aux for the job.

As part of this, add drm_dp_mst_is_virtual_dpcd. Virtual DPCD
is a DP feature new in DP v1.4, which exposes certain DPCD
registers on virtual ports.

v2: Remember to unlock mutex on all paths
v3: Refactor to match coding style and increase brevity

Reviewed-by: Lyude Paul 
Reviewed-by: Wenjing Liu 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 127 ++
 include/drm/drm_dp_mst_helper.h   |   2 +
 2 files changed, 129 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index d74b767d0fe1..9df02090aa9f 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -5029,3 +5029,130 @@ static void drm_dp_mst_unregister_i2c_bus(struct 
drm_dp_aux *aux)
 {
i2c_del_adapter(>ddc);
 }
+
+/**
+ * drm_dp_mst_is_virtual_dpcd() - Is the given port a virtual DP Peer Device
+ * @port: The port to check
+ *
+ * A single physical MST hub object can be represented in the topology
+ * by multiple branches, with virtual ports between those branches.
+ *
+ * As of DP1.4, An MST hub with internal (virtual) ports must expose
+ * certain DPCD registers over those ports. See sections 2.6.1.1.1
+ * and 2.6.1.1.2 of Display Port specification v1.4 for details.
+ *
+ * May acquire mgr->lock
+ *
+ * Returns:
+ * true if the port is a virtual DP peer device, false otherwise
+ */
+static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port)
+{
+   struct drm_dp_mst_port *downstream_port;
+
+   if (!port || port->dpcd_rev < DP_DPCD_REV_14)
+   return false;
+
+   /* Virtual DP Sink (Internal Display Panel) */
+   if (port->port_num >= 8)
+   return true;
+
+   /* DP-to-HDMI Protocol Converter */
+   if (port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV &&
+   !port->mcs &&
+   port->ldps)
+   return true;
+
+   /* DP-to-DP */
+   mutex_lock(>mgr->lock);
+   if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
+   port->mstb &&
+   port->mstb->num_ports == 2) {
+   list_for_each_entry(downstream_port, >mstb->ports, next) {
+   if (downstream_port->pdt == DP_PEER_DEVICE_SST_SINK &&
+   !downstream_port->input) {
+   mutex_unlock(>mgr->lock);
+   return true;
+   }
+   }
+   }
+   mutex_unlock(>mgr->lock);
+
+   return false;
+}
+
+/**
+ * drm_dp_mst_dsc_aux_for_port() - Find the correct aux for DSC
+ * @port: The port to check. A leaf of the MST tree with an attached display.
+ *
+ * Depending on the situation, DSC may be enabled via the endpoint aux,
+ * the immediately upstream aux, or the connector's physical aux.
+ *
+ * This is both the correct aux to read DSC_CAPABILITY and the
+ * correct aux to write DSC_ENABLED.
+ *
+ * This operation can be expensive (up to four aux reads), so
+ * the caller should cache the return.
+ *
+ * Returns:
+ * NULL if DSC cannot be enabled on this port, otherwise the aux device
+ */
+struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
+{
+   struct drm_dp_mst_port *immediate_upstream_port;
+   struct drm_dp_mst_port *fec_port;
+
+   if (!port)
+   return NULL;
+
+   if (port->parent)
+   immediate_upstream_port = port->parent->port_parent;
+   else
+   immediate_upstream_port = NULL;
+
+   fec_port = immediate_upstream_port;
+   while (fec_port) {
+   /*
+* Each physical link (i.e. not a virtual port) between the
+* output and the primary device must support FEC
+*/
+   if (!drm_dp_mst_is_virtual_dpcd(fec_port) &&
+   !fec_port->fec_capable)
+   return NULL;
+
+   fec_port = fec_port->parent->port_parent;
+   }
+
+   /* DP-to-DP peer device */
+   if (drm_dp_mst_is_virtual_dpcd(immediate_upstream_port)) {
+   u8 upstream_dsc;
+   u8 endpoint_dsc;
+   u8 endpoint_fec;
+
+   if (drm_dp_dpcd_read(>aux,
+DP_DSC_SUPPORT, _dsc, 1) < 0)
+   return NULL;
+   if (drm_dp_dpcd_read(>aux,
+DP_FEC_CAPABILITY, _fec, 1) < 0)
+   return NULL;
+   if (drm_dp_dpcd_read(_upstream_port->aux,
+DP_DSC_SUPPORT, _dsc, 1) < 0)
+   return NULL;
+
+   /* Enpoint decompression with DP-to-DP peer 

[PATCH v8 09/17] drm/amd/display: Write DSC enable to MST DPCD

[mikita.lipski]

From: David Francis 

Rework the dm_helpers_write_dsc_enable callback to
handle the MST case.

Use the cached dsc_aux field.

Reviewed-by: Wenjing Liu 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 66f266a5e10b..069b7a6f5597 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -37,6 +37,7 @@
 #include "dc.h"
 #include "amdgpu_dm.h"
 #include "amdgpu_dm_irq.h"
+#include "amdgpu_dm_mst_types.h"
 
 #include "dm_helpers.h"
 
@@ -516,8 +517,24 @@ bool dm_helpers_dp_write_dsc_enable(
 )
 {
uint8_t enable_dsc = enable ? 1 : 0;
+   struct amdgpu_dm_connector *aconnector;
+
+   if (!stream)
+   return false;
+
+   if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+   aconnector = (struct amdgpu_dm_connector 
*)stream->dm_stream_context;
+
+   if (!aconnector->dsc_aux)
+   return false;
+
+   return (drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, 
_dsc, 1) >= 0);
+   }
+
+   if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT)
+   return dm_helpers_dp_write_dpcd(ctx, stream->link, 
DP_DSC_ENABLE, _dsc, 1);
 
-   return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, 
_dsc, 1);
+   return false;
 }
 
 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
-- 
2.17.1

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[PATCH v8 04/17] drm/dp_mst: Fill branch->num_ports

[mikita.lipski]

From: David Francis 

This field on drm_dp_mst_branch was never filled

It is initialized to zero when the port is kzallocced.
When a port is added to the list, increment num_ports,
and when a port is removed from the list, decrement num_ports.

v2: remember to decrement on port removal
v3: don't explicitly init to 0

Reviewed-by: Lyude Paul 
Reviewed-by: Harry Wentland 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 06aae9b52e8a..d74b767d0fe1 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -2129,6 +2129,7 @@ drm_dp_mst_port_add_connector(struct drm_dp_mst_branch 
*mstb,
build_mst_prop_path(mstb, port->port_num, proppath, sizeof(proppath));
port->connector = mgr->cbs->add_connector(mgr, port, proppath);
if (!port->connector) {
+   mstb->num_ports--;
ret = -ENOMEM;
goto error;
}
@@ -2256,6 +2257,7 @@ drm_dp_mst_handle_link_address_port(struct 
drm_dp_mst_branch *mstb,
mutex_lock(>lock);
drm_dp_mst_topology_get_port(port);
list_add(>next, >ports);
+   mstb->num_ports++;
mutex_unlock(>lock);
}
 
-- 
2.17.1

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[PATCH v8 08/17] drm/amd/display: Validate DSC caps on MST endpoints

[mikita.lipski]

From: David Francis 

During MST mode enumeration, if a new dc_sink is created,
populate it with dsc caps as appropriate.

Use drm_dp_mst_dsc_aux_for_port to get the raw caps,
then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd.

Reviewed-by: Wenjing Liu 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  1 +
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 27 ++-
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index ae36d99d0fb2..b544498d435e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -323,6 +323,7 @@ struct amdgpu_dm_connector {
struct drm_dp_mst_port *port;
struct amdgpu_dm_connector *mst_port;
struct amdgpu_encoder *mst_encoder;
+   struct drm_dp_aux *dsc_aux;
 
/* TODO see if we can merge with ddc_bus or make a dm_connector */
struct amdgpu_i2c_adapter *i2c;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 81367c869134..7557edee7db0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -25,6 +25,7 @@
 
 #include 
 #include 
+#include 
 #include "dm_services.h"
 #include "amdgpu.h"
 #include "amdgpu_dm.h"
@@ -180,6 +181,26 @@ static const struct drm_connector_funcs 
dm_dp_mst_connector_funcs = {
.early_unregister = amdgpu_dm_mst_connector_early_unregister,
 };
 
+static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector 
*aconnector)
+{
+   struct dc_sink *dc_sink = aconnector->dc_sink;
+   struct drm_dp_mst_port *port = aconnector->port;
+   u8 dsc_caps[16] = { 0 };
+
+   aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
+
+   if (!aconnector->dsc_aux)
+   return false;
+
+   if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) 
< 0)
+   return false;
+
+   if (!dc_dsc_parse_dsc_dpcd(dsc_caps, NULL, 
_sink->sink_dsc_caps.dsc_dec_caps))
+   return false;
+
+   return true;
+}
+
 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 {
struct amdgpu_dm_connector *aconnector = 
to_amdgpu_dm_connector(connector);
@@ -222,10 +243,14 @@ static int dm_dp_mst_get_modes(struct drm_connector 
*connector)
/* dc_link_add_remote_sink returns a new reference */
aconnector->dc_sink = dc_sink;
 
-   if (aconnector->dc_sink)
+   if (aconnector->dc_sink) {
amdgpu_dm_update_freesync_caps(
connector, aconnector->edid);
 
+   if (!validate_dsc_caps_on_connector(aconnector))
+   memset(>dc_sink->sink_dsc_caps,
+  0, 
sizeof(aconnector->dc_sink->sink_dsc_caps));
+   }
}
 
drm_connector_update_edid_property(
-- 
2.17.1

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[PATCH v8 01/17] drm/dp_mst: Add PBN calculation for DSC modes

[mikita.lipski]

From: David Francis 

With DSC, bpp can be fractional in multiples of 1/16.

Change drm_dp_calc_pbn_mode to reflect this, adding a new
parameter bool dsc. When this parameter is true, treat the
bpp parameter as having units not of bits per pixel, but
1/16 of a bit per pixel

v2: Don't add separate function for this

v3: Keep the calculation in a single equation

Cc: Lyude Paul 
Reviewed-by: Manasi Navare 
Reviewed-by: Lyude Paul 
Reviewed-by: Harry Wentland 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 +-
 drivers/gpu/drm/drm_dp_mst_topology.c | 38 ++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  3 +-
 drivers/gpu/drm/nouveau/dispnv50/disp.c   |  2 +-
 drivers/gpu/drm/radeon/radeon_dp_mst.c|  2 +-
 include/drm/drm_dp_mst_helper.h   |  3 +-
 6 files changed, 43 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 455c51c38720..9fc03fc1017d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4967,7 +4967,7 @@ static int dm_encoder_helper_atomic_check(struct 
drm_encoder *encoder,
is_y420);
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
clock = adjusted_mode->clock;
-   dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp);
+   dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, 
false);
}
dm_new_connector_state->vcpi_slots = 
drm_dp_atomic_find_vcpi_slots(state,
   
mst_mgr,
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index ae5809a1f19a..261e2c1828c6 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4342,10 +4342,11 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
  * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
  * @clock: dot clock for the mode
  * @bpp: bpp for the mode.
+ * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
  *
  * This uses the formula in the spec to calculate the PBN value for a mode.
  */
-int drm_dp_calc_pbn_mode(int clock, int bpp)
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
 {
/*
 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
@@ -4356,12 +4357,47 @@ int drm_dp_calc_pbn_mode(int clock, int bpp)
 * peak_kbps *= (1006/1000)
 * peak_kbps *= (64/54)
 * peak_kbps *= 8convert to bytes
+*
+* If the bpp is in units of 1/16, further divide by 16. Put this
+* factor in the numerator rather than the denominator to avoid
+* integer overflow
 */
+
+   if (dsc)
+   return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 / 
16),
+   8 * 54 * 1000 * 1000);
+
return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
8 * 54 * 1000 * 1000);
+
 }
 EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
 
+static int test_calc_pbn_mode(void)
+{
+   int ret;
+   ret = drm_dp_calc_pbn_mode(154000, 30, false);
+   if (ret != 689) {
+   DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, 
expected PBN %d, actual PBN %d.\n",
+   154000, 30, 689, ret);
+   return -EINVAL;
+   }
+   ret = drm_dp_calc_pbn_mode(234000, 30, false);
+   if (ret != 1047) {
+   DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, 
expected PBN %d, actual PBN %d.\n",
+   234000, 30, 1047, ret);
+   return -EINVAL;
+   }
+   ret = drm_dp_calc_pbn_mode(297000, 24, false);
+   if (ret != 1063) {
+   DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, 
expected PBN %d, actual PBN %d.\n",
+   297000, 24, 1063, ret);
+   return -EINVAL;
+   }
+   return 0;
+}
+
+
 /* we want to kick the TX after we've ack the up/down IRQs. */
 static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 03d1cba0b696..92be17711287 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -61,7 +61,8 @@ static int intel_dp_mst_compute_link_config(struct 
intel_encoder *encoder,
crtc_state->pipe_bpp = bpp;
 
crtc_state->pbn = 
drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
-  crtc_state->pipe_bpp);
+  

[PATCH v8 02/17] drm/dp_mst: Parse FEC capability on MST ports

[mikita.lipski]

From: David Francis 

As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating
if FEC can be supported up to that point in the MST network.

The bit is the first byte of the ENUM_PATH_RESOURCES ack reply,
bottom-most bit (refer to section 2.11.9.4 of DP standard,
v1.4)

That value is needed for FEC and DSC support

Store it on drm_dp_mst_port

Reviewed-by: Lyude Paul 
Reviewed-by: Harry Wentland 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
 include/drm/drm_dp_mst_helper.h   | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 261e2c1828c6..06aae9b52e8a 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -846,6 +846,7 @@ static bool 
drm_dp_sideband_parse_enum_path_resources_ack(struct drm_dp_sideband
 {
int idx = 1;
repmsg->u.path_resources.port_number = (raw->msg[idx] >> 4) & 0xf;
+   repmsg->u.path_resources.fec_capable = raw->msg[idx] & 0x1;
idx++;
if (idx > raw->curlen)
goto fail_len;
@@ -2894,6 +2895,7 @@ drm_dp_send_enum_path_resources(struct 
drm_dp_mst_topology_mgr *mgr,
  path_res->avail_payload_bw_number);
port->available_pbn =
path_res->avail_payload_bw_number;
+   port->fec_capable = path_res->fec_capable;
}
}
 
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 68656913cfe5..0cada01e8139 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -156,6 +156,8 @@ struct drm_dp_mst_port {
 * audio-capable.
 */
bool has_audio;
+
+   bool fec_capable;
 };
 
 /**
@@ -383,6 +385,7 @@ struct drm_dp_port_number_req {
 
 struct drm_dp_enum_path_resources_ack_reply {
u8 port_number;
+   bool fec_capable;
u16 full_payload_bw_number;
u16 avail_payload_bw_number;
 };
-- 
2.17.1

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RE: [PATCH 1/2] drm/amdgpu: avoid using invalidate semaphore for SRIOV

[Zhu, Changfeng]

[AMD Official Use Only - Internal Distribution Only]

OK Chris.

I'll try and test it.

BR,
Changfeng.

-Original Message-
From: Christian König  
Sent: Tuesday, December 3, 2019 8:18 PM
To: Zhu, Changfeng ; amd-gfx@lists.freedesktop.org; 
Koenig, Christian ; Huang, Ray ; 
Huang, Shimmer ; Deucher, Alexander 

Subject: Re: [PATCH 1/2] drm/amdgpu: avoid using invalidate semaphore for SRIOV

Am 03.12.19 um 09:50 schrieb Changfeng.Zhu:
> From: changzhu 
>
> It may fail to load guest driver in round 2 when using invalidate 
> semaphore for SRIOV. So it needs to avoid using invalidate semaphore 
> for SRIOV.

That sounds like the registers are just not correctly initialized when the 
driver is reloaded.

I would just add that to mmhub_*_program_invalidation(). Something like this 
should already do it:
>     for (i = 0; i < 18; ++i) {
>     WREG32_SOC15_OFFSET(MMHUB, 0, 
> mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
>     2 * i, 0x);
>     WREG32_SOC15_OFFSET(MMHUB, 0, 
> mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
>     2 * i, 0x1f);

WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM, i, 0x0);

>     }

Regards,
Christian.

>
> Change-Id: I8db1dc6f990fd0c458953571936467551cd4102d
> Signed-off-by: changzhu 
> ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 21 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 20 
>   2 files changed, 25 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 381bb709f021..d4c7d0319650 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -243,8 +243,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
> *adev, uint32_t vmid,
>*/
>   
>   /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> - if (vmhub == AMDGPU_MMHUB_0 ||
> - vmhub == AMDGPU_MMHUB_1) {
> + if ((vmhub == AMDGPU_MMHUB_0 ||
> +  vmhub == AMDGPU_MMHUB_1) &&
> + (!amdgpu_sriov_vf(adev))) {
>   for (i = 0; i < adev->usec_timeout; i++) {
>   /* a read return value of 1 means semaphore acuqire */
>   tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng); @@ 
> -277,8 +278,9 
> @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t 
> vmid,
>   }
>   
>   /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> - if (vmhub == AMDGPU_MMHUB_0 ||
> - vmhub == AMDGPU_MMHUB_1)
> + if ((vmhub == AMDGPU_MMHUB_0 ||
> +  vmhub == AMDGPU_MMHUB_1) &&
> + (!amdgpu_sriov_vf(adev)))
>   /*
>* add semaphore release after invalidation,
>* write with 0 means semaphore release @@ -369,6 +371,7 @@ 
> static 
> void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
>   static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>unsigned vmid, uint64_t pd_addr)
>   {
> + struct amdgpu_device *adev = ring->adev;
>   struct amdgpu_vmhub *hub = >adev->vmhub[ring->funcs->vmhub];
>   uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
>   unsigned eng = ring->vm_inv_eng;
> @@ -381,8 +384,9 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
> amdgpu_ring *ring,
>*/
>   
>   /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> - if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> - ring->funcs->vmhub == AMDGPU_MMHUB_1)
> + if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> +  ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
> + (!amdgpu_sriov_vf(adev)))
>   /* a read return value of 1 means semaphore acuqire */
>   amdgpu_ring_emit_reg_wait(ring,
> hub->vm_inv_eng0_sem + eng, 0x1, 
> 0x1); @@ -398,8 +402,9 @@ 
> static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>   req, 1 << vmid);
>   
>   /* TODO: It needs to continue working on debugging with semaphore for 
> GFXHUB as well. */
> - if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> - ring->funcs->vmhub == AMDGPU_MMHUB_1)
> + if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> +  ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
> + (!amdgpu_sriov_vf(adev)))
>   /*
>* add semaphore release after invalidation,
>* write with 0 means semaphore release diff --git 
> a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 231ea9762cb5..6c9a9c09cdb1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -464,8 +464,9 @@ static 

Re: [error] Drm -> amdgpu Unrecoverable Machine Check

[Yusuf Altıparmak]

Hi Christian,

> 0001f000
>
> Exactly as I thought. The hardware does support BAR resize, but
> unfortunately 256MB is already the minimum.
>
> Sorry, but there isn't anything I could do from the GPU drivers point of
> view.
>

Yes unfortunately there is nothing remained to about GPU side.

The only good news I have is that 256M+2M+512K+128K=260M address space
> should be enough for the GPU to work, maybe that makes things a bit simpler.
>
>
Right now I am trying to increase MMIO size config to 512 MB, I hope that
should help me. By the way I wonder how can I get at least VGA output from
GPU. Maybe I can get a text console on screen or something like X server?
Do you have any recommendations? I tried this GPU with my own Ubuntu 18.04
and its special driver. Everything worked fine.



> But you definitely got an interesting use case here :)
>

This is the worlds the most interesting use case I think. I can't increase
MMIO size because U-boot freezes. I can't decrease it to 256 MB again
because driver does not accept :D. I am just wondering, does modern gaming
motherboards have more than 4GB PCIe buffer for this job ? :D


Am 03.12.19 um 11:31 schrieb Yusuf Altıparmak:
>
> Hello Christian,
> My "setpci -s 0001:01:00.0 ECAP15+4.l ECAP15+8.l" output is;
>
> 0001f000
>
> 0820
>
> Regards.
>
>
>
> Yusuf Altıparmak , 2 Ara 2019 Pzt, 19:31
> tarihinde şunu yazdı:
>
>> Most likely not. There is support for resizing the VRAM BAR, but usually
>>> you can only make it larger and not smaller.
>>> Please give me the output of "sudo setpci -s 0001:01:00.0 ECAP15+4.l
>>> ECAP15+8.l" if you want to double check that.
>>>
>>
>> Okay I'll try it tomorrow. What does the " sudo setpci -s 0001:01:00.0
>> ECAP15+4.l ECAP15+8.l" command exactly do ?
>>
>>
>>
>>> Well you rather need to ask if anybody has sample PCIe configuration for
>>> GPUs in general. That problem is not really E9171 related. You might want
>>> to ask NXP for that maybe.
>>> Sorry, no idea if that is correct or not. You need to ask NXP for help
>>> with that.
>>>
>>>
>> Okay no problem. At least I know what is the missing point now. The
>> problem is probably because of the .dtsi and u-boot config files. Memory
>> ranges are overwriting like you said. I'll ask nxp to take some sample PCIe
>> configuration for GPUs.
>>
>> Thank you for your interest Christian.
>> Regards .
>>
>>
>>>
>>> Am 02.12.19 um 14:32 schrieb Yusuf Altıparmak:


> I attached my dts file.
>
> System is working fine when GPU is not plugged in.
>
> *This is the last console log before freeze:*
> [drm] amdgpu kernel modesetting enabled.
>
> [drm] initializing kernel modesetting (POLARIS12 0x1002:0x6987
> 0x1787:0x2389 0x80).
> [drm] register mmio base: 0x2020
>
> fsl-fman-port ffe488000.port fm1-gb0: renamed from eth0
>
> [drm] register mmio size: 262144
>
> [drm] add ip block number 0 
>
> [drm] add ip block number 1 
>
> [drm] add ip block number 2 
>
> [drm] add ip block number 3 
>
> [drm] add ip block number 4 
>
> [drm] add ip block number 5 
>
> [drm] add ip block number 6 
>
> [drm] add ip block number 7 
>
> [drm] add ip block number 8 
>
> [drm] UVD is enabled in VM mode
>
> [drm] UVD ENC is enabled in VM mode
>
> [drm] VCE enabled in VM mode
>
> ATOM BIOS: 113-ER16BFC-001
>
> [drm] GPU posting now...
>
> Disabling lock debugging due to kernel taint
>
> Machine check in kernel mode.
>
> Caused by (from MCSR=a000): Load Error Report
>
> Guarded Load Error Report
>
> Kernel panic - not syncing: Unrecoverable Machine check
>
> CPU: 1 PID: 2023 Comm: udevd Tainted: G   M
>  4.19.26+gc0c2141 #1
> Call Trace:
>
>
>
> ___
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>  
> 
>
>
>

 Christian König , 2 Ara 2019 Pzt,
 15:28 tarihinde şunu yazdı:

> Hi Yusuf,
>
> Am 02.12.19 um 12:41 schrieb Yusuf Altıparmak:
>
> My embedded board is freezing when I put E9171 on PCIe. What is the
> meaning of Unrecoverable Machine Check error about GPU?
>
>
> Well see the explanation on Wikipedia for example:
> https://en.wikipedia.org/wiki/Machine-check_exception
> 

Re: [PATCH 1/2] drm/amdgpu: avoid using invalidate semaphore for SRIOV

[Christian König]

Am 03.12.19 um 09:50 schrieb Changfeng.Zhu:

From: changzhu 

It may fail to load guest driver in round 2 when using invalidate
semaphore for SRIOV. So it needs to avoid using invalidate semaphore for
SRIOV.


That sounds like the registers are just not correctly initialized when 
the driver is reloaded.


I would just add that to mmhub_*_program_invalidation(). Something like 
this should already do it:

    for (i = 0; i < 18; ++i) {
    WREG32_SOC15_OFFSET(MMHUB, 0, 
mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

    2 * i, 0x);
    WREG32_SOC15_OFFSET(MMHUB, 0, 
mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

    2 * i, 0x1f);


WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM, i, 0x0);


    }


Regards,
Christian.



Change-Id: I8db1dc6f990fd0c458953571936467551cd4102d
Signed-off-by: changzhu 
---
  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 21 +
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 20 
  2 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 381bb709f021..d4c7d0319650 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -243,8 +243,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
 */
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1) {
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev))) {
for (i = 0; i < adev->usec_timeout; i++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -277,8 +278,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
}
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1)
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -369,6 +371,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
  static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 unsigned vmid, uint64_t pd_addr)
  {
+   struct amdgpu_device *adev = ring->adev;
struct amdgpu_vmhub *hub = >adev->vmhub[ring->funcs->vmhub];
uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
unsigned eng = ring->vm_inv_eng;
@@ -381,8 +384,9 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
 */
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
+ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)))
/* a read return value of 1 means semaphore acuqire */
amdgpu_ring_emit_reg_wait(ring,
  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
@@ -398,8 +402,9 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
req, 1 << vmid);
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
+ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 231ea9762cb5..6c9a9c09cdb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -464,8 +464,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
 */
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1) {
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev))) {
for (j = 0; j < adev->usec_timeout; j++) {
/* a read return value of 1 means semaphore acuqire */
 

Re: [PATCH 1/2] drm/amdkfd: Contain MMHUB number in the implementation

[Christian König]

Am 03.12.19 um 05:42 schrieb Yong Zhao:

Adjust the exposed function prototype so that the caller does not need
to know the MMHUB number.

Change-Id: I4420d1715984f703954f074682b075fc59e2a330
Signed-off-by: Yong Zhao 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c |  6 ++
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h |  8 
  drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c   | 13 +++--
  drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h   |  2 ++
  4 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 47c853ef1051..6f1a4676ddde 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -40,7 +40,7 @@
  #include "soc15d.h"
  #include "mmhub_v1_0.h"
  #include "gfxhub_v1_0.h"
-#include "gmc_v9_0.h"
+#include "mmhub_v9_4.h"
  
  
  enum hqd_dequeue_request_type {

@@ -774,9 +774,7 @@ void kgd_gfx_v9_set_vm_context_page_table_base(struct 
kgd_dev *kgd, uint32_t vmi
 * on GFX8 and older.
 */
if (adev->asic_type == CHIP_ARCTURUS) {
-   /* Two MMHUBs */
-   mmhub_v9_4_setup_vm_pt_regs(adev, 0, vmid, page_table_base);
-   mmhub_v9_4_setup_vm_pt_regs(adev, 1, vmid, page_table_base);
+   mmhub_v9_4_setup_vm_pt_regs(adev, vmid, page_table_base);
} else
mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
  
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h

index 971c0840358f..49e8be761214 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
@@ -36,12 +36,4 @@
  
  extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;

  extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
-
-/* amdgpu_amdkfd*.c */
-void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
-   uint64_t value);
-void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
-   uint64_t value);
-void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
-   uint32_t vmid, uint64_t value);
  #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index 8599bfdb9a9e..0b621bf8bbd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -54,7 +54,7 @@ u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
return base;
  }
  
-void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,

+static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int 
hubid,
uint32_t vmid, uint64_t value)
  {
/* two registers distance between mmVML2VC0_VM_CONTEXT0_* to
@@ -80,7 +80,7 @@ static void mmhub_v9_4_init_gart_aperture_regs(struct 
amdgpu_device *adev,
  {
uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  
-	mmhub_v9_4_setup_vm_pt_regs(adev, hubid, 0, pt_base);

+   mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base);
  
  	WREG32_SOC15_OFFSET(MMHUB, 0,

mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
@@ -101,6 +101,15 @@ static void mmhub_v9_4_init_gart_aperture_regs(struct 
amdgpu_device *adev,
(u32)(adev->gmc.gart_end >> 44));
  }
  
+void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

+   uint64_t page_table_base)
+{
+   int i;


You should add an empty line between declaration and code.


+   for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
+   mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid, 
page_table_base);
+   }


Please don't add {} for single line statements.

Regards,
Christian.


+}
+
  static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
 int hubid)
  {
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
index 354a4b7e875b..1b979773776c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
@@ -34,5 +34,7 @@ void mmhub_v9_4_init(struct amdgpu_device *adev);
  int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
   enum amd_clockgating_state state);
  void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags);
+void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
+   uint64_t page_table_base);
  
  #endif


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Re: [error] Drm -> amdgpu Unrecoverable Machine Check

[Christian König]

Hi Yusuf,


0001f000
Exactly as I thought. The hardware does support BAR resize, but 
unfortunately 256MB is already the minimum.


Sorry, but there isn't anything I could do from the GPU drivers point of 
view.


The only good news I have is that 256M+2M+512K+128K=260M address space 
should be enough for the GPU to work, maybe that makes things a bit simpler.


But you definitely got an interesting use case here :)

Regards,
Christian.

Am 03.12.19 um 11:31 schrieb Yusuf Altıparmak:

Hello Christian,
My "setpci -s 0001:01:00.0 ECAP15+4.l ECAP15+8.l" output is;

0001f000
0820

Regards.



Yusuf Altıparmak >, 2 Ara 2019 Pzt, 19:31 tarihinde 
şunu yazdı:


Most likely not. There is support for resizing the VRAM BAR,
but usually you can only make it larger and not smaller.
Please give me the output of "sudo setpci -s 0001:01:00.0
ECAP15+4.l ECAP15+8.l" if you want to double check that.


Okay I'll try it tomorrow. What does the " sudo setpci -s
0001:01:00.0 ECAP15+4.l ECAP15+8.l" command exactly do ?

Well you rather need to ask if anybody has sample PCIe
configuration for GPUs in general. That problem is not really
E9171 related. You might want to ask NXP for that maybe.
Sorry, no idea if that is correct or not. You need to ask NXP
for help with that.


Okay no problem. At least I know what is the missing point now.
The problem is probably because of the .dtsi and u-boot config
files. Memory ranges are overwriting like you said. I'll ask nxp
to take some sample PCIe configuration for GPUs.

Thank you for your interest Christian.
Regards .



Am 02.12.19 um 14:32 schrieb Yusuf Altıparmak:




I attached my dts file.

System is working fine when GPU is not plugged in.
*
*
*This is the last console log before freeze:*
[drm] amdgpu kernel modesetting enabled.
[drm] initializing kernel modesetting (POLARIS12
0x1002:0x6987 0x1787:0x2389 0x80).
[drm] register mmio base: 0x2020
fsl-fman-port ffe488000.port fm1-gb0: renamed from
eth0
[drm] register mmio size: 262144
[drm] add ip block number 0 
[drm] add ip block number 1 
[drm] add ip block number 2 
[drm] add ip block number 3 
[drm] add ip block number 4 
[drm] add ip block number 5 
[drm] add ip block number 6 
[drm] add ip block number 7 
[drm] add ip block number 8 
[drm] UVD is enabled in VM mode
[drm] UVD ENC is enabled in VM mode
[drm] VCE enabled in VM mode
ATOM BIOS: 113-ER16BFC-001
[drm] GPU posting now...
Disabling lock debugging due to kernel taint
Machine check in kernel mode.
Caused by (from MCSR=a000): Load Error Report
Guarded Load Error Report
Kernel panic - not syncing: Unrecoverable Machine
check
CPU: 1 PID: 2023 Comm: udevd Tainted: G   M
 4.19.26+gc0c2141 #1
Call Trace:





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Christian König mailto:ckoenig.leichtzumer...@gmail.com>>, 2 Ara 2019
Pzt, 15:28 tarihinde şunu yazdı:

Hi Yusuf,

Am 02.12.19 um 12:41 schrieb Yusuf Altıparmak:

My embedded board is freezing when I put E9171 on
PCIe. What is the meaning of Unrecoverable Machine
Check error about GPU?


Well see the explanation on Wikipedia for example:
https://en.wikipedia.org/wiki/Machine-check_exception



In general it means you have messed up something in
your hardware configuration.


Could PCIe settings in .dts file 

Re: [error] Drm -> amdgpu Unrecoverable Machine Check

[Yusuf Altıparmak]

Hello Christian,
My "setpci -s 0001:01:00.0 ECAP15+4.l ECAP15+8.l" output is;

0001f000

0820

Regards.



Yusuf Altıparmak , 2 Ara 2019 Pzt, 19:31 tarihinde
şunu yazdı:

> Most likely not. There is support for resizing the VRAM BAR, but usually
>> you can only make it larger and not smaller.
>> Please give me the output of "sudo setpci -s 0001:01:00.0 ECAP15+4.l
>> ECAP15+8.l" if you want to double check that.
>>
>
> Okay I'll try it tomorrow. What does the " sudo setpci -s 0001:01:00.0
> ECAP15+4.l ECAP15+8.l" command exactly do ?
>
>
>
>> Well you rather need to ask if anybody has sample PCIe configuration for
>> GPUs in general. That problem is not really E9171 related. You might want
>> to ask NXP for that maybe.
>> Sorry, no idea if that is correct or not. You need to ask NXP for help
>> with that.
>>
>>
> Okay no problem. At least I know what is the missing point now. The
> problem is probably because of the .dtsi and u-boot config files. Memory
> ranges are overwriting like you said. I'll ask nxp to take some sample PCIe
> configuration for GPUs.
>
> Thank you for your interest Christian.
> Regards .
>
>
>>
>> Am 02.12.19 um 14:32 schrieb Yusuf Altıparmak:
>>>
>>>
 I attached my dts file.

 System is working fine when GPU is not plugged in.

 *This is the last console log before freeze:*
 [drm] amdgpu kernel modesetting enabled.

 [drm] initializing kernel modesetting (POLARIS12 0x1002:0x6987
 0x1787:0x2389 0x80).
 [drm] register mmio base: 0x2020

 fsl-fman-port ffe488000.port fm1-gb0: renamed from eth0

 [drm] register mmio size: 262144

 [drm] add ip block number 0 

 [drm] add ip block number 1 

 [drm] add ip block number 2 

 [drm] add ip block number 3 

 [drm] add ip block number 4 

 [drm] add ip block number 5 

 [drm] add ip block number 6 

 [drm] add ip block number 7 

 [drm] add ip block number 8 

 [drm] UVD is enabled in VM mode

 [drm] UVD ENC is enabled in VM mode

 [drm] VCE enabled in VM mode

 ATOM BIOS: 113-ER16BFC-001

 [drm] GPU posting now...

 Disabling lock debugging due to kernel taint

 Machine check in kernel mode.

 Caused by (from MCSR=a000): Load Error Report

 Guarded Load Error Report

 Kernel panic - not syncing: Unrecoverable Machine check

 CPU: 1 PID: 2023 Comm: udevd Tainted: G   M
  4.19.26+gc0c2141 #1
 Call Trace:



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>>>
>>> Christian König , 2 Ara 2019 Pzt,
>>> 15:28 tarihinde şunu yazdı:
>>>
 Hi Yusuf,

 Am 02.12.19 um 12:41 schrieb Yusuf Altıparmak:

 My embedded board is freezing when I put E9171 on PCIe. What is the
 meaning of Unrecoverable Machine Check error about GPU?


 Well see the explanation on Wikipedia for example:
 https://en.wikipedia.org/wiki/Machine-check_exception
 

 In general it means you have messed up something in your hardware
 configuration.

 Could PCIe settings in .dts file cause this problem?


 Possible, but rather unlikely. My best guess is that it is some problem
 with the power supply.

 If it is, is there any sample PCIe configuration for E9171?


 The E9171 is just a PCIe device, so the dtsi is actually rather
 uninteresting. What we really need is a full dmesg and maybe lspci output
 would help as well.

 Regards,
 Christian.

>>>
>>>
>>> Hi Christian,
>>>
>>> At first, I am using NXP T1042D4RDB-64B which has 256 MB PCIe buffer
>>> according to its. PCIe memory range was arranged to 256 MB in .dts file and
>>> in U-boot configuration file. Driver was giving error with exit code -12
>>> (OUT_OF_MEMORY). But I was able to reach the linux console.
>>>
>>> [5.512922] [drm] amdgpu kernel modesetting enabled.
>>> [5.517065] [drm] initializing kernel modesetting (POLARIS12
>>> 0x1002:0x6987 0x1787:0x2389 0x80).
>>> [5.524507] amdgpu 0001:01:00.0: Fatal error during GPU init
>>> [5.529296] amdgpu: probe of 0001:01:00.0 failed with error -12
>>>
>>> Then I 

[PATCH 2/2] drm/amdgpu: avoid using invalidate semaphore for picasso

[Changfeng.Zhu]

From: changzhu 

It may cause timeout waiting for sem acquire in VM flush when using
invalidate semaphore for picasso. So it needs to avoid using invalidate
semaphore for piasso.

Change-Id: I300e96af5c66b33a7d61e6420caa33d70471d44a
Signed-off-by: changzhu 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 20 
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 20 
 2 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index d4c7d0319650..bd998177d557 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -245,7 +245,10 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
if ((vmhub == AMDGPU_MMHUB_0 ||
 vmhub == AMDGPU_MMHUB_1) &&
-   (!amdgpu_sriov_vf(adev))) {
+   (!amdgpu_sriov_vf(adev)) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8))) {
for (i = 0; i < adev->usec_timeout; i++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -280,7 +283,10 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
if ((vmhub == AMDGPU_MMHUB_0 ||
 vmhub == AMDGPU_MMHUB_1) &&
-   (!amdgpu_sriov_vf(adev)))
+   (!amdgpu_sriov_vf(adev)) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -386,7 +392,10 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
 ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
-   (!amdgpu_sriov_vf(adev)))
+   (!amdgpu_sriov_vf(adev)) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
/* a read return value of 1 means semaphore acuqire */
amdgpu_ring_emit_reg_wait(ring,
  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
@@ -404,7 +413,10 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
 ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
-   (!amdgpu_sriov_vf(adev)))
+   (!amdgpu_sriov_vf(adev)) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 6c9a9c09cdb1..1cfed8787031 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -466,7 +466,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
if ((vmhub == AMDGPU_MMHUB_0 ||
 vmhub == AMDGPU_MMHUB_1) &&
-   (!amdgpu_sriov_vf(adev))) {
+   (!amdgpu_sriov_vf(adev)) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8))) {
for (j = 0; j < adev->usec_timeout; j++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -498,7 +501,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
if ((vmhub == AMDGPU_MMHUB_0 ||
 vmhub == AMDGPU_MMHUB_1) &&
-   (!amdgpu_sriov_vf(adev)))
+   (!amdgpu_sriov_vf(adev)) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -531,7 +537,10 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
   

[PATCH 1/2] drm/amdgpu: avoid using invalidate semaphore for SRIOV

[Changfeng.Zhu]

From: changzhu 

It may fail to load guest driver in round 2 when using invalidate
semaphore for SRIOV. So it needs to avoid using invalidate semaphore for
SRIOV.

Change-Id: I8db1dc6f990fd0c458953571936467551cd4102d
Signed-off-by: changzhu 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 21 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 20 
 2 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 381bb709f021..d4c7d0319650 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -243,8 +243,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
 */
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1) {
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev))) {
for (i = 0; i < adev->usec_timeout; i++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -277,8 +278,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
}
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1)
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -369,6 +371,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 unsigned vmid, uint64_t pd_addr)
 {
+   struct amdgpu_device *adev = ring->adev;
struct amdgpu_vmhub *hub = >adev->vmhub[ring->funcs->vmhub];
uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
unsigned eng = ring->vm_inv_eng;
@@ -381,8 +384,9 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
 */
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
+ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)))
/* a read return value of 1 means semaphore acuqire */
amdgpu_ring_emit_reg_wait(ring,
  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
@@ -398,8 +402,9 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
req, 1 << vmid);
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-   ring->funcs->vmhub == AMDGPU_MMHUB_1)
+   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
+ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 231ea9762cb5..6c9a9c09cdb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -464,8 +464,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
 */
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1) {
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev))) {
for (j = 0; j < adev->usec_timeout; j++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -495,8 +496,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
}
 
/* TODO: It needs to continue working on debugging with semaphore for 
GFXHUB as well. */
-   if (vmhub == AMDGPU_MMHUB_0 ||
-   vmhub == AMDGPU_MMHUB_1)
+   if ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)))
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -527,8 +529,9 @@ static uint64_t