RE: [RESEND PATCH 5/5] drm/amdgpu: Switch from system_highpri_wq to system_unbound_wq

[Ma, Le]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Le Ma 

Regards,
Ma Le

-Original Message-
From: Andrey Grodzovsky  
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ; 
Zhang, Hawking ; Quan, Evan ; 
Grodzovsky, Andrey 
Subject: [RESEND PATCH 5/5] drm/amdgpu: Switch from system_highpri_wq to 
system_unbound_wq

This is to avoid queueing jobs to same CPU during XGMI hive reset because there 
is a strict timeline for when the reset commands must reach all the GPUs in the 
hive.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e4089a0..1518565 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3842,7 +3842,7 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info 
*hive,
list_for_each_entry(tmp_adev, device_list_handle, 
gmc.xgmi.head) {
/* For XGMI run all resets in parallel to speed up the 
process */
if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
-   if (!queue_work(system_highpri_wq, 
_adev->xgmi_reset_work))
+   if (!queue_work(system_unbound_wq, 
_adev->xgmi_reset_work))
r = -EALREADY;
} else
r = amdgpu_asic_reset(tmp_adev);
--
2.7.4
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RE: [RESEND PATCH 4/5] Subject: drm/amdgpu: Redo XGMI reset synchronization.

[Ma, Le]

[AMD Official Use Only - Internal Distribution Only]






-Original Message-
From: Andrey Grodzovsky 
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ; 
Zhang, Hawking ; Quan, Evan ; 
Grodzovsky, Andrey 
Subject: [RESEND PATCH 4/5] Subject: drm/amdgpu: Redo XGMI reset 
synchronization.



Use task barrier in XGMI hive to synchronize ASIC resets across devices in XGMI 
hive.



Signed-off-by: Andrey Grodzovsky 
mailto:andrey.grodzov...@amd.com>>

---

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 42 +-

1 file changed, 36 insertions(+), 6 deletions(-)



diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index 1d19edfa..e4089a0 100644

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

@@ -67,6 +67,7 @@

#include "amdgpu_tmz.h"



 #include 

+#include 



 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");

MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");

@@ -2663,14 +2664,43 @@ static void amdgpu_device_xgmi_reset_func(struct 
work_struct *__work)  {

   struct amdgpu_device *adev =

   container_of(__work, struct amdgpu_device, 
xgmi_reset_work);

+  struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);



-   if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)

-   adev->asic_reset_res = (adev->in_baco == false) ?

-   
amdgpu_device_baco_enter(adev->ddev) :

-   
qamdgpu_device_baco_exit(adev->ddev);

-   else

-   adev->asic_reset_res = amdgpu_asic_reset(adev);

+  /*

+  * Use task barrier to synchronize all xgmi reset works across the

+  * hive.

+  * task_barrier_enter and task_barrier_exit will block untill all the

+  * threads running the xgmi reset works reach those points. I assume

+  * guarantee of progress here for all the threads as the workqueue 
code

+  * creates new worker threads as needed by amount of work items in 
queue

+  * (see worker_thread) and also each thread sleeps in the barrir and 
by

+  * this yielding the CPU for other work threads to make progress.

+  */

[Le]: This comments can be adjusted since we switch to system_unbound_wq in 
patch #5.

+  if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {

+

+  if (hive)

+  task_barrier_enter(>tb);

[Le]: The multiple hive condition can be checked only once and moved to the 
location right after the assignment.

+

+  adev->asic_reset_res = 
amdgpu_device_baco_enter(adev->ddev);

+

+  if (adev->asic_reset_res)

+  goto fail;

+

+  if (hive)

+  task_barrier_exit(>tb);

[Le]: Same as above.

+

+  adev->asic_reset_res = 
amdgpu_device_baco_exit(adev->ddev);

+

+  if (adev->asic_reset_res)

+  goto fail;

+  } else {

+  if (hive)

+  task_barrier_full(>tb);

[Le]: Same as above.



With above addressed, Reviewed-by: Le Ma mailto:le...@amd.com>>



Regards,

Ma Le

+

+  adev->asic_reset_res =  amdgpu_asic_reset(adev);

+  }



+fail:

   if (adev->asic_reset_res)

   DRM_WARN("ASIC reset failed with error, %d for drm dev, 
%s",

adev->asic_reset_res, adev->ddev->unique);

--

2.7.4


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RE: [RESEND PATCH 1/5] drm/amdgpu: reverts commit b01245ff54db66073b104ac9d9fbefb7b264b36d.

[Ma, Le]

[AMD Official Use Only - Internal Distribution Only]




-Original Message-
From: Andrey Grodzovsky 
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ; 
Zhang, Hawking ; Quan, Evan ; 
Grodzovsky, Andrey 
Subject: [RESEND PATCH 1/5] drm/amdgpu: reverts commit 
b01245ff54db66073b104ac9d9fbefb7b264b36d.



In preparation for doing XGMI reset synchronization using task barrier.



Signed-off-by: Andrey Grodzovsky 

---

drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 -

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 76 +-

2 files changed, 12 insertions(+), 66 deletions(-)



diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index a78a363..50bab33 100644

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h

+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

@@ -1001,8 +1001,6 @@ struct amdgpu_device {



boolpm_sysfs_en;

   boolucode_sysfs_en;

-

-   boolin_baco;

};



 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device 
*bdev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index 7324a5f..1d19edfa 100644

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

@@ -2667,7 +2667,7 @@ static void amdgpu_device_xgmi_reset_func(struct 
work_struct *__work)

   if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)

   adev->asic_reset_res = (adev->in_baco == false) ?

   
amdgpu_device_baco_enter(adev->ddev) :

-   
amdgpu_device_baco_exit(adev->ddev);

+  
qamdgpu_device_baco_exit(adev->ddev);

[Le]: Typo here. With it fixed, Reviewed-by: Le Ma 
mailto:le...@amd.com>>



Regards,

Ma Le

   else

   adev->asic_reset_res = amdgpu_asic_reset(adev);



@@ -3796,18 +3796,13 @@ static int amdgpu_device_pre_asic_reset(struct 
amdgpu_device *adev,

   return r;

}



-static int amdgpu_do_asic_reset(struct amdgpu_device *adev,

-  struct amdgpu_hive_info *hive,

+static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,

  struct list_head *device_list_handle,

  bool *need_full_reset_arg)

{

   struct amdgpu_device *tmp_adev = NULL;

   bool need_full_reset = *need_full_reset_arg, vram_lost = false;

   int r = 0;

-   int cpu = smp_processor_id();

-   bool use_baco =

-   (amdgpu_asic_reset_method(adev) == 
AMD_RESET_METHOD_BACO) ?

-   true : false;



/*

* ASIC reset has to be done on all HGMI hive nodes ASAP @@ -3815,62 
+3810,22 @@ static int amdgpu_do_asic_reset(struct amdgpu_device *adev,

*/

   if (need_full_reset) {

   list_for_each_entry(tmp_adev, device_list_handle, 
gmc.xgmi.head) {

-   /*

-   * For XGMI run all resets in parallel to 
speed up the

-   * process by scheduling the highpri wq on 
different

-   * cpus. For XGMI with baco reset, all nodes 
must enter

-   * baco within close proximity before anyone 
exit.

-   */

+  /* For XGMI run all resets in parallel to 
speed up the process */

   if (tmp_adev->gmc.xgmi.num_physical_nodes > 
1) {

-   if (!queue_work_on(cpu, 
system_highpri_wq,

-  
_adev->xgmi_reset_work))

+  if 
(!queue_work(system_highpri_wq, _adev->xgmi_reset_work))

   r = -EALREADY;

-   cpu = cpumask_next(cpu, 
cpu_online_mask);

   } else

   r = amdgpu_asic_reset(tmp_adev);

-   if (r)

-   break;

-   }

-

-   /* For XGMI wait for all work to complete before 
proceed */

-   if (!r) {

-   list_for_each_entry(tmp_adev, 
device_list_handle,

-   gmc.xgmi.head) {

-   if 

RE: [RESEND PATCH 2/5] drm: Add Reusable task barrier.

[Ma, Le]

[AMD Official Use Only - Internal Distribution Only]






-Original Message-
From: Andrey Grodzovsky 
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ; 
Zhang, Hawking ; Quan, Evan ; 
Grodzovsky, Andrey 
Subject: [RESEND PATCH 2/5] drm: Add Reusable task barrier.



It is used to synchronize N threads at a rendevouz point before execution of 
critical code that has to be started by all the threads at approximatly the 
same time.



Signed-off-by: Andrey Grodzovsky 
mailto:andrey.grodzov...@amd.com>>

---

include/drm/task_barrier.h | 106 +

1 file changed, 106 insertions(+)

create mode 100644 include/drm/task_barrier.h



diff --git a/include/drm/task_barrier.h b/include/drm/task_barrier.h new file 
mode 100644 index 000..81fb0f7

--- /dev/null

+++ b/include/drm/task_barrier.h

@@ -0,0 +1,106 @@

+/*

+ * Copyright 2019 Advanced Micro Devices, Inc.

+ *

+ * Permission is hereby granted, free of charge, to any person

+obtaining a

+ * copy of this software and associated documentation files (the

+"Software"),

+ * to deal in the Software without restriction, including without

+limitation

+ * the rights to use, copy, modify, merge, publish, distribute,

+sublicense,

+ * and/or sell copies of the Software, and to permit persons to whom

+the

+ * Software is furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be

+included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

+EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

+MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT

+SHALL

+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,

+DAMAGES OR

+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR

+OTHERWISE,

+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE

+OR

+ * OTHER DEALINGS IN THE SOFTWARE.

+ *

+ */

+#include 

+#include 

+

+/*

+ * Reusable 2 PHASE task barrier (randevouz point) implementation for N tasks.

+ * Based on the Little book of sempahores -

+https://greenteapress.com/wp/semaphores/

+ */

+

+

+

+#ifndef DRM_TASK_BARRIER_H_

+#define DRM_TASK_BARRIER_H_

+



[Le]: It might be better to prefix "drm_" to the functions and structure below, 
even this header file name.



+/*

+ * Represents an instance of a task barrier.

+ */

+struct task_barrier {

+  unsigned int n;

[Le]: We can define it as signed type here for more common use.

+  atomic_t count;

+  struct semaphore enter_turnstile;

+  struct semaphore exit_turnstile;

+};

+

+static inline void task_barrier_signal_turnstile(struct semaphore *turnstile,

+  unsigned 
int n)

+{

+  int i;

+

+  for (i = 0 ; i < n; i++)

+  up(turnstile);

+}

+

+static inline void task_barrier_init(struct task_barrier *tb) {

+  tb->n = 0;

+  atomic_set(>count, 0);

+  sema_init(>enter_turnstile, 0);

+  sema_init(>exit_turnstile, 0);

+}

+

+static inline void task_barrier_add_task(struct task_barrier *tb) {

+  tb->n++;

+}

+

+static inline void task_barrier_rem_task(struct task_barrier *tb) {

+  tb->n--;

+}

+

+/*

+ * Lines up all the threads BEFORE the critical point.

+ *

+ * When all thread passed this code the entry barrier is back to locked state.

+ */

+static inline void task_barrier_enter(struct task_barrier *tb) {

+  if (atomic_inc_return(>count) == tb->n)

+  task_barrier_signal_turnstile(>enter_turnstile, 
tb->n);

+

+  down(>enter_turnstile);

+}

+

+/*

+ * Lines up all the threads AFTER the critical point.

+ *

+ * This function is used to avoid any one thread running ahead of the

+reset if

[Le]: No need to mention "reset" here.



With the above addressed, Acked-by: Le Ma le...@amd.com



Regards,

Ma Le

+ * the barrier is used in a loop (repeatedly) .

+ */

+static inline void task_barrier_exit(struct task_barrier *tb) {

+  if (atomic_dec_return(>count) == 0)

+  task_barrier_signal_turnstile(>exit_turnstile, 
tb->n);

+

+  down(>exit_turnstile);

+}

+

+static inline void task_barrier_full(struct task_barrier *tb) {

+  task_barrier_enter(tb);

+  task_barrier_exit(tb);

+}

+

+#endif

--

2.7.4


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RE: [RESEND PATCH 3/5] drm/amdgpu: Add task barrier to XGMI hive.

[Ma, Le]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Le Ma 

Regards,
Ma Le

-Original Message-
From: Andrey Grodzovsky  
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ; 
Zhang, Hawking ; Quan, Evan ; 
Grodzovsky, Andrey 
Subject: [RESEND PATCH 3/5] drm/amdgpu: Add task barrier to XGMI hive.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4   
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 61d13d8..5cf920d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -261,6 +261,7 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct 
amdgpu_device *adev, int lo
INIT_LIST_HEAD(>device_list);
mutex_init(>hive_lock);
mutex_init(>reset_lock);
+   task_barrier_init(>tb);
 
if (lock)
mutex_lock(>hive_lock);
@@ -408,6 +409,8 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
top_info->num_nodes = count;
hive->number_devices = count;
 
+   task_barrier_add_task(>tb);
+
if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
list_for_each_entry(tmp_adev, >device_list, 
gmc.xgmi.head) {
/* update node list for other device in the hive */ @@ 
-470,6 +473,7 @@ void amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
mutex_destroy(>hive_lock);
mutex_destroy(>reset_lock);
} else {
+   task_barrier_rem_task(>tb);
amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
mutex_unlock(>hive_lock);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
index bbf504f..74011fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
@@ -22,6 +22,7 @@
 #ifndef __AMDGPU_XGMI_H__
 #define __AMDGPU_XGMI_H__
 
+#include 
 #include "amdgpu_psp.h"
 
 struct amdgpu_hive_info {
@@ -33,6 +34,7 @@ struct amdgpu_hive_info {
struct device_attribute dev_attr;
struct amdgpu_device *adev;
int pstate; /*0 -- low , 1 -- high , -1 unknown*/
+   struct task_barrier tb;
 };
 
 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int 
lock);
--
2.7.4
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Re: [PATCH 5/5] drm/amdgpu: immedially invalidate PTEs

[Felix Kuehling]

Hi Christian,

Alex started trying to invalidate PTEs in the MMU notifiers and we're 
finding that we still need to reserve the VM reservation for 
amdgpu_sync_resv in amdgpu_vm_sdma_prepare. Is that sync_resv still 
needed now, given that VM fences aren't in that reservation object any more?


Regards,
  Felix

On 2019-12-05 5:39, Christian König wrote:

When a BO is evicted immedially invalidate the mapped PTEs.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 -
  1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 839d6df394fc..e578113bfd55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2565,6 +2565,7 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 struct amdgpu_bo *bo, bool evicted)
  {
struct amdgpu_vm_bo_base *bo_base;
+   int r;
  
  	/* shadow bo doesn't have bo base, its validation needs its parent */

if (bo->parent && bo->parent->shadow == bo)
@@ -2572,8 +2573,22 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
  
  	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {

struct amdgpu_vm *vm = bo_base->vm;
+   struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
+
+   if (bo->tbo.type != ttm_bo_type_kernel) {
+   struct amdgpu_bo_va *bo_va;
+
+   bo_va = container_of(bo_base, struct amdgpu_bo_va,
+base);
+   r = amdgpu_vm_bo_update(adev, bo_va,
+   bo->tbo.base.resv != resv);
+   if (!r) {
+   amdgpu_vm_bo_idle(bo_base);
+   continue;
+   }
+   }
  
-		if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {

+   if (evicted && bo->tbo.base.resv == resv) {
amdgpu_vm_bo_evicted(bo_base);
continue;
}

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[PATCH] drm/amdgpu: Add CU info print log

[Yong Zhao]

The log will be useful for easily getting the CU info on various
emulation models or ASICs.

Change-Id: Ic1c914938aa3445d8dbfdf6a237bc1d58b0d5267
Signed-off-by: Yong Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8992506541d8..c778b6db5e42 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3032,6 +3032,12 @@ int amdgpu_device_init(struct amdgpu_device *adev,
goto failed;
}
 
+   DRM_DEBUG("SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
+   adev->gfx.config.max_shader_engines,
+   adev->gfx.config.max_sh_per_se,
+   adev->gfx.config.max_cu_per_sh,
+   adev->gfx.cu_info.number);
+
adev->accel_working = true;
 
amdgpu_vm_check_compute_bug(adev);
-- 
2.17.1

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[pull] amdgpu, amdkfd, radeon drm-next-5.6

[Alex Deucher]

Hi Dave, Daniel,

Kicking off 5.6 with new stuff from AMD.  There is a UAPI addition.  We
added a new firmware for display, and this just adds the version query
to our existing firmware query interface.  UMDs like mesa use this interface to
query things like CP or UVD firmware versions to see what features are
supported.

The following changes since commit 622b2a0ab647d2755f2c1f1000d3403e86a69763:

  drm/amdgpu/vcn: finish delay work before release resources (2019-11-13 
15:29:42 -0500)

are available in the Git repository at:

  git://people.freedesktop.org/~agd5f/linux tags/drm-next-5.6-2019-12-11

for you to fetch changes up to ad808910be68dcf8da5d837d4511d00ad5d3678a:

  drm/amdgpu: fix license on Kconfig and Makefiles (2019-12-11 15:22:08 -0500)


drm-next-5.6-2019-12-11:

amdgpu:
- Add MST atomic routines
- Add support for DMCUB (new helper microengine for displays)
- Add OEM i2c support in DC
- Use vstartup for vblank events on DCN
- Simplify Kconfig for DC
- Renoir fixes for DC
- Clean up function pointers in DC
- Initial support for HDCP 2.x
- Misc code cleanups
- GFX10 fixes
- Rework JPEG engine handling for VCN
- Add clock and power gating support for JPEG
- BACO support for Arcturus
- Cleanup PSP ring handling
- Add framework for using BACO with runtime pm to save power
- Move core pci state handling out of the driver for pm ops
- Allow guest power control in 1 VF case with SR-IOV
- SR-IOV fixes
- RAS fixes
- Support for power metrics on renoir
- Golden settings updates for gfx10
- Enable gfxoff on supported navi10 skus
- Update MAINTAINERS

amdkfd:
- Clean up generational gfx code
- Fixes for gfx10
- DIQ fixes
- Share more code with amdgpu

radeon:
- PPC DMA fix
- Register checker fixes for r1xx/r2xx
- Misc cleanups


Alex Deucher (34):
  drm/amdgpu/display: fix the build when CONFIG_DRM_AMD_DC_DCN is not set
  drm/amdgpu/display: fix warning when CONFIG_DRM_AMD_DC_DCN is not set
  drm/amdgpu/soc15: move struct definition around to align with other soc15 
asics
  drm/amdgpu/nv: add asic func for fetching vbios from rom directly
  drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK (v2)
  drm/amdgpu: disable gfxoff when using register read interface
  drm/amdgpu: remove experimental flag for Navi14
  drm/amdgpu: disable gfxoff on original raven
  Revert "drm/amd/display: enable S/G for RAVEN chip"
  drm/amdgpu: add asic callback for BACO support
  drm/amdgpu: add supports_baco callback for soc15 asics. (v2)
  drm/amdgpu: add supports_baco callback for SI asics.
  drm/amdgpu: add supports_baco callback for CIK asics.
  drm/amdgpu: add supports_baco callback for VI asics.
  drm/amdgpu: add supports_baco callback for NV asics.
  drm/amdgpu: add a amdgpu_device_supports_baco helper
  drm/amdgpu: rename amdgpu_device_is_px to amdgpu_device_supports_boco (v2)
  drm/amdgpu: add additional boco checks to runtime suspend/resume (v2)
  drm/amdgpu: split swSMU baco_reset into enter and exit
  drm/amdgpu: add helpers for baco entry and exit
  drm/amdgpu: add baco support to runtime suspend/resume
  drm/amdgpu: start to disentangle boco from runtime pm
  drm/amdgpu: disentangle runtime pm and vga_switcheroo
  drm/amdgpu: enable runtime pm on BACO capable boards if runpm=1
  drm/amdgpu: simplify runtime suspend
  drm/amd/display: add default clocks if not able to fetch them
  MAINTAINERS: Drop Rex Zhu for amdgpu powerplay
  drm/amdgpu: move pci handling out of pm ops
  drm/amdgpu: flag vram lost on baco reset for VI/CIK
  drm/amd/display: re-enable wait in pipelock, but add timeout
  drm/radeon: fix r1xx/r2xx register checker for POT textures
  drm/amdgpu: add header line for power profile on Arcturus
  drm/amdgpu/display: add fallthrough comment
  drm/amdgpu: fix license on Kconfig and Makefiles

Alex Sierra (2):
  drm/amdgpu: add flag to indicate amdgpu vm context
  amd/amdgpu: force to trigger a no-retry-fault after a retry-fault

Alvin Lee (1):
  drm/amd/display: Changes in dc to allow full update in some cases

Amanda Liu (1):
  drm/amd/display: Fix screen tearing on vrr tests

Andrey Grodzovsky (1):
  drm/amdgpu: Fix BACO entry failure in NAVI10.

Anthony Koo (8):
  drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC SDP
  drm/amd/display: Clean up some code with unused registers
  drm/amd/display: cleanup of construct and destruct funcs
  drm/amd/display: cleanup of function pointer tables
  drm/amd/display: rename core_dc to dc
  drm/amd/display: add separate of private hwss functions
  drm/amd/display: add DP protocol version
  drm/amd/display: Limit NV12 chroma workaround

Aric Cyr (7):
  drm/amd/display: 3.2.57
  drm/amd/display: 3.2.58
  drm/amd/display: 

Re: [PATCH] drm/amdgpu: Add CU info print log

[Alex Deucher]

On Wed, Dec 11, 2019 at 3:26 PM Yong Zhao  wrote:
>
> The log will be useful for easily getting the CU info on various
> emulation models or ASICs.
>

You can probably just put this all in once place at the end of init
rather than sprinkling the print statements across all the IP modules.
Also, can we make it debug only?  Our driver is already pretty chatty.

Alex

> Change-Id: Ic1c914938aa3445d8dbfdf6a237bc1d58b0d5267
> Signed-off-by: Yong Zhao 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 6 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 2 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++
>  7 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 8992506541d8..df9732510012 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1529,6 +1529,12 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
> amdgpu_device *adev)
> adev->gfx.config.max_shader_engines = 
> le32_to_cpu(gpu_info_fw->gc_num_se);
> adev->gfx.config.max_cu_per_sh = 
> le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
> adev->gfx.config.max_sh_per_se = 
> le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
> +
> +   DRM_INFO("gpu_info: SE %d, SH per SE %d, CU per SH %d\n",
> +   adev->gfx.config.max_shader_engines,
> +   adev->gfx.config.max_sh_per_se,
> +   adev->gfx.config.max_cu_per_sh);
> +
> adev->gfx.config.max_backends_per_se = 
> le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
> adev->gfx.config.max_texture_channel_caches =
> le32_to_cpu(gpu_info_fw->gc_num_tccs);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index f95092741c38..8001a067700c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -388,6 +388,12 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device 
> *adev)
> adev->gfx.config.max_cu_per_sh = 2 * 
> (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
>   
> le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
> adev->gfx.config.max_sh_per_se = 
> le32_to_cpu(gc_info->gc_num_sa_per_se);
> +
> +   DRM_INFO("discovery: SE %d, SH per SE %d, CU per SH %d\n",
> +   adev->gfx.config.max_shader_engines,
> +   adev->gfx.config.max_sh_per_se,
> +   adev->gfx.config.max_cu_per_sh);
> +
> adev->gfx.config.max_backends_per_se = 
> le32_to_cpu(gc_info->gc_num_rb_per_se);
> adev->gfx.config.max_texture_channel_caches = 
> le32_to_cpu(gc_info->gc_num_gl2c);
> adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 8cdef79de9d4..a26892e71680 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -5432,6 +5432,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device 
> *adev,
> cu_info->ao_cu_mask = ao_cu_mask;
> cu_info->simd_per_cu = NUM_SIMD_PER_CU;
>
> +   DRM_INFO("active_cu_number: %d\n", cu_info->number);
> +
> return 0;
>  }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 95bb2422b27c..bb05a94690d2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -3620,6 +3620,8 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device 
> *adev)
>
> cu_info->number = active_cu_number;
> cu_info->ao_cu_mask = ao_cu_mask;
> +
> +   DRM_INFO("active_cu_number: %d\n", cu_info->number);
>  }
>
>  const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 648d767d14e7..6d16216d5c7c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -5159,6 +5159,8 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device 
> *adev)
> cu_info->max_scratch_slots_per_cu = 32;
> cu_info->wave_front_size = 64;
> cu_info->lds_size = 64;
> +
> +   DRM_INFO("active_cu_number: %d\n", cu_info->number);
>  }
>
>  const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 8b9f440688ed..1073eb5c3cec 100644
> --- 

[RESEND PATCH 3/5] drm/amdgpu: Add task barrier to XGMI hive.

[Andrey Grodzovsky]

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 61d13d8..5cf920d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -261,6 +261,7 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct 
amdgpu_device *adev, int lo
INIT_LIST_HEAD(>device_list);
mutex_init(>hive_lock);
mutex_init(>reset_lock);
+   task_barrier_init(>tb);
 
if (lock)
mutex_lock(>hive_lock);
@@ -408,6 +409,8 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
top_info->num_nodes = count;
hive->number_devices = count;
 
+   task_barrier_add_task(>tb);
+
if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
list_for_each_entry(tmp_adev, >device_list, 
gmc.xgmi.head) {
/* update node list for other device in the hive */
@@ -470,6 +473,7 @@ void amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
mutex_destroy(>hive_lock);
mutex_destroy(>reset_lock);
} else {
+   task_barrier_rem_task(>tb);
amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
mutex_unlock(>hive_lock);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
index bbf504f..74011fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
@@ -22,6 +22,7 @@
 #ifndef __AMDGPU_XGMI_H__
 #define __AMDGPU_XGMI_H__
 
+#include 
 #include "amdgpu_psp.h"
 
 struct amdgpu_hive_info {
@@ -33,6 +34,7 @@ struct amdgpu_hive_info {
struct device_attribute dev_attr;
struct amdgpu_device *adev;
int pstate; /*0 -- low , 1 -- high , -1 unknown*/
+   struct task_barrier tb;
 };
 
 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int 
lock);
-- 
2.7.4

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[RESEND PATCH 5/5] drm/amdgpu: Switch from system_highpri_wq to system_unbound_wq

[Andrey Grodzovsky]

This is to avoid queueing jobs to same CPU during XGMI hive reset
because there is a strict timeline for when the reset commands
must reach all the GPUs in the hive.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e4089a0..1518565 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3842,7 +3842,7 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info 
*hive,
list_for_each_entry(tmp_adev, device_list_handle, 
gmc.xgmi.head) {
/* For XGMI run all resets in parallel to speed up the 
process */
if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
-   if (!queue_work(system_highpri_wq, 
_adev->xgmi_reset_work))
+   if (!queue_work(system_unbound_wq, 
_adev->xgmi_reset_work))
r = -EALREADY;
} else
r = amdgpu_asic_reset(tmp_adev);
-- 
2.7.4

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[RESEND PATCH 4/5] Subject: drm/amdgpu: Redo XGMI reset synchronization.

[Andrey Grodzovsky]

Use task barrier in XGMI hive to synchronize ASIC resets
across devices in XGMI hive.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 42 +-
 1 file changed, 36 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1d19edfa..e4089a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -67,6 +67,7 @@
 #include "amdgpu_tmz.h"
 
 #include 
+#include 
 
 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
@@ -2663,14 +2664,43 @@ static void amdgpu_device_xgmi_reset_func(struct 
work_struct *__work)
 {
struct amdgpu_device *adev =
container_of(__work, struct amdgpu_device, xgmi_reset_work);
+   struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
 
-   if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
-   adev->asic_reset_res = (adev->in_baco == false) ?
-   amdgpu_device_baco_enter(adev->ddev) :
-   qamdgpu_device_baco_exit(adev->ddev);
-   else
-   adev->asic_reset_res = amdgpu_asic_reset(adev);
+   /*
+* Use task barrier to synchronize all xgmi reset works across the
+* hive.
+* task_barrier_enter and task_barrier_exit will block untill all the
+* threads running the xgmi reset works reach those points. I assume
+* guarantee of progress here for all the threads as the workqueue code
+* creates new worker threads as needed by amount of work items in queue
+* (see worker_thread) and also each thread sleeps in the barrir and by
+* this yielding the CPU for other work threads to make progress.
+*/
+   if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
+
+   if (hive)
+   task_barrier_enter(>tb);
+
+   adev->asic_reset_res = amdgpu_device_baco_enter(adev->ddev);
+
+   if (adev->asic_reset_res)
+   goto fail;
+
+   if (hive)
+   task_barrier_exit(>tb);
+
+   adev->asic_reset_res = amdgpu_device_baco_exit(adev->ddev);
+
+   if (adev->asic_reset_res)
+   goto fail;
+   } else {
+   if (hive)
+   task_barrier_full(>tb);
+
+   adev->asic_reset_res =  amdgpu_asic_reset(adev);
+   }
 
+fail:
if (adev->asic_reset_res)
DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
 adev->asic_reset_res, adev->ddev->unique);
-- 
2.7.4

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[RESEND PATCH 2/5] drm: Add Reusable task barrier.

[Andrey Grodzovsky]

It is used to synchronize N threads at a rendevouz point before execution
of critical code that has to be started by all the threads at approximatly
the same time.

Signed-off-by: Andrey Grodzovsky 
---
 include/drm/task_barrier.h | 106 +
 1 file changed, 106 insertions(+)
 create mode 100644 include/drm/task_barrier.h

diff --git a/include/drm/task_barrier.h b/include/drm/task_barrier.h
new file mode 100644
index 000..81fb0f7
--- /dev/null
+++ b/include/drm/task_barrier.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include 
+#include 
+
+/*
+ * Reusable 2 PHASE task barrier (randevouz point) implementation for N tasks.
+ * Based on the Little book of sempahores - 
https://greenteapress.com/wp/semaphores/
+ */
+
+
+
+#ifndef DRM_TASK_BARRIER_H_
+#define DRM_TASK_BARRIER_H_
+
+/*
+ * Represents an instance of a task barrier.
+ */
+struct task_barrier {
+   unsigned int n;
+   atomic_t count;
+   struct semaphore enter_turnstile;
+   struct semaphore exit_turnstile;
+};
+
+static inline void task_barrier_signal_turnstile(struct semaphore *turnstile,
+unsigned int n)
+{
+   int i;
+
+   for (i = 0 ; i < n; i++)
+   up(turnstile);
+}
+
+static inline void task_barrier_init(struct task_barrier *tb)
+{
+   tb->n = 0;
+   atomic_set(>count, 0);
+   sema_init(>enter_turnstile, 0);
+   sema_init(>exit_turnstile, 0);
+}
+
+static inline void task_barrier_add_task(struct task_barrier *tb)
+{
+   tb->n++;
+}
+
+static inline void task_barrier_rem_task(struct task_barrier *tb)
+{
+   tb->n--;
+}
+
+/*
+ * Lines up all the threads BEFORE the critical point.
+ *
+ * When all thread passed this code the entry barrier is back to locked state.
+ */
+static inline void task_barrier_enter(struct task_barrier *tb)
+{
+   if (atomic_inc_return(>count) == tb->n)
+   task_barrier_signal_turnstile(>enter_turnstile, tb->n);
+
+   down(>enter_turnstile);
+}
+
+/*
+ * Lines up all the threads AFTER the critical point.
+ *
+ * This function is used to avoid any one thread running ahead of the reset if
+ * the barrier is used in a loop (repeatedly) .
+ */
+static inline void task_barrier_exit(struct task_barrier *tb)
+{
+   if (atomic_dec_return(>count) == 0)
+   task_barrier_signal_turnstile(>exit_turnstile, tb->n);
+
+   down(>exit_turnstile);
+}
+
+static inline void task_barrier_full(struct task_barrier *tb)
+{
+   task_barrier_enter(tb);
+   task_barrier_exit(tb);
+}
+
+#endif
-- 
2.7.4

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[RESEND PATCH 1/5] drm/amdgpu: reverts commit b01245ff54db66073b104ac9d9fbefb7b264b36d.

[Andrey Grodzovsky]

In preparation for doing XGMI reset synchronization using task barrier.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 76 +-
 2 files changed, 12 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a78a363..50bab33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1001,8 +1001,6 @@ struct amdgpu_device {
 
boolpm_sysfs_en;
boolucode_sysfs_en;
-
-   boolin_baco;
 };
 
 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5f..1d19edfa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2667,7 +2667,7 @@ static void amdgpu_device_xgmi_reset_func(struct 
work_struct *__work)
if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
adev->asic_reset_res = (adev->in_baco == false) ?
amdgpu_device_baco_enter(adev->ddev) :
-   amdgpu_device_baco_exit(adev->ddev);
+   qamdgpu_device_baco_exit(adev->ddev);
else
adev->asic_reset_res = amdgpu_asic_reset(adev);
 
@@ -3796,18 +3796,13 @@ static int amdgpu_device_pre_asic_reset(struct 
amdgpu_device *adev,
return r;
 }
 
-static int amdgpu_do_asic_reset(struct amdgpu_device *adev,
-  struct amdgpu_hive_info *hive,
+static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
   struct list_head *device_list_handle,
   bool *need_full_reset_arg)
 {
struct amdgpu_device *tmp_adev = NULL;
bool need_full_reset = *need_full_reset_arg, vram_lost = false;
int r = 0;
-   int cpu = smp_processor_id();
-   bool use_baco =
-   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ?
-   true : false;
 
/*
 * ASIC reset has to be done on all HGMI hive nodes ASAP
@@ -3815,62 +3810,22 @@ static int amdgpu_do_asic_reset(struct amdgpu_device 
*adev,
 */
if (need_full_reset) {
list_for_each_entry(tmp_adev, device_list_handle, 
gmc.xgmi.head) {
-   /*
-* For XGMI run all resets in parallel to speed up the
-* process by scheduling the highpri wq on different
-* cpus. For XGMI with baco reset, all nodes must enter
-* baco within close proximity before anyone exit.
-*/
+   /* For XGMI run all resets in parallel to speed up the 
process */
if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
-   if (!queue_work_on(cpu, system_highpri_wq,
-  _adev->xgmi_reset_work))
+   if (!queue_work(system_highpri_wq, 
_adev->xgmi_reset_work))
r = -EALREADY;
-   cpu = cpumask_next(cpu, cpu_online_mask);
} else
r = amdgpu_asic_reset(tmp_adev);
-   if (r)
-   break;
-   }
-
-   /* For XGMI wait for all work to complete before proceed */
-   if (!r) {
-   list_for_each_entry(tmp_adev, device_list_handle,
-   gmc.xgmi.head) {
-   if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
-   flush_work(_adev->xgmi_reset_work);
-   r = tmp_adev->asic_reset_res;
-   if (r)
-   break;
-   if (use_baco)
-   tmp_adev->in_baco = true;
-   }
-   }
-   }
 
-   /*
-* For XGMI with baco reset, need exit baco phase by scheduling
-* xgmi_reset_work one more time. PSP reset and sGPU skips this
-* phase. Not assume the situation that PSP reset and baco reset
-* coexist within an XGMI hive.
-*/
-
-   if (!r && use_baco) {
-   cpu = smp_processor_id();
-   list_for_each_entry(tmp_adev, device_list_handle,
-   gmc.xgmi.head) {
-  

[PATCH] drm/amdgpu: Add CU info print log

[Yong Zhao]

The log will be useful for easily getting the CU info on various
emulation models or ASICs.

Change-Id: Ic1c914938aa3445d8dbfdf6a237bc1d58b0d5267
Signed-off-by: Yong Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 6 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++
 7 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8992506541d8..df9732510012 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1529,6 +1529,12 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
amdgpu_device *adev)
adev->gfx.config.max_shader_engines = 
le32_to_cpu(gpu_info_fw->gc_num_se);
adev->gfx.config.max_cu_per_sh = 
le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
adev->gfx.config.max_sh_per_se = 
le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
+
+   DRM_INFO("gpu_info: SE %d, SH per SE %d, CU per SH %d\n",
+   adev->gfx.config.max_shader_engines,
+   adev->gfx.config.max_sh_per_se,
+   adev->gfx.config.max_cu_per_sh);
+
adev->gfx.config.max_backends_per_se = 
le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
adev->gfx.config.max_texture_channel_caches =
le32_to_cpu(gpu_info_fw->gc_num_tccs);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index f95092741c38..8001a067700c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -388,6 +388,12 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device 
*adev)
adev->gfx.config.max_cu_per_sh = 2 * 
(le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
  
le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
+
+   DRM_INFO("discovery: SE %d, SH per SE %d, CU per SH %d\n",
+   adev->gfx.config.max_shader_engines,
+   adev->gfx.config.max_sh_per_se,
+   adev->gfx.config.max_cu_per_sh);
+
adev->gfx.config.max_backends_per_se = 
le32_to_cpu(gc_info->gc_num_rb_per_se);
adev->gfx.config.max_texture_channel_caches = 
le32_to_cpu(gc_info->gc_num_gl2c);
adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8cdef79de9d4..a26892e71680 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5432,6 +5432,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device 
*adev,
cu_info->ao_cu_mask = ao_cu_mask;
cu_info->simd_per_cu = NUM_SIMD_PER_CU;
 
+   DRM_INFO("active_cu_number: %d\n", cu_info->number);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 95bb2422b27c..bb05a94690d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3620,6 +3620,8 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device 
*adev)
 
cu_info->number = active_cu_number;
cu_info->ao_cu_mask = ao_cu_mask;
+
+   DRM_INFO("active_cu_number: %d\n", cu_info->number);
 }
 
 const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 648d767d14e7..6d16216d5c7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -5159,6 +5159,8 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device 
*adev)
cu_info->max_scratch_slots_per_cu = 32;
cu_info->wave_front_size = 64;
cu_info->lds_size = 64;
+
+   DRM_INFO("active_cu_number: %d\n", cu_info->number);
 }
 
 const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 8b9f440688ed..1073eb5c3cec 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7141,6 +7141,8 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device 
*adev)
cu_info->max_scratch_slots_per_cu = 32;
cu_info->wave_front_size = 64;
cu_info->lds_size = 64;
+
+   DRM_INFO("active_cu_number: %d\n", cu_info->number);
 }
 
 const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Re: [PATCH 2/5] drm: Add Reusable task barrier.

[Alex Deucher]

On Wed, Dec 11, 2019 at 3:07 PM Andrey Grodzovsky
 wrote:
>
> It is used to synchronize N threads at a rendevouz point before execution
> of critical code that has to be started by all the threads at approximatly
> the same time.
>
> Signed-off-by: Andrey Grodzovsky 

You should resend to dri-devel since this task barrier is being added
to common code.

Alex

> ---
>  include/drm/task_barrier.h | 106 
> +
>  1 file changed, 106 insertions(+)
>  create mode 100644 include/drm/task_barrier.h
>
> diff --git a/include/drm/task_barrier.h b/include/drm/task_barrier.h
> new file mode 100644
> index 000..81fb0f7
> --- /dev/null
> +++ b/include/drm/task_barrier.h
> @@ -0,0 +1,106 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +#include 
> +#include 
> +
> +/*
> + * Reusable 2 PHASE task barrier (randevouz point) implementation for N 
> tasks.
> + * Based on the Little book of sempahores - 
> https://greenteapress.com/wp/semaphores/
> + */
> +
> +
> +
> +#ifndef DRM_TASK_BARRIER_H_
> +#define DRM_TASK_BARRIER_H_
> +
> +/*
> + * Represents an instance of a task barrier.
> + */
> +struct task_barrier {
> +   unsigned int n;
> +   atomic_t count;
> +   struct semaphore enter_turnstile;
> +   struct semaphore exit_turnstile;
> +};
> +
> +static inline void task_barrier_signal_turnstile(struct semaphore *turnstile,
> +unsigned int n)
> +{
> +   int i;
> +
> +   for (i = 0 ; i < n; i++)
> +   up(turnstile);
> +}
> +
> +static inline void task_barrier_init(struct task_barrier *tb)
> +{
> +   tb->n = 0;
> +   atomic_set(>count, 0);
> +   sema_init(>enter_turnstile, 0);
> +   sema_init(>exit_turnstile, 0);
> +}
> +
> +static inline void task_barrier_add_task(struct task_barrier *tb)
> +{
> +   tb->n++;
> +}
> +
> +static inline void task_barrier_rem_task(struct task_barrier *tb)
> +{
> +   tb->n--;
> +}
> +
> +/*
> + * Lines up all the threads BEFORE the critical point.
> + *
> + * When all thread passed this code the entry barrier is back to locked 
> state.
> + */
> +static inline void task_barrier_enter(struct task_barrier *tb)
> +{
> +   if (atomic_inc_return(>count) == tb->n)
> +   task_barrier_signal_turnstile(>enter_turnstile, tb->n);
> +
> +   down(>enter_turnstile);
> +}
> +
> +/*
> + * Lines up all the threads AFTER the critical point.
> + *
> + * This function is used to avoid any one thread running ahead of the reset 
> if
> + * the barrier is used in a loop (repeatedly) .
> + */
> +static inline void task_barrier_exit(struct task_barrier *tb)
> +{
> +   if (atomic_dec_return(>count) == 0)
> +   task_barrier_signal_turnstile(>exit_turnstile, tb->n);
> +
> +   down(>exit_turnstile);
> +}
> +
> +static inline void task_barrier_full(struct task_barrier *tb)
> +{
> +   task_barrier_enter(tb);
> +   task_barrier_exit(tb);
> +}
> +
> +#endif
> --
> 2.7.4
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 1/5] drm/amdgpu: reverts commit b01245ff54db66073b104ac9d9fbefb7b264b36d.

[Andrey Grodzovsky]

In preparation for doing XGMI reset synchronization using task barrier.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 76 +-
 2 files changed, 12 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a78a363..50bab33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1001,8 +1001,6 @@ struct amdgpu_device {
 
boolpm_sysfs_en;
boolucode_sysfs_en;
-
-   boolin_baco;
 };
 
 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5f..1d19edfa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2667,7 +2667,7 @@ static void amdgpu_device_xgmi_reset_func(struct 
work_struct *__work)
if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
adev->asic_reset_res = (adev->in_baco == false) ?
amdgpu_device_baco_enter(adev->ddev) :
-   amdgpu_device_baco_exit(adev->ddev);
+   qamdgpu_device_baco_exit(adev->ddev);
else
adev->asic_reset_res = amdgpu_asic_reset(adev);
 
@@ -3796,18 +3796,13 @@ static int amdgpu_device_pre_asic_reset(struct 
amdgpu_device *adev,
return r;
 }
 
-static int amdgpu_do_asic_reset(struct amdgpu_device *adev,
-  struct amdgpu_hive_info *hive,
+static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
   struct list_head *device_list_handle,
   bool *need_full_reset_arg)
 {
struct amdgpu_device *tmp_adev = NULL;
bool need_full_reset = *need_full_reset_arg, vram_lost = false;
int r = 0;
-   int cpu = smp_processor_id();
-   bool use_baco =
-   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ?
-   true : false;
 
/*
 * ASIC reset has to be done on all HGMI hive nodes ASAP
@@ -3815,62 +3810,22 @@ static int amdgpu_do_asic_reset(struct amdgpu_device 
*adev,
 */
if (need_full_reset) {
list_for_each_entry(tmp_adev, device_list_handle, 
gmc.xgmi.head) {
-   /*
-* For XGMI run all resets in parallel to speed up the
-* process by scheduling the highpri wq on different
-* cpus. For XGMI with baco reset, all nodes must enter
-* baco within close proximity before anyone exit.
-*/
+   /* For XGMI run all resets in parallel to speed up the 
process */
if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
-   if (!queue_work_on(cpu, system_highpri_wq,
-  _adev->xgmi_reset_work))
+   if (!queue_work(system_highpri_wq, 
_adev->xgmi_reset_work))
r = -EALREADY;
-   cpu = cpumask_next(cpu, cpu_online_mask);
} else
r = amdgpu_asic_reset(tmp_adev);
-   if (r)
-   break;
-   }
-
-   /* For XGMI wait for all work to complete before proceed */
-   if (!r) {
-   list_for_each_entry(tmp_adev, device_list_handle,
-   gmc.xgmi.head) {
-   if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
-   flush_work(_adev->xgmi_reset_work);
-   r = tmp_adev->asic_reset_res;
-   if (r)
-   break;
-   if (use_baco)
-   tmp_adev->in_baco = true;
-   }
-   }
-   }
 
-   /*
-* For XGMI with baco reset, need exit baco phase by scheduling
-* xgmi_reset_work one more time. PSP reset and sGPU skips this
-* phase. Not assume the situation that PSP reset and baco reset
-* coexist within an XGMI hive.
-*/
-
-   if (!r && use_baco) {
-   cpu = smp_processor_id();
-   list_for_each_entry(tmp_adev, device_list_handle,
-   gmc.xgmi.head) {
-  

[PATCH 2/5] drm: Add Reusable task barrier.

[Andrey Grodzovsky]

It is used to synchronize N threads at a rendevouz point before execution
of critical code that has to be started by all the threads at approximatly
the same time.

Signed-off-by: Andrey Grodzovsky 
---
 include/drm/task_barrier.h | 106 +
 1 file changed, 106 insertions(+)
 create mode 100644 include/drm/task_barrier.h

diff --git a/include/drm/task_barrier.h b/include/drm/task_barrier.h
new file mode 100644
index 000..81fb0f7
--- /dev/null
+++ b/include/drm/task_barrier.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include 
+#include 
+
+/*
+ * Reusable 2 PHASE task barrier (randevouz point) implementation for N tasks.
+ * Based on the Little book of sempahores - 
https://greenteapress.com/wp/semaphores/
+ */
+
+
+
+#ifndef DRM_TASK_BARRIER_H_
+#define DRM_TASK_BARRIER_H_
+
+/*
+ * Represents an instance of a task barrier.
+ */
+struct task_barrier {
+   unsigned int n;
+   atomic_t count;
+   struct semaphore enter_turnstile;
+   struct semaphore exit_turnstile;
+};
+
+static inline void task_barrier_signal_turnstile(struct semaphore *turnstile,
+unsigned int n)
+{
+   int i;
+
+   for (i = 0 ; i < n; i++)
+   up(turnstile);
+}
+
+static inline void task_barrier_init(struct task_barrier *tb)
+{
+   tb->n = 0;
+   atomic_set(>count, 0);
+   sema_init(>enter_turnstile, 0);
+   sema_init(>exit_turnstile, 0);
+}
+
+static inline void task_barrier_add_task(struct task_barrier *tb)
+{
+   tb->n++;
+}
+
+static inline void task_barrier_rem_task(struct task_barrier *tb)
+{
+   tb->n--;
+}
+
+/*
+ * Lines up all the threads BEFORE the critical point.
+ *
+ * When all thread passed this code the entry barrier is back to locked state.
+ */
+static inline void task_barrier_enter(struct task_barrier *tb)
+{
+   if (atomic_inc_return(>count) == tb->n)
+   task_barrier_signal_turnstile(>enter_turnstile, tb->n);
+
+   down(>enter_turnstile);
+}
+
+/*
+ * Lines up all the threads AFTER the critical point.
+ *
+ * This function is used to avoid any one thread running ahead of the reset if
+ * the barrier is used in a loop (repeatedly) .
+ */
+static inline void task_barrier_exit(struct task_barrier *tb)
+{
+   if (atomic_dec_return(>count) == 0)
+   task_barrier_signal_turnstile(>exit_turnstile, tb->n);
+
+   down(>exit_turnstile);
+}
+
+static inline void task_barrier_full(struct task_barrier *tb)
+{
+   task_barrier_enter(tb);
+   task_barrier_exit(tb);
+}
+
+#endif
-- 
2.7.4

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[PATCH 3/5] drm/amdgpu: Add task barrier to XGMI hive.

[Andrey Grodzovsky]

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 61d13d8..5cf920d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -261,6 +261,7 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct 
amdgpu_device *adev, int lo
INIT_LIST_HEAD(>device_list);
mutex_init(>hive_lock);
mutex_init(>reset_lock);
+   task_barrier_init(>tb);
 
if (lock)
mutex_lock(>hive_lock);
@@ -408,6 +409,8 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
top_info->num_nodes = count;
hive->number_devices = count;
 
+   task_barrier_add_task(>tb);
+
if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
list_for_each_entry(tmp_adev, >device_list, 
gmc.xgmi.head) {
/* update node list for other device in the hive */
@@ -470,6 +473,7 @@ void amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
mutex_destroy(>hive_lock);
mutex_destroy(>reset_lock);
} else {
+   task_barrier_rem_task(>tb);
amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
mutex_unlock(>hive_lock);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
index bbf504f..74011fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
@@ -22,6 +22,7 @@
 #ifndef __AMDGPU_XGMI_H__
 #define __AMDGPU_XGMI_H__
 
+#include 
 #include "amdgpu_psp.h"
 
 struct amdgpu_hive_info {
@@ -33,6 +34,7 @@ struct amdgpu_hive_info {
struct device_attribute dev_attr;
struct amdgpu_device *adev;
int pstate; /*0 -- low , 1 -- high , -1 unknown*/
+   struct task_barrier tb;
 };
 
 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int 
lock);
-- 
2.7.4

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[PATCH 5/5] drm/amdgpu: Switch from system_highpri_wq to system_unbound_wq

[Andrey Grodzovsky]

This is to avoid queueing jobs to same CPU during XGMI hive reset
because there is a strict timeline for when the reset commands
must reach all the GPUs in the hive.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e4089a0..1518565 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3842,7 +3842,7 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info 
*hive,
list_for_each_entry(tmp_adev, device_list_handle, 
gmc.xgmi.head) {
/* For XGMI run all resets in parallel to speed up the 
process */
if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
-   if (!queue_work(system_highpri_wq, 
_adev->xgmi_reset_work))
+   if (!queue_work(system_unbound_wq, 
_adev->xgmi_reset_work))
r = -EALREADY;
} else
r = amdgpu_asic_reset(tmp_adev);
-- 
2.7.4

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[PATCH 4/5] Subject: drm/amdgpu: Redo XGMI reset synchronization.

[Andrey Grodzovsky]

Use task barrier in XGMI hive to synchronize ASIC resets
across devices in XGMI hive.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 42 +-
 1 file changed, 36 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1d19edfa..e4089a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -67,6 +67,7 @@
 #include "amdgpu_tmz.h"
 
 #include 
+#include 
 
 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
@@ -2663,14 +2664,43 @@ static void amdgpu_device_xgmi_reset_func(struct 
work_struct *__work)
 {
struct amdgpu_device *adev =
container_of(__work, struct amdgpu_device, xgmi_reset_work);
+   struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
 
-   if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
-   adev->asic_reset_res = (adev->in_baco == false) ?
-   amdgpu_device_baco_enter(adev->ddev) :
-   qamdgpu_device_baco_exit(adev->ddev);
-   else
-   adev->asic_reset_res = amdgpu_asic_reset(adev);
+   /*
+* Use task barrier to synchronize all xgmi reset works across the
+* hive.
+* task_barrier_enter and task_barrier_exit will block untill all the
+* threads running the xgmi reset works reach those points. I assume
+* guarantee of progress here for all the threads as the workqueue code
+* creates new worker threads as needed by amount of work items in queue
+* (see worker_thread) and also each thread sleeps in the barrir and by
+* this yielding the CPU for other work threads to make progress.
+*/
+   if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
+
+   if (hive)
+   task_barrier_enter(>tb);
+
+   adev->asic_reset_res = amdgpu_device_baco_enter(adev->ddev);
+
+   if (adev->asic_reset_res)
+   goto fail;
+
+   if (hive)
+   task_barrier_exit(>tb);
+
+   adev->asic_reset_res = amdgpu_device_baco_exit(adev->ddev);
+
+   if (adev->asic_reset_res)
+   goto fail;
+   } else {
+   if (hive)
+   task_barrier_full(>tb);
+
+   adev->asic_reset_res =  amdgpu_asic_reset(adev);
+   }
 
+fail:
if (adev->asic_reset_res)
DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
 adev->asic_reset_res, adev->ddev->unique);
-- 
2.7.4

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RE: [PATCH] drm/amdgpu: add JPEG check to VCN idle handler and begin use

[Zhang, Boyuan]

This patch is 
Reviewed-by: Boyuan Zhang 


-Original Message-
From: amd-gfx  On Behalf Of Leo Liu
Sent: December 11, 2019 2:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Leo 
Subject: [PATCH] drm/amdgpu: add JPEG check to VCN idle handler and begin use

Since it's only needed with VCN1.0 when HW has no its own JPEG HW IP block

Signed-off-by: Leo Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 29 +++--  
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  2 ++
 2 files changed, 20 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 428cfd58b37d..95ac721f2de0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -186,6 +186,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
}
}
 
+   adev->vcn.has_jpeg_block = (amdgpu_device_ip_get_ip_block(adev, 
AMD_IP_BLOCK_TYPE_JPEG)) ?
+   true : false;
+
return 0;
 }
 
@@ -306,15 +309,17 @@ static void amdgpu_vcn_idle_work_handler(struct 
work_struct *work)
else
new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 
-   if 
(amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec))
-   new_state.jpeg = VCN_DPG_STATE__PAUSE;
-   else
-   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
-
+   if (!adev->vcn.has_jpeg_block) {
+   if 
(amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec))
+   new_state.jpeg = VCN_DPG_STATE__PAUSE;
+   else
+   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+   }
adev->vcn.pause_dpg_mode(adev, _state);
}
 
-   fence[j] += 
amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec);
+   if (!adev->vcn.has_jpeg_block)
+   fence[j] += 
+amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec);
fence[j] += 
amdgpu_fence_count_emitted(>vcn.inst[j].ring_dec);
fences += fence[j];
}
@@ -358,14 +363,16 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
else
new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 
-   if 
(amdgpu_fence_count_emitted(>jpeg.inst[ring->me].ring_dec))
-   new_state.jpeg = VCN_DPG_STATE__PAUSE;
-   else
-   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+   if (!adev->vcn.has_jpeg_block) {
+   if 
(amdgpu_fence_count_emitted(>jpeg.inst[ring->me].ring_dec))
+   new_state.jpeg = VCN_DPG_STATE__PAUSE;
+   else
+   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+   }
 
if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
new_state.fw_based = VCN_DPG_STATE__PAUSE;
-   else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
+   else if (!adev->vcn.has_jpeg_block && ring->funcs->type == 
+AMDGPU_RING_TYPE_VCN_JPEG)
new_state.jpeg = VCN_DPG_STATE__PAUSE;
 
adev->vcn.pause_dpg_mode(adev, _state); diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 402a5046b985..9a2381d006c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -192,6 +192,8 @@ struct amdgpu_vcn {
unsignedharvest_config;
int (*pause_dpg_mode)(struct amdgpu_device *adev,
struct dpg_pause_state *new_state);
+
+   bool has_jpeg_block;
 };
 
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
--
2.17.1

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Re: [PATCH] drm/amdgpu: add JPEG check to VCN idle handler and begin use

[Alex Deucher]

On Wed, Dec 11, 2019 at 2:49 PM Leo Liu  wrote:
>
> Since it's only needed with VCN1.0 when HW has no its
> own JPEG HW IP block

typo "HW does not have its own"
With that fixed:
Reviewed-by: Alex Deucher 

>
> Signed-off-by: Leo Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 29 +++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  2 ++
>  2 files changed, 20 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 428cfd58b37d..95ac721f2de0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -186,6 +186,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> }
> }
>
> +   adev->vcn.has_jpeg_block = (amdgpu_device_ip_get_ip_block(adev, 
> AMD_IP_BLOCK_TYPE_JPEG)) ?
> +   true : false;
> +
> return 0;
>  }
>
> @@ -306,15 +309,17 @@ static void amdgpu_vcn_idle_work_handler(struct 
> work_struct *work)
> else
> new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
>
> -   if 
> (amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec))
> -   new_state.jpeg = VCN_DPG_STATE__PAUSE;
> -   else
> -   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
> -
> +   if (!adev->vcn.has_jpeg_block) {
> +   if 
> (amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec))
> +   new_state.jpeg = VCN_DPG_STATE__PAUSE;
> +   else
> +   new_state.jpeg = 
> VCN_DPG_STATE__UNPAUSE;
> +   }
> adev->vcn.pause_dpg_mode(adev, _state);
> }
>
> -   fence[j] += 
> amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec);
> +   if (!adev->vcn.has_jpeg_block)
> +   fence[j] += 
> amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec);
> fence[j] += 
> amdgpu_fence_count_emitted(>vcn.inst[j].ring_dec);
> fences += fence[j];
> }
> @@ -358,14 +363,16 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
> else
> new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
>
> -   if 
> (amdgpu_fence_count_emitted(>jpeg.inst[ring->me].ring_dec))
> -   new_state.jpeg = VCN_DPG_STATE__PAUSE;
> -   else
> -   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
> +   if (!adev->vcn.has_jpeg_block) {
> +   if 
> (amdgpu_fence_count_emitted(>jpeg.inst[ring->me].ring_dec))
> +   new_state.jpeg = VCN_DPG_STATE__PAUSE;
> +   else
> +   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
> +   }
>
> if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
> new_state.fw_based = VCN_DPG_STATE__PAUSE;
> -   else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
> +   else if (!adev->vcn.has_jpeg_block && ring->funcs->type == 
> AMDGPU_RING_TYPE_VCN_JPEG)
> new_state.jpeg = VCN_DPG_STATE__PAUSE;
>
> adev->vcn.pause_dpg_mode(adev, _state);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index 402a5046b985..9a2381d006c6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -192,6 +192,8 @@ struct amdgpu_vcn {
> unsignedharvest_config;
> int (*pause_dpg_mode)(struct amdgpu_device *adev,
> struct dpg_pause_state *new_state);
> +
> +   bool has_jpeg_block;
>  };
>
>  int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
> --
> 2.17.1
>
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[PATCH] drm/amdgpu: add JPEG check to VCN idle handler and begin use

[Leo Liu]

Since it's only needed with VCN1.0 when HW has no its
own JPEG HW IP block

Signed-off-by: Leo Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 29 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  2 ++
 2 files changed, 20 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 428cfd58b37d..95ac721f2de0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -186,6 +186,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
}
}
 
+   adev->vcn.has_jpeg_block = (amdgpu_device_ip_get_ip_block(adev, 
AMD_IP_BLOCK_TYPE_JPEG)) ?
+   true : false;
+
return 0;
 }
 
@@ -306,15 +309,17 @@ static void amdgpu_vcn_idle_work_handler(struct 
work_struct *work)
else
new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 
-   if 
(amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec))
-   new_state.jpeg = VCN_DPG_STATE__PAUSE;
-   else
-   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
-
+   if (!adev->vcn.has_jpeg_block) {
+   if 
(amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec))
+   new_state.jpeg = VCN_DPG_STATE__PAUSE;
+   else
+   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+   }
adev->vcn.pause_dpg_mode(adev, _state);
}
 
-   fence[j] += 
amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec);
+   if (!adev->vcn.has_jpeg_block)
+   fence[j] += 
amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec);
fence[j] += 
amdgpu_fence_count_emitted(>vcn.inst[j].ring_dec);
fences += fence[j];
}
@@ -358,14 +363,16 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
else
new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 
-   if 
(amdgpu_fence_count_emitted(>jpeg.inst[ring->me].ring_dec))
-   new_state.jpeg = VCN_DPG_STATE__PAUSE;
-   else
-   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+   if (!adev->vcn.has_jpeg_block) {
+   if 
(amdgpu_fence_count_emitted(>jpeg.inst[ring->me].ring_dec))
+   new_state.jpeg = VCN_DPG_STATE__PAUSE;
+   else
+   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+   }
 
if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
new_state.fw_based = VCN_DPG_STATE__PAUSE;
-   else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
+   else if (!adev->vcn.has_jpeg_block && ring->funcs->type == 
AMDGPU_RING_TYPE_VCN_JPEG)
new_state.jpeg = VCN_DPG_STATE__PAUSE;
 
adev->vcn.pause_dpg_mode(adev, _state);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 402a5046b985..9a2381d006c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -192,6 +192,8 @@ struct amdgpu_vcn {
unsignedharvest_config;
int (*pause_dpg_mode)(struct amdgpu_device *adev,
struct dpg_pause_state *new_state);
+
+   bool has_jpeg_block;
 };
 
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
-- 
2.17.1

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[PATCH] Revert "drm/amdgpu: dont schedule jobs while in reset"

[Alex Deucher]

This reverts commit f2efc6e60089c99c342a6b7da47f1037e06c4296.

This was fixed properly for 5.5, but came back via 5.4 merge
into drm-next, so revert it again.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 2cdaf3b2a721..6614d8a6f4c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -604,11 +604,8 @@ void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
continue;
}
 
-   for (i = 0; i < num_entities; i++) {
-   mutex_lock(>adev->lock_reset);
+   for (i = 0; i < num_entities; i++)
drm_sched_entity_fini(>entities[0][i].entity);
-   mutex_unlock(>adev->lock_reset);
-   }
}
 }
 
-- 
2.23.0

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Re: [PATCH] drm/dp_mst: clear time slots for ports invalid

[Sasha Levin]

Hi,

[This is an automated email]

This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all

The bot has tested the following trees: v5.4.2, v5.3.15, v4.19.88, v4.14.158, 
v4.9.206, v4.4.206.

v5.4.2: Failed to apply! Possible dependencies:
14692a3637d4 ("drm/dp_mst: Add probe_lock")
37dfdc55ffeb ("drm/dp_mst: Cleanup drm_dp_send_link_address() a bit")
3f9b3f02dda5 ("drm/dp_mst: Protect drm_dp_mst_port members with locking")
50094b5dcd32 ("drm/dp_mst: Destroy topology_mgr mutexes")
5950f0b797fc ("drm/dp_mst: Move link address dumping into a function")
60f9ae9d0d3d ("drm/dp_mst: Remove huge conditional in 
drm_dp_mst_handle_up_req()")
7cb12d48314e ("drm/dp_mst: Destroy MSTBs asynchronously")
9408cc94eb04 ("drm/dp_mst: Handle UP requests asynchronously")
a29d881875fc ("drm/dp_mst: Refactor drm_dp_mst_handle_up_req()")
c485e2c97dae ("drm/dp_mst: Refactor pdt setup/teardown, add more locking")
caf81ec6cd72 ("drm: Destroy the correct mutex name in 
drm_dp_mst_topology_mgr_destroy")
dad7d84f8835 ("drm/dp_mst: Don't forget to update port->input in 
drm_dp_mst_handle_conn_stat()")
e2839ff692c6 ("drm/dp_mst: Rename drm_dp_add_port and drm_dp_update_port")

v5.3.15: Failed to apply! Possible dependencies:
14692a3637d4 ("drm/dp_mst: Add probe_lock")
37dfdc55ffeb ("drm/dp_mst: Cleanup drm_dp_send_link_address() a bit")
3f9b3f02dda5 ("drm/dp_mst: Protect drm_dp_mst_port members with locking")
50094b5dcd32 ("drm/dp_mst: Destroy topology_mgr mutexes")
562836a269e3 ("drm/dp_mst: Enable registration of AUX devices for MST 
ports")
5950f0b797fc ("drm/dp_mst: Move link address dumping into a function")
60f9ae9d0d3d ("drm/dp_mst: Remove huge conditional in 
drm_dp_mst_handle_up_req()")
7cb12d48314e ("drm/dp_mst: Destroy MSTBs asynchronously")
9408cc94eb04 ("drm/dp_mst: Handle UP requests asynchronously")
a29d881875fc ("drm/dp_mst: Refactor drm_dp_mst_handle_up_req()")
c485e2c97dae ("drm/dp_mst: Refactor pdt setup/teardown, add more locking")
caf81ec6cd72 ("drm: Destroy the correct mutex name in 
drm_dp_mst_topology_mgr_destroy")
dad7d84f8835 ("drm/dp_mst: Don't forget to update port->input in 
drm_dp_mst_handle_conn_stat()")
e2839ff692c6 ("drm/dp_mst: Rename drm_dp_add_port and drm_dp_update_port")

v4.19.88: Failed to apply! Possible dependencies:
1e55a53a28d3 ("drm: Trivial comment grammar cleanups")
706246c761dd ("drm/dp_mst: Refactor drm_dp_update_payload_part1()")
72fdb40c1a4b ("drm: extract drm_atomic_uapi.c")
7f4de521001f ("drm/atomic: Add __drm_atomic_helper_plane_reset")
a5ec8332d428 ("drm: Add per-plane pixel blend mode property")
c485e2c97dae ("drm/dp_mst: Refactor pdt setup/teardown, add more locking")
d0757afd00d7 ("drm/dp_mst: Rename drm_dp_mst_get_validated_(port|mstb)_ref 
and friends")
d86552efe10a ("drm/atomic: trim driver interface/docs")
dad7d84f8835 ("drm/dp_mst: Don't forget to update port->input in 
drm_dp_mst_handle_conn_stat()")
de9f8eea5a44 ("drm/atomic_helper: Stop modesets on unregistered connectors 
harder")
ebcc0e6b5091 ("drm/dp_mst: Introduce new refcounting scheme for mstbs and 
ports")
fc63668656bd ("drm/dp_mst: Remove bogus conditional in 
drm_dp_update_payload_part1()")

v4.14.158: Failed to apply! Possible dependencies:
0bb9c2b27f5e ("drm/dp/mst: Sideband message transaction to power up/down 
nodes")
163bcc2c74a2 ("drm/atomic: Move drm_crtc_commit to drm_crtc_state, v4.")
179c02fe90a4 ("drm/tve200: Add new driver for TVE200")
1e55a53a28d3 ("drm: Trivial comment grammar cleanups")
21a01abbe32a ("drm/atomic: Fix freeing connector/plane state too early by 
tracking commits, v3.")
22a07038c0ea ("drm: NULL pointer dereference [null-pointer-deref] (CWE 476) 
problem")
24557865c8b1 ("drm: Add Content Protection property")
2ed077e467ee ("drm: Add drm_object lease infrastructure [v5]")
34ca26a98ad6 ("drm/atomic_helper: Allow DPMS On<->Off changes for 
unregistered connectors")
0d4cf21b ("drm: add connector info/property for non-desktop displays 
[v2]")
6d544fd6f4e1 ("drm/doc: Put all driver docs into a separate chapter")
706246c761dd ("drm/dp_mst: Refactor drm_dp_update_payload_part1()")
72fdb40c1a4b ("drm: extract drm_atomic_uapi.c")
8d70f395e6cb ("drm: Add support for a panel-orientation connector property, 
v6")
935774cd71fe ("drm: Add writeback connector type")
c485e2c97dae ("drm/dp_mst: Refactor pdt setup/teardown, add more locking")
c76f0f7cb546 ("drm: Begin an API for in-kernel clients")
d0757afd00d7 ("drm/dp_mst: Rename drm_dp_mst_get_validated_(port|mstb)_ref 
and friends")
dad7d84f8835 ("drm/dp_mst: Don't forget to update port->input in 
drm_dp_mst_handle_conn_stat()")
de9f8eea5a44 ("drm/atomic_helper: Stop modesets on unregistered connectors 
harder")
e96550956fbc 

[PATCH] drm/amdgpu: s/ENCRYPTED/SECURE/ on GEM create flag

[Alex Deucher]

Rename to SECURE to align with the CS flag naming.

Signed-off-by: Alex Deucher 
---

Several other teams thought it would be cleaner to call it SECURE
since it aligns better with the CS interface.  I don't have a
strong opinion either way.

 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +-
 include/uapi/drm/amdgpu_drm.h  | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index f39012e4a0fa..0691692f096e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -227,7 +227,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void 
*data,
  AMDGPU_GEM_CREATE_VRAM_CLEARED |
  AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
  AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
- AMDGPU_GEM_CREATE_ENCRYPTED))
+ AMDGPU_GEM_CREATE_SECURE))
 
return -EINVAL;
 
@@ -235,7 +235,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void 
*data,
if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
return -EINVAL;
 
-   if (!adev->tmz.enabled && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
+   if (!adev->tmz.enabled && (flags & AMDGPU_GEM_CREATE_SECURE)) {
DRM_ERROR("Cannot allocate secure buffer while tmz is 
disabled\n");
return -EINVAL;
}
@@ -261,7 +261,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void 
*data,
resv = vm->root.base.bo->tbo.base.resv;
}
 
-   if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
+   if (flags & AMDGPU_GEM_CREATE_SECURE) {
/* XXX: pad out alignment to meet TMZ requirements */
}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 2eeafc77c9c1..5728e5a27fb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -232,7 +232,7 @@ static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo 
*bo)
  */
 static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
 {
-   return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
+   return bo->flags & AMDGPU_GEM_CREATE_SECURE;
 }
 
 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 918ac3548cd3..2ae80d31aecf 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -135,11 +135,11 @@ extern "C" {
  * releasing the memory
  */
 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
-/* Flag that BO will be encrypted and that the TMZ bit should be
+/* Flag that BO will be secure and that the TMZ bit should be
  * set in the PTEs when mapping this buffer via GPUVM or
  * accessing it with various hw blocks
  */
-#define AMDGPU_GEM_CREATE_ENCRYPTED(1 << 10)
+#define AMDGPU_GEM_CREATE_SECURE   (1 << 10)
 
 struct drm_amdgpu_gem_create_in  {
/** the requested memory size */
-- 
2.23.0

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Re: [PATCH] drm/amdgpu: fix license on Kconfig and Makefiles

[Christian König]

Am 11.12.19 um 16:33 schrieb Alex Deucher:

amdgpu is MIT licensed.

Fixes: ec8f24b7faaf3d ("treewide: Add SPDX license identifier - 
Makefile/Kconfig")
Signed-off-by: Alex Deucher 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/acp/Kconfig   | 2 +-
  drivers/gpu/drm/amd/amdgpu/Kconfig| 2 +-
  drivers/gpu/drm/amd/amdkfd/Kconfig| 2 +-
  drivers/gpu/drm/amd/display/Kconfig   | 2 +-
  drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 1 +
  drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 1 +
  drivers/gpu/drm/amd/display/dc/dsc/Makefile   | 1 +
  7 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig
index 19bae9100da4..13340f353ea8 100644
--- a/drivers/gpu/drm/amd/acp/Kconfig
+++ b/drivers/gpu/drm/amd/acp/Kconfig
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-License-Identifier: MIT
  menu "ACP (Audio CoProcessor) Configuration"
  
  config DRM_AMD_ACP

diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig 
b/drivers/gpu/drm/amd/amdgpu/Kconfig
index 2e98c016cb47..9375e7f12420 100644
--- a/drivers/gpu/drm/amd/amdgpu/Kconfig
+++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-License-Identifier: MIT
  config DRM_AMDGPU_SI
bool "Enable amdgpu support for SI parts"
depends on DRM_AMDGPU
diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig 
b/drivers/gpu/drm/amd/amdkfd/Kconfig
index ba0e68057a89..b3672d10ea54 100644
--- a/drivers/gpu/drm/amd/amdkfd/Kconfig
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-License-Identifier: MIT
  #
  # Heterogenous system architecture configuration
  #
diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index 2a2f621c0d6c..87858bc57e64 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-License-Identifier: MIT
  menu "Display Engine Configuration"
depends on DRM && DRM_AMDGPU
  
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile

index 2eeb03818072..5fcaf78334ff 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: MIT
  #
  # Makefile for DCN.
  
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile

index b3688900d211..07684d3e375a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: MIT
  #
  # Makefile for DCN21.
  
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile

index 7415b8bf6318..3f66868df171 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: MIT
  #
  # Makefile for the 'dsc' sub-component of DAL.
  


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[PATCH 3/3] drm/amd/display: add missing dcn link encoder regs

[Roman.Li]

From: Roman Li 

[Why]
The earlier change: "check phy dpalt lane count config"
uses link encoder registers not defined properly.
That caused regression with mst-enabled display not
lighting up.

[How]
Add missing reg definitions.

Signed-off-by: Roman Li 
---
 .../drm/amd/display/dc/dcn10/dcn10_link_encoder.h  |  20 +++
 .../drm/amd/display/dc/dcn20/dcn20_link_encoder.h  | 180 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  |   9 +-
 .../drm/amd/display/dc/dcn21/dcn21_link_encoder.h  |  39 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_resource.c  |  11 +-
 5 files changed, 253 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 7493a63..eb13589 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -124,6 +124,26 @@ struct dcn10_link_enc_registers {
uint32_t RDPCSTX_PHY_CNTL13;
uint32_t RDPCSTX_PHY_CNTL14;
uint32_t RDPCSTX_PHY_CNTL15;
+   uint32_t RDPCSTX_CNTL;
+   uint32_t RDPCSTX_CLOCK_CNTL;
+   uint32_t RDPCSTX_PHY_CNTL0;
+   uint32_t RDPCSTX_PHY_CNTL2;
+   uint32_t RDPCSTX_PLL_UPDATE_DATA;
+   uint32_t RDPCS_TX_CR_ADDR;
+   uint32_t RDPCS_TX_CR_DATA;
+   uint32_t DPCSTX_TX_CLOCK_CNTL;
+   uint32_t DPCSTX_TX_CNTL;
+   uint32_t RDPCSTX_INTERRUPT_CONTROL;
+   uint32_t RDPCSTX_PHY_FUSE0;
+   uint32_t RDPCSTX_PHY_FUSE1;
+   uint32_t RDPCSTX_PHY_FUSE2;
+   uint32_t RDPCSTX_PHY_FUSE3;
+   uint32_t RDPCSTX_PHY_RX_LD_VAL;
+   uint32_t DPCSTX_DEBUG_CONFIG;
+   uint32_t RDPCSTX_DEBUG_CONFIG;
+   uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
+   uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
+   uint32_t DCIO_SOFT_RESET;
/* indirect registers */
uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
index 62dfd34..8cab810 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
@@ -33,7 +33,142 @@
SRI(AUX_DPHY_TX_CONTROL, DP_AUX, id)
 
 #define UNIPHY_MASK_SH_LIST(mask_sh)\
-   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh)
+   LE_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\
+   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh),\
+   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\
+   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL1_XBAR_SOURCE, mask_sh),\
+   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL2_XBAR_SOURCE, mask_sh),\
+   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL3_XBAR_SOURCE, mask_sh)
+
+#define DPCS_MASK_SH_LIST(mask_sh)\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, 
mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, 
mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, 
mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, 
mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, 
mask_sh),\
+   

[PATCH 4/4] drm/scheduler: do not keep a copy of sched list

[Nirmoy Das]

entity should not keep copy and maintain sched list for
itself.

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/scheduler/sched_entity.c | 19 ---
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c
index f9b6ce29c58f..2e3a058fc239 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -56,8 +56,6 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
  unsigned int num_sched_list,
  atomic_t *guilty)
 {
-   int i;
-
if (!(entity && sched_list && (num_sched_list == 0 || sched_list[0])))
return -EINVAL;
 
@@ -67,22 +65,14 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
entity->guilty = guilty;
entity->num_sched_list = num_sched_list;
entity->priority = priority;
-   entity->sched_list =  kcalloc(num_sched_list,
- sizeof(struct drm_gpu_scheduler *), 
GFP_KERNEL);
+   entity->sched_list = num_sched_list > 1 ? sched_list : NULL;
+   entity->last_scheduled = NULL;
 
-   if(!entity->sched_list)
-   return -ENOMEM;
+   if(num_sched_list)
+   entity->rq = _list[0]->sched_rq[entity->priority];
 
init_completion(>entity_idle);
 
-   for (i = 0; i < num_sched_list; i++)
-   entity->sched_list[i] = sched_list[i];
-
-   if (num_sched_list)
-   entity->rq = >sched_list[0]->sched_rq[entity->priority];
-
-   entity->last_scheduled = NULL;
-
spin_lock_init(>rq_lock);
spsc_queue_init(>job_queue);
 
@@ -312,7 +302,6 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
 
dma_fence_put(entity->last_scheduled);
entity->last_scheduled = NULL;
-   kfree(entity->sched_list);
 }
 EXPORT_SYMBOL(drm_sched_entity_fini);
 
-- 
2.24.0

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[PATCH 2/4] drm/amdgpu: replace vm_pte's run-queue list with drm gpu scheds list

[Nirmoy Das]

drm_sched_entity_init() takes drm gpu scheduler list instead of
drm_sched_rq list. This makes conversion of drm_sched_rq list
to drm gpu scheduler list unnecessary

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  4 ++--
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c  |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  5 ++---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/si_dma.c|  8 +++-
 9 files changed, 24 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 47b4f359f07c..8c5b0cda9a3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2785,7 +2785,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->mman.buffer_funcs = NULL;
adev->mman.buffer_funcs_ring = NULL;
adev->vm_manager.vm_pte_funcs = NULL;
-   adev->vm_manager.vm_pte_num_rqs = 0;
+   adev->vm_manager.vm_pte_num_scheds = 0;
adev->gmc.gmc_funcs = NULL;
adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1c65b5bffa6b..b999b67ff57a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2744,7 +2744,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
 {
struct amdgpu_bo_param bp;
struct amdgpu_bo *root;
-   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
int r, i;
 
vm->va = RB_ROOT_CACHED;
@@ -2758,19 +2757,17 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
spin_lock_init(>invalidated_lock);
INIT_LIST_HEAD(>freed);
 
-   for (i = 0; i < adev->vm_manager.vm_pte_num_rqs; i++)
-   sched_list[i] = adev->vm_manager.vm_pte_rqs[i]->sched;
 
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(>direct, DRM_SCHED_PRIORITY_NORMAL,
- sched_list, adev->vm_manager.vm_pte_num_rqs,
- NULL);
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds, NULL);
if (r)
return r;
 
r = drm_sched_entity_init(>delayed, DRM_SCHED_PRIORITY_NORMAL,
- sched_list, adev->vm_manager.vm_pte_num_rqs,
- NULL);
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds, NULL);
if (r)
goto error_free_direct;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index d5613d184e99..100547f094ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -330,8 +330,8 @@ struct amdgpu_vm_manager {
u64 vram_base_offset;
/* vm pte handling */
const struct amdgpu_vm_pte_funcs*vm_pte_funcs;
-   struct drm_sched_rq *vm_pte_rqs[AMDGPU_MAX_RINGS];
-   unsignedvm_pte_num_rqs;
+   struct drm_gpu_scheduler
*vm_pte_scheds[AMDGPU_MAX_RINGS];
+   unsignedvm_pte_num_scheds;
struct amdgpu_ring  *page_fault;
 
/* partial resident texture handling */
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 82cdb8f57bfd..1f22a8d0f7f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1373,16 +1373,14 @@ static const struct amdgpu_vm_pte_funcs 
cik_sdma_vm_pte_funcs = {
 
 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
-   struct drm_gpu_scheduler *sched;
unsigned i;
 
adev->vm_manager.vm_pte_funcs = _sdma_vm_pte_funcs;
for (i = 0; i < adev->sdma.num_instances; i++) {
-   sched = >sdma.instance[i].ring.sched;
-   adev->vm_manager.vm_pte_rqs[i] =
-   >sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+   adev->vm_manager.vm_pte_scheds[i] =
+   >sdma.instance[i].ring.sched;
}
-   adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
+   adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
 }
 
 const struct 

[PATCH 3/4] amd/amdgpu: add sched array to IPs with multiple run-queues

[Nirmoy Das]

This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h|   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h|   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h   |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|   9 +-
 7 files changed, 89 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 1d6850af9908..165d1a397266 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
   struct amdgpu_ctx *ctx)
 {
unsigned num_entities = amdgpu_ctx_total_num_entities();
-   unsigned i, j, k;
+   unsigned i, j;
int r;

if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -121,73 +121,56 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;

for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
-   struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
-   unsigned num_rings = 0;
-   unsigned num_rqs = 0;
+   struct drm_gpu_scheduler **scheds;
+   struct drm_gpu_scheduler *sched;
+   unsigned num_scheds = 0;

switch (i) {
case AMDGPU_HW_IP_GFX:
-   rings[0] = >gfx.gfx_ring[0];
-   num_rings = 1;
+   scheds = adev->gfx.gfx_sched;
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_COMPUTE:
-   for (j = 0; j < adev->gfx.num_compute_rings; ++j)
-   rings[j] = >gfx.compute_ring[j];
-   num_rings = adev->gfx.num_compute_rings;
+   scheds = adev->gfx.compute_sched;
+   num_scheds = adev->gfx.num_compute_sched;
break;
case AMDGPU_HW_IP_DMA:
-   for (j = 0; j < adev->sdma.num_instances; ++j)
-   rings[j] = >sdma.instance[j].ring;
-   num_rings = adev->sdma.num_instances;
+   scheds = adev->sdma.sdma_sched;
+   num_scheds = adev->sdma.num_sdma_sched;
break;
case AMDGPU_HW_IP_UVD:
-   rings[0] = >uvd.inst[0].ring;
-   num_rings = 1;
+   sched = >uvd.inst[0].ring.sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCE:
-   rings[0] = >vce.ring[0];
-   num_rings = 1;
+   sched = >vce.ring[0].sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_UVD_ENC:
-   rings[0] = >uvd.inst[0].ring_enc[0];
-   num_rings = 1;
+   sched = >uvd.inst[0].ring_enc[0].sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCN_DEC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   rings[num_rings++] = 
>vcn.inst[j].ring_dec;
-   }
+   scheds = adev->vcn.vcn_dec_sched;
+   num_scheds =  adev->vcn.num_vcn_dec_sched;
break;
case AMDGPU_HW_IP_VCN_ENC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   for (k = 0; k < adev->vcn.num_enc_rings; ++k)
-   rings[num_rings++] = 
>vcn.inst[j].ring_enc[k];
-   }
+   scheds = adev->vcn.vcn_enc_sched;
+   num_scheds =  adev->vcn.num_vcn_enc_sched;
break;
case AMDGPU_HW_IP_VCN_JPEG:
-   for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-  

[PATCH 1/4] drm/scheduler: rework entity creation

[Nirmoy Das]

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  8 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
 drivers/gpu/drm/etnaviv/etnaviv_drv.c|  7 ++-
 drivers/gpu/drm/lima/lima_sched.c|  5 +-
 drivers/gpu/drm/panfrost/panfrost_job.c  |  8 ++-
 drivers/gpu/drm/scheduler/sched_entity.c | 74 ++--
 drivers/gpu/drm/v3d/v3d_drv.c|  8 ++-
 include/drm/gpu_scheduler.h  |  8 ++-
 11 files changed, 78 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..1d6850af9908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,

for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;

@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
if (!rings[j]->adev)
continue;

-   rqs[num_rqs++] = [j]->sched.sched_rq[priority];
+   sched_list[num_rqs++] = [j]->sched;
}

for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ priority, sched_list,
+ num_rqs, >guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 81f6764f1ba6..2ff63d0414c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1954,11 +1954,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)

if (enable) {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;

ring = adev->mman.buffer_funcs_ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, ,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index d587ffe2af8e..a92f3b18e657 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;

ring = >uvd.inst[0].ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ , 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;

ring = >vce.ring[0];
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = 

[PATCH 32/39] drm/amd/display: Update extended timeout support for DCN20 and DCN21

[Rodrigo Siqueira]

From: abdoulaye berthe 

[Why]
DCN21 and DCN2 extended timeout support cap is not set correctly.

[How]
Set extended timeout support for ASIC families to their right values.

Signed-off-by: abdoulaye berthe 
Reviewed-by: Martin Leung 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 1368b74d1124..cfc69919ef9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3467,7 +3467,7 @@ static bool dcn20_resource_construct(
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.hw_3d_lut = true;
-   dc->caps.extended_aux_timeout_support = false;
+   dc->caps.extended_aux_timeout_support = true;
 
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
dc->debug = debug_defaults_drv;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 111f2c30c6b7..990e88cdf1bb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1670,7 +1670,7 @@ static bool dcn21_resource_construct(
dc->caps.max_slave_planes = 1;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
-   dc->caps.extended_aux_timeout_support = false;
+   dc->caps.extended_aux_timeout_support = true;
dc->caps.dmcub_support = true;
 
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
-- 
2.24.0

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[PATCH 23/39] drm/amd/display: disable lttpr for Navi

[Rodrigo Siqueira]

From: Hugo Hu 

Signed-off-by: Hugo Hu 
Reviewed-by: Abdoulaye Berthe 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index cfc69919ef9e..1368b74d1124 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3467,7 +3467,7 @@ static bool dcn20_resource_construct(
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.hw_3d_lut = true;
-   dc->caps.extended_aux_timeout_support = true;
+   dc->caps.extended_aux_timeout_support = false;
 
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
dc->debug = debug_defaults_drv;
-- 
2.24.0

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[PATCH 19/39] drm/amd/display: fix regamma build optimization

[Rodrigo Siqueira]

From: Josip Pavic 

[Why]
When the global variable pow_buffer_ptr is set to -1, by definition
optimizations should not be used to build the regamma. Since
translate_from_linear_space unconditionally increments this global, it
inadvertently enables the optimization.

[How]
Increment pow_buffer_ptr only if it is not -1.

Signed-off-by: Josip Pavic 
Reviewed-by: Krunoslav Kovac 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index b52c4d379651..1b278c42809a 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -364,8 +364,10 @@ static struct fixed31_32 translate_from_linear_space(
scratch_2 = dc_fixpt_mul(gamma_of_2,
pow_buffer[pow_buffer_ptr%16]);
 
-   pow_buffer[pow_buffer_ptr%16] = scratch_2;
-   pow_buffer_ptr++;
+   if (pow_buffer_ptr != -1) {
+   pow_buffer[pow_buffer_ptr%16] = scratch_2;
+   pow_buffer_ptr++;
+   }
 
scratch_1 = dc_fixpt_mul(scratch_1, scratch_2);
scratch_1 = dc_fixpt_sub(scratch_1, args->a2);
-- 
2.24.0

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[PATCH 12/39] drm/amd/display: update chroma viewport wa

[Rodrigo Siqueira]

From: Eric Yang 

[Why]
Need previously implemented chroma vp wa to work for rotation cases.

[How]
Implement rotation specific wa.

Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |   4 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   3 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  14 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 314 --
 .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h |   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   7 +-
 7 files changed, 305 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 4d1301e5eaf5..31b64733d693 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -810,8 +810,7 @@ static void hubp1_set_vm_context0_settings(struct hubp 
*hubp,
 void min_set_viewport(
struct hubp *hubp,
const struct rect *viewport,
-   const struct rect *viewport_c,
-   enum dc_rotation_angle rotation)
+   const struct rect *viewport_c)
 {
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index e44eaae5033b..780af5b3c16f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -749,9 +749,7 @@ void hubp1_set_blank(struct hubp *hubp, bool blank);
 
 void min_set_viewport(struct hubp *hubp,
const struct rect *viewport,
-   const struct rect *viewport_c,
-   enum dc_rotation_angle rotation);
-/* rotation angle added for use by hubp21_set_viewport */
+   const struct rect *viewport_c);
 
 void hubp1_clk_cntl(struct hubp *hubp, bool enable);
 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 3996fef56948..c9f7c0af58e3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2291,8 +2291,7 @@ static void dcn10_update_dchubp_dpp(
hubp->funcs->mem_program_viewport(
hubp,
_ctx->plane_res.scl_data.viewport,
-   _ctx->plane_res.scl_data.viewport_c,
-   plane_state->rotation);
+   _ctx->plane_res.scl_data.viewport_c);
}
 
if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index cafbd08f1cf2..8d779062a4e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1305,6 +1305,7 @@ static void dcn20_update_dchubp_dpp(
struct hubp *hubp = pipe_ctx->plane_res.hubp;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+   bool viewport_changed = false;
 
if (pipe_ctx->update_flags.bits.dppclk)
dpp->funcs->dpp_dppclk_control(dpp, false, true);
@@ -1383,12 +1384,14 @@ static void dcn20_update_dchubp_dpp(
 
if (pipe_ctx->update_flags.bits.viewport ||
(context == dc->current_state && 
plane_state->update_flags.bits.scaling_change) ||
-   (context == dc->current_state && 
pipe_ctx->stream->update_flags.bits.scaling))
+   (context == dc->current_state && 
pipe_ctx->stream->update_flags.bits.scaling)) {
+
hubp->funcs->mem_program_viewport(
hubp,
_ctx->plane_res.scl_data.viewport,
-   _ctx->plane_res.scl_data.viewport_c,
-   plane_state->rotation);
+   _ctx->plane_res.scl_data.viewport_c);
+   viewport_changed = true;
+   }
 
/* Any updates are handled in dc interface, just need to apply existing 
for plane enable */
if ((pipe_ctx->update_flags.bits.enable || 
pipe_ctx->update_flags.bits.opp_changed)
@@ -1441,9 +1444,14 @@ static void dcn20_update_dchubp_dpp(
hubp->power_gated = false;
}
 
+   if (hubp->funcs->apply_PLAT_54186_wa && viewport_changed)
+   hubp->funcs->apply_PLAT_54186_wa(hubp, _state->address);
+
if (pipe_ctx->update_flags.bits.enable || 
plane_state->update_flags.bits.addr_update)
hws->funcs.update_plane_addr(dc, pipe_ctx);
 
+
+
if (pipe_ctx->update_flags.bits.enable)
hubp->funcs->set_blank(hubp, false);
 }
diff --git 

[PATCH 18/39] drm/amd/display: scaling changes should also be a full update

[Rodrigo Siqueira]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Jun Lei 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2cb31f403b74..c13480685853 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1577,7 +1577,7 @@ static enum surface_update_type 
get_scaling_info_update_type(
 
update_flags->bits.scaling_change = 1;
if (u->scaling_info->src_rect.width > u->surface->src_rect.width
-   && u->scaling_info->src_rect.height > 
u->surface->src_rect.height)
+   || u->scaling_info->src_rect.height > 
u->surface->src_rect.height)
/* Making src rect bigger requires a bandwidth change */
update_flags->bits.clock_change = 1;
}
@@ -1591,11 +1591,11 @@ static enum surface_update_type 
get_scaling_info_update_type(
update_flags->bits.position_change = 1;
 
if (update_flags->bits.clock_change
-   || update_flags->bits.bandwidth_change)
+   || update_flags->bits.bandwidth_change
+   || update_flags->bits.scaling_change)
return UPDATE_TYPE_FULL;
 
-   if (update_flags->bits.scaling_change
-   || update_flags->bits.position_change)
+   if (update_flags->bits.position_change)
return UPDATE_TYPE_MED;
 
return UPDATE_TYPE_FAST;
-- 
2.24.0

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[PATCH 13/39] drm/amd/display: Collapse resource arrays when pipe is disabled

[Rodrigo Siqueira]

From: Noah Abradjian 

[Why]
Currently, pipe resources are assigned to an index that matches the pipe 
position.
However, if pipe 1 or 2 is disabled, there will be a gap in the arrays which 
causes a crash when iterating based on pipe_count.

[How]
Fix resource construct to assign resources to minimum available array index.

Signed-off-by: Noah Abradjian 
Reviewed-by: Yongqiang Sun 
Acked-by: Rodrigo Siqueira 
---
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 20 +--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 98f0267300a0..a662769b0c48 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1774,41 +1774,41 @@ static bool dcn21_resource_construct(
if ((pipe_fuses & (1 << i)) != 0)
continue;
 
-   pool->base.hubps[i] = dcn21_hubp_create(ctx, i);
-   if (pool->base.hubps[i] == NULL) {
+   pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
+   if (pool->base.hubps[j] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create memory input!\n");
goto create_fail;
}
 
-   pool->base.ipps[i] = dcn21_ipp_create(ctx, i);
-   if (pool->base.ipps[i] == NULL) {
+   pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
+   if (pool->base.ipps[j] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create input pixel 
processor!\n");
goto create_fail;
}
 
-   pool->base.dpps[i] = dcn21_dpp_create(ctx, i);
-   if (pool->base.dpps[i] == NULL) {
+   pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
+   if (pool->base.dpps[j] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create dpps!\n");
goto create_fail;
}
 
-   pool->base.opps[i] = dcn21_opp_create(ctx, i);
-   if (pool->base.opps[i] == NULL) {
+   pool->base.opps[j] = dcn21_opp_create(ctx, i);
+   if (pool->base.opps[j] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create output pixel 
processor!\n");
goto create_fail;
}
 
-   pool->base.timing_generators[i] = dcn21_timing_generator_create(
+   pool->base.timing_generators[j] = dcn21_timing_generator_create(
ctx, i);
-   if (pool->base.timing_generators[i] == NULL) {
+   if (pool->base.timing_generators[j] == NULL) {
BREAK_TO_DEBUGGER();
dm_error("DC: failed to create tg!\n");
goto create_fail;
-- 
2.24.0

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[PATCH 35/39] drm/amd/display: Lower DPP DTO only when safe

[Rodrigo Siqueira]

From: Sung Lee 

[Why]
A corner case currently exists where DPP DTO is lowered before
pipes are updated to a higher viewport. This causes underflow
as the DPPCLK is too low for the current viewport.

[How]
Only lower DPP DTO when it is safe to lower, or if
the newer clocks are higher than the current ones.

Signed-off-by: Sung Lee 
Reviewed-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 16 ++--
 .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h |  2 +-
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c|  8 
 3 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 3ae1d23f7342..495f01e9f2ca 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -101,13 +101,13 @@ uint32_t dentist_get_did_from_divider(int divider)
 }
 
 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
-   struct dc_state *context)
+   struct dc_state *context, bool safe_to_lower)
 {
int i;
 
clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
-   int dpp_inst, dppclk_khz;
+   int dpp_inst, dppclk_khz, prev_dppclk_khz;
 
/* Loop index will match dpp->inst if resource exists,
 * and we want to avoid dependency on dpp object
@@ -115,8 +115,12 @@ void dcn20_update_clocks_update_dpp_dto(struct 
clk_mgr_internal *clk_mgr,
dpp_inst = i;
dppclk_khz = 
context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
 
-   clk_mgr->dccg->funcs->update_dpp_dto(
-   clk_mgr->dccg, dpp_inst, dppclk_khz);
+   prev_dppclk_khz = 
clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
+
+   if (safe_to_lower || prev_dppclk_khz < dppclk_khz) {
+   clk_mgr->dccg->funcs->update_dpp_dto(
+   clk_mgr->dccg, 
dpp_inst, dppclk_khz);
+   }
}
 }
 
@@ -244,7 +248,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
if (dc->config.forced_clocks == false || (force_reset && 
safe_to_lower)) {
if (dpp_clock_lowered) {
// if clock is being lowered, increase DTO before 
lowering refclk
-   dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+   dcn20_update_clocks_update_dpp_dto(clk_mgr, context, 
safe_to_lower);
dcn20_update_clocks_update_dentist(clk_mgr);
} else {
// if clock is being raised, increase refclk before 
lowering DTO
@@ -252,7 +256,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
dcn20_update_clocks_update_dentist(clk_mgr);
// always update dtos unless clock is lowered and not 
safe to lower
if (new_clocks->dppclk_khz >= 
dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
-   dcn20_update_clocks_update_dpp_dto(clk_mgr, 
context);
+   dcn20_update_clocks_update_dpp_dto(clk_mgr, 
context, safe_to_lower);
}
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
index b64a4e9d71d7..0b9c045b0c8e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
@@ -34,7 +34,7 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
struct dc_state *context,
bool safe_to_lower);
 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
-   struct dc_state *context);
+   struct dc_state *context, bool safe_to_lower);
 
 void dcn2_init_clocks(struct clk_mgr *clk_mgr);
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index de51ef12e33a..b02b4dc554a4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -164,16 +164,16 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
}
 
if (dpp_clock_lowered) {
-   // if clock is being lowered, increase DTO before lowering 
refclk
-   dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+   // increase per DPP DTO before lowering global dppclk
+   dcn20_update_clocks_update_dpp_dto(clk_mgr, context, 

[PATCH 38/39] drm/amd/display: Do not handle linkloss for eDP

[Rodrigo Siqueira]

From: Anthony Koo 

[Why]
eDP is internal link and link loss is unexpected.
It is typically going to be PSR related errors, which is
handled separately.

[How]
Check for eDP and skip check for link loss

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 42aa889fd0f5..38b0f4347383 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2854,10 +2854,12 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, 
union hpd_irq_data *out_hpd
/* For now we only handle 'Downstream port status' case.
 * If we got sink count changed it means
 * Downstream port status changed,
-* then DM should call DC to do the detection. */
-   if (hpd_rx_irq_check_link_loss_status(
-   link,
-   _irq_dpcd_data)) {
+* then DM should call DC to do the detection.
+* NOTE: Do not handle link loss on eDP since it is internal link*/
+   if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
+   hpd_rx_irq_check_link_loss_status(
+   link,
+   _irq_dpcd_data)) {
/* Connectivity log: link loss */
CONN_DATA_LINK_LOSS(link,
hpd_irq_dpcd_data.raw,
-- 
2.24.0

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[PATCH 34/39] drm/amd/display: support virtual DCN

[Rodrigo Siqueira]

From: Jun Lei 

[why]
DAL3 should support SRIOV

[how]
Add support for the virtual dal flag.  This flag should skip
most/all of DC construction since the HW isn't accessible, but
still construct WindowsDM (almost) normally but with only SW display
targets

Signed-off-by: Jun Lei 
Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 113 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h |   7 +-
 2 files changed, 74 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c13480685853..3d89904003f0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -582,6 +582,40 @@ static void dc_destruct(struct dc *dc)
 
 }
 
+static bool dc_construct_ctx(struct dc *dc,
+   const struct dc_init_data *init_params)
+{
+   struct dc_context *dc_ctx;
+   enum dce_version dc_version = DCE_VERSION_UNKNOWN;
+
+   dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
+   if (!dc_ctx)
+   return false;
+
+   dc_ctx->cgs_device = init_params->cgs_device;
+   dc_ctx->driver_context = init_params->driver;
+   dc_ctx->dc = dc;
+   dc_ctx->asic_id = init_params->asic_id;
+   dc_ctx->dc_sink_id_count = 0;
+   dc_ctx->dc_stream_id_count = 0;
+   dc_ctx->dce_environment = init_params->dce_environment;
+
+   /* Create logger */
+
+   dc_version = resource_parse_asic_id(init_params->asic_id);
+   dc_ctx->dce_version = dc_version;
+
+   dc_ctx->perf_trace = dc_perf_trace_create();
+   if (!dc_ctx->perf_trace) {
+   ASSERT_CRITICAL(false);
+   return false;
+   }
+
+   dc->ctx = dc_ctx;
+
+   return true;
+}
+
 static bool dc_construct(struct dc *dc,
const struct dc_init_data *init_params)
 {
@@ -593,7 +627,6 @@ static bool dc_construct(struct dc *dc,
struct dcn_ip_params *dcn_ip;
 #endif
 
-   enum dce_version dc_version = DCE_VERSION_UNKNOWN;
dc->config = init_params->flags;
 
// Allocate memory for the vm_helper
@@ -639,26 +672,12 @@ static bool dc_construct(struct dc *dc,
dc->soc_bounding_box = init_params->soc_bounding_box;
 #endif
 
-   dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
-   if (!dc_ctx) {
+   if (!dc_construct_ctx(dc, init_params)) {
dm_error("%s: failed to create ctx\n", __func__);
goto fail;
}
 
-   dc_ctx->cgs_device = init_params->cgs_device;
-   dc_ctx->driver_context = init_params->driver;
-   dc_ctx->dc = dc;
-   dc_ctx->asic_id = init_params->asic_id;
-   dc_ctx->dc_sink_id_count = 0;
-   dc_ctx->dc_stream_id_count = 0;
-   dc->ctx = dc_ctx;
-
-   /* Create logger */
-
-   dc_ctx->dce_environment = init_params->dce_environment;
-
-   dc_version = resource_parse_asic_id(init_params->asic_id);
-   dc_ctx->dce_version = dc_version;
+dc_ctx = dc->ctx;
 
/* Resource should construct all asic specific resources.
 * This should be the only place where we need to parse the asic id
@@ -673,7 +692,7 @@ static bool dc_construct(struct dc *dc,
bp_init_data.bios = init_params->asic_id.atombios_base_address;
 
dc_ctx->dc_bios = dal_bios_parser_create(
-   _init_data, dc_version);
+   _init_data, dc_ctx->dce_version);
 
if (!dc_ctx->dc_bios) {
ASSERT_CRITICAL(false);
@@ -681,17 +700,13 @@ static bool dc_construct(struct dc *dc,
}
 
dc_ctx->created_bios = true;
-   }
-
-   dc_ctx->perf_trace = dc_perf_trace_create();
-   if (!dc_ctx->perf_trace) {
-   ASSERT_CRITICAL(false);
-   goto fail;
}
 
+
+
/* Create GPIO service */
dc_ctx->gpio_service = dal_gpio_service_create(
-   dc_version,
+   dc_ctx->dce_version,
dc_ctx->dce_environment,
dc_ctx);
 
@@ -700,7 +715,7 @@ static bool dc_construct(struct dc *dc,
goto fail;
}
 
-   dc->res_pool = dc_create_resource_pool(dc, init_params, dc_version);
+   dc->res_pool = dc_create_resource_pool(dc, init_params, 
dc_ctx->dce_version);
if (!dc->res_pool)
goto fail;
 
@@ -731,8 +746,6 @@ static bool dc_construct(struct dc *dc,
return true;
 
 fail:
-
-   dc_destruct(dc);
return false;
 }
 
@@ -825,29 +838,38 @@ struct dc *dc_create(const struct dc_init_data 
*init_params)
if (NULL == dc)
goto alloc_fail;
 
-   if (false == dc_construct(dc, init_params))
-   goto construct_fail;
+   if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
+   if (false == dc_construct_ctx(dc, 

[PATCH 28/39] drm/amd/display: fix 270 degree rotation for mixed-SLS mode

[Rodrigo Siqueira]

From: Samson Tam 

[Why]
When we rotate 270 in mixed SLS mode, the recouts occupy the
right side of the display.  So all the recout_skip_v values
are relative to the left side of the display.  This causes
adjust_vp_and_init_for_seamless_clip() to incorrectly increase
the data->viewport.height for that recout.  The rotation looks
like the bottom half is duplicated twice.

[How]
recout.x values are being adjusted based on
stream->timing.h_border_left.  Instead of using h_border_left,
use dst.x to represent the border.  Shift dst.x by the amount of
stream->timing.h_border_left and set
stream->timing.h_border_left to 0.  Do all the calculations
and then revert stream->timing.h_border_left and
stream->dst.x back to their original values.
When calculating pipe_ctx->plane_res.scl_data.h_active,
make sure to use the original stream->timing.h_border_left
value.

Signed-off-by: Samson Tam 
Reviewed-by: Jun Lei 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 57 ++-
 1 file changed, 54 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 51e0f4472dbd..64a0e08fd019 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -940,11 +940,51 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx 
*pipe_ctx)
 
 }
 
+/*
+ * When handling 270 rotation in mixed SLS mode, we have
+ * stream->timing.h_border_left that is non zero.  If we are doing
+ * pipe-splitting, this h_border_left value gets added to recout.x and when it
+ * calls calculate_inits_and_adj_vp() and
+ * adjust_vp_and_init_for_seamless_clip(), it can cause viewport.height for a
+ * pipe to be incorrect.
+ *
+ * To fix this, instead of using stream->timing.h_border_left, we can use
+ * stream->dst.x to represent the border instead.  So we will set h_border_left
+ * to 0 and shift the appropriate amount in stream->dst.x.  We will then
+ * perform all calculations in resource_build_scaling_params() based on this
+ * and then restore the h_border_left and stream->dst.x to their original
+ * values.
+ *
+ * shift_border_left_to_dst() will shift the amount of h_border_left to
+ * stream->dst.x and set h_border_left to 0.  restore_border_left_from_dst()
+ * will restore h_border_left and stream->dst.x back to their original values
+ * We also need to make sure pipe_ctx->plane_res.scl_data.h_active uses the
+ * original h_border_left value in its calculation.
+ */
+int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx)
+{
+   int store_h_border_left = pipe_ctx->stream->timing.h_border_left;
+
+   if (store_h_border_left) {
+   pipe_ctx->stream->timing.h_border_left = 0;
+   pipe_ctx->stream->dst.x += store_h_border_left;
+   }
+   return store_h_border_left;
+}
+
+void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx,
+  int store_h_border_left)
+{
+   pipe_ctx->stream->dst.x -= store_h_border_left;
+   pipe_ctx->stream->timing.h_border_left = store_h_border_left;
+}
+
 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 {
const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct dc_crtc_timing *timing = _ctx->stream->timing;
bool res = false;
+   int store_h_border_left = shift_border_left_to_dst(pipe_ctx);
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
/* Important: scaling ratio calculation requires pixel format,
 * lb depth calculation requires recout and taps require scaling ratios.
@@ -957,8 +997,14 @@ bool resource_build_scaling_params(struct pipe_ctx 
*pipe_ctx)
 
calculate_viewport(pipe_ctx);
 
-   if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || 
pipe_ctx->plane_res.scl_data.viewport.width < 16)
+   if (pipe_ctx->plane_res.scl_data.viewport.height < 16 ||
+   pipe_ctx->plane_res.scl_data.viewport.width < 16) {
+   if (store_h_border_left) {
+   restore_border_left_from_dst(pipe_ctx,
+   store_h_border_left);
+   }
return false;
+   }
 
calculate_recout(pipe_ctx);
 
@@ -971,8 +1017,10 @@ bool resource_build_scaling_params(struct pipe_ctx 
*pipe_ctx)
pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
 
-   pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + 
timing->h_border_left + timing->h_border_right;
-   pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + 
timing->v_border_top + timing->v_border_bottom;
+   pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
+   store_h_border_left + timing->h_border_right;
+   pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
+   

[PATCH 25/39] drm/amd/display: Specified VR patch skip to reset segment to 0

[Rodrigo Siqueira]

From: Derek Lai 

[Why]
After read the 3rd Edid blocks, we will reset segment to 0,
which causes this VR fail to read Edid successfully.

[How]
Skip to reset segment to 0 for this VR device.

Signed-off-by: Derek Lai 
Reviewed-by: Aric Cyr 
Acked-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h 
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 1ff79f703734..f420aeac7fbd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -133,6 +133,7 @@ struct dc_link {
struct link_flags {
bool dp_keep_receiver_powered;
bool dp_skip_DID2;
+   bool dp_skip_reset_segment;
} wa_flags;
struct link_mst_stream_allocation_table mst_stream_alloc_table;
 
-- 
2.24.0

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[PATCH 33/39] drm/amd/display: Fix manual trigger source for DCN2

[Rodrigo Siqueira]

From: Aric Cyr 

Fix manual trigger source correctly be TRIGA for DCN2
rather than MANUAL_FLOW.

Signed-off-by: Aric Cyr 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 8 +---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 1 +
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 9b36fec549d7..d875b0c38fde 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -390,14 +390,8 @@ void optc2_setup_manual_trigger(struct timing_generator 
*optc)
 {
struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
-   REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
-   MANUAL_FLOW_CONTROL, 1);
-
-   REG_SET(OTG_GLOBAL_CONTROL2, 0,
-   MANUAL_FLOW_CONTROL_SEL, optc->inst);
-
REG_SET_8(OTG_TRIGA_CNTL, 0,
-   OTG_TRIGA_SOURCE_SELECT, 22,
+   OTG_TRIGA_SOURCE_SELECT, 21,
OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index ac93fbfaee03..239cc40ae474 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -106,6 +106,7 @@ void optc2_triplebuffer_lock(struct timing_generator *optc);
 void optc2_triplebuffer_unlock(struct timing_generator *optc);
 void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
 void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
+void optc2_setup_manual_trigger(struct timing_generator *optc);
 void optc2_program_manual_trigger(struct timing_generator *optc);
 bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
 #endif /* __DC_OPTC_DCN20_H__ */
-- 
2.24.0

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[PATCH 05/39] drm/amd/display: Use physical addressing for DMCUB on both dcn20/21

[Rodrigo Siqueira]

From: Nicholas Kazlauskas 

[Why]
CW0 and CW1 need to use physical addressing mode for dcn20 and dcn21.

The current code for dcn20 is using virtual.

[How]
We already program the DMCUB like this on dcn21 so we should just use
the same sequence for both.

Copy the dcn21 sequences into the dmjub_dcn20.c file and rename them.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 59 ---
 .../gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 97 +--
 .../gpu/drm/amd/display/dmub/src/dmub_dcn21.h | 11 ---
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |  2 -
 4 files changed, 44 insertions(+), 125 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 5760f25c3309..f45e14ada685 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -54,6 +54,14 @@ const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
 
 /* Shared functions. */
 
+static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
+uint64_t fb_base,
+uint64_t fb_offset,
+union dmub_addr *addr_out)
+{
+   addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
+}
+
 void dmub_dcn20_reset(struct dmub_srv *dmub)
 {
REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
@@ -71,19 +79,26 @@ void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
  const struct dmub_window *cw0,
  const struct dmub_window *cw1)
 {
+   union dmub_addr offset;
+   uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
+
REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
-   REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x4,
-DMCUB_MEM_WRITE_SPACE, 0x4);
+   REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
+DMCUB_MEM_WRITE_SPACE, 0x3);
+
+   dmub_dcn20_translate_addr(>offset, fb_base, fb_offset, );
 
-   REG_WRITE(DMCUB_REGION3_CW0_OFFSET, cw0->offset.u.low_part);
-   REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, cw0->offset.u.high_part);
+   REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
+   REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
  DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
  DMCUB_REGION3_CW0_ENABLE, 1);
 
-   REG_WRITE(DMCUB_REGION3_CW1_OFFSET, cw1->offset.u.low_part);
-   REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, cw1->offset.u.high_part);
+   dmub_dcn20_translate_addr(>offset, fb_base, fb_offset, );
+
+   REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
+   REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
  DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
@@ -100,37 +115,49 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
  const struct dmub_window *cw5,
  const struct dmub_window *cw6)
 {
-   REG_WRITE(DMCUB_REGION3_CW2_OFFSET, cw2->offset.u.low_part);
-   REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, cw2->offset.u.high_part);
+   union dmub_addr offset;
+   uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
+
+   dmub_dcn20_translate_addr(>offset, fb_base, fb_offset, );
+
+   REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
+   REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
  DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
  DMCUB_REGION3_CW2_ENABLE, 1);
 
-   REG_WRITE(DMCUB_REGION3_CW3_OFFSET, cw3->offset.u.low_part);
-   REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, cw3->offset.u.high_part);
+   dmub_dcn20_translate_addr(>offset, fb_base, fb_offset, );
+
+   REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
+   REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
  DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
  DMCUB_REGION3_CW3_ENABLE, 1);
 
/* TODO: Move this to CW4. */
+   dmub_dcn20_translate_addr(>offset, fb_base, fb_offset, );
 
-   REG_WRITE(DMCUB_REGION4_OFFSET, cw4->offset.u.low_part);
-   REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, cw4->offset.u.high_part);
+   

[PATCH 24/39] drm/amd/display: check link status before disable stream

[Rodrigo Siqueira]

From: Paul Hsieh 

[Why]
1. Set second screen only then unplug external monitor
2. Enter to S4 then plug in external monitor
3. Resume from S4, eDP will not turn off when OS set
   second screen only
Sometimes OS will not set eDP power up cause eDP dpms_off
keep true then driver skipp disable stream

[How]
When drvier try to disable stream, add link status condition

Signed-off-by: Paul Hsieh 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 11 +--
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 11 +--
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index c9f7c0af58e3..aa389dea279d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -860,6 +860,7 @@ static void dcn10_reset_back_end_for_pipe(
struct dc_state *context)
 {
int i;
+   struct dc_link *link;
DC_LOGGER_INIT(dc->ctx->logger);
if (pipe_ctx->stream_res.stream_enc == NULL) {
pipe_ctx->stream = NULL;
@@ -867,8 +868,14 @@ static void dcn10_reset_back_end_for_pipe(
}
 
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-   /* DPMS may already disable */
-   if (!pipe_ctx->stream->dpms_off)
+   link = pipe_ctx->stream->link;
+   /* DPMS may already disable or */
+   /* dpms_off status is incorrect due to fastboot
+* feature. When system resume from S4 with second
+* screen only, the dpms_off would be true but
+* VBIOS lit up eDP, so check link status too.
+*/
+   if (!pipe_ctx->stream->dpms_off || 
link->link_status.link_active)
core_link_disable_stream(pipe_ctx);
else if (pipe_ctx->stream_res.audio)
dc->hwss.disable_audio_stream(pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fb667546db09..3706299906e4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2002,6 +2002,7 @@ static void dcn20_reset_back_end_for_pipe(
struct dc_state *context)
 {
int i;
+   struct dc_link *link;
DC_LOGGER_INIT(dc->ctx->logger);
if (pipe_ctx->stream_res.stream_enc == NULL) {
pipe_ctx->stream = NULL;
@@ -2009,8 +2010,14 @@ static void dcn20_reset_back_end_for_pipe(
}
 
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-   /* DPMS may already disable */
-   if (!pipe_ctx->stream->dpms_off)
+   link = pipe_ctx->stream->link;
+   /* DPMS may already disable or */
+   /* dpms_off status is incorrect due to fastboot
+* feature. When system resume from S4 with second
+* screen only, the dpms_off would be true but
+* VBIOS lit up eDP, so check link status too.
+*/
+   if (!pipe_ctx->stream->dpms_off || 
link->link_status.link_active)
core_link_disable_stream(pipe_ctx);
else if (pipe_ctx->stream_res.audio)
dc->hwss.disable_audio_stream(pipe_ctx);
-- 
2.24.0

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[PATCH 21/39] drm/amd/display: Map ODM memory correctly when doing ODM combine

[Rodrigo Siqueira]

From: Nikola Cornij 

[why]
Up to 4 ODM memory pieces are required per ODM combine and cannot
overlap, i.e. each ODM "session" has to use its own memory pieces.
The ODM-memory mapping is currently broken for generic case.

The maximum number of memory pieces is ASIC-dependent, but it's always
big enough to satisfy maximum number of ODM combines. Memory pieces
are mapped as a bit-map, i.e. one memory piece corresponds to one bit.
The OPTC doing ODM needs to select memory pieces by setting the
corresponding bits, making sure there's no overlap with other OPTC
instances that might be doing ODM.

The current mapping works only for OPTC instance indexes smaller than
3. For instance indexes 3 and up it practically maps no ODM memory,
causing black, gray or white screen in display configs that include
ODM on OPTC instance 3 or up.

[how]
Statically map two unique ODM memory pieces for each OPTC instance
and piece them together when programming ODM combine mode.

Signed-off-by: Nikola Cornij 
Reviewed-by: Jun Lei 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c| 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 673c83e2afd4..9b36fec549d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -236,12 +236,13 @@ void optc2_set_odm_combine(struct timing_generator *optc, 
int *opp_id, int opp_c
struct dc_crtc_timing *timing)
 {
struct optc *optc1 = DCN10TG_FROM_TG(optc);
-   /* 2 pieces of memory required for up to 5120 displays, 4 for up to 
8192 */
int mpcc_hactive = (timing->h_addressable + timing->h_border_left + 
timing->h_border_right)
/ opp_cnt;
-   int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf;
+   uint32_t memory_mask;
uint32_t data_fmt = 0;
 
+   ASSERT(opp_cnt == 2);
+
/* TODO: In pseudocode but does not affect maximus, delete comment if 
we dont need on asic
 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position 
before DP frame start
@@ -249,9 +250,17 @@ void optc2_set_odm_combine(struct timing_generator *optc, 
int *opp_id, int opp_c
 *  MASTER_UPDATE_LOCK_DB_X, 160,
 *  MASTER_UPDATE_LOCK_DB_Y, 240);
 */
+
+   /* 2 pieces of memory required for up to 5120 displays, 4 for up to 
8192,
+* however, for ODM combine we can simplify by always using 4.
+* To make sure there's no overlap, each instance "reserves" 2 memories 
and
+* they are uniquely combined here.
+*/
+   memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+
if (REG(OPTC_MEMORY_CONFIG))
REG_SET(OPTC_MEMORY_CONFIG, 0,
-   OPTC_MEM_SEL, memory_mask << (optc->inst * 4));
+   OPTC_MEM_SEL, memory_mask);
 
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
data_fmt = 1;
@@ -260,7 +269,6 @@ void optc2_set_odm_combine(struct timing_generator *optc, 
int *opp_id, int opp_c
 
REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
 
-   ASSERT(opp_cnt == 2);
REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
OPTC_NUM_OF_INPUT_SEGMENT, 1,
OPTC_SEG0_SRC_SEL, opp_id[0],
-- 
2.24.0

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[PATCH 17/39] drm/amd/display: 3.2.63

[Rodrigo Siqueira]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 91b60a549d35..5c48111deabc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.62"
+#define DC_VER "3.2.63"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.24.0

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[PATCH 36/39] drm/amd/display: Formula refactor for calculating DPP CLK DTO

[Rodrigo Siqueira]

From: Sung Lee 

[Why]
Previous formula for calculating DPP CLK DTO was
hard to understand.

[How]
Replace with easier to understand formula that produces
same results.

Signed-off-by: Sung Lee 
Reviewed-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 20 +--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
index 1e1151356e60..50bffbfdd394 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
@@ -50,20 +50,20 @@ void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, 
int req_dppclk)
 
if (dccg->ref_dppclk && req_dppclk) {
int ref_dppclk = dccg->ref_dppclk;
+   int modulo, phase;
 
-   ASSERT(req_dppclk <= ref_dppclk);
-   /* need to clamp to 8 bits */
-   if (ref_dppclk > 0xff) {
-   int divider = (ref_dppclk + 0xfe) / 0xff;
+   // phase / modulo = dpp pipe clk / dpp global clk
+   modulo = 0xff;   // use FF at the end
+   phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
 
-   ref_dppclk /= divider;
-   req_dppclk = (req_dppclk + divider - 1) / divider;
-   if (req_dppclk > ref_dppclk)
-   req_dppclk = ref_dppclk;
+   if (phase > 0xff) {
+   ASSERT(false);
+   phase = 0xff;
}
+
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
-   DPPCLK0_DTO_PHASE, req_dppclk,
-   DPPCLK0_DTO_MODULO, ref_dppclk);
+   DPPCLK0_DTO_PHASE, phase,
+   DPPCLK0_DTO_MODULO, modulo);
REG_UPDATE(DPPCLK_DTO_CTRL,
DPPCLK_DTO_ENABLE[dpp_inst], 1);
} else {
-- 
2.24.0

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[PATCH 39/39] drm/amd/display: Add debug option to override DSC target bpp increment

[Rodrigo Siqueira]

From: Nikola Cornij 

[why]
It's required for debug purposes.

[how]
Add a dsc_bpp_increment_div debug option that overrides DPCD
BITS_PER_PIXEL_INCREMENT value. The value dsc_bpp_increment_div should
be set to is the one after parsing, i.e. it could be 1, 2, 4, 8 or 16
(meaning 1pix, 1/2pix, ..., 1/16pix).

Signed-off-by: Nikola Cornij 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 ++-
 drivers/gpu/drm/amd/display/dc/dc.h   |  1 +
 drivers/gpu/drm/amd/display/dc/dc_dsc.h   |  3 ++-
 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c   | 19 ++-
 4 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 745d8719ccc1..f90b5eb8db82 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4148,7 +4148,8 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
 
if (aconnector->dc_link && sink->sink_signal == 
SIGNAL_TYPE_DISPLAY_PORT) {
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-   
dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
+   dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
+ 
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
  
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
  _caps);
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 4c2ba93ab7e0..039004344dc6 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -367,6 +367,7 @@ struct dc_debug_options {
bool disable_hubp_power_gate;
bool disable_dsc_power_gate;
int dsc_min_slice_height_override;
+   int dsc_bpp_increment_div;
bool native422_support;
bool disable_pplib_wm_range;
enum wm_report_mode pplib_wm_report_mode;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h 
b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index 7ece8eb5f48c..3800340a5b4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -53,7 +53,8 @@ struct dc_dsc_policy {
uint32_t min_target_bpp;
 };
 
-bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data,
+bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
+   const uint8_t *dpcd_dsc_basic_data,
const uint8_t *dpcd_dsc_ext_data,
struct dsc_dec_dpcd_caps *dsc_sink_caps);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 71b048363506..8b78fcbfe746 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -760,7 +760,7 @@ static bool setup_dsc_config(
return is_dsc_possible;
 }
 
-bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data, const uint8_t 
*dpcd_dsc_ext_data, struct dsc_dec_dpcd_caps *dsc_sink_caps)
+bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, const uint8_t 
*dpcd_dsc_basic_data, const uint8_t *dpcd_dsc_ext_data, struct 
dsc_dec_dpcd_caps *dsc_sink_caps)
 {
if (!dpcd_dsc_basic_data)
return false;
@@ -813,6 +813,23 @@ bool dc_dsc_parse_dsc_dpcd(const uint8_t 
*dpcd_dsc_basic_data, const uint8_t *dp
if 
(!dsc_bpp_increment_div_from_dpcd(dpcd_dsc_basic_data[DP_DSC_BITS_PER_PIXEL_INC 
- DP_DSC_SUPPORT], _sink_caps->bpp_increment_div))
return false;
 
+   if (dc->debug.dsc_bpp_increment_div) {
+   /* dsc_bpp_increment_div should onl be 1, 2, 4, 8 or 16, but 
rather than rejecting invalid values,
+* we'll accept all and get it into range. This also makes the 
above check against 0 redundant,
+* but that one stresses out the override will be only used if 
it's not 0.
+*/
+   if (dc->debug.dsc_bpp_increment_div >= 1)
+   dsc_sink_caps->bpp_increment_div = 1;
+   if (dc->debug.dsc_bpp_increment_div >= 2)
+   dsc_sink_caps->bpp_increment_div = 2;
+   if (dc->debug.dsc_bpp_increment_div >= 4)
+   dsc_sink_caps->bpp_increment_div = 4;
+   if (dc->debug.dsc_bpp_increment_div >= 8)
+   dsc_sink_caps->bpp_increment_div = 8;
+   if (dc->debug.dsc_bpp_increment_div >= 16)
+   dsc_sink_caps->bpp_increment_div = 16;
+   }
+
/* Extended caps */
if (dpcd_dsc_ext_data == NULL) { // Extended DPCD DSC data can be null, 
e.g. because it doesn't apply to SST
dsc_sink_caps->branch_overall_throughput_0_mps = 0;
-- 
2.24.0

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[PATCH 37/39] drm/amd/display: fix missing cursor on some rotated SLS displays

[Rodrigo Siqueira]

From: Samson Tam 

[Why]
Cursor disappears for some SLS displays that are rotated 180
and 270 degrees.  This occurs when there is no pipe split being
done ( ex. 3 or more displays ).  The cursor calculations assume
pipe splitting is done so when it calculates the new cursor
position in hwss.set_cursor_position(), it is out-of-bounds so
it disables the cursor in hubp.set_cursor_position().

[How]
In non pipe split cases, calculate cursor using viewport size
( width or height ) instead of viewport size * 2 ( the two
because pipe splitting divides the rectangle into two ).

Signed-off-by: Samson Tam 
Reviewed-by: Jun Lei 
Acked-by: Rodrigo Siqueira 
---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 51 +--
 1 file changed, 36 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9e53bbd5d2b5..9c55e4897fca 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2916,6 +2916,8 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
.rotation = pipe_ctx->plane_state->rotation,
.mirror = pipe_ctx->plane_state->horizontal_mirror
};
+   bool pipe_split_on = (pipe_ctx->top_pipe != NULL) ||
+   (pipe_ctx->bottom_pipe != NULL);
 
int x_plane = pipe_ctx->plane_state->dst_rect.x;
int y_plane = pipe_ctx->plane_state->dst_rect.y;
@@ -2948,6 +2950,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
// Swap axis and mirror horizontally
if (param.rotation == ROTATION_ANGLE_90) {
uint32_t temp_x = pos_cpy.x;
+
pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -
(pos_cpy.y - 
pipe_ctx->plane_res.scl_data.viewport.x) + 
pipe_ctx->plane_res.scl_data.viewport.x;
pos_cpy.y = temp_x;
@@ -2955,26 +2958,44 @@ void dcn10_set_cursor_position(struct pipe_ctx 
*pipe_ctx)
// Swap axis and mirror vertically
else if (param.rotation == ROTATION_ANGLE_270) {
uint32_t temp_y = pos_cpy.y;
-   if (pos_cpy.x >  pipe_ctx->plane_res.scl_data.viewport.height) {
-   pos_cpy.x = pos_cpy.x - 
pipe_ctx->plane_res.scl_data.viewport.height;
-   pos_cpy.y = 
pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
-   } else {
-   pos_cpy.y = 2 * 
pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
-   }
+   int viewport_height =
+   pipe_ctx->plane_res.scl_data.viewport.height;
+
+   if (pipe_split_on) {
+   if (pos_cpy.x > viewport_height) {
+   pos_cpy.x = pos_cpy.x - viewport_height;
+   pos_cpy.y = viewport_height - pos_cpy.x;
+   } else {
+   pos_cpy.y = 2 * viewport_height - pos_cpy.x;
+   }
+   } else
+   pos_cpy.y = viewport_height - pos_cpy.x;
pos_cpy.x = temp_y;
}
// Mirror horizontally and vertically
else if (param.rotation == ROTATION_ANGLE_180) {
-   if (pos_cpy.x >= pipe_ctx->plane_res.scl_data.viewport.width + 
pipe_ctx->plane_res.scl_data.viewport.x) {
-   pos_cpy.x = 2 * 
pipe_ctx->plane_res.scl_data.viewport.width
-   - pos_cpy.x + 2 * 
pipe_ctx->plane_res.scl_data.viewport.x;
-   } else {
-   uint32_t temp_x = pos_cpy.x;
-   pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.x 
- pos_cpy.x;
-   if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + 
(int)hubp->curs_attr.width
-   || pos_cpy.x <= 
(int)hubp->curs_attr.width + pipe_ctx->plane_state->src_rect.x) {
-   pos_cpy.x = temp_x + 
pipe_ctx->plane_res.scl_data.viewport.width;
+   int viewport_width =
+   pipe_ctx->plane_res.scl_data.viewport.width;
+   int viewport_x =
+   pipe_ctx->plane_res.scl_data.viewport.x;
+
+   if (pipe_split_on) {
+   if (pos_cpy.x >= viewport_width + viewport_x) {
+   pos_cpy.x = 2 * viewport_width
+   - pos_cpy.x + 2 * viewport_x;
+   } else {
+   uint32_t temp_x = pos_cpy.x;
+
+   pos_cpy.x = 2 * viewport_x - pos_cpy.x;
+   if (temp_x >= viewport_x +
+   (int)hubp->curs_attr.width || pos_cpy.x
+   <= 

[PATCH 30/39] drm/amd/display: Use absolute time stamp to follow the eDP T7 spec requirement

[Rodrigo Siqueira]

From: Dale Zhao 

[Why]:
According to eDP spec, max T7 delay should be 50 ms. Current code uses 300
retry counters may not be accurate enough for different panels.

[How]:
Use absolute time stamp to achive accurate delay.

Signed-off-by: Dale Zhao 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 548aac02ca11..d1df0541e10a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -173,15 +173,20 @@ bool edp_receiver_ready_T9(struct dc_link *link)
 }
 bool edp_receiver_ready_T7(struct dc_link *link)
 {
-   unsigned int tries = 0;
unsigned char sinkstatus = 0;
unsigned char edpRev = 0;
enum dc_status result = DC_OK;
 
+   /* use absolute time stamp to constrain max T7*/
+   unsigned long long enter_timestamp = 0;
+   unsigned long long finish_timestamp = 0;
+   unsigned long long time_taken_in_ns = 0;
+
result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, , 
sizeof(edpRev));
if (result == DC_OK && edpRev < DP_EDP_12)
return true;
/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
+   enter_timestamp = dm_get_timestamp(link->ctx);
do {
sinkstatus = 0;
result = core_link_read_dpcd(link, DP_SINK_STATUS, , 
sizeof(sinkstatus));
@@ -189,8 +194,10 @@ bool edp_receiver_ready_T7(struct dc_link *link)
break;
if (result != DC_OK)
break;
-   udelay(25); //MAx T7 is 50ms
-   } while (++tries < 300);
+   udelay(25);
+   finish_timestamp = dm_get_timestamp(link->ctx);
+   time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, 
finish_timestamp, enter_timestamp);
+   } while (time_taken_in_ns < 50 * 100); //MAx T7 is 50ms
 
if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0)
udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 
1000);
-- 
2.24.0

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[PATCH 31/39] drm/amd/display: Fix update_bw_bounding_box Calcs

[Rodrigo Siqueira]

From: Sung Lee 

[Why]
Previously update_bw_bounding_box for RN was commented out
due to incorrect values causing BSOD on Hybrid Graphics.
However, commenting out this function also may cause issues
such as underflow in certain cases such as 2x4K displays.

[How]
Fix dram_speed_mts calculations.
Update from proper index of clock_limits[]

Signed-off-by: Sung Lee 
Reviewed-by: Yongqiang Sun 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 11 ++-
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index a662769b0c48..111f2c30c6b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1317,12 +1317,6 @@ struct display_stream_compressor *dcn21_dsc_create(
 
 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params 
*bw_params)
 {
-   /*
-   TODO: Fix this function to calcualte correct values.
-   There are known issues with this function currently
-   that will need to be investigated. Use hardcoded known good values for 
now.
-
-
struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
struct clk_limit_table *clk_table = _params->clk_table;
int i;
@@ -1337,11 +1331,10 @@ static void update_bw_bounding_box(struct dc *dc, 
struct clk_bw_params *bw_param
dcn2_1_soc.clock_limits[i].dcfclk_mhz = 
clk_table->entries[i].dcfclk_mhz;
dcn2_1_soc.clock_limits[i].fabricclk_mhz = 
clk_table->entries[i].fclk_mhz;
dcn2_1_soc.clock_limits[i].socclk_mhz = 
clk_table->entries[i].socclk_mhz;
-   dcn2_1_soc.clock_limits[i].dram_speed_mts = 
clk_table->entries[i].memclk_mhz * 16 / 1000;
+   dcn2_1_soc.clock_limits[i].dram_speed_mts = 
clk_table->entries[i].memclk_mhz * 2;
}
-   dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i];
+   dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - 1];
dcn2_1_soc.num_states = i;
-   */
 }
 
 /* Temporary Place holder until we can get them from fuse */
-- 
2.24.0

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[PATCH 14/39] drm/amd/display: Default max bpc to 16 for eDP

[Rodrigo Siqueira]

From: Roman Li 

[Why]
Some 10bit eDP panels don't lightup after we cap bpc to 8.

[How]
Set default max_bpc to 16 for edp connector type.

Signed-off-by: Roman Li 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 455c51c38720..7972286bac23 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5647,9 +5647,9 @@ void amdgpu_dm_connector_init_helper(struct 
amdgpu_display_manager *dm,
 
drm_connector_attach_max_bpc_property(>base, 8, 16);
 
-   /* This defaults to the max in the range, but we want 8bpc. */
-   aconnector->base.state->max_bpc = 8;
-   aconnector->base.state->max_requested_bpc = 8;
+   /* This defaults to the max in the range, but we want 8bpc for non-edp. 
*/
+   aconnector->base.state->max_bpc = (connector_type == 
DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
+   aconnector->base.state->max_requested_bpc = 
aconnector->base.state->max_bpc;
 
if (connector_type == DRM_MODE_CONNECTOR_eDP &&
dc_is_dmcu_initialized(adev->dm.dc)) {
-- 
2.24.0

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[PATCH 11/39] drm/amd/display: Use pipe_count for num of opps

[Rodrigo Siqueira]

From: Noah Abradjian 

[Why]
There is one opp per pipe. For certain RN parts, the fourth pipe is disabled, 
so there is no opp for it.
res_cap->num_opp is hardcoded to 4, so if we use that to iterate over opps we 
will crash.

[How]
Use the pipe_count value instead, which is not hardcoded and so will have the 
correct number.

Signed-off-by: Noah Abradjian 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 32878a65bdd7..cafbd08f1cf2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1357,7 +1357,7 @@ static void dcn20_update_dchubp_dpp(
// MPCC inst is equal to pipe index in practice
int mpcc_inst = pipe_ctx->pipe_idx;
int opp_inst;
-   int opp_count = dc->res_pool->res_cap->num_opp;
+   int opp_count = dc->res_pool->pipe_count;
 
for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
if 
(dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
-- 
2.24.0

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[PATCH 03/39] drm/amd/display: Add wait for flip not pending on pipe unlock

[Rodrigo Siqueira]

From: Noah Abradjian 

[Why]
Lack of proper timing caused intermittent underflow on unplug external DP.
A previous fix was invalid and caused S0i3 regression, so had to be reverted.

[How]
When unlocking pipe, wait for no pipes to have flip pending before unlocking.

Signed-off-by: Noah Abradjian 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 39 ++--
 1 file changed, 36 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 39fe38cb39b6..879cedd79d9e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -66,6 +66,9 @@
 
 #include "dce/dce_i2c.h"
 
+#define CTX \
+   dc->ctx
+
 #define DC_LOGGER \
dc->ctx->logger
 
@@ -783,6 +786,33 @@ static void disable_dangling_plane(struct dc *dc, struct 
dc_state *context)
dc_release_state(current_ctx);
 }
 
+static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
+{
+   int i;
+   int count = 0;
+   struct pipe_ctx *pipe;
+   PERF_TRACE();
+   for (i = 0; i < MAX_PIPES; i++) {
+   pipe = >res_ctx.pipe_ctx[i];
+
+   if (!pipe->plane_state)
+   continue;
+
+   /* Timeout 100 ms */
+   while (count < 10) {
+   /* Must set to false to start with, due to OR in update 
function */
+   pipe->plane_state->status.is_flip_pending = false;
+   dc->hwss.update_pending_status(pipe);
+   if (!pipe->plane_state->status.is_flip_pending)
+   break;
+   udelay(1);
+   count++;
+   }
+   ASSERT(!pipe->plane_state->status.is_flip_pending);
+   }
+   PERF_TRACE();
+}
+
 
/***
  * Public functions
  
**/
@@ -1224,9 +1254,12 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
 
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
-   if (!dc->optimize_seamless_boot)
-   /* pplib is notified if disp_num changed */
-   dc->hwss.optimize_bandwidth(dc, context);
+   if (!dc->optimize_seamless_boot) {
+   /* Must wait for no flips to be pending before doing optimize 
bw */
+   wait_for_no_pipes_pending(dc, context);
+   /* pplib is notified if disp_num changed */
+   dc->hwss.optimize_bandwidth(dc, context);
+   }
 
for (i = 0; i < context->stream_count; i++)
context->streams[i]->mode_changed = false;
-- 
2.24.0

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[PATCH 22/39] drm/amd/display: Perform DMUB hw_init on resume

[Rodrigo Siqueira]

From: Nicholas Kazlauskas 

[Why]
The DMUB is put into reset on suspend and is not running on resume,
disabling PSR/ABM features.

[How]
Move the allocation of the framebuffer to sw_init.

Do DMUB hardware init and framebuffer filling only from hw_init.

On resume the contents of the framebuffer will be invalid so those
should be cleared.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Roman Li 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 196 +++---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   7 +
 2 files changed, 128 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7972286bac23..8cdfb3ccb710 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -98,6 +98,12 @@ MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 #define FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 
+/* Number of bytes in PSP header for firmware. */
+#define PSP_HEADER_BYTES 0x100
+
+/* Number of bytes in PSP footer for firmware. */
+#define PSP_FOOTER_BYTES 0x100
+
 /**
  * DOC: overview
  *
@@ -741,28 +747,27 @@ void amdgpu_dm_audio_eld_notify(struct amdgpu_device 
*adev, int pin)
 
 static int dm_dmub_hw_init(struct amdgpu_device *adev)
 {
-   const unsigned int psp_header_bytes = 0x100;
-   const unsigned int psp_footer_bytes = 0x100;
const struct dmcub_firmware_header_v1_0 *hdr;
struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
+   struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
const struct firmware *dmub_fw = adev->dm.dmub_fw;
struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
struct abm *abm = adev->dm.dc->res_pool->abm;
-   struct dmub_srv_region_params region_params;
-   struct dmub_srv_region_info region_info;
-   struct dmub_srv_fb_params fb_params;
-   struct dmub_srv_fb_info fb_info;
struct dmub_srv_hw_params hw_params;
enum dmub_status status;
const unsigned char *fw_inst_const, *fw_bss_data;
-   uint32_t i;
-   int r;
+   uint32_t i, fw_inst_const_size, fw_bss_data_size;
bool has_hw_support;
 
if (!dmub_srv)
/* DMUB isn't supported on the ASIC. */
return 0;
 
+   if (!fb_info) {
+   DRM_ERROR("No framebuffer info for DMUB service.\n");
+   return -EINVAL;
+   }
+
if (!dmub_fw) {
/* Firmware required for DMUB support. */
DRM_ERROR("No firmware provided for DMUB.\n");
@@ -782,60 +787,36 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
 
hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
 
-   /* Calculate the size of all the regions for the DMUB service. */
-   memset(_params, 0, sizeof(region_params));
-
-   region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
-   psp_header_bytes - psp_footer_bytes;
-   region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
-   region_params.vbios_size = adev->dm.dc->ctx->dc_bios->bios_size;
-
-   status = dmub_srv_calc_region_info(dmub_srv, _params,
-  _info);
-
-   if (status != DMUB_STATUS_OK) {
-   DRM_ERROR("Error calculating DMUB region info: %d\n", status);
-   return -EINVAL;
-   }
-
-   /*
-* Allocate a framebuffer based on the total size of all the regions.
-* TODO: Move this into GART.
-*/
-   r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
-   AMDGPU_GEM_DOMAIN_VRAM, >dm.dmub_bo,
-   >dm.dmub_bo_gpu_addr,
-   >dm.dmub_bo_cpu_addr);
-   if (r)
-   return r;
-
-   /* Rebase the regions on the framebuffer address. */
-   memset(_params, 0, sizeof(fb_params));
-   fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
-   fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
-   fb_params.region_info = _info;
-
-   status = dmub_srv_calc_fb_info(dmub_srv, _params, _info);
-   if (status != DMUB_STATUS_OK) {
-   DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
-   return -EINVAL;
-   }
-
fw_inst_const = dmub_fw->data +
le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
-   psp_header_bytes;
+   PSP_HEADER_BYTES;
 
fw_bss_data = dmub_fw->data +
  le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
  le32_to_cpu(hdr->inst_const_bytes);
 
/* Copy firmware and bios info into FB memory. */
-   memcpy(fb_info.fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
-  

[PATCH 00/39] DC Patches 11 Dec 2019

[Rodrigo Siqueira]

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* Fixes on DCN2, bounding box calcs, regamma, and other;
* Enhancements in DMUB;
* Improvements on DCN20/21, freesync, DSC and others.

Aidan Yang (1):
  drm/amd/display: Disable integerscaling for downscale and MPO

Amanda Liu (1):
  drm/amd/display: Reinstate LFC optimization

Anthony Koo (1):
  drm/amd/display: Do not handle linkloss for eDP

Aric Cyr (5):
  drm/amd/display: Remove integer scaling code from DC and fix cursor
  drm/amd/display: 3.2.63
  drm/amd/display: scaling changes should also be a full update
  drm/amd/display: 3.2.64
  drm/amd/display: Fix manual trigger source for DCN2

Camille Cho (1):
  drm/amd/display: Add definition for number of backlight data points

Charlene Liu (2):
  drm/amd/display: HDMI 2.x audio bandwidth check
  drm/amd/display: Add warmup escape call support

Dale Zhao (1):
  drm/amd/display: Use absolute time stamp to follow the eDP T7 spec
requirement

Derek Lai (1):
  drm/amd/display: Specified VR patch skip to reset segment to 0

Eric Yang (1):
  drm/amd/display: update chroma viewport wa

Hugo Hu (1):
  drm/amd/display: disable lttpr for Navi

Joshua Aberback (1):
  drm/amd/display: Add interface to adjust DSC max target bpp limit

Josip Pavic (1):
  drm/amd/display: fix regamma build optimization

Jun Lei (1):
  drm/amd/display: support virtual DCN

Martin Leung (1):
  drm/amd/display: Enable Seamless Boot Transition for Multiple Streams

Nicholas Kazlauskas (4):
  drm/amd/display: Get DMUB registers from ASIC specific structs
  drm/amd/display: Use physical addressing for DMCUB on both dcn20/21
  drm/amd/display: Perform DMUB hw_init on resume
  drm/amd/display: Get cache window sizes from DMCUB firmware

Nikola Cornij (2):
  drm/amd/display: Map ODM memory correctly when doing ODM combine
  drm/amd/display: Add debug option to override DSC target bpp increment

Noah Abradjian (4):
  drm/amd/display: Add wait for flip not pending on pipe unlock
  drm/amd/display: Use pipe_count for num of opps
  drm/amd/display: Collapse resource arrays when pipe is disabled
  drm/amd/display: Remove reliance on pipe indexing

Paul Hsieh (1):
  drm/amd/display: check link status before disable stream

Qingqing Zhuo (1):
  drm/amd/display: AVI info package change due to spec update

Roman Li (1):
  drm/amd/display: Default max bpc to 16 for eDP

Samson Tam (2):
  drm/amd/display: fix 270 degree rotation for mixed-SLS mode
  drm/amd/display: fix missing cursor on some rotated SLS displays

Sung Lee (3):
  drm/amd/display: Fix update_bw_bounding_box Calcs
  drm/amd/display: Lower DPP DTO only when safe
  drm/amd/display: Formula refactor for calculating DPP CLK DTO

abdoulaye berthe (2):
  drm/amd/display: disable lttpr for RN
  drm/amd/display: Update extended timeout support for DCN20 and DCN21

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 209 +++-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   7 +
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  |  46 ++-
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h  |   6 +-
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |   8 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 177 ++
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  10 +-
 .../drm/amd/display/dc/core/dc_link_hwss.c|  13 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 145 ++--
 .../gpu/drm/amd/display/dc/core/dc_stream.c   |  59 ++--
 drivers/gpu/drm/amd/display/dc/dc.h   |   5 +-
 drivers/gpu/drm/amd/display/dc/dc_dsc.h   |   5 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h  |   1 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h|   7 +
 drivers/gpu/drm/amd/display/dc/dc_types.h |  13 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |   4 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  68 ++--
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c |  20 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  36 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|   1 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  24 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   1 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 314 --
 .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h |   1 +
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  31 +-
 .../drm/amd/display/dc/dm_services_types.h|   3 +-
 .../amd/display/dc/dml/display_mode_structs.h |   1 +
 .../drm/amd/display/dc/dml/display_mode_vba.c |   2 +-
 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c   |  33 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h   |   3 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   7 +-
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   6 +-
 drivers/gpu/drm/amd/display/dc/inc/resource.h |   2 +
 .../inc/{dmub_fw_state.h => dmub_fw_meta.h}   |  64 ++--
 .../gpu/drm/amd/display/dmub/inc/dmub_srv.h   |   7 +-
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c |  84 -
 

[PATCH 07/39] drm/amd/display: Add interface to adjust DSC max target bpp limit

[Rodrigo Siqueira]

From: Joshua Aberback 

[Why]
For some use cases we need to be able to adjust the maximum target bpp
allowed by DSC policy.

[How]
New interface dc_dsc_policy_set_max_target_bpp_limit

Signed-off-by: Joshua Aberback 
Reviewed-by: Nikola Cornij 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dc_dsc.h |  2 ++
 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 14 +++---
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h 
b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index 8ec09813ee17..7ece8eb5f48c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -77,4 +77,6 @@ bool dc_dsc_compute_config(
 void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
struct dc_dsc_policy *policy);
 
+void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index d2423ad1fac2..71b048363506 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -29,6 +29,9 @@
 
 /* This module's internal functions */
 
+/* default DSC policy target bitrate limit is 16bpp */
+static uint32_t dsc_policy_max_target_bpp_limit = 16;
+
 static uint32_t dc_dsc_bandwidth_in_kbps_from_timing(
const struct dc_crtc_timing *timing)
 {
@@ -951,7 +954,12 @@ void dc_dsc_get_policy_for_timing(const struct 
dc_crtc_timing *timing, struct dc
default:
return;
}
-   /* internal upper limit to 16 bpp */
-   if (policy->max_target_bpp > 16)
-   policy->max_target_bpp = 16;
+   /* internal upper limit, default 16 bpp */
+   if (policy->max_target_bpp > dsc_policy_max_target_bpp_limit)
+   policy->max_target_bpp = dsc_policy_max_target_bpp_limit;
+}
+
+void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit)
+{
+   dsc_policy_max_target_bpp_limit = limit;
 }
-- 
2.24.0

___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 20/39] drm/amd/display: Add warmup escape call support

[Rodrigo Siqueira]

From: Charlene Liu 

Add warmup escape support, for diags, in a way that is possible to
choose a new or an existing sequence. For achieving this goal, this
commit adds separated MCIF buffer as VCN request.

Signed-off-by: Charlene Liu 
Reviewed-by: Chris Park 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dc/core/dc_stream.c   | 59 ---
 drivers/gpu/drm/amd/display/dc/dc_stream.h|  7 +++
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  4 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|  1 -
 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h   |  3 +-
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  6 +-
 .../gpu/drm/amd/display/include/dal_asic_id.h |  6 +-
 7 files changed, 56 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index b43a4b115fd8..6ddbb00ed37a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -406,25 +406,30 @@ bool dc_stream_add_writeback(struct dc *dc,
stream->writeback_info[stream->num_wb_info++] = *wb_info;
}
 
-   if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
-   dm_error("DC: update_bandwidth failed!\n");
-   return false;
-   }
-
-   /* enable writeback */
if (dc->hwss.enable_writeback) {
struct dc_stream_status *stream_status = 
dc_stream_get_status(stream);
struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
+   dwb->otg_inst = stream_status->primary_otg_inst;
+   }
+   if (IS_DIAG_DC(dc->ctx->dce_environment)) {
+   if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
+   dm_error("DC: update_bandwidth failed!\n");
+   return false;
+   }
 
-   if (dwb->funcs->is_enabled(dwb)) {
-   /* writeback pipe already enabled, only need to update 
*/
-   dc->hwss.update_writeback(dc, stream_status, wb_info, 
dc->current_state);
-   } else {
-   /* Enable writeback pipe from scratch*/
-   dc->hwss.enable_writeback(dc, stream_status, wb_info, 
dc->current_state);
+   /* enable writeback */
+   if (dc->hwss.enable_writeback) {
+   struct dwbc *dwb = 
dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
+
+   if (dwb->funcs->is_enabled(dwb)) {
+   /* writeback pipe already enabled, only need to 
update */
+   dc->hwss.update_writeback(dc, wb_info, 
dc->current_state);
+   } else {
+   /* Enable writeback pipe from scratch*/
+   dc->hwss.enable_writeback(dc, wb_info, 
dc->current_state);
+   }
}
}
-
return true;
 }
 
@@ -463,19 +468,29 @@ bool dc_stream_remove_writeback(struct dc *dc,
}
stream->num_wb_info = j;
 
-   /* recalculate and apply DML parameters */
-   if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
-   dm_error("DC: update_bandwidth failed!\n");
-   return false;
-   }
-
-   /* disable writeback */
-   if (dc->hwss.disable_writeback)
-   dc->hwss.disable_writeback(dc, dwb_pipe_inst);
+   if (IS_DIAG_DC(dc->ctx->dce_environment)) {
+   /* recalculate and apply DML parameters */
+   if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
+   dm_error("DC: update_bandwidth failed!\n");
+   return false;
+   }
 
+   /* disable writeback */
+   if (dc->hwss.disable_writeback)
+   dc->hwss.disable_writeback(dc, dwb_pipe_inst);
+   }
return true;
 }
 
+bool dc_stream_warmup_writeback(struct dc *dc,
+   int num_dwb,
+   struct dc_writeback_info *wb_info)
+{
+   if (dc->hwss.mmhubbub_warmup)
+   return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);
+   else
+   return false;
+}
 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
 {
uint8_t i;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 3ea54321b045..37c10dbf269e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -344,10 +344,17 @@ bool dc_add_all_planes_for_stream(
 bool dc_stream_add_writeback(struct dc *dc,
struct dc_stream_state *stream,
struct dc_writeback_info *wb_info);
+
 bool dc_stream_remove_writeback(struct dc *dc,
struct dc_stream_state *stream,
uint32_t dwb_pipe_inst);
+
+bool dc_stream_warmup_writeback(struct dc 

[PATCH 10/39] drm/amd/display: Reinstate LFC optimization

[Rodrigo Siqueira]

From: Amanda Liu 

[why]
We want to streamline the calculations made when entering LFC.
Previously, the optimizations led to screen tearing and were backed out
to unblock development.

[how]
Integrate deflicker window calculations as well as screen tearing fixes
with the original LFC calculation optimizations.

Signed-off-by: Amanda Liu 
Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
---
 .../amd/display/modules/freesync/freesync.c   | 32 +++
 .../amd/display/modules/inc/mod_freesync.h|  1 +
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index a94700940fd6..fa57885503d4 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -37,8 +37,8 @@
 #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
 /* Number of elements in the render times cache array */
 #define RENDER_TIMES_MAX_COUNT 10
-/* Threshold to exit BTR (to avoid frequent enter-exits at the lower limit) */
-#define BTR_EXIT_MARGIN 2000
+/* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower 
limit) */
+#define BTR_MAX_MARGIN 2500
 /* Threshold to change BTR multiplier (to avoid frequent changes) */
 #define BTR_DRIFT_MARGIN 2000
 /*Threshold to exit fixed refresh rate*/
@@ -254,24 +254,22 @@ static void apply_below_the_range(struct core_freesync 
*core_freesync,
unsigned int delta_from_mid_point_in_us_1 = 0x;
unsigned int delta_from_mid_point_in_us_2 = 0x;
unsigned int frames_to_insert = 0;
-   unsigned int min_frame_duration_in_ns = 0;
-   unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
unsigned int delta_from_mid_point_delta_in_us;
-
-   min_frame_duration_in_ns = ((unsigned int) (div64_u64(
-   (10ULL * 100),
-   in_out_vrr->max_refresh_in_uhz)));
+   unsigned int max_render_time_in_us =
+   in_out_vrr->max_duration_in_us - 
in_out_vrr->btr.margin_in_us;
 
/* Program BTR */
-   if (last_render_time_in_us + BTR_EXIT_MARGIN < max_render_time_in_us) {
+   if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < 
max_render_time_in_us) {
/* Exit Below the Range */
if (in_out_vrr->btr.btr_active) {
in_out_vrr->btr.frame_counter = 0;
in_out_vrr->btr.btr_active = false;
}
-   } else if (last_render_time_in_us > max_render_time_in_us) {
+   } else if (last_render_time_in_us > (max_render_time_in_us + 
in_out_vrr->btr.margin_in_us / 2)) {
/* Enter Below the Range */
-   in_out_vrr->btr.btr_active = true;
+   if (!in_out_vrr->btr.btr_active) {
+   in_out_vrr->btr.btr_active = true;
+   }
}
 
/* BTR set to "not active" so disengage */
@@ -327,7 +325,9 @@ static void apply_below_the_range(struct core_freesync 
*core_freesync,
/* Choose number of frames to insert based on how close it
 * can get to the mid point of the variable range.
 */
-   if (delta_from_mid_point_in_us_1 < 
delta_from_mid_point_in_us_2) {
+   if ((frame_time_in_us / mid_point_frames_ceil) > 
in_out_vrr->min_duration_in_us &&
+   (delta_from_mid_point_in_us_1 < 
delta_from_mid_point_in_us_2 ||
+   mid_point_frames_floor < 2)) {
frames_to_insert = mid_point_frames_ceil;
delta_from_mid_point_delta_in_us = 
delta_from_mid_point_in_us_2 -
delta_from_mid_point_in_us_1;
@@ -343,7 +343,7 @@ static void apply_below_the_range(struct core_freesync 
*core_freesync,
if (in_out_vrr->btr.frames_to_insert != 0 &&
delta_from_mid_point_delta_in_us < 
BTR_DRIFT_MARGIN) {
if (((last_render_time_in_us / 
in_out_vrr->btr.frames_to_insert) <
-   in_out_vrr->max_duration_in_us) &&
+   max_render_time_in_us) &&
((last_render_time_in_us / 
in_out_vrr->btr.frames_to_insert) >
in_out_vrr->min_duration_in_us))
frames_to_insert = 
in_out_vrr->btr.frames_to_insert;
@@ -796,6 +796,11 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
refresh_range = in_out_vrr->max_refresh_in_uhz -
in_out_vrr->min_refresh_in_uhz;
 
+   in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
+   2 * 

[PATCH 27/39] drm/amd/display: Get cache window sizes from DMCUB firmware

[Rodrigo Siqueira]

From: Nicholas Kazlauskas 

[Why]
Firmware state and tracebuffer shouldn't be considered stable API
between firmware versions.

Driver shouldn't be querying anything from firmware state or tracebuffer
outside of debugging.

Commands are the stable API for this once we have the outbox.

[How]
Add metadata struct to the end of the data firmware that describes
fw_state_size and some reserved area for future use.

Drop the tracebuffer and firmware state headers since they can differ
per version.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  4 ++
 .../inc/{dmub_fw_state.h => dmub_fw_meta.h}   | 64 ---
 .../gpu/drm/amd/display/dmub/inc/dmub_srv.h   |  3 +-
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   | 51 +--
 4 files changed, 78 insertions(+), 44 deletions(-)
 rename drivers/gpu/drm/amd/display/dmub/inc/{dmub_fw_state.h => 
dmub_fw_meta.h} (57%)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8cdfb3ccb710..745d8719ccc1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1234,6 +1234,10 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
region_params.vbios_size = adev->bios_size;
+   region_params.fw_bss_data =
+   adev->dm.dmub_fw->data +
+   le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
+   le32_to_cpu(hdr->inst_const_bytes);
 
status = dmub_srv_calc_region_info(dmub_srv, _params,
   _info);
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_meta.h
similarity index 57%
rename from drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h
rename to drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_meta.h
index c87b1ba7590e..242ec257998c 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_meta.h
@@ -22,52 +22,42 @@
  * Authors: AMD
  *
  */
-
-#ifndef _DMUB_FW_STATE_H_
-#define _DMUB_FW_STATE_H_
+#ifndef _DMUB_META_H_
+#define _DMUB_META_H_
 
 #include "dmub_types.h"
 
 #pragma pack(push, 1)
 
-struct dmub_fw_state {
-   /**
-* @phy_initialized_during_fw_boot:
-*
-* Detects if VBIOS/VBL has ran before firmware boot.
-* A value of 1 will usually mean S0i3 boot.
-*/
-   uint8_t phy_initialized_during_fw_boot;
-
-   /**
-* @intialized_phy:
-*
-* Bit vector of initialized PHY.
-*/
-   uint8_t initialized_phy;
+/* Magic value for identifying dmub_fw_meta_info */
+#define DMUB_FW_META_MAGIC 0x444D5542
 
-   /**
-* @enabled_phy:
-*
-* Bit vector of enabled PHY for DP alt mode switch tracking.
-*/
-   uint8_t enabled_phy;
+/* Offset from the end of the file to the dmub_fw_meta_info */
+#define DMUB_FW_META_OFFSET 0x24
 
-   /**
-* @dmcu_fw_loaded:
-*
-* DMCU auto load state.
-*/
-   uint8_t dmcu_fw_loaded;
+/**
+ * struct dmub_fw_meta_info - metadata associated with fw binary
+ *
+ * NOTE: This should be considered a stable API. Fields should
+ *   not be repurposed or reordered. New fields should be
+ *   added instead to extend the structure.
+ *
+ * @magic_value: magic value identifying DMUB firmware meta info
+ * @fw_region_size: size of the firmware state region
+ * @trace_buffer_size: size of the tracebuffer region
+ */
+struct dmub_fw_meta_info {
+   uint32_t magic_value;
+   uint32_t fw_region_size;
+   uint32_t trace_buffer_size;
+};
 
-   /**
-* @psr_state:
-*
-* PSR state tracking.
-*/
-   uint8_t psr_state;
+/* Ensure that the structure remains 64 bytes. */
+union dmub_fw_meta {
+   struct dmub_fw_meta_info info;
+   uint8_t reserved[64];
 };
 
 #pragma pack(pop)
 
-#endif /* _DMUB_FW_STATE_H_ */
+#endif /* _DMUB_META_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
index 689806b6ee31..f34a50dd36ea 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
@@ -67,7 +67,6 @@
 #include "dmub_types.h"
 #include "dmub_cmd.h"
 #include "dmub_rb.h"
-#include "dmub_fw_state.h"
 
 #if defined(__cplusplus)
 extern "C" {
@@ -145,11 +144,13 @@ struct dmub_fb {
  * @inst_const_size: size of the fw inst const section
  * @bss_data_size: size of the fw bss data section
  * @vbios_size: size of the vbios data
+ * @fw_bss_data: raw firmware bss data section
  */
 struct dmub_srv_region_params {
uint32_t inst_const_size;

[PATCH 26/39] drm/amd/display: Remove reliance on pipe indexing

[Rodrigo Siqueira]

From: Noah Abradjian 

[Why]
In certain instances, there was a reliance on pipe indexing being accurate. 
However, this
assumption fails with harvesting of pipes 1 or 2, which can occur in production 
B6 parts.
HW hang would occur as a result.

[How]
Use hubp index for mpcc, and do mpc_init for all theoretical pipes (including 
disabled ones).

Signed-off-by: Noah Abradjian 
Reviewed-by: Yongqiang Sun 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index aa389dea279d..9e53bbd5d2b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1163,7 +1163,8 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state 
*context)
}
}
 
-   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   /* num_opp will be equal to number of mpcc */
+   for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[i];
 
/* Cannot reset the MPC mux if seamless boot */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 3706299906e4..aa00fbe49c6e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1356,7 +1356,7 @@ static void dcn20_update_dchubp_dpp(
|| plane_state->update_flags.bits.global_alpha_change
|| 
plane_state->update_flags.bits.per_pixel_alpha_change) {
// MPCC inst is equal to pipe index in practice
-   int mpcc_inst = pipe_ctx->pipe_idx;
+   int mpcc_inst = hubp->inst;
int opp_inst;
int opp_count = dc->res_pool->pipe_count;
 
-- 
2.24.0

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[PATCH 29/39] drm/amd/display: 3.2.64

[Rodrigo Siqueira]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 5c48111deabc..4c2ba93ab7e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.63"
+#define DC_VER "3.2.64"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.24.0

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[PATCH] drm/amdgpu: fix license on Kconfig and Makefiles

[Alex Deucher]

amdgpu is MIT licensed.

Fixes: ec8f24b7faaf3d ("treewide: Add SPDX license identifier - 
Makefile/Kconfig")
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/acp/Kconfig   | 2 +-
 drivers/gpu/drm/amd/amdgpu/Kconfig| 2 +-
 drivers/gpu/drm/amd/amdkfd/Kconfig| 2 +-
 drivers/gpu/drm/amd/display/Kconfig   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 1 +
 drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 1 +
 drivers/gpu/drm/amd/display/dc/dsc/Makefile   | 1 +
 7 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig
index 19bae9100da4..13340f353ea8 100644
--- a/drivers/gpu/drm/amd/acp/Kconfig
+++ b/drivers/gpu/drm/amd/acp/Kconfig
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-License-Identifier: MIT
 menu "ACP (Audio CoProcessor) Configuration"
 
 config DRM_AMD_ACP
diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig 
b/drivers/gpu/drm/amd/amdgpu/Kconfig
index 2e98c016cb47..9375e7f12420 100644
--- a/drivers/gpu/drm/amd/amdgpu/Kconfig
+++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-License-Identifier: MIT
 config DRM_AMDGPU_SI
bool "Enable amdgpu support for SI parts"
depends on DRM_AMDGPU
diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig 
b/drivers/gpu/drm/amd/amdkfd/Kconfig
index ba0e68057a89..b3672d10ea54 100644
--- a/drivers/gpu/drm/amd/amdkfd/Kconfig
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-License-Identifier: MIT
 #
 # Heterogenous system architecture configuration
 #
diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index 2a2f621c0d6c..87858bc57e64 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-License-Identifier: MIT
 menu "Display Engine Configuration"
depends on DRM && DRM_AMDGPU
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
index 2eeb03818072..5fcaf78334ff 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: MIT
 #
 # Makefile for DCN.
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
index b3688900d211..07684d3e375a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: MIT
 #
 # Makefile for DCN21.
 
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile 
b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
index 7415b8bf6318..3f66868df171 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: MIT
 #
 # Makefile for the 'dsc' sub-component of DAL.
 
-- 
2.23.0

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[PATCH 16/39] drm/amd/display: Remove integer scaling code from DC and fix cursor

[Rodrigo Siqueira]

From: Aric Cyr 

[Why]
Scaling better handled by upper layers before pipe splitting.

[How]
Remove DC code for integer scaling and force cursor update if
viewport or scaling changes occur to prevent underflow from
invalid cursor position.

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 44 ---
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  3 +-
 2 files changed, 2 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 594731182641..51e0f4472dbd 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -940,48 +940,6 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx 
*pipe_ctx)
 
 }
 
-static bool is_downscaled(const struct rect *src_rect, const struct rect 
*dst_rect)
-{
-if (src_rect->width > dst_rect->width || src_rect->height > 
dst_rect->height)
-   return true;
-   return false;
-}
-
-static bool is_mpo(int layer_index)
-{
-   if (layer_index > 0)
-   return true;
-   return false;
-}
-
-static void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
-{
-   unsigned int integer_multiple = 1;
-
-   if (pipe_ctx->plane_state->scaling_quality.integer_scaling &&
-   !is_downscaled(_ctx->plane_state->src_rect, 
_ctx->plane_state->dst_rect) &&
-   !is_mpo(pipe_ctx->plane_state->layer_index)) {
-   // calculate maximum # of replication of src onto addressable
-   integer_multiple = min(
-   pipe_ctx->stream->timing.h_addressable / 
pipe_ctx->stream->src.width,
-   pipe_ctx->stream->timing.v_addressable  / 
pipe_ctx->stream->src.height);
-
-   //scale dst
-   pipe_ctx->stream->dst.width  = integer_multiple * 
pipe_ctx->stream->src.width;
-   pipe_ctx->stream->dst.height = integer_multiple * 
pipe_ctx->stream->src.height;
-
-   //center dst onto addressable
-   pipe_ctx->stream->dst.x = 
(pipe_ctx->stream->timing.h_addressable - pipe_ctx->stream->dst.width)/2;
-   pipe_ctx->stream->dst.y = 
(pipe_ctx->stream->timing.v_addressable - pipe_ctx->stream->dst.height)/2;
-
-   //We are guaranteed that we are scaling in integer ratio
-   pipe_ctx->plane_state->scaling_quality.v_taps = 1;
-   pipe_ctx->plane_state->scaling_quality.h_taps = 1;
-   pipe_ctx->plane_state->scaling_quality.v_taps_c = 1;
-   pipe_ctx->plane_state->scaling_quality.h_taps_c = 1;
-   }
-}
-
 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 {
const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
@@ -995,8 +953,6 @@ bool resource_build_scaling_params(struct pipe_ctx 
*pipe_ctx)
pipe_ctx->plane_res.scl_data.format = 
convert_pixel_format_to_dalsurface(
pipe_ctx->plane_state->format);
 
-   calculate_integer_scaling(pipe_ctx);
-
calculate_scaling_ratios(pipe_ctx);
 
calculate_viewport(pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 8d779062a4e8..e1e274018049 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1394,7 +1394,8 @@ static void dcn20_update_dchubp_dpp(
}
 
/* Any updates are handled in dc interface, just need to apply existing 
for plane enable */
-   if ((pipe_ctx->update_flags.bits.enable || 
pipe_ctx->update_flags.bits.opp_changed)
+   if ((pipe_ctx->update_flags.bits.enable || 
pipe_ctx->update_flags.bits.opp_changed ||
+   pipe_ctx->update_flags.bits.scaler || 
pipe_ctx->update_flags.bits.viewport)
&& 
pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
dc->hwss.set_cursor_position(pipe_ctx);
dc->hwss.set_cursor_attribute(pipe_ctx);
-- 
2.24.0

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[PATCH 04/39] drm/amd/display: Get DMUB registers from ASIC specific structs

[Rodrigo Siqueira]

From: Nicholas Kazlauskas 

[Why]
These values can differ per ASIC and should follow the full DC style
register programming model.

[How]
Define a common list and fill in the common list separately for
dcn20 and dcn21.

Unlike DC we're not using designated initializers for better compiler
compatibility since this resides in the DMUB service.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dmub/inc/dmub_srv.h   |   4 +-
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c |  25 +++-
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 117 ++
 .../gpu/drm/amd/display/dmub/src/dmub_dcn21.c |  18 +++
 .../gpu/drm/amd/display/dmub/src/dmub_dcn21.h |   4 +
 .../gpu/drm/amd/display/dmub/src/dmub_reg.h   |  10 +-
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |   4 +
 7 files changed, 176 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
index 528243e35add..689806b6ee31 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
@@ -76,7 +76,7 @@ extern "C" {
 /* Forward declarations */
 struct dmub_srv;
 struct dmub_cmd_header;
-struct dmcu;
+struct dmub_srv_common_regs;
 
 /* enum dmub_status - return code for dmcub functions */
 enum dmub_status {
@@ -307,6 +307,8 @@ struct dmub_srv {
volatile const struct dmub_fw_state *fw_state;
 
/* private: internal use only */
+   const struct dmub_srv_common_regs *regs;
+
struct dmub_srv_base_funcs funcs;
struct dmub_srv_hw_funcs hw_funcs;
struct dmub_rb inbox1_rb;
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 951ea7053c7e..5760f25c3309 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -25,6 +25,7 @@
 
 #include "../inc/dmub_srv.h"
 #include "dmub_reg.h"
+#include "dmub_dcn20.h"
 
 #include "dcn/dcn_2_0_0_offset.h"
 #include "dcn/dcn_2_0_0_sh_mask.h"
@@ -33,6 +34,25 @@
 
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
 #define CTX dmub
+#define REGS dmub->regs
+
+/* Registers. */
+
+const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
+#define DMUB_SR(reg) REG_OFFSET(reg),
+   { DMUB_COMMON_REGS() },
+#undef DMUB_SR
+
+#define DMUB_SF(reg, field) FD_MASK(reg, field),
+   { DMUB_COMMON_FIELDS() },
+#undef DMUB_SF
+
+#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
+   { DMUB_COMMON_FIELDS() },
+#undef DMUB_SF
+};
+
+/* Shared functions. */
 
 void dmub_dcn20_reset(struct dmub_srv *dmub)
 {
@@ -47,8 +67,9 @@ void dmub_dcn20_reset_release(struct dmub_srv *dmub)
REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
 }
 
-void dmub_dcn20_backdoor_load(struct dmub_srv *dmub, struct dmub_window *cw0,
- struct dmub_window *cw1)
+void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
+ const struct dmub_window *cw0,
+ const struct dmub_window *cw1)
 {
REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x4,
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
index e70a57573467..68af9b190288 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
@@ -30,6 +30,123 @@
 
 struct dmub_srv;
 
+/* DCN20 register definitions. */
+
+#define DMUB_COMMON_REGS() \
+   DMUB_SR(DMCUB_CNTL) \
+   DMUB_SR(DMCUB_MEM_CNTL) \
+   DMUB_SR(DMCUB_SEC_CNTL) \
+   DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
+   DMUB_SR(DMCUB_INBOX1_SIZE) \
+   DMUB_SR(DMCUB_INBOX1_RPTR) \
+   DMUB_SR(DMCUB_INBOX1_WPTR) \
+   DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
+   DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
+   DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
+   DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
+   DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
+   DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
+   DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
+   DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
+   DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
+   DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
+   DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
+   DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
+   DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
+   DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
+   DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
+   DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
+   DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
+   DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
+   DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
+   DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
+   DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
+   DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
+   DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
+   

[PATCH 09/39] drm/amd/display: AVI info package change due to spec update

[Rodrigo Siqueira]

From: Qingqing Zhuo 

YQ should be limited range for all cases.

Signed-off-by: Qingqing Zhuo 
Reviewed-by: Charlene Liu 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 39cc71bedf69..4700c785566b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2297,7 +2297,7 @@ static void set_avi_info_frame(
if (color_space == COLOR_SPACE_SRGB ||
color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_FULL_RANGE;
-   hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
+   hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
} else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
color_space == 
COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_LIMITED_RANGE;
-- 
2.24.0

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[PATCH 08/39] drm/amd/display: Add definition for number of backlight data points

[Rodrigo Siqueira]

From: Camille Cho 

[Why]
A hardcoded number is used today

[How]
Add definition for number of BL data points

Signed-off-by: Camille Cho 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dm_services_types.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h 
b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index a3d1be20dd9d..b52ba6ffabe1 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -220,6 +220,7 @@ struct dm_bl_data_point {
 };
 
 /* Total size of the structure should not exceed 256 bytes */
+#define BL_DATA_POINTS 99
 struct dm_acpi_atif_backlight_caps {
uint16_t size; /* Bytes 0-1 (2 bytes) */
uint16_t flags; /* Byted 2-3 (2 bytes) */
@@ -229,7 +230,7 @@ struct dm_acpi_atif_backlight_caps {
uint8_t  min_input_signal; /* Byte 7 */
uint8_t  max_input_signal; /* Byte 8 */
uint8_t  num_data_points; /* Byte 9 */
-   struct dm_bl_data_point data_points[99]; /* Bytes 10-207 (198 bytes)*/
+   struct dm_bl_data_point data_points[BL_DATA_POINTS]; /* Bytes 10-207 
(198 bytes)*/
 };
 
 enum dm_acpi_display_type {
-- 
2.24.0

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[PATCH 02/39] drm/amd/display: disable lttpr for RN

[Rodrigo Siqueira]

From: abdoulaye berthe 

Signed-off-by: abdoulaye berthe 
Reviewed-by: George Shen 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 8fa63929d3b9..98f0267300a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1677,7 +1677,7 @@ static bool dcn21_resource_construct(
dc->caps.max_slave_planes = 1;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
-   dc->caps.extended_aux_timeout_support = true;
+   dc->caps.extended_aux_timeout_support = false;
dc->caps.dmcub_support = true;
 
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
-- 
2.24.0

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[PATCH 06/39] drm/amd/display: Disable integerscaling for downscale and MPO

[Rodrigo Siqueira]

From: Aidan Yang 

[Why]
Integer scaling is applied to MPO planes when downscaling,
MPO planes use variable taps and integer scaling sets taps=1

[How]
Disable integer scaling on MPO planes,
Disable integer scaling for downscaling planes

Signed-off-by: Aidan Yang 
Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c  | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 6c6f5640234c..39cc71bedf69 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -940,11 +940,27 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx 
*pipe_ctx)
 
 }
 
+static bool is_downscaled(const struct rect *src_rect, const struct rect 
*dst_rect)
+{
+if (src_rect->width > dst_rect->width || src_rect->height > 
dst_rect->height)
+   return true;
+   return false;
+}
+
+static bool is_mpo(int layer_index)
+{
+   if (layer_index > 0)
+   return true;
+   return false;
+}
+
 static void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
 {
unsigned int integer_multiple = 1;
 
-   if (pipe_ctx->plane_state->scaling_quality.integer_scaling) {
+   if (pipe_ctx->plane_state->scaling_quality.integer_scaling &&
+   !is_downscaled(_ctx->plane_state->src_rect, 
_ctx->plane_state->dst_rect) &&
+   !is_mpo(pipe_ctx->plane_state->layer_index)) {
// calculate maximum # of replication of src onto addressable
integer_multiple = min(
pipe_ctx->stream->timing.h_addressable / 
pipe_ctx->stream->src.width,
-- 
2.24.0

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Re: [PATCH] drm/amdgpu: wait for all rings to drain before runtime suspending

[Alex Deucher]

On Wed, Dec 11, 2019 at 8:07 AM Christian König
 wrote:
>
> Am 11.12.19 um 03:26 schrieb zhoucm1:
> >
> > On 2019/12/11 上午6:08, Alex Deucher wrote:
> >> Add a safety check to runtime suspend to make sure all outstanding
> >> fences have signaled before we suspend.  Doesn't fix any known issue.
> >>
> >> We already do this via the fence driver suspend function, but we
> >> just force completion rather than bailing.  This bails on runtime
> >> suspend so we can try again later once the fences are signaled to
> >> avoid missing any outstanding work.
> >
> > The idea sounds OK to me, but if you want to drain the rings, you
> > should make sure no more submission, right?
> >
> > So you should park all schedulers before waiting for all outstanding
> > fences completed.
>
> At that point userspace should already be put to hold, so no new
> submissions. But it probably won't hurt stopping the scheduler anyway.
>

Any ioctl calls will wake the hw again or increase the usage count.

> But another issue I see is what happens if we locked up the hardware?
>

Regular GPU reset would kick in eventually.

Alex

> Christian.
>
> >
> > -David
> >
> >>
> >> Signed-off-by: Alex Deucher 
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12 +++-
> >>   1 file changed, 11 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> index 2f367146c72c..81322b0a8acf 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> @@ -1214,13 +1214,23 @@ static int
> >> amdgpu_pmops_runtime_suspend(struct device *dev)
> >>   struct pci_dev *pdev = to_pci_dev(dev);
> >>   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> >>   struct amdgpu_device *adev = drm_dev->dev_private;
> >> -int ret;
> >> +int ret, i;
> >> if (!adev->runpm) {
> >>   pm_runtime_forbid(dev);
> >>   return -EBUSY;
> >>   }
> >>   +/* wait for all rings to drain before suspending */
> >> +for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
> >> +struct amdgpu_ring *ring = adev->rings[i];
> >> +if (ring && ring->sched.ready) {
> >> +ret = amdgpu_fence_wait_empty(ring);
> >> +if (ret)
> >> +return -EBUSY;
> >> +}
> >> +}
> >> +
> >>   if (amdgpu_device_supports_boco(drm_dev))
> >>   drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
> >>   drm_kms_helper_poll_disable(drm_dev);
> > ___
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> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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Re: [PATCH] drm/amdgpu: log when amdgpu.dc=1 but ASIC is unsupported

[Alex Deucher]

On Wed, Dec 11, 2019 at 5:27 AM Simon Ser  wrote:
>
> This makes it easier to figure out whether the kernel parameter has been
> taken into account.
>
> Signed-off-by: Simon Ser 
> Cc: Harry Wentland 
> Cc: Alex Deucher 

Applied. thanks.

Alex


> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7a6c837c0a85..10618353383f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2525,6 +2525,9 @@ bool amdgpu_device_asic_has_dc_support(enum 
> amd_asic_type asic_type)
> return amdgpu_dc != 0;
>  #endif
> default:
> +   if (amdgpu_dc > 0)
> +   DRM_INFO("Display Core has been requested via kernel 
> parameter "
> +"but isn't supported by ASIC, 
> ignoring\n");
> return false;
> }
>  }
> --
> 2.24.0
>
>
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[PATCH 4/4] drm/scheduler: do not keep a copy of sched list

[Nirmoy Das]

entity should not keep copy and maintain sched list for
itself.

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/scheduler/sched_entity.c | 19 ---
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c
index f9b6ce29c58f..2e3a058fc239 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -56,8 +56,6 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
  unsigned int num_sched_list,
  atomic_t *guilty)
 {
-   int i;
-
if (!(entity && sched_list && (num_sched_list == 0 || sched_list[0])))
return -EINVAL;
 
@@ -67,22 +65,14 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
entity->guilty = guilty;
entity->num_sched_list = num_sched_list;
entity->priority = priority;
-   entity->sched_list =  kcalloc(num_sched_list,
- sizeof(struct drm_gpu_scheduler *), 
GFP_KERNEL);
+   entity->sched_list = num_sched_list > 1 ? sched_list : NULL;
+   entity->last_scheduled = NULL;
 
-   if(!entity->sched_list)
-   return -ENOMEM;
+   if(num_sched_list)
+   entity->rq = _list[0]->sched_rq[entity->priority];
 
init_completion(>entity_idle);
 
-   for (i = 0; i < num_sched_list; i++)
-   entity->sched_list[i] = sched_list[i];
-
-   if (num_sched_list)
-   entity->rq = >sched_list[0]->sched_rq[entity->priority];
-
-   entity->last_scheduled = NULL;
-
spin_lock_init(>rq_lock);
spsc_queue_init(>job_queue);
 
@@ -312,7 +302,6 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
 
dma_fence_put(entity->last_scheduled);
entity->last_scheduled = NULL;
-   kfree(entity->sched_list);
 }
 EXPORT_SYMBOL(drm_sched_entity_fini);
 
-- 
2.24.0

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[PATCH 1/4 v2] drm/scheduler: rework entity creation

[Nirmoy Das]

Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a  drm scheduler.

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  8 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c  |  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 14 +++--
 drivers/gpu/drm/etnaviv/etnaviv_drv.c|  7 ++-
 drivers/gpu/drm/lima/lima_sched.c|  5 +-
 drivers/gpu/drm/panfrost/panfrost_job.c  |  8 ++-
 drivers/gpu/drm/scheduler/sched_entity.c | 74 ++--
 drivers/gpu/drm/v3d/v3d_drv.c|  8 ++-
 include/drm/gpu_scheduler.h  |  8 ++-
 11 files changed, 78 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a0d3d7b756eb..1d6850af9908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,

for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;

@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
if (!rings[j]->adev)
continue;

-   rqs[num_rqs++] = [j]->sched.sched_rq[priority];
+   sched_list[num_rqs++] = [j]->sched;
}

for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
r = drm_sched_entity_init(>entities[i][j].entity,
- rqs, num_rqs, >guilty);
+ priority, sched_list,
+ num_rqs, >guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 81f6764f1ba6..2ff63d0414c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1954,11 +1954,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct 
amdgpu_device *adev, bool enable)

if (enable) {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;

ring = adev->mman.buffer_funcs_ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-   r = drm_sched_entity_init(>mman.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, ,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
  r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index d587ffe2af8e..a92f3b18e657 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;

ring = >uvd.inst[0].ring;
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>uvd.entity, , 1, NULL);
+   sched = >sched;
+   r = drm_sched_entity_init(>uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ , 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   struct drm_sched_rq *rq;
+   struct drm_gpu_scheduler *sched;
int r;

ring = >vce.ring[0];
-   rq = >sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-   r = drm_sched_entity_init(>vce.entity, , 1, NULL);
+   sched = >sched;
+   r = 

[PATCH 2/4] drm/amdgpu: replace vm_pte's run-queue list with drm gpu scheds list

[Nirmoy Das]

drm_sched_entity_init() takes drm gpu scheduler list instead of
drm_sched_rq list. This makes conversion of drm_sched_rq list
to drm gpu scheduler list unnecessary

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  4 ++--
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c  |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  5 ++---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/si_dma.c|  8 +++-
 9 files changed, 24 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 47b4f359f07c..8c5b0cda9a3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2785,7 +2785,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->mman.buffer_funcs = NULL;
adev->mman.buffer_funcs_ring = NULL;
adev->vm_manager.vm_pte_funcs = NULL;
-   adev->vm_manager.vm_pte_num_rqs = 0;
+   adev->vm_manager.vm_pte_num_scheds = 0;
adev->gmc.gmc_funcs = NULL;
adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1c65b5bffa6b..b999b67ff57a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2744,7 +2744,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
 {
struct amdgpu_bo_param bp;
struct amdgpu_bo *root;
-   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
int r, i;
 
vm->va = RB_ROOT_CACHED;
@@ -2758,19 +2757,17 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
spin_lock_init(>invalidated_lock);
INIT_LIST_HEAD(>freed);
 
-   for (i = 0; i < adev->vm_manager.vm_pte_num_rqs; i++)
-   sched_list[i] = adev->vm_manager.vm_pte_rqs[i]->sched;
 
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(>direct, DRM_SCHED_PRIORITY_NORMAL,
- sched_list, adev->vm_manager.vm_pte_num_rqs,
- NULL);
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds, NULL);
if (r)
return r;
 
r = drm_sched_entity_init(>delayed, DRM_SCHED_PRIORITY_NORMAL,
- sched_list, adev->vm_manager.vm_pte_num_rqs,
- NULL);
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds, NULL);
if (r)
goto error_free_direct;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index d5613d184e99..100547f094ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -330,8 +330,8 @@ struct amdgpu_vm_manager {
u64 vram_base_offset;
/* vm pte handling */
const struct amdgpu_vm_pte_funcs*vm_pte_funcs;
-   struct drm_sched_rq *vm_pte_rqs[AMDGPU_MAX_RINGS];
-   unsignedvm_pte_num_rqs;
+   struct drm_gpu_scheduler
*vm_pte_scheds[AMDGPU_MAX_RINGS];
+   unsignedvm_pte_num_scheds;
struct amdgpu_ring  *page_fault;
 
/* partial resident texture handling */
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 82cdb8f57bfd..1f22a8d0f7f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1373,16 +1373,14 @@ static const struct amdgpu_vm_pte_funcs 
cik_sdma_vm_pte_funcs = {
 
 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
-   struct drm_gpu_scheduler *sched;
unsigned i;
 
adev->vm_manager.vm_pte_funcs = _sdma_vm_pte_funcs;
for (i = 0; i < adev->sdma.num_instances; i++) {
-   sched = >sdma.instance[i].ring.sched;
-   adev->vm_manager.vm_pte_rqs[i] =
-   >sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+   adev->vm_manager.vm_pte_scheds[i] =
+   >sdma.instance[i].ring.sched;
}
-   adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
+   adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
 }
 
 const struct 

[PATCH 3/4 v2] amd/amdgpu: add sched array to IPs with multiple run-queues

[Nirmoy Das]

This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.

Signed-off-by: Nirmoy Das 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h|   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h|   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h   |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|   9 +-
 7 files changed, 89 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 1d6850af9908..165d1a397266 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
   struct amdgpu_ctx *ctx)
 {
unsigned num_entities = amdgpu_ctx_total_num_entities();
-   unsigned i, j, k;
+   unsigned i, j;
int r;

if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -121,73 +121,56 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;

for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
-   struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-   struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
-   unsigned num_rings = 0;
-   unsigned num_rqs = 0;
+   struct drm_gpu_scheduler **scheds;
+   struct drm_gpu_scheduler *sched;
+   unsigned num_scheds = 0;

switch (i) {
case AMDGPU_HW_IP_GFX:
-   rings[0] = >gfx.gfx_ring[0];
-   num_rings = 1;
+   scheds = adev->gfx.gfx_sched;
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_COMPUTE:
-   for (j = 0; j < adev->gfx.num_compute_rings; ++j)
-   rings[j] = >gfx.compute_ring[j];
-   num_rings = adev->gfx.num_compute_rings;
+   scheds = adev->gfx.compute_sched;
+   num_scheds = adev->gfx.num_compute_sched;
break;
case AMDGPU_HW_IP_DMA:
-   for (j = 0; j < adev->sdma.num_instances; ++j)
-   rings[j] = >sdma.instance[j].ring;
-   num_rings = adev->sdma.num_instances;
+   scheds = adev->sdma.sdma_sched;
+   num_scheds = adev->sdma.num_sdma_sched;
break;
case AMDGPU_HW_IP_UVD:
-   rings[0] = >uvd.inst[0].ring;
-   num_rings = 1;
+   sched = >uvd.inst[0].ring.sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCE:
-   rings[0] = >vce.ring[0];
-   num_rings = 1;
+   sched = >vce.ring[0].sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_UVD_ENC:
-   rings[0] = >uvd.inst[0].ring_enc[0];
-   num_rings = 1;
+   sched = >uvd.inst[0].ring_enc[0].sched;
+   scheds = 
+   num_scheds = 1;
break;
case AMDGPU_HW_IP_VCN_DEC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   rings[num_rings++] = 
>vcn.inst[j].ring_dec;
-   }
+   scheds = adev->vcn.vcn_dec_sched;
+   num_scheds =  adev->vcn.num_vcn_dec_sched;
break;
case AMDGPU_HW_IP_VCN_ENC:
-   for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-   continue;
-   for (k = 0; k < adev->vcn.num_enc_rings; ++k)
-   rings[num_rings++] = 
>vcn.inst[j].ring_enc[k];
-   }
+   scheds = adev->vcn.vcn_enc_sched;
+   num_scheds =  adev->vcn.num_vcn_enc_sched;
break;
case AMDGPU_HW_IP_VCN_JPEG:
-   for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
-   if (adev->vcn.harvest_config & (1 << j))
-  

Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for XGMI

[Andrey Grodzovsky]

Great! I will update the patches to also use the barrier in PSP MODE 1 
reset case and resend the patches for formal review.


Andrey

On 12/11/19 7:18 AM, Ma, Le wrote:


[AMD Official Use Only - Internal Distribution Only]

I tried your new patches to run BACO for about 10 loops and the result 
looks positive, without observing enter/exit baco message failure again.


The time interval between BACO entries or exits in my environment was 
almost less than 10 us: max 36us, min 2us. I think it’s safe enough 
according to the sample data we collected in both sides.


And it looks not necessary to continue using system_highpri_wq any 
more because we require all the nodes enter or exit at the same time, 
while do not mind how long the time interval is b/t enter and exit. 
The system_unbound_wq can satisfy our requirement here since it wakes 
different CPUs up to work at the same time.


Regards,

Ma Le

*From:*Grodzovsky, Andrey 
*Sent:* Wednesday, December 11, 2019 3:56 AM
*To:* Ma, Le ; amd-gfx@lists.freedesktop.org; Zhou1, 
Tao ; Deucher, Alexander 
; Li, Dennis ; Zhang, 
Hawking 

*Cc:* Chen, Guchun 
*Subject:* Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset 
support for XGMI


I switched the workqueue we were using for xgmi_reset_work from 
system_highpri_wq to system_unbound_wq - the difference is that 
workers servicing the queue in system_unbound_wq are not bounded to 
specific CPU and so the reset jobs for each XGMI node are getting 
scheduled to different CPU while system_highpri_wq is a bounded work 
queue. I traced it as bellow for 10 consecutive times and didn't see 
errors any more. Also the time diff between BACO entries or exits was 
never more then around 2 uS.


Please give this updated patchset a try

   kworker/u16:2-57    [004] ...1   243.276312: trace_code: func: 
vega20_baco_set_state, line 91 <- - Before BEACO enter
   <...>-60    [007] ...1   243.276312: trace_code: func: 
vega20_baco_set_state, line 91 <- - Before BEACO enter
   kworker/u16:2-57    [004] ...1   243.276384: trace_code: func: 
vega20_baco_set_state, line 105 <- - After BEACO enter done
   <...>-60    [007] ...1   243.276392: trace_code: func: 
vega20_baco_set_state, line 105 <- - After BEACO enter done
   kworker/u16:3-60    [007] ...1   243.276397: trace_code: func: 
vega20_baco_set_state, line 108 <- - Before BEACO exit
   kworker/u16:2-57    [004] ...1   243.276399: trace_code: func: 
vega20_baco_set_state, line 108 <- - Before BEACO exit
   kworker/u16:3-60    [007] ...1   243.288067: trace_code: func: 
vega20_baco_set_state, line 114 <- - After BEACO exit done
   kworker/u16:2-57    [004] ...1   243.295624: trace_code: func: 
vega20_baco_set_state, line 114 <- - After BEACO exit done


Andrey

On 12/9/19 9:45 PM, Ma, Le wrote:

[AMD Official Use Only - Internal Distribution Only]

I’m fine with your solution if synchronization time interval
satisfies BACO requirements and loop test can pass on XGMI system.

Regards,

Ma Le

*From:*Grodzovsky, Andrey 

*Sent:* Monday, December 9, 2019 11:52 PM
*To:* Ma, Le  ;
amd-gfx@lists.freedesktop.org
; Zhou1, Tao
 ; Deucher, Alexander
 ;
Li, Dennis  ; Zhang,
Hawking  
*Cc:* Chen, Guchun  
*Subject:* Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset
support for XGMI

Thanks a lot Ma for trying - I think I have to have my own system
to debug this so I will keep trying enabling XGMI - i still think
the is the right and the generic solution for multiple nodes reset
synchronization and in fact the barrier should also be used for
synchronizing PSP mode 1 XGMI reset too.

Andrey

On 12/9/19 6:34 AM, Ma, Le wrote:

[AMD Official Use Only - Internal Distribution Only]

Hi Andrey,

I tried your patches on my 2P XGMI platform. The baco can work
at most time, and randomly got following error:

[ 1701.542298] amdgpu: [powerplay] Failed to send message
0x25, response 0x0

This error usually means some sync issue exist for xgmi baco
case. Feel free to debug your patches on my XGMI platform.

Regards,

Ma Le

*From:*Grodzovsky, Andrey 

*Sent:* Saturday, December 7, 2019 5:51 AM
*To:* Ma, Le  ;
amd-gfx@lists.freedesktop.org
; Zhou1, Tao
 ; Deucher,
Alexander 
; Li, Dennis
 ; Zhang, Hawking
 
*Cc:* Chen, Guchun 

Re: [PATCH] drm/amdgpu: wait for all rings to drain before runtime suspending

[Christian König]

Am 11.12.19 um 03:26 schrieb zhoucm1:


On 2019/12/11 上午6:08, Alex Deucher wrote:

Add a safety check to runtime suspend to make sure all outstanding
fences have signaled before we suspend.  Doesn't fix any known issue.

We already do this via the fence driver suspend function, but we
just force completion rather than bailing.  This bails on runtime
suspend so we can try again later once the fences are signaled to
avoid missing any outstanding work.


The idea sounds OK to me, but if you want to drain the rings, you 
should make sure no more submission, right?


So you should park all schedulers before waiting for all outstanding 
fences completed.


At that point userspace should already be put to hold, so no new 
submissions. But it probably won't hurt stopping the scheduler anyway.


But another issue I see is what happens if we locked up the hardware?

Christian.



-David



Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12 +++-
  1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

index 2f367146c72c..81322b0a8acf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1214,13 +1214,23 @@ static int 
amdgpu_pmops_runtime_suspend(struct device *dev)

  struct pci_dev *pdev = to_pci_dev(dev);
  struct drm_device *drm_dev = pci_get_drvdata(pdev);
  struct amdgpu_device *adev = drm_dev->dev_private;
-    int ret;
+    int ret, i;
    if (!adev->runpm) {
  pm_runtime_forbid(dev);
  return -EBUSY;
  }
  +    /* wait for all rings to drain before suspending */
+    for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
+    struct amdgpu_ring *ring = adev->rings[i];
+    if (ring && ring->sched.ready) {
+    ret = amdgpu_fence_wait_empty(ring);
+    if (ret)
+    return -EBUSY;
+    }
+    }
+
  if (amdgpu_device_supports_boco(drm_dev))
  drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  drm_kms_helper_poll_disable(drm_dev);

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Re: [PATCH 4/4] drm/scheduler: do not keep a copy of sched list

[Christian König]

Am 10.12.19 um 19:17 schrieb Nirmoy Das:

entity should not keep copy and maintain sched list for
itself.

Signed-off-by: Nirmoy Das 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/scheduler/sched_entity.c | 19 ---
  1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_entity.c 
b/drivers/gpu/drm/scheduler/sched_entity.c
index f9b6ce29c58f..2e3a058fc239 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -56,8 +56,6 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
  unsigned int num_sched_list,
  atomic_t *guilty)
  {
-   int i;
-
if (!(entity && sched_list && (num_sched_list == 0 || sched_list[0])))
return -EINVAL;
  
@@ -67,22 +65,14 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,

entity->guilty = guilty;
entity->num_sched_list = num_sched_list;
entity->priority = priority;
-   entity->sched_list =  kcalloc(num_sched_list,
- sizeof(struct drm_gpu_scheduler *), 
GFP_KERNEL);
+   entity->sched_list = num_sched_list > 1 ? sched_list : NULL;
+   entity->last_scheduled = NULL;
  
-	if(!entity->sched_list)

-   return -ENOMEM;
+   if(num_sched_list)
+   entity->rq = _list[0]->sched_rq[entity->priority];
  
  	init_completion(>entity_idle);
  
-	for (i = 0; i < num_sched_list; i++)

-   entity->sched_list[i] = sched_list[i];
-
-   if (num_sched_list)
-   entity->rq = >sched_list[0]->sched_rq[entity->priority];
-
-   entity->last_scheduled = NULL;
-
spin_lock_init(>rq_lock);
spsc_queue_init(>job_queue);
  
@@ -312,7 +302,6 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
  
  	dma_fence_put(entity->last_scheduled);

entity->last_scheduled = NULL;
-   kfree(entity->sched_list);
  }
  EXPORT_SYMBOL(drm_sched_entity_fini);
  


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Re: [PATCH 1/2] drm/amdgpu: add invalidate semaphore limit for SRIOV and picasso in gmc9

[Christian König]

Am 11.12.19 um 08:36 schrieb Changfeng.Zhu:

From: changzhu 

It may fail to load guest driver in round 2 or cause Xstart problem
when using invalidate semaphore for SRIOV or picasso. So it needs avoid
using invalidate semaphore for SRIOV and picasso.

Change-Id: I806f8e99ec97be84e6aed0f5c499a53b1931b490
Signed-off-by: changzhu 


Reviewed-by: Christian König  for the series.


---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 44 +++
  1 file changed, 24 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 601667246a1c..efa55e9676be 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -412,6 +412,24 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int 
vmid,
return req;
  }
  
+/**

+ * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
+ *
+ * @adev: amdgpu_device pointer
+ * @vmhub: vmhub type
+ *
+ */
+static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
+  uint32_t vmhub)
+{
+   return ((vmhub == AMDGPU_MMHUB_0 ||
+vmhub == AMDGPU_MMHUB_1) &&
+   (!amdgpu_sriov_vf(adev)) &&
+   (!(adev->asic_type == CHIP_RAVEN &&
+  adev->rev_id < 0x8 &&
+  adev->pdev->device == 0x15d8)));
+}
+
  /*
   * GART
   * VMID 0 is the physical GPU addresses as used by the kernel.
@@ -431,6 +449,7 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int 
vmid,
  static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
uint32_t vmhub, uint32_t flush_type)
  {
+   bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
const unsigned eng = 17;
u32 j, tmp;
struct amdgpu_vmhub *hub;
@@ -464,11 +483,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
 */
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if ((vmhub == AMDGPU_MMHUB_0 ||
-vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8))) {
+   if (use_semaphore) {
for (j = 0; j < adev->usec_timeout; j++) {
/* a read return value of 1 means semaphore acuqire */
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
@@ -498,11 +513,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
}
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if ((vmhub == AMDGPU_MMHUB_0 ||
-vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (use_semaphore)
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
@@ -520,6 +531,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
  static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
unsigned vmid, uint64_t pd_addr)
  {
+   bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, 
ring->funcs->vmhub);
struct amdgpu_device *adev = ring->adev;
struct amdgpu_vmhub *hub = >vmhub[ring->funcs->vmhub];
uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
@@ -533,11 +545,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
 */
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (use_semaphore)
/* a read return value of 1 means semaphore acuqire */
amdgpu_ring_emit_reg_wait(ring,
  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
@@ -553,11 +561,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct 
amdgpu_ring *ring,
req, 1 << vmid);
  
  	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */

-   if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
-ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
-   (!(adev->asic_type == CHIP_RAVEN &&
-  adev->rev_id < 0x8 &&
-  adev->pdev->device == 0x15d8)))
+   if (use_semaphore)
/*
 * add semaphore release after invalidation,
 * write with 0 means semaphore release

RE: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for XGMI

[Ma, Le]

[AMD Official Use Only - Internal Distribution Only]

I tried your new patches to run BACO for about 10 loops and the result looks 
positive, without observing enter/exit baco message failure again.

The time interval between BACO entries or exits in my environment was almost 
less than 10 us: max 36us, min 2us. I think it's safe enough according to the 
sample data we collected in both sides.

And it looks not necessary to continue using system_highpri_wq any more because 
we require all the nodes enter or exit at the same time, while do not mind how 
long the time interval is b/t enter and exit. The system_unbound_wq can satisfy 
our requirement here since it wakes different CPUs up to work at the same time.

Regards,
Ma Le

From: Grodzovsky, Andrey 
Sent: Wednesday, December 11, 2019 3:56 AM
To: Ma, Le ; amd-gfx@lists.freedesktop.org; Zhou1, Tao 
; Deucher, Alexander ; Li, Dennis 
; Zhang, Hawking 
Cc: Chen, Guchun 
Subject: Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for 
XGMI


I switched the workqueue we were using for xgmi_reset_work from 
system_highpri_wq to system_unbound_wq - the difference is that workers 
servicing the queue in system_unbound_wq are not bounded to specific CPU and so 
the reset jobs for each XGMI node are getting scheduled to different CPU while 
system_highpri_wq is a bounded work queue. I traced it as bellow for 10 
consecutive times and didn't see errors any more. Also the time diff between 
BACO entries or exits was never more then around 2 uS.

Please give this updated patchset a try

   kworker/u16:2-57[004] ...1   243.276312: trace_code: func: 
vega20_baco_set_state, line 91 <- - Before BEACO enter
   <...>-60[007] ...1   243.276312: trace_code: func: 
vega20_baco_set_state, line 91 <- - Before BEACO enter
   kworker/u16:2-57[004] ...1   243.276384: trace_code: func: 
vega20_baco_set_state, line 105 <- - After BEACO enter done
   <...>-60[007] ...1   243.276392: trace_code: func: 
vega20_baco_set_state, line 105 <- - After BEACO enter done
   kworker/u16:3-60[007] ...1   243.276397: trace_code: func: 
vega20_baco_set_state, line 108 <- - Before BEACO exit
   kworker/u16:2-57[004] ...1   243.276399: trace_code: func: 
vega20_baco_set_state, line 108 <- - Before BEACO exit
   kworker/u16:3-60[007] ...1   243.288067: trace_code: func: 
vega20_baco_set_state, line 114 <- - After BEACO exit done
   kworker/u16:2-57[004] ...1   243.295624: trace_code: func: 
vega20_baco_set_state, line 114 <- - After BEACO exit done

Andrey
On 12/9/19 9:45 PM, Ma, Le wrote:

[AMD Official Use Only - Internal Distribution Only]

I'm fine with your solution if synchronization time interval satisfies BACO 
requirements and loop test can pass on XGMI system.

Regards,
Ma Le

From: Grodzovsky, Andrey 

Sent: Monday, December 9, 2019 11:52 PM
To: Ma, Le ; 
amd-gfx@lists.freedesktop.org; Zhou1, Tao 
; Deucher, Alexander 
; Li, Dennis 
; Zhang, Hawking 

Cc: Chen, Guchun 
Subject: Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for 
XGMI


Thanks a lot Ma for trying - I think I have to have my own system to debug this 
so I will keep trying enabling XGMI - i still think the is the right and the 
generic solution for multiple nodes reset synchronization and in fact the 
barrier should also be used for synchronizing PSP mode 1 XGMI reset too.

Andrey
On 12/9/19 6:34 AM, Ma, Le wrote:

[AMD Official Use Only - Internal Distribution Only]

Hi Andrey,

I tried your patches on my 2P XGMI platform. The baco can work at most time, 
and randomly got following error:
[ 1701.542298] amdgpu: [powerplay] Failed to send message 0x25, response 0x0

This error usually means some sync issue exist for xgmi baco case. Feel free to 
debug your patches on my XGMI platform.

Regards,
Ma Le

From: Grodzovsky, Andrey 

Sent: Saturday, December 7, 2019 5:51 AM
To: Ma, Le ; 
amd-gfx@lists.freedesktop.org; Zhou1, Tao 
; Deucher, Alexander 
; Li, Dennis 
; Zhang, Hawking 

Cc: Chen, Guchun 
Subject: Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for 
XGMI


Hey Ma, attached a solution - it's just compiled as I still can't make my XGMI 
setup work (with bridge connected only one device is visible to the system 
while the other is not). Please try it on your system if you have a chance.

Andrey
On 12/4/19 10:14 PM, Ma, Le wrote:

AFAIK it's enough for even single one node in the hive to to fail the enter the 
BACO state on time to 

RE: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14

[Xu, Feifei]

Series is Reviewed-by: Feifei Xu 

-Original Message-
From: Tianci Yin  
Sent: Wednesday, December 11, 2019 8:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ; 
Yuan, Xiaojie ; Long, Gang ; Li, 
Pauline ; Yin, Tianci (Rico) 
Subject: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14

From: "Tianci.Yin" 

add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2

Change-Id: I1fc3fb481b2d9edc482a32497242a8be6cd6b8d7
Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index e5637a6efb05..8cdef79de9d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -162,8 +162,10 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x0fff, 
0x1100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0x, 0x1402002f),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xbfff, 0x0188),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 
0x, 0x0800),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fff, 0x0809),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x0040, 
0x0444),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x0800, 
0x0820),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, 
0x00070105),
-- 
2.17.1

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[PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings

[Tianci Yin]

From: "Tianci.Yin" 

add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2

Change-Id: I23dabb0e706af0b5376f9749200832e894944eca
Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d1e0a07060bd..e5637a6efb05 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -114,8 +114,10 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x1000, 
0x1100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0x, 0x1402002f),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x9fff, 0x1188),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 
0x, 0x0800),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fff, 0x0809),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x0040, 
0x0444),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x0800, 
0x0820),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, 
0x00070104),
-- 
2.17.1

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[PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14

[Tianci Yin]

From: "Tianci.Yin" 

add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2

Change-Id: I1fc3fb481b2d9edc482a32497242a8be6cd6b8d7
Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index e5637a6efb05..8cdef79de9d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -162,8 +162,10 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x0fff, 
0x1100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0x, 0x1402002f),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xbfff, 0x0188),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 
0x, 0x0800),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fff, 0x0809),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x0040, 
0x0444),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x0800, 
0x0820),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f, 
0x00070105),
-- 
2.17.1

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[PATCH] drm/amdgpu: log when amdgpu.dc=1 but ASIC is unsupported

[Simon Ser]

This makes it easier to figure out whether the kernel parameter has been
taken into account.

Signed-off-by: Simon Ser 
Cc: Harry Wentland 
Cc: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7a6c837c0a85..10618353383f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2525,6 +2525,9 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type 
asic_type)
return amdgpu_dc != 0;
 #endif
default:
+   if (amdgpu_dc > 0)
+   DRM_INFO("Display Core has been requested via kernel 
parameter "
+"but isn't supported by ASIC, 
ignoring\n");
return false;
}
 }
--
2.24.0


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