[PATCH 1/1] register refresh to add mmGC_CAC_INDEX_AUTO_INCR_EN

[raykwok1150]

From: Guo Lei 

sync form drm-next

Signed-off-by: Guo Lei 
---
 src/lib/ip/gfx90_bits.i | 7 ++-
 src/lib/ip/gfx90_regs.i | 2 +-
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/lib/ip/gfx90_bits.i b/src/lib/ip/gfx90_bits.i
index 6741947..8aabb8a 100644
--- a/src/lib/ip/gfx90_bits.i
+++ b/src/lib/ip/gfx90_bits.i
@@ -8711,11 +8711,8 @@ static struct umr_bitfield mmGC_CAC_CTRL_2[] = {
 { "CAC_SOFT_CTRL_ENABLE", 1, 1, _bitfield_default },
 { "UNUSED_0", 2, 31, _bitfield_default },
 };
-static struct umr_bitfield mmGC_CAC_CGTT_CLK_CTRL[] = {
-{ "ON_DELAY", 0, 3, _bitfield_default },
-{ "OFF_HYSTERESIS", 4, 11, _bitfield_default },
-{ "SOFT_OVERRIDE_DYN", 30, 30, _bitfield_default },
-{ "SOFT_OVERRIDE_REG", 31, 31, _bitfield_default },
+static struct umr_bitfield mmGC_CAC_INDEX_AUTO_INCR_EN[] = {
+{ "GC_CAC_INDEX_AUTO_INCR_EN", 0, 0, _bitfield_default },
 };
 static struct umr_bitfield mmGC_CAC_AGGR_LOWER[] = {
 { "AGGR_31_0", 0, 31, _bitfield_default },
diff --git a/src/lib/ip/gfx90_regs.i b/src/lib/ip/gfx90_regs.i
index 1342a66..a9ef9c6 100644
--- a/src/lib/ip/gfx90_regs.i
+++ b/src/lib/ip/gfx90_regs.i
@@ -1418,7 +1418,7 @@
{ "mmDIDT_IND_DATA", REG_MMIO, 0x1281, 0, _IND_DATA[0], 
sizeof(mmDIDT_IND_DATA)/sizeof(mmDIDT_IND_DATA[0]), 0, 0 },
{ "mmGC_CAC_CTRL_1", REG_MMIO, 0x1284, 0, _CAC_CTRL_1[0], 
sizeof(mmGC_CAC_CTRL_1)/sizeof(mmGC_CAC_CTRL_1[0]), 0, 0 },
{ "mmGC_CAC_CTRL_2", REG_MMIO, 0x1285, 0, _CAC_CTRL_2[0], 
sizeof(mmGC_CAC_CTRL_2)/sizeof(mmGC_CAC_CTRL_2[0]), 0, 0 },
-   { "mmGC_CAC_CGTT_CLK_CTRL", REG_MMIO, 0x1286, 0, 
_CAC_CGTT_CLK_CTRL[0], 
sizeof(mmGC_CAC_CGTT_CLK_CTRL)/sizeof(mmGC_CAC_CGTT_CLK_CTRL[0]), 0, 0 },
+   { "mmGC_CAC_INDEX_AUTO_INCR_EN", REG_MMIO, 0x1286, 0, 
_CAC_INDEX_AUTO_INCR_EN[0], 
sizeof(mmGC_CAC_INDEX_AUTO_INCR_EN)/sizeof(mmGC_CAC_INDEX_AUTO_INCR_EN[0]), 0, 
0 },
{ "mmGC_CAC_AGGR_LOWER", REG_MMIO, 0x1287, 0, _CAC_AGGR_LOWER[0], 
sizeof(mmGC_CAC_AGGR_LOWER)/sizeof(mmGC_CAC_AGGR_LOWER[0]), 0, 0 },
{ "mmGC_CAC_AGGR_UPPER", REG_MMIO, 0x1288, 0, _CAC_AGGR_UPPER[0], 
sizeof(mmGC_CAC_AGGR_UPPER)/sizeof(mmGC_CAC_AGGR_UPPER[0]), 0, 0 },
{ "mmGC_CAC_SOFT_CTRL", REG_MMIO, 0x128d, 0, _CAC_SOFT_CTRL[0], 
sizeof(mmGC_CAC_SOFT_CTRL)/sizeof(mmGC_CAC_SOFT_CTRL[0]), 0, 0 },
-- 
2.17.1


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Re: [PATCH 2/2] drm/amd/display: Fix HDMI deep color output for DCE 6-11.

[Mario Kleiner]

Thanks Alex and Nicholas! Brings quite a bit of extra shiny to those older
asics :)

Nicholas, any thoughts on my cover-letter wrt. why a similar patch (that I
wrote and tested to no good or bad effect) not seem to be needed on DCN,
and probably not DCE-11.2+ either? Is what is left in DC for those asic's
just dead code? My Atombios disassembly sort of pointed into that
direction, but reading disassembly is not easy on the brain, and my brain
was getting quite mushy towards the end of digging through all the code. So
some official statement would add peace of mind on my side. Is there a
certain DCE version at which your team starts validating output precision /
HDR etc. on hw?

Thanks,
-mario


On Mon, Jan 25, 2021 at 8:16 PM Kazlauskas, Nicholas <
nicholas.kazlaus...@amd.com> wrote:

> On 2021-01-25 12:57 p.m., Alex Deucher wrote:
> > On Thu, Jan 21, 2021 at 1:17 AM Mario Kleiner
> >  wrote:
> >>
> >> This fixes corrupted display output in HDMI deep color
> >> 10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3.
> >>
> >> It will hopefully also provide fixes for other DCE's up to
> >> DCE-11, assuming those will need similar fixes, but i could
> >> not test that for HDMI due to lack of suitable hw, so viewer
> >> discretion is advised.
> >>
> >> dce110_stream_encoder_hdmi_set_stream_attribute() is used for
> >> HDMI setup on all DCE's and is missing color_depth assignment.
> >>
> >> dce110_program_pix_clk() is used for pixel clock setup on HDMI
> >> for DCE 6-11, and is missing color_depth assignment.
> >>
> >> Additionally some of the underlying Atombios specific encoder
> >> and pixelclock setup functions are missing code which is in
> >> the classic amdgpu kms modesetting path and the in the radeon
> >> kms driver for DCE6/DCE8.
> >>
> >> encoder_control_digx_v3() - Was missing setup code wrt. amdgpu
> >> and radeon kms classic drivers. Added here, but untested due to
> >> lack of suitable test hw.
> >>
> >> encoder_control_digx_v4() - Added missing setup code.
> >> Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color
> >> output at 10 bpc and 12 bpc.
> >>
> >> Note that encoder_control_digx_v5() has proper setup code in place
> >> and is used, e.g., by DCE-11.2, but this code wasn't used for deep
> >> color setup due to the missing cntl.color_depth setup in the calling
> >> function for HDMI.
> >>
> >> set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon
> >> kms. Added here, but untested due to lack of hw.
> >>
> >> set_pixel_clock_v6() - Missing setup code added. Successfully tested
> >> on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI
> >> deep color output with 10 bpc or 12 bpc.
> >>
> >> Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
> >>
> >> Signed-off-by: Mario Kleiner 
> >> Cc: Harry Wentland 
> >
> > These make sense. I've applied the series.  I'll let the display guys
> > gauge the other points in your cover letter.
> >
> > Alex
>
> I don't have any concerns with this patch.
>
> Even though it's already applied feel free to have my:
>
> Reviewed-by: Nicholas Kazlauskas 
>
> Regards,
> Nicholas Kazlauskas
>
> >
> >
> >> ---
> >>   .../drm/amd/display/dc/bios/command_table.c   | 61 +++
> >>   .../drm/amd/display/dc/dce/dce_clock_source.c | 14 +
> >>   .../amd/display/dc/dce/dce_stream_encoder.c   |  1 +
> >>   3 files changed, 76 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> >> index 070459e3e407..afc10b954ffa 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> >> @@ -245,6 +245,23 @@ static enum bp_result encoder_control_digx_v3(
> >>  cntl->enable_dp_audio);
> >>  params.ucLaneNum = (uint8_t)(cntl->lanes_number);
> >>
> >> +   switch (cntl->color_depth) {
> >> +   case COLOR_DEPTH_888:
> >> +   params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
> >> +   break;
> >> +   case COLOR_DEPTH_101010:
> >> +   params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
> >> +   break;
> >> +   case COLOR_DEPTH_121212:
> >> +   params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
> >> +   break;
> >> +   case COLOR_DEPTH_161616:
> >> +   params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
> >> +   break;
> >> +   default:
> >> +   break;
> >> +   }
> >> +
> >>  if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
> >>  result = BP_RESULT_OK;
> >>
> >> @@ -274,6 +291,23 @@ static enum bp_result encoder_control_digx_v4(
> >>  cntl->enable_dp_audio));
> >>  params.ucLaneNum = (uint8_t)(cntl->lanes_number);
> >>
> >> +   switch (cntl->color_depth) {
> >> +   case COLOR_DEPTH_888:
> >> +   

Re: [PATCH 2/2] drm/amd/display: Fix HDMI deep color output for DCE 6-11.

[Kazlauskas, Nicholas]

On 2021-01-25 12:57 p.m., Alex Deucher wrote:

On Thu, Jan 21, 2021 at 1:17 AM Mario Kleiner
 wrote:


This fixes corrupted display output in HDMI deep color
10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3.

It will hopefully also provide fixes for other DCE's up to
DCE-11, assuming those will need similar fixes, but i could
not test that for HDMI due to lack of suitable hw, so viewer
discretion is advised.

dce110_stream_encoder_hdmi_set_stream_attribute() is used for
HDMI setup on all DCE's and is missing color_depth assignment.

dce110_program_pix_clk() is used for pixel clock setup on HDMI
for DCE 6-11, and is missing color_depth assignment.

Additionally some of the underlying Atombios specific encoder
and pixelclock setup functions are missing code which is in
the classic amdgpu kms modesetting path and the in the radeon
kms driver for DCE6/DCE8.

encoder_control_digx_v3() - Was missing setup code wrt. amdgpu
and radeon kms classic drivers. Added here, but untested due to
lack of suitable test hw.

encoder_control_digx_v4() - Added missing setup code.
Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color
output at 10 bpc and 12 bpc.

Note that encoder_control_digx_v5() has proper setup code in place
and is used, e.g., by DCE-11.2, but this code wasn't used for deep
color setup due to the missing cntl.color_depth setup in the calling
function for HDMI.

set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon
kms. Added here, but untested due to lack of hw.

set_pixel_clock_v6() - Missing setup code added. Successfully tested
on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI
deep color output with 10 bpc or 12 bpc.

Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")

Signed-off-by: Mario Kleiner 
Cc: Harry Wentland 


These make sense. I've applied the series.  I'll let the display guys
gauge the other points in your cover letter.

Alex


I don't have any concerns with this patch.

Even though it's already applied feel free to have my:

Reviewed-by: Nicholas Kazlauskas 

Regards,
Nicholas Kazlauskas





---
  .../drm/amd/display/dc/bios/command_table.c   | 61 +++
  .../drm/amd/display/dc/dce/dce_clock_source.c | 14 +
  .../amd/display/dc/dce/dce_stream_encoder.c   |  1 +
  3 files changed, 76 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 070459e3e407..afc10b954ffa 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -245,6 +245,23 @@ static enum bp_result encoder_control_digx_v3(
 cntl->enable_dp_audio);
 params.ucLaneNum = (uint8_t)(cntl->lanes_number);

+   switch (cntl->color_depth) {
+   case COLOR_DEPTH_888:
+   params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+   break;
+   case COLOR_DEPTH_101010:
+   params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
+   break;
+   case COLOR_DEPTH_121212:
+   params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
+   break;
+   case COLOR_DEPTH_161616:
+   params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
+   break;
+   default:
+   break;
+   }
+
 if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
 result = BP_RESULT_OK;

@@ -274,6 +291,23 @@ static enum bp_result encoder_control_digx_v4(
 cntl->enable_dp_audio));
 params.ucLaneNum = (uint8_t)(cntl->lanes_number);

+   switch (cntl->color_depth) {
+   case COLOR_DEPTH_888:
+   params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+   break;
+   case COLOR_DEPTH_101010:
+   params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
+   break;
+   case COLOR_DEPTH_121212:
+   params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
+   break;
+   case COLOR_DEPTH_161616:
+   params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
+   break;
+   default:
+   break;
+   }
+
 if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
 result = BP_RESULT_OK;

@@ -1057,6 +1091,19 @@ static enum bp_result set_pixel_clock_v5(
  * driver choose program it itself, i.e. here we program it
  * to 888 by default.
  */
+   if (bp_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
+   switch (bp_params->color_depth) {
+   case TRANSMITTER_COLOR_DEPTH_30:
+   /* yes this is correct, the atom define is 
wrong */
+   clk.sPCLKInput.ucMiscInfo |= 
PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
+   break;
+   case TRANSMITTER_COLOR_DEPTH_36:
+

Re: [PATCH 2/2] drm/amd/display: Fix HDMI deep color output for DCE 6-11.

[Alex Deucher]

On Thu, Jan 21, 2021 at 1:17 AM Mario Kleiner
 wrote:
>
> This fixes corrupted display output in HDMI deep color
> 10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3.
>
> It will hopefully also provide fixes for other DCE's up to
> DCE-11, assuming those will need similar fixes, but i could
> not test that for HDMI due to lack of suitable hw, so viewer
> discretion is advised.
>
> dce110_stream_encoder_hdmi_set_stream_attribute() is used for
> HDMI setup on all DCE's and is missing color_depth assignment.
>
> dce110_program_pix_clk() is used for pixel clock setup on HDMI
> for DCE 6-11, and is missing color_depth assignment.
>
> Additionally some of the underlying Atombios specific encoder
> and pixelclock setup functions are missing code which is in
> the classic amdgpu kms modesetting path and the in the radeon
> kms driver for DCE6/DCE8.
>
> encoder_control_digx_v3() - Was missing setup code wrt. amdgpu
> and radeon kms classic drivers. Added here, but untested due to
> lack of suitable test hw.
>
> encoder_control_digx_v4() - Added missing setup code.
> Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color
> output at 10 bpc and 12 bpc.
>
> Note that encoder_control_digx_v5() has proper setup code in place
> and is used, e.g., by DCE-11.2, but this code wasn't used for deep
> color setup due to the missing cntl.color_depth setup in the calling
> function for HDMI.
>
> set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon
> kms. Added here, but untested due to lack of hw.
>
> set_pixel_clock_v6() - Missing setup code added. Successfully tested
> on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI
> deep color output with 10 bpc or 12 bpc.
>
> Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
>
> Signed-off-by: Mario Kleiner 
> Cc: Harry Wentland 

These make sense. I've applied the series.  I'll let the display guys
gauge the other points in your cover letter.

Alex


> ---
>  .../drm/amd/display/dc/bios/command_table.c   | 61 +++
>  .../drm/amd/display/dc/dce/dce_clock_source.c | 14 +
>  .../amd/display/dc/dce/dce_stream_encoder.c   |  1 +
>  3 files changed, 76 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c 
> b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> index 070459e3e407..afc10b954ffa 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> @@ -245,6 +245,23 @@ static enum bp_result encoder_control_digx_v3(
> cntl->enable_dp_audio);
> params.ucLaneNum = (uint8_t)(cntl->lanes_number);
>
> +   switch (cntl->color_depth) {
> +   case COLOR_DEPTH_888:
> +   params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
> +   break;
> +   case COLOR_DEPTH_101010:
> +   params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
> +   break;
> +   case COLOR_DEPTH_121212:
> +   params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
> +   break;
> +   case COLOR_DEPTH_161616:
> +   params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
> +   break;
> +   default:
> +   break;
> +   }
> +
> if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
> result = BP_RESULT_OK;
>
> @@ -274,6 +291,23 @@ static enum bp_result encoder_control_digx_v4(
> cntl->enable_dp_audio));
> params.ucLaneNum = (uint8_t)(cntl->lanes_number);
>
> +   switch (cntl->color_depth) {
> +   case COLOR_DEPTH_888:
> +   params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
> +   break;
> +   case COLOR_DEPTH_101010:
> +   params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
> +   break;
> +   case COLOR_DEPTH_121212:
> +   params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
> +   break;
> +   case COLOR_DEPTH_161616:
> +   params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
> +   break;
> +   default:
> +   break;
> +   }
> +
> if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
> result = BP_RESULT_OK;
>
> @@ -1057,6 +1091,19 @@ static enum bp_result set_pixel_clock_v5(
>  * driver choose program it itself, i.e. here we program it
>  * to 888 by default.
>  */
> +   if (bp_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
> +   switch (bp_params->color_depth) {
> +   case TRANSMITTER_COLOR_DEPTH_30:
> +   /* yes this is correct, the atom define is 
> wrong */
> +   clk.sPCLKInput.ucMiscInfo |= 
> PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
> +   break;
> +   case TRANSMITTER_COLOR_DEPTH_36:
> + 

Re: [PATCH] amdgpu: fix clang build warning

[Alex Deucher]

On Mon, Jan 25, 2021 at 7:24 AM Arnd Bergmann  wrote:
>
> From: Arnd Bergmann 
>
> clang warns about the -mhard-float command line arguments
> on architectures that do not support this:
>
> clang: error: argument unused during compilation: '-mhard-float' 
> [-Werror,-Wunused-command-line-argument]
>
> Move this into the gcc-specific arguments.
>
> Fixes: e77165bf7b02 ("drm/amd/display: Add DCN3 blocks to Makefile")
> Signed-off-by: Arnd Bergmann 

Applied.  Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/dcn30/Makefile  | 6 --
>  drivers/gpu/drm/amd/display/dc/dcn301/Makefile | 3 ++-
>  drivers/gpu/drm/amd/display/dc/dcn302/Makefile | 3 ++-
>  3 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile 
> b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
> index c20331eb62e0..dfd77b3cc84d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
> @@ -32,8 +32,8 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o 
> dcn30_dpp.o dcn30_optc.o \
>
>
>  ifdef CONFIG_X86
> -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse
> -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse
> +CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -msse
> +CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -msse
>  endif
>
>  ifdef CONFIG_PPC64
> @@ -45,6 +45,8 @@ ifdef CONFIG_CC_IS_GCC
>  ifeq ($(call cc-ifversion, -lt, 0701, y), y)
>  IS_OLD_GCC = 1
>  endif
> +CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -mhard-float
> +CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -mhard-float
>  endif
>
>  ifdef CONFIG_X86
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile 
> b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
> index 3ca7d911d25c..09264716d1dc 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
> @@ -14,7 +14,7 @@ DCN301 = dcn301_init.o dcn301_resource.o dcn301_dccg.o \
> dcn301_dio_link_encoder.o dcn301_hwseq.o dcn301_panel_cntl.o 
> dcn301_hubbub.o
>
>  ifdef CONFIG_X86
> -CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -mhard-float -msse
> +CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -msse
>  endif
>
>  ifdef CONFIG_PPC64
> @@ -25,6 +25,7 @@ ifdef CONFIG_CC_IS_GCC
>  ifeq ($(call cc-ifversion, -lt, 0701, y), y)
>  IS_OLD_GCC = 1
>  endif
> +CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o += -mhard-float
>  endif
>
>  ifdef CONFIG_X86
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile 
> b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
> index 8d4924b7dc22..101620a8867a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
> @@ -13,7 +13,7 @@
>  DCN3_02 = dcn302_init.o dcn302_hwseq.o dcn302_resource.o
>
>  ifdef CONFIG_X86
> -CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -msse
> +CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -msse
>  endif
>
>  ifdef CONFIG_PPC64
> @@ -24,6 +24,7 @@ ifdef CONFIG_CC_IS_GCC
>  ifeq ($(call cc-ifversion, -lt, 0701, y), y)
>  IS_OLD_GCC = 1
>  endif
> +CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o += -mhard-float
>  endif
>
>  ifdef CONFIG_X86
> --
> 2.29.2
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH] drm/amdgpu: fix bitwise vs logical negate

[Alex Deucher]

On Mon, Jan 25, 2021 at 3:46 AM Dan Carpenter  wrote:
>
> There was a mixup between logical and bitwise negate so it just sets
> "data1" and "data2" to zero.
>
> Fixes: 3c9a7b7d6e75 ("drm/amdgpu: update mmhub mgcg for mmhub_v2_3")
> Signed-off-by: Dan Carpenter 

Someone else sent the same fix last week.  Applied that one.

Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c 
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> index 1961745e89c7..ab9be5ad5a5f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> @@ -531,12 +531,12 @@ mmhub_v2_3_update_medium_grain_light_sleep(struct 
> amdgpu_device *adev,
>
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
> data &= ~MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;
> -   data1 &= !(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> +   data1 &= ~(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
> DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
> -   data2 &= !(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> +   data2 &= ~(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
> DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
> --
> 2.29.2
>
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Re: [PATCH] drm/amd/display: Fix a potential NULL dereference

[Alex Deucher]

On Mon, Jan 25, 2021 at 3:47 AM Dan Carpenter  wrote:
>
> The debug printk dereferences "link->link_enc" before we have ensured
> that it is non-NULL.  Fix this potential NULL derefence by moving the
> printk after the check.
>
> Fixes: 1975b95ad4e7 ("drm/amd/display: Log link/connector info provided in 
> BIOS object table")
> Signed-off-by: Dan Carpenter 

Applied.  Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index c16af3983fdb..4d31b2fae1f9 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -1525,13 +1525,13 @@ static bool dc_link_construct(struct dc_link *link,
> link->link_enc =
> link->dc->res_pool->funcs->link_enc_create(_init_data);
>
> -   DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", 
> link->link_enc->features.flags.bits.DP_IS_USB_C);
> -
> if (!link->link_enc) {
> DC_ERROR("Failed to create link encoder!\n");
> goto link_enc_create_fail;
> }
>
> +   DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", 
> link->link_enc->features.flags.bits.DP_IS_USB_C);
> +
> link->link_enc_hw_inst = link->link_enc->transmitter;
>
> for (i = 0; i < 4; i++) {
> --
> 2.29.2
>
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Re: [PATCH] drm/amd/display: change license of color_table.c

[Alex Deucher]

On Mon, Jan 25, 2021 at 7:07 AM Jonathan Gray  wrote:
>
> This still needs to be corrected.

Applied.  Thanks!

Alex

>
> On Thu, Nov 19, 2020 at 01:30:41PM +1100, Jonathan Gray wrote:
> > Change the license of color_table.c to match color_table.h granting
> > permission to modify and distribute.
> >
> > Signed-off-by: Jonathan Gray 
> > ---
> >  .../amd/display/modules/color/color_table.c   | 26 +++
> >  1 file changed, 21 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/modules/color/color_table.c 
> > b/drivers/gpu/drm/amd/display/modules/color/color_table.c
> > index 692e536e7d05..410f2a82b9a2 100644
> > --- a/drivers/gpu/drm/amd/display/modules/color/color_table.c
> > +++ b/drivers/gpu/drm/amd/display/modules/color/color_table.c
> > @@ -1,10 +1,26 @@
> >  /*
> > - * Copyright (c) 2019 Advanced Micro Devices, Inc. (unpublished)
> > + * Copyright 2019 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the 
> > "Software"),
> > + * to deal in the Software without restriction, including without 
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included 
> > in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
> > OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> >   *
> > - * All rights reserved.  This notice is intended as a precaution against
> > - * inadvertent publication and does not imply publication or any waiver
> > - * of confidentiality.  The year included in the foregoing notice is the
> > - * year of creation of the work.
> >   */
> >
> >  #include "color_table.h"
> > --
> > 2.29.2
> >
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Re: [PATCH] drm/amd/display: fix unused variable warning

[Harry Wentland]

On 2021-01-25 7:48 a.m., Arnd Bergmann wrote:

From: Arnd Bergmann 

After all users of the 'dm' warnings got hidden in an #ifdef,
the compiler started warning about it being unused:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5380:33: error: 
unused variable 'dm' [-Werror,-Wunused-variable]

Add another such #ifdef.

Fixes: 98ab5f3513f9 ("drm/amd/display: Fix deadlock during gpu reset v3")
Signed-off-by: Arnd Bergmann 


Reviewed-by: Harry Wentland 

Harry


---
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a90dc4d31c32..37bf2dd87e1e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5377,7 +5377,9 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, 
bool enable)
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
+#if defined(CONFIG_DRM_AMD_DC_DCN)
struct amdgpu_display_manager *dm = >dm;
+#endif
int rc = 0;
  
  	if (enable) {



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Re: [RFC 0/7] Proposal for isolating FPU operation

[Christian König]

Hi Rodrigo,

good to see this finally be tackled. The whole approach looks solid to 
me, just one things I've noted.



+void dcn3x_populate_dml_writeback_from_context(struct dc *dc,
+   struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
+{
+   DC_FP_START();
+   _dcn3x_populate_dml_writeback_from_context(dc, res_ctx, pipes);
+   DC_FP_END();
+}


The calls to DC_FP_START()/DC_FP_END() must be outside of the 
fpu_operation directory.


The problem is that even before the call to DC_FP_START() the compiler 
might think it is a good idea to use FP registers for spilling on some 
architectures.


So my understanding is that all calls of functions declared inside the 
fpu_operation directory must be made with DC_FP_START()/DC_FP_END() in 
the calleing and not the called function.


Regards,
Christian.

Am 25.01.21 um 14:43 schrieb Rodrigo Siqueira:

Hi,

In the display core, we utilize floats and doubles units for calculating
modesetting parameters. One side effect of our approach to use double-precision
is the fact that we spread multiple FPU access across our driver, which means
that we can accidentally clobber user space FPU state. As an attempt to fix
this problem, we have the following proposal:

1. We first need to move functions that deal with FPU to a single place in
order to make things more manageable;
2. After we isolate these function in a single place, we want to remove any
compilation flag that deals with FPU from other files and centralize it only
in the files that need it;
3. We need to implement an interface for safely calling those FPU functions.
The idea is to add a thin function layer where FPU functions are invoked
under the protection of kernel_fpu_begin/end.

One of the challenges from the above steps is identifying which function uses
FPU registers; fortunately, Peter Zijlstra wrote a patch a couple of months ago
where he introduced an FPU check for objtool. I used the following command for
identifying the potential FPU usage:

  ./tools/objtool/objtool check -Ffa "drivers/gpu/drm/amd/display/dc/ANY_FILE.o"

Based on the above command output and the step-by-step approach that we want to
adopt, I decided to start this work focusing on DCN3 and DCN302. I believe that
the best way to see this RFC is:

1. The first patch introduces an FPU folder inside display/dc, intending to
centralize functions that deal with FPU. Note that I introduced two new C
files named dcn3x_commons inside a new folder called fpu_operation; I used
the name dcn3x because some of the functions inside this folder are shared
with DCN301 and DCN302. In other words, all FPU function which is shared
across DCN3x will be placed in that file.
2. The next set of patches, start to move some of the function that requires
FPU access to the file dcn3x_commons. I did it in a small chunk to make it
easy to bisect in case of regressions.
3. Note that one of the patch touch DCN2, the reason for that is the fact that
the function dcn20_calculate_dlg_params is shared from DCN2 to DCN3. Because
of that, I create a new file named fpu_commons for keeping functions that
are shared across multiple ASICs.
4. When we move some of the functions, notice that I also add an API for
accessing it via fpu_kernel_begin/end.
5. At the end of the series, I dropped the FPU flags from the files that I
initialize refactored.

We are also working on test stress for validating this change from the user
space and kernel perspective.

Keep in mind that this series is not done yet. I'm looking for feedback about
this approach because we have plans to use it for trying to fix our FPU
problems for the next couple of weeks. Finally, we want to do this work
step-by-step because it is easy to introduce regression when dealing with these
FPU problems.

Best Regards

Rodrigo Siqueira (7):
   drm/amd/display: Introduce FPU directory inside DC
   drm/amd/display: Moves dcn30_set_mcif_arb_params to FPU folder
   drm/amd/display: Add FPU file for functions shared across ASICs
   drm/amd/display: Move calculate_wm_and_dlg to FPU folder
   drm/amd/display: Move patch bounding box to FPU folder
   drm/amd/display: Move bounding box functions to FPU folder
   drm/amd/display: Drop float flages from DCN30 files

  drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
  .../drm/amd/display/dc/dcn20/dcn20_resource.c | 106 +--
  .../drm/amd/display/dc/dcn20/dcn20_resource.h |   8 -
  .../drm/amd/display/dc/dcn21/dcn21_resource.c |   2 +
  drivers/gpu/drm/amd/display/dc/dcn30/Makefile |  30 -
  .../drm/amd/display/dc/dcn30/dcn30_resource.c | 683 +---
  .../drm/amd/display/dc/dcn30/dcn30_resource.h |  20 -
  .../amd/display/dc/dcn301/dcn301_resource.c   |  10 +-
  .../gpu/drm/amd/display/dc/dcn302/Makefile|  25 -
  .../amd/display/dc/dcn302/dcn302_resource.c   |  10 +-
  .../drm/amd/display/dc/fpu_operation/Makefile |  58 ++
  

Re: [PATCH v4 01/14] drm/ttm: Remap all page faults to per process dummy page.

[Andrey Grodzovsky]

On 1/19/21 8:56 AM, Daniel Vetter wrote:

On Mon, Jan 18, 2021 at 04:01:10PM -0500, Andrey Grodzovsky wrote:

On device removal reroute all CPU mappings to dummy page.

v3:
Remove loop to find DRM file and instead access it
by vma->vm_file->private_data. Move dummy page installation
into a separate function.

v4:
Map the entire BOs VA space into on demand allocated dummy page
on the first fault for that BO.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/ttm/ttm_bo_vm.c | 82 -
  include/drm/ttm/ttm_bo_api.h|  2 +
  2 files changed, 83 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index 6dc96cf..ed89da3 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -34,6 +34,8 @@
  #include 
  #include 
  #include 
+#include 
+#include 
  #include 
  #include 
  #include 
@@ -380,25 +382,103 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf,
  }
  EXPORT_SYMBOL(ttm_bo_vm_fault_reserved);
  
+static void ttm_bo_release_dummy_page(struct drm_device *dev, void *res)

+{
+   struct page *dummy_page = (struct page *)res;
+
+   __free_page(dummy_page);
+}
+
+vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot)
+{
+   struct vm_area_struct *vma = vmf->vma;
+   struct ttm_buffer_object *bo = vma->vm_private_data;
+   struct ttm_bo_device *bdev = bo->bdev;
+   struct drm_device *ddev = bo->base.dev;
+   vm_fault_t ret = VM_FAULT_NOPAGE;
+   unsigned long address = vma->vm_start;
+   unsigned long num_prefault = (vma->vm_end - vma->vm_start) >> 
PAGE_SHIFT;
+   unsigned long pfn;
+   struct page *page;
+   int i;
+
+   /*
+* Wait for buffer data in transit, due to a pipelined
+* move.
+*/
+   ret = ttm_bo_vm_fault_idle(bo, vmf);
+   if (unlikely(ret != 0))
+   return ret;
+
+   /* Allocate new dummy page to map all the VA range in this VMA to it*/
+   page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+   if (!page)
+   return VM_FAULT_OOM;
+
+   pfn = page_to_pfn(page);
+
+   /*
+* Prefault the entire VMA range right away to avoid further faults
+*/
+   for (i = 0; i < num_prefault; ++i) {
+
+   if (unlikely(address >= vma->vm_end))
+   break;
+
+   if (vma->vm_flags & VM_MIXEDMAP)
+   ret = vmf_insert_mixed_prot(vma, address,
+   __pfn_to_pfn_t(pfn, 
PFN_DEV),
+   prot);
+   else
+   ret = vmf_insert_pfn_prot(vma, address, pfn, prot);
+
+   /* Never error on prefaulted PTEs */
+   if (unlikely((ret & VM_FAULT_ERROR))) {
+   if (i == 0)
+   return VM_FAULT_NOPAGE;
+   else
+   break;
+   }
+
+   address += PAGE_SIZE;
+   }
+
+   /* Set the page to be freed using drmm release action */
+   if (drmm_add_action_or_reset(ddev, ttm_bo_release_dummy_page, page))
+   return VM_FAULT_OOM;
+
+   return ret;
+}
+EXPORT_SYMBOL(ttm_bo_vm_dummy_page);

I think we can lift this entire thing (once the ttm_bo_vm_fault_idle is
gone) to the drm level, since nothing ttm specific in here. Probably stuff
it into drm_gem.c (but really it's not even gem specific, it's fully
generic "replace this vma with dummy pages pls" function.



Once I started with this I noticed that drmm_add_action_or_reset depends
on struct drm_device *ddev = bo->base.dev  and bo is the private data
we embed at the TTM level when setting up the mapping and so this forces
to move drmm_add_action_or_reset out of this function to every client who uses
this function, and then you separate the logic of page allocation from it's 
release.
So I suggest we keep it as is.

Andrey




Aside from this nit I think the overall approach you have here is starting
to look good. Lots of work, but imo we're getting there and can
start landing stuff soon.
-Daniel


+
  vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
  {
struct vm_area_struct *vma = vmf->vma;
pgprot_t prot;
struct ttm_buffer_object *bo = vma->vm_private_data;
+   struct drm_device *ddev = bo->base.dev;
vm_fault_t ret;
+   int idx;
  
  	ret = ttm_bo_vm_reserve(bo, vmf);

if (ret)
return ret;
  
  	prot = vma->vm_page_prot;

-   ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT, 1);
+   if (drm_dev_enter(ddev, )) {
+   ret = ttm_bo_vm_fault_reserved(vmf, prot, 
TTM_BO_VM_NUM_PREFAULT, 1);
+   drm_dev_exit(idx);
+   } else {
+   ret = ttm_bo_vm_dummy_page(vmf, prot);
+   }
if (ret == VM_FAULT_RETRY && !(vmf->flags & 

Re: [PATCH][next] drm/amdgpu: Fix masking binary not operator on two mask operations

[Alex Deucher]

Applied.  Thanks!

Alex

On Sun, Jan 24, 2021 at 11:36 PM Huang Rui  wrote:
>
> On Fri, Jan 22, 2021 at 11:00:22PM +0800, Colin King wrote:
> > From: Colin Ian King 
> >
> > Currently the ! operator is incorrectly being used to flip bits on
> > mask values. Fix this by using the bit-wise ~ operator instead.
> >
> > Addresses-Coverity: ("Logical vs. bitwise operator")
> > Fixes: 3c9a7b7d6e75 ("drm/amdgpu: update mmhub mgcg for mmhub_v2_3")
> > Signed-off-by: Colin Ian King 
>
> Thanks.
>
> Reviewed-by: Huang Rui 
>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c 
> > b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > index 1961745e89c7..ab9be5ad5a5f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > @@ -531,12 +531,12 @@ mmhub_v2_3_update_medium_grain_light_sleep(struct 
> > amdgpu_device *adev,
> >
> >   if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
> >   data &= ~MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;
> > - data1 &= !(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> > + data1 &= ~(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> >   DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
> >   DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
> >   DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
> >   DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
> > - data2 &= !(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> > + data2 &= ~(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
> >   DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
> >   DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
> >   DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
> > --
> > 2.29.2
> >
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[RFC 4/7] drm/amd/display: Move calculate_wm_and_dlg to FPU folder

[Rodrigo Siqueira]

The function dcn3x_calculate_wm_and_dlg and
dcn30_calculate_wm_and_dlg_fp require access to FPU operation; for this
reason, this commit moves this function to the fpu directory.

Signed-off-by: Rodrigo Siqueira 
---
 .../drm/amd/display/dc/dcn30/dcn30_resource.c | 181 +-
 .../drm/amd/display/dc/dcn30/dcn30_resource.h |   5 -
 .../amd/display/dc/dcn301/dcn301_resource.c   |   2 +-
 .../amd/display/dc/dcn302/dcn302_resource.c   |   2 +-
 .../display/dc/fpu_operation/dcn3x_commons.c  | 177 +
 .../display/dc/fpu_operation/dcn3x_commons.h  |   3 +
 6 files changed, 183 insertions(+), 187 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index c97533b4ad09..4edebee00095 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1938,185 +1938,6 @@ static noinline bool dcn30_internal_validate_bw(
return out;
 }
 
-/*
- * This must be noinline to ensure anything that deals with FP registers
- * is contained within this call; previously our compiling with hard-float
- * would result in fp instructions being emitted outside of the boundaries
- * of the DC_FP_START/END macros, which makes sense as the compiler has no
- * idea about what is wrapped and what is not
- *
- * This is largely just a workaround to avoid breakage introduced with 5.6,
- * ideally all fp-using code should be moved into its own file, only that
- * should be compiled with hard-float, and all code exported from there
- * should be strictly wrapped with DC_FP_START/END
- */
-static noinline void dcn30_calculate_wm_and_dlg_fp(
-   struct dc *dc, struct dc_state *context,
-   display_e2e_pipe_params_st *pipes,
-   int pipe_cnt,
-   int vlevel)
-{
-   int i, pipe_idx;
-   double dcfclk = 
context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
-   bool pstate_en = 
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
 !=
-   dm_dram_clock_change_unsupported;
-
-   if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
-   dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
-
-   pipes[0].clks_cfg.voltage = vlevel;
-   pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
-   pipes[0].clks_cfg.socclk_mhz = 
context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
-
-   /* Set B:
-* DCFCLK: 1GHz or min required above 1GHz
-* FCLK/UCLK: Max
-*/
-   if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
-   if (vlevel == 0) {
-   pipes[0].clks_cfg.voltage = 1;
-   pipes[0].clks_cfg.dcfclk_mhz = 
context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
-   }
-   context->bw_ctx.dml.soc.dram_clock_change_latency_us = 
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
-   context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = 
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
-   context->bw_ctx.dml.soc.sr_exit_time_us = 
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
-   }
-   context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = 
get_wm_urgent(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
-   
context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = 
get_wm_stutter_enter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
-   context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = 
get_wm_stutter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
-   context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = 
get_wm_dram_clock_change(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
-   context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = 
get_wm_memory_trip(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
-   context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = 
get_fraction_of_urgent_bandwidth(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
-   context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = 
get_fraction_of_urgent_bandwidth_imm_flip(>bw_ctx.dml, pipes, 
pipe_cnt) * 1000;
-   context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = 
get_urgent_latency(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
-   pipes[0].clks_cfg.voltage = vlevel;
-   pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
-
-   /* Set D:
-* DCFCLK: Min Required
-* FCLK(proportional to UCLK): 1GHz or Max
-* MALL stutter, sr_enter_exit = 4, sr_exit = 2us
-*/
-   /*
-   if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
-   context->bw_ctx.dml.soc.dram_clock_change_latency_us = 
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
-   context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = 

[RFC 7/7] drm/amd/display: Drop float flages from DCN30 files

[Rodrigo Siqueira]

All functions that require FPU access associated with DCN30 were moved
to the specific file inside the FPU directory. For this reason, we don't
need to use the `-mhard-float -msse` flags for any DCN30 file directly,
which means that we can safely drop those flags from the Makefile and
any other unrelated FPU code.

Signed-off-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 30 ---
 .../drm/amd/display/dc/dcn30/dcn30_resource.c |  3 --
 .../gpu/drm/amd/display/dc/dcn302/Makefile| 25 
 3 files changed, 58 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
index c20331eb62e0..b7c2ae9ddfda 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
@@ -30,36 +30,6 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o dcn30_dpp.o 
dcn30_optc.o \
dcn30_dpp_cm.o dcn30_dwb_cm.o dcn30_cm_common.o dcn30_mmhubbub.o \
dcn30_dio_link_encoder.o dcn30_resource.o
 
-
-ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse
-endif
-
-ifdef CONFIG_PPC64
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -maltivec
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -maltivec
-endif
-
-ifdef CONFIG_CC_IS_GCC
-ifeq ($(call cc-ifversion, -lt, 0701, y), y)
-IS_OLD_GCC = 1
-endif
-endif
-
-ifdef CONFIG_X86
-ifdef IS_OLD_GCC
-# Stack alignment mismatch, proceed with caution.
-# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
-# (8B stack alignment).
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -mpreferred-stack-boundary=4
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -mpreferred-stack-boundary=4
-else
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -msse2
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -msse2
-endif
-endif
-
 AMD_DAL_DCN30 = $(addprefix $(AMDDALPATH)/dc/dcn30/,$(DCN30))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_DCN30)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index cd2598bd193f..d00f98174f21 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1403,9 +1403,6 @@ bool dcn30_release_post_bldn_3dlut(
return ret;
 }
 
-#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
-#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
-
 static bool dcn30_split_stream_for_mpc_or_odm(
const struct dc *dc,
struct resource_context *res_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
index 8d4924b7dc22..3ea9bff27912 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
@@ -12,31 +12,6 @@
 
 DCN3_02 = dcn302_init.o dcn302_hwseq.o dcn302_resource.o
 
-ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -msse
-endif
-
-ifdef CONFIG_PPC64
-CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -maltivec
-endif
-
-ifdef CONFIG_CC_IS_GCC
-ifeq ($(call cc-ifversion, -lt, 0701, y), y)
-IS_OLD_GCC = 1
-endif
-endif
-
-ifdef CONFIG_X86
-ifdef IS_OLD_GCC
-# Stack alignment mismatch, proceed with caution.
-# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
-# (8B stack alignment).
-CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o += 
-mpreferred-stack-boundary=4
-else
-CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o += -msse2
-endif
-endif
-
 AMD_DAL_DCN3_02 = $(addprefix $(AMDDALPATH)/dc/dcn302/,$(DCN3_02))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_DCN3_02)
-- 
2.25.1

___
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[RFC 6/7] drm/amd/display: Move bounding box functions to FPU folder

[Rodrigo Siqueira]

This commit moves all operations and data structures related to the
bounding box for DCN30 to the FPU folders.

Signed-off-by: Rodrigo Siqueira 
---
 .../drm/amd/display/dc/dcn30/dcn30_resource.c | 325 +
 .../drm/amd/display/dc/dcn30/dcn30_resource.h |   2 -
 .../display/dc/fpu_operation/dcn3x_commons.c  | 335 ++
 .../display/dc/fpu_operation/dcn3x_commons.h  |   6 +
 4 files changed, 342 insertions(+), 326 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 98acc8be698f..cd2598bd193f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -93,137 +93,6 @@
 
 #define DC_LOGGER_INIT(logger)
 
-struct _vcs_dpi_ip_params_st dcn3_0_ip = {
-   .use_min_dcfclk = 1,
-   .clamp_min_dcfclk = 0,
-   .odm_capable = 1,
-   .gpuvm_enable = 0,
-   .hostvm_enable = 0,
-   .gpuvm_max_page_table_levels = 4,
-   .hostvm_max_page_table_levels = 4,
-   .hostvm_cached_page_table_levels = 0,
-   .pte_group_size_bytes = 2048,
-   .num_dsc = 6,
-   .rob_buffer_size_kbytes = 184,
-   .det_buffer_size_kbytes = 184,
-   .dpte_buffer_size_in_pte_reqs_luma = 84,
-   .pde_proc_buffer_size_64k_reqs = 48,
-   .dpp_output_buffer_pixels = 2560,
-   .opp_output_buffer_lines = 1,
-   .pixel_chunk_size_kbytes = 8,
-   .pte_enable = 1,
-   .max_page_table_levels = 2,
-   .pte_chunk_size_kbytes = 2,  // ?
-   .meta_chunk_size_kbytes = 2,
-   .writeback_chunk_size_kbytes = 8,
-   .line_buffer_size_bits = 789504,
-   .is_line_buffer_bpp_fixed = 0,  // ?
-   .line_buffer_fixed_bpp = 0, // ?
-   .dcc_supported = true,
-   .writeback_interface_buffer_size_kbytes = 90,
-   .writeback_line_buffer_buffer_size = 0,
-   .max_line_buffer_lines = 12,
-   .writeback_luma_buffer_size_kbytes = 12,  // 
writeback_line_buffer_buffer_size = 656640
-   .writeback_chroma_buffer_size_kbytes = 8,
-   .writeback_chroma_line_buffer_width_pixels = 4,
-   .writeback_max_hscl_ratio = 1,
-   .writeback_max_vscl_ratio = 1,
-   .writeback_min_hscl_ratio = 1,
-   .writeback_min_vscl_ratio = 1,
-   .writeback_max_hscl_taps = 1,
-   .writeback_max_vscl_taps = 1,
-   .writeback_line_buffer_luma_buffer_size = 0,
-   .writeback_line_buffer_chroma_buffer_size = 14643,
-   .cursor_buffer_size = 8,
-   .cursor_chunk_size = 2,
-   .max_num_otg = 6,
-   .max_num_dpp = 6,
-   .max_num_wb = 1,
-   .max_dchub_pscl_bw_pix_per_clk = 4,
-   .max_pscl_lb_bw_pix_per_clk = 2,
-   .max_lb_vscl_bw_pix_per_clk = 4,
-   .max_vscl_hscl_bw_pix_per_clk = 4,
-   .max_hscl_ratio = 6,
-   .max_vscl_ratio = 6,
-   .hscl_mults = 4,
-   .vscl_mults = 4,
-   .max_hscl_taps = 8,
-   .max_vscl_taps = 8,
-   .dispclk_ramp_margin_percent = 1,
-   .underscan_factor = 1.11,
-   .min_vblank_lines = 32,
-   .dppclk_delay_subtotal = 46,
-   .dynamic_metadata_vm_enabled = true,
-   .dppclk_delay_scl_lb_only = 16,
-   .dppclk_delay_scl = 50,
-   .dppclk_delay_cnvc_formatter = 27,
-   .dppclk_delay_cnvc_cursor = 6,
-   .dispclk_delay_subtotal = 119,
-   .dcfclk_cstate_latency = 5.2, // SRExitTime
-   .max_inter_dcn_tile_repeaters = 8,
-   .odm_combine_4to1_supported = true,
-
-   .xfc_supported = false,
-   .xfc_fill_bw_overhead_percent = 10.0,
-   .xfc_fill_constant_bytes = 0,
-   .gfx7_compat_tiling_supported = 0,
-   .number_of_cursors = 1,
-};
-
-struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
-   .clock_limits = {
-   {
-   .state = 0,
-   .dispclk_mhz = 562.0,
-   .dppclk_mhz = 300.0,
-   .phyclk_mhz = 300.0,
-   .phyclk_d18_mhz = 667.0,
-   .dscclk_mhz = 405.6,
-   },
-   },
-   .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
-   .num_states = 1,
-   .sr_exit_time_us = 12,
-   .sr_enter_plus_exit_time_us = 20,
-   .urgent_latency_us = 4.0,
-   .urgent_latency_pixel_data_only_us = 4.0,
-   .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
-   .urgent_latency_vm_data_only_us = 4.0,
-   .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
-   .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
-   .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
-   .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
-   .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
-   .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
-   .max_avg_sdp_bw_use_normal_percent = 60.0,
-   

[RFC 5/7] drm/amd/display: Move patch bounding box to FPU folder

[Rodrigo Siqueira]

The function dcn20_patch_bounding_box is shared from DCN2 to DCN3 and
uses FPU operations. For this reason, this commit moves this function to
the fpu_commons file.

Signed-off-by: Rodrigo Siqueira 
---
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 36 +---
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |  3 --
 .../drm/amd/display/dc/dcn30/dcn30_resource.c |  2 +-
 .../amd/display/dc/dcn301/dcn301_resource.c   |  3 +-
 .../amd/display/dc/dcn302/dcn302_resource.c   |  3 +-
 .../display/dc/fpu_operation/fpu_commons.c| 43 +++
 .../display/dc/fpu_operation/fpu_commons.h|  3 ++
 7 files changed, 52 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d5bf740b408c..e9257999148e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3472,40 +3472,6 @@ void dcn20_update_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_s
bb->clock_limits[num_calculated_states].state = bb->num_states;
 }
 
-void dcn20_patch_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_st *bb)
-{
-   if ((int)(bb->sr_exit_time_us * 1000) != 
dc->bb_overrides.sr_exit_time_ns
-   && dc->bb_overrides.sr_exit_time_ns) {
-   bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
-   }
-
-   if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
-   != dc->bb_overrides.sr_enter_plus_exit_time_ns
-   && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
-   bb->sr_enter_plus_exit_time_us =
-   dc->bb_overrides.sr_enter_plus_exit_time_ns / 
1000.0;
-   }
-
-   if ((int)(bb->urgent_latency_us * 1000) != 
dc->bb_overrides.urgent_latency_ns
-   && dc->bb_overrides.urgent_latency_ns) {
-   bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 
1000.0;
-   }
-
-   if ((int)(bb->dram_clock_change_latency_us * 1000)
-   != dc->bb_overrides.dram_clock_change_latency_ns
-   && dc->bb_overrides.dram_clock_change_latency_ns) {
-   bb->dram_clock_change_latency_us =
-   dc->bb_overrides.dram_clock_change_latency_ns / 
1000.0;
-   }
-
-   if ((int)(bb->dummy_pstate_latency_us * 1000)
-   != 
dc->bb_overrides.dummy_clock_change_latency_ns
-   && dc->bb_overrides.dummy_clock_change_latency_ns) {
-   bb->dummy_pstate_latency_us =
-   dc->bb_overrides.dummy_clock_change_latency_ns 
/ 1000.0;
-   }
-}
-
 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
uint32_t hw_internal_rev)
 {
@@ -3580,7 +3546,7 @@ static bool init_soc_bounding_box(struct dc *dc,
 
loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
loaded_ip->max_num_dpp = pool->base.pipe_count;
-   dcn20_patch_bounding_box(dc, loaded_bb);
+   dcn_patch_bounding_box(dc, loaded_bb);
 
return true;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index 11ec655a18e3..4e6fda59ec29 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -167,9 +167,6 @@ enum dc_status dcn20_add_dsc_to_stream_resource(struct dc 
*dc, struct dc_state *
 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state 
*new_ctx, struct dc_stream_state *dc_stream);
 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state 
*plane_state);
 
-void dcn20_patch_bounding_box(
-   struct dc *dc,
-   struct _vcs_dpi_soc_bounding_box_st *bb);
 void dcn20_cap_soc_clocks(
struct _vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table max_clocks);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 4edebee00095..98acc8be698f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1563,7 +1563,7 @@ static bool init_soc_bounding_box(struct dc *dc,
loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
loaded_ip->max_num_dpp = pool->base.pipe_count;
loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
-   dcn20_patch_bounding_box(dc, loaded_bb);
+   dcn_patch_bounding_box(dc, loaded_bb);
 
if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
struct bp_soc_bb_info bb_info = {0};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 

[RFC 3/7] drm/amd/display: Add FPU file for functions shared across ASICs

[Rodrigo Siqueira]

In our DC code, we have a couple of functions that use FPU and are
shared between multiples ASICs; this situation complicates the work of
centralizing FPU functions in a single place. This commit tries to
alleviate this problem by creating a file named fpu_commons to
centralize shared functions that use FPU operation in a single file. As
a start point, we move dcn20_calculate_dlg_params to this file.

Signed-off-by: Rodrigo Siqueira 
---
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  70 +---
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |   5 -
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |   2 +
 .../drm/amd/display/dc/dcn30/dcn30_resource.c |   1 +
 .../drm/amd/display/dc/fpu_operation/Makefile |   3 +-
 .../display/dc/fpu_operation/dcn3x_commons.c  |   1 +
 .../display/dc/fpu_operation/fpu_commons.c| 102 ++
 .../display/dc/fpu_operation/fpu_commons.h|  34 ++
 8 files changed, 144 insertions(+), 74 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/fpu_operation/fpu_commons.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/fpu_operation/fpu_commons.h

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 064f158ce671..d5bf740b408c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -87,6 +87,8 @@
 
 #include "amdgpu_socbb.h"
 
+#include "fpu_operation/fpu_commons.h"
+
 #define DC_LOGGER_INIT(logger)
 
 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
@@ -3060,74 +3062,6 @@ static void dcn20_calculate_wm(
context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = 
get_fraction_of_urgent_bandwidth_imm_flip(>bw_ctx.dml, pipes, 
pipe_cnt) * 1000;
 }
 
-void dcn20_calculate_dlg_params(
-   struct dc *dc, struct dc_state *context,
-   display_e2e_pipe_params_st *pipes,
-   int pipe_cnt,
-   int vlevel)
-{
-   int i, pipe_idx;
-
-   /* Writeback MCIF_WB arbitration parameters */
-   dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
-
-   context->bw_ctx.bw.dcn.clk.dispclk_khz = 
context->bw_ctx.dml.vba.DISPCLK * 1000;
-   context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK 
* 1000;
-   context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK 
* 1000;
-   context->bw_ctx.bw.dcn.clk.dramclk_khz = 
context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
-   context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 
context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
-   context->bw_ctx.bw.dcn.clk.fclk_khz = 
context->bw_ctx.dml.vba.FabricClock * 1000;
-   context->bw_ctx.bw.dcn.clk.p_state_change_support =
-   
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
-   != 
dm_dram_clock_change_unsupported;
-   context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
-
-   if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
-   context->bw_ctx.bw.dcn.clk.dispclk_khz = 
dc->debug.min_disp_clk_khz;
-
-   for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
-   if (!context->res_ctx.pipe_ctx[i].stream)
-   continue;
-   pipes[pipe_idx].pipe.dest.vstartup_start = 
get_vstartup(>bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
-   pipes[pipe_idx].pipe.dest.vupdate_offset = 
get_vupdate_offset(>bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
-   pipes[pipe_idx].pipe.dest.vupdate_width = 
get_vupdate_width(>bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
-   pipes[pipe_idx].pipe.dest.vready_offset = 
get_vready_offset(>bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
-   if (context->bw_ctx.bw.dcn.clk.dppclk_khz < 
pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
-   context->bw_ctx.bw.dcn.clk.dppclk_khz = 
pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
-   context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
-   
pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
-   context->res_ctx.pipe_ctx[i].pipe_dlg_param = 
pipes[pipe_idx].pipe.dest;
-   pipe_idx++;
-   }
-   /*save a original dppclock copy*/
-   context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = 
context->bw_ctx.bw.dcn.clk.dppclk_khz;
-   context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = 
context->bw_ctx.bw.dcn.clk.dispclk_khz;
-   context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = 
context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
-   context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = 
context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
-
-   for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
-   bool cstate_en = 

[RFC 2/7] drm/amd/display: Moves dcn30_set_mcif_arb_params to FPU folder

[Rodrigo Siqueira]

The function dcn30_set_mcif_arb_params uses some double-precision
operation; for this reason, this commit moves this function to the
directory fpu_operation, where all FPU operations should be centralized.

Signed-off-by: Rodrigo Siqueira 
---
 .../drm/amd/display/dc/dcn30/dcn30_resource.c | 81 +-
 .../drm/amd/display/dc/dcn30/dcn30_resource.h | 11 ---
 .../amd/display/dc/dcn301/dcn301_resource.c   |  2 +-
 .../amd/display/dc/dcn302/dcn302_resource.c   |  2 +-
 .../display/dc/fpu_operation/dcn3x_commons.c  | 84 +++
 .../display/dc/fpu_operation/dcn3x_commons.h  |  3 +
 6 files changed, 90 insertions(+), 93 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 02e3107f04ee..b82d616f8a21 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1471,85 +1471,6 @@ int dcn30_populate_dml_pipes_from_context(
return pipe_cnt;
 }
 
-unsigned int dcn30_calc_max_scaled_time(
-   unsigned int time_per_pixel,
-   enum mmhubbub_wbif_mode mode,
-   unsigned int urgent_watermark)
-{
-   unsigned int time_per_byte = 0;
-   unsigned int total_free_entry = 0xb40;
-   unsigned int buf_lh_capability;
-   unsigned int max_scaled_time;
-
-   if (mode == PACKED_444) /* packed mode 32 bpp */
-   time_per_byte = time_per_pixel/4;
-   else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
-   time_per_byte = time_per_pixel/8;
-
-   if (time_per_byte == 0)
-   time_per_byte = 1;
-
-   buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* 
time_per_byte is in u6.6*/
-   max_scaled_time   = buf_lh_capability - urgent_watermark;
-   return max_scaled_time;
-}
-
-void dcn30_set_mcif_arb_params(
-   struct dc *dc,
-   struct dc_state *context,
-   display_e2e_pipe_params_st *pipes,
-   int pipe_cnt)
-{
-   enum mmhubbub_wbif_mode wbif_mode;
-   struct display_mode_lib *dml = >bw_ctx.dml;
-   struct mcif_arb_params *wb_arb_params;
-   int i, j, k, dwb_pipe;
-
-   /* Writeback MCIF_WB arbitration parameters */
-   dwb_pipe = 0;
-   for (i = 0; i < dc->res_pool->pipe_count; i++) {
-
-   if (!context->res_ctx.pipe_ctx[i].stream)
-   continue;
-
-   for (j = 0; j < MAX_DWB_PIPES; j++) {
-   struct dc_writeback_info *writeback_info = 
>res_ctx.pipe_ctx[i].stream->writeback_info[j];
-
-   if (writeback_info->wb_enabled == false)
-   continue;
-
-   //wb_arb_params = 
>res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
-   wb_arb_params = 
>bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
-
-   if (writeback_info->dwb_params.cnv_params.fc_out_format 
== DWB_OUT_FORMAT_64BPP_ARGB ||
-   
writeback_info->dwb_params.cnv_params.fc_out_format == 
DWB_OUT_FORMAT_64BPP_RGBA)
-   wbif_mode = PACKED_444_FP16;
-   else
-   wbif_mode = PACKED_444;
-
-   for (k = 0; k < 
sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); 
k++) {
-   wb_arb_params->cli_watermark[k] = 
get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;
-   wb_arb_params->pstate_watermark[k] = 
get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
-   }
-   wb_arb_params->time_per_pixel = (100 << 6) / 
context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be 
in u6.6 format */
-   wb_arb_params->slice_lines = 32;
-   wb_arb_params->arbitration_slice = 2; /* irrelevant 
since there is no YUV output */
-   wb_arb_params->max_scaled_time = 
dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
-   wbif_mode,
-   wb_arb_params->cli_watermark[0]); /* 
assume 4 watermark sets have the same value */
-   wb_arb_params->dram_speed_change_duration = 
dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * 
pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
-
-   dwb_pipe++;
-
-   if (dwb_pipe >= MAX_DWB_PIPES)
-   return;
-   }
-   if (dwb_pipe >= MAX_DWB_PIPES)
-   return;
-   }
-
-}
-
 static struct dc_cap_funcs cap_funcs = {
.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
 };
@@ -2402,7 +2323,7 @@ static const struct resource_funcs 

[RFC 1/7] drm/amd/display: Introduce FPU directory inside DC

[Rodrigo Siqueira]

The display core files rely on FPU operation, which requires to be
compiled with special flags. Ideally, we don't want these FPU operations
to get spread around the DC code; nevertheless, it happens in the
current source. This commit introduces a new directory named
fpu_operation that intends to centralize all files that require the FPU
compilation flag. As part of this new component, this patch also moves
one of the functions that require FPU access to a single shared file.
Notice that this is the first part of the work, and it does not fix the
FPU issue yet; we still need other patches for achieving the complete
isolation of this file.

Signed-off-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
 .../drm/amd/display/dc/dcn30/dcn30_resource.c |  92 +--
 .../drm/amd/display/dc/dcn30/dcn30_resource.h |   2 -
 .../amd/display/dc/dcn301/dcn301_resource.c   |   3 +-
 .../amd/display/dc/dcn302/dcn302_resource.c   |   3 +-
 .../drm/amd/display/dc/fpu_operation/Makefile |  57 +++
 .../display/dc/fpu_operation/dcn3x_commons.c  | 146 ++
 .../display/dc/fpu_operation/dcn3x_commons.h  |  32 
 8 files changed, 242 insertions(+), 94 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/fpu_operation/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.h

diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
b/drivers/gpu/drm/amd/display/dc/Makefile
index bf8fe0471b8f..61dd2c5865c7 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -33,6 +33,7 @@ DC_LIBS += dcn21
 DC_LIBS += dcn30
 DC_LIBS += dcn301
 DC_LIBS += dcn302
+DC_LIBS += fpu_operation
 endif
 
 DC_LIBS += dce120
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index dcf848f747a5..02e3107f04ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -34,6 +34,7 @@
 #include "dcn20/dcn20_resource.h"
 
 #include "dcn30_resource.h"
+#include "fpu_operation/dcn3x_commons.h"
 
 #include "dcn10/dcn10_ipp.h"
 #include "dcn30/dcn30_hubbub.h"
@@ -1470,95 +1471,6 @@ int dcn30_populate_dml_pipes_from_context(
return pipe_cnt;
 }
 
-void dcn30_populate_dml_writeback_from_context(
-   struct dc *dc, struct resource_context *res_ctx, 
display_e2e_pipe_params_st *pipes)
-{
-   int pipe_cnt, i, j;
-   double max_calc_writeback_dispclk;
-   double writeback_dispclk;
-   struct writeback_st dout_wb;
-
-   for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
-   struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
-
-   if (!stream)
-   continue;
-   max_calc_writeback_dispclk = 0;
-
-   /* Set writeback information */
-   pipes[pipe_cnt].dout.wb_enable = 0;
-   pipes[pipe_cnt].dout.num_active_wb = 0;
-   for (j = 0; j < stream->num_wb_info; j++) {
-   struct dc_writeback_info *wb_info = 
>writeback_info[j];
-
-   if (wb_info->wb_enabled && 
wb_info->writeback_source_plane &&
-   (wb_info->writeback_source_plane == 
res_ctx->pipe_ctx[i].plane_state)) {
-   pipes[pipe_cnt].dout.wb_enable = 1;
-   pipes[pipe_cnt].dout.num_active_wb++;
-   dout_wb.wb_src_height = 
wb_info->dwb_params.cnv_params.crop_en ?
-   
wb_info->dwb_params.cnv_params.crop_height :
-   
wb_info->dwb_params.cnv_params.src_height;
-   dout_wb.wb_src_width = 
wb_info->dwb_params.cnv_params.crop_en ?
-   
wb_info->dwb_params.cnv_params.crop_width :
-   
wb_info->dwb_params.cnv_params.src_width;
-   dout_wb.wb_dst_width = 
wb_info->dwb_params.dest_width;
-   dout_wb.wb_dst_height = 
wb_info->dwb_params.dest_height;
-
-   /* For IP that doesn't support WB scaling, set 
h/v taps to 1 to avoid DML validation failure */
-   if (dc->dml.ip.writeback_max_hscl_taps > 1) {
-   dout_wb.wb_htaps_luma = 
wb_info->dwb_params.scaler_taps.h_taps;
-   dout_wb.wb_vtaps_luma = 
wb_info->dwb_params.scaler_taps.v_taps;
-   } else {
-   dout_wb.wb_htaps_luma = 1;
-   dout_wb.wb_vtaps_luma = 1;
-   }
-   dout_wb.wb_htaps_chroma = 0;
-   

[RFC 0/7] Proposal for isolating FPU operation

[Rodrigo Siqueira]

Hi,

In the display core, we utilize floats and doubles units for calculating
modesetting parameters. One side effect of our approach to use double-precision
is the fact that we spread multiple FPU access across our driver, which means
that we can accidentally clobber user space FPU state. As an attempt to fix
this problem, we have the following proposal:

1. We first need to move functions that deal with FPU to a single place in
   order to make things more manageable;
2. After we isolate these function in a single place, we want to remove any
   compilation flag that deals with FPU from other files and centralize it only
   in the files that need it;
3. We need to implement an interface for safely calling those FPU functions.
   The idea is to add a thin function layer where FPU functions are invoked
   under the protection of kernel_fpu_begin/end.

One of the challenges from the above steps is identifying which function uses
FPU registers; fortunately, Peter Zijlstra wrote a patch a couple of months ago
where he introduced an FPU check for objtool. I used the following command for
identifying the potential FPU usage:

 ./tools/objtool/objtool check -Ffa "drivers/gpu/drm/amd/display/dc/ANY_FILE.o"

Based on the above command output and the step-by-step approach that we want to
adopt, I decided to start this work focusing on DCN3 and DCN302. I believe that
the best way to see this RFC is:

1. The first patch introduces an FPU folder inside display/dc, intending to
   centralize functions that deal with FPU. Note that I introduced two new C
   files named dcn3x_commons inside a new folder called fpu_operation; I used
   the name dcn3x because some of the functions inside this folder are shared
   with DCN301 and DCN302. In other words, all FPU function which is shared
   across DCN3x will be placed in that file.
2. The next set of patches, start to move some of the function that requires
   FPU access to the file dcn3x_commons. I did it in a small chunk to make it
   easy to bisect in case of regressions.
3. Note that one of the patch touch DCN2, the reason for that is the fact that
   the function dcn20_calculate_dlg_params is shared from DCN2 to DCN3. Because
   of that, I create a new file named fpu_commons for keeping functions that
   are shared across multiple ASICs.
4. When we move some of the functions, notice that I also add an API for
   accessing it via fpu_kernel_begin/end.
5. At the end of the series, I dropped the FPU flags from the files that I
   initialize refactored.

We are also working on test stress for validating this change from the user
space and kernel perspective.

Keep in mind that this series is not done yet. I'm looking for feedback about
this approach because we have plans to use it for trying to fix our FPU
problems for the next couple of weeks. Finally, we want to do this work
step-by-step because it is easy to introduce regression when dealing with these
FPU problems.

Best Regards

Rodrigo Siqueira (7):
  drm/amd/display: Introduce FPU directory inside DC
  drm/amd/display: Moves dcn30_set_mcif_arb_params to FPU folder
  drm/amd/display: Add FPU file for functions shared across ASICs
  drm/amd/display: Move calculate_wm_and_dlg to FPU folder
  drm/amd/display: Move patch bounding box to FPU folder
  drm/amd/display: Move bounding box functions to FPU folder
  drm/amd/display: Drop float flages from DCN30 files

 drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 106 +--
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |   8 -
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |   2 +
 drivers/gpu/drm/amd/display/dc/dcn30/Makefile |  30 -
 .../drm/amd/display/dc/dcn30/dcn30_resource.c | 683 +---
 .../drm/amd/display/dc/dcn30/dcn30_resource.h |  20 -
 .../amd/display/dc/dcn301/dcn301_resource.c   |  10 +-
 .../gpu/drm/amd/display/dc/dcn302/Makefile|  25 -
 .../amd/display/dc/dcn302/dcn302_resource.c   |  10 +-
 .../drm/amd/display/dc/fpu_operation/Makefile |  58 ++
 .../display/dc/fpu_operation/dcn3x_commons.c  | 743 ++
 .../display/dc/fpu_operation/dcn3x_commons.h  |  44 ++
 .../display/dc/fpu_operation/fpu_commons.c| 145 
 .../display/dc/fpu_operation/fpu_commons.h|  37 +
 15 files changed, 1051 insertions(+), 871 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/fpu_operation/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/fpu_operation/fpu_commons.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/fpu_operation/fpu_commons.h

-- 
2.25.1

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Re: [PATCH] drm/amd/display: use div_s64() for 64-bit division

[Arnd Bergmann]

On Mon, Jan 25, 2021 at 1:51 PM Chen, Guchun  wrote:
>
> [AMD Public Use]
>
> Hi Arnd Bergmann,
>
> Thanks for your patch. This link error during compile has been fixed by below 
> commit and been submitted to drm-next branch already.
>
> 5da047444e82 drm/amd/display: fix 64-bit division issue on 32-bit OS

Ok, thanks. I assume this will make it into linux-next in the coming days then.

 Arnd
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RE: [PATCH] drm/amd/display: use div_s64() for 64-bit division

[Chen, Guchun]

[AMD Public Use]

Hi Arnd Bergmann,

Thanks for your patch. This link error during compile has been fixed by below 
commit and been submitted to drm-next branch already.

5da047444e82 drm/amd/display: fix 64-bit division issue on 32-bit OS

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Arnd Bergmann
Sent: Monday, January 25, 2021 7:40 PM
To: Wentland, Harry ; Li, Sun peng (Leo) 
; Deucher, Alexander ; Koenig, 
Christian ; David Airlie ; Daniel 
Vetter ; Aberback, Joshua ; Lakha, 
Bhawanpreet ; Kazlauskas, Nicholas 

Cc: Arnd Bergmann ; Chalmers, Wesley ; 
Zhuo, Qingqing ; Siqueira, Rodrigo 
; linux-ker...@vger.kernel.org; 
amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Jacky Liao 
; Leung, Martin 
Subject: [PATCH] drm/amd/display: use div_s64() for 64-bit division

From: Arnd Bergmann 

The open-coded 64-bit division causes a link error on 32-bit
machines:

ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!

Use the div_s64() to perform the division here. One of them was an unsigned 
division originally, but it looks like signed division was intended, so use 
that to consistently allow a negative delay.

Fixes: ea7154d8d9fb ("drm/amd/display: Update 
dcn30_apply_idle_power_optimizations() code")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index dff83c6a142a..a133e399e76d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -772,8 +772,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, 
bool enable)
cursor_cache_enable ? 
_attr : NULL)) {
unsigned int v_total = 
stream->adjust.v_total_max ?
stream->adjust.v_total_max : 
stream->timing.v_total;
-   unsigned int refresh_hz = (unsigned long long) 
stream->timing.pix_clk_100hz *
-   100LL / (v_total * 
stream->timing.h_total);
+   unsigned int refresh_hz = div_s64((unsigned 
long long) stream->timing.pix_clk_100hz *
+   100LL, v_total * 
stream->timing.h_total);
 
/*
 * one frame time in microsec:
@@ -800,8 +800,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, 
bool enable)
unsigned int denom = refresh_hz * 6528;
unsigned int stutter_period = 
dc->current_state->perf_params.stutter_period_us;
 
-   tmr_delay = (((100LL + 2 * stutter_period * 
refresh_hz) *
-   (100LL + 
dc->debug.mall_additional_timer_percent) + denom - 1) /
+   tmr_delay = div_s64(((100LL + 2 * 
stutter_period * refresh_hz) *
+   (100LL + 
dc->debug.mall_additional_timer_percent) + denom - 1),
denom) - 64LL;
 
/* scale should be increased until it fits into 
6 bits */ @@ -815,8 +815,8 @@ bool dcn30_apply_idle_power_optimizations(struct 
dc *dc, bool enable)
}
 
denom *= 2;
-   tmr_delay = (((100LL + 2 * 
stutter_period * refresh_hz) *
-   (100LL + 
dc->debug.mall_additional_timer_percent) + denom - 1) /
+   tmr_delay = div_s64(((100LL + 2 * 
stutter_period * refresh_hz) *
+   (100LL + 
dc->debug.mall_additional_timer_percent) + denom - 1),
denom) - 64LL;
}
 
--
2.29.2

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[PATCH] drm/amd/display: fix unused variable warning

[Arnd Bergmann]

From: Arnd Bergmann 

After all users of the 'dm' warnings got hidden in an #ifdef,
the compiler started warning about it being unused:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5380:33: error: 
unused variable 'dm' [-Werror,-Wunused-variable]

Add another such #ifdef.

Fixes: 98ab5f3513f9 ("drm/amd/display: Fix deadlock during gpu reset v3")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a90dc4d31c32..37bf2dd87e1e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5377,7 +5377,9 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, 
bool enable)
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
+#if defined(CONFIG_DRM_AMD_DC_DCN)
struct amdgpu_display_manager *dm = >dm;
+#endif
int rc = 0;
 
if (enable) {
-- 
2.29.2

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[PATCH] amdgpu: fix clang build warning

[Arnd Bergmann]

From: Arnd Bergmann 

clang warns about the -mhard-float command line arguments
on architectures that do not support this:

clang: error: argument unused during compilation: '-mhard-float' 
[-Werror,-Wunused-command-line-argument]

Move this into the gcc-specific arguments.

Fixes: e77165bf7b02 ("drm/amd/display: Add DCN3 blocks to Makefile")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/display/dc/dcn30/Makefile  | 6 --
 drivers/gpu/drm/amd/display/dc/dcn301/Makefile | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn302/Makefile | 3 ++-
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
index c20331eb62e0..dfd77b3cc84d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
@@ -32,8 +32,8 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o dcn30_dpp.o 
dcn30_optc.o \
 
 
 ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -msse
 endif
 
 ifdef CONFIG_PPC64
@@ -45,6 +45,8 @@ ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -mhard-float
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -mhard-float
 endif
 
 ifdef CONFIG_X86
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
index 3ca7d911d25c..09264716d1dc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
@@ -14,7 +14,7 @@ DCN301 = dcn301_init.o dcn301_resource.o dcn301_dccg.o \
dcn301_dio_link_encoder.o dcn301_hwseq.o dcn301_panel_cntl.o 
dcn301_hubbub.o
 
 ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -mhard-float -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -msse
 endif
 
 ifdef CONFIG_PPC64
@@ -25,6 +25,7 @@ ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
+CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o += -mhard-float
 endif
 
 ifdef CONFIG_X86
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
index 8d4924b7dc22..101620a8867a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
@@ -13,7 +13,7 @@
 DCN3_02 = dcn302_init.o dcn302_hwseq.o dcn302_resource.o
 
 ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -msse
 endif
 
 ifdef CONFIG_PPC64
@@ -24,6 +24,7 @@ ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
+CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o += -mhard-float
 endif
 
 ifdef CONFIG_X86
-- 
2.29.2

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Re: [PATCH] drm/amd/display: change license of color_table.c

[Jonathan Gray]

This still needs to be corrected.

On Thu, Nov 19, 2020 at 01:30:41PM +1100, Jonathan Gray wrote:
> Change the license of color_table.c to match color_table.h granting
> permission to modify and distribute.
> 
> Signed-off-by: Jonathan Gray 
> ---
>  .../amd/display/modules/color/color_table.c   | 26 +++
>  1 file changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/modules/color/color_table.c 
> b/drivers/gpu/drm/amd/display/modules/color/color_table.c
> index 692e536e7d05..410f2a82b9a2 100644
> --- a/drivers/gpu/drm/amd/display/modules/color/color_table.c
> +++ b/drivers/gpu/drm/amd/display/modules/color/color_table.c
> @@ -1,10 +1,26 @@
>  /*
> - * Copyright (c) 2019 Advanced Micro Devices, Inc. (unpublished)
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
>   *
> - * All rights reserved.  This notice is intended as a precaution against
> - * inadvertent publication and does not imply publication or any waiver
> - * of confidentiality.  The year included in the foregoing notice is the
> - * year of creation of the work.
>   */
>  
>  #include "color_table.h"
> -- 
> 2.29.2
> 
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[PATCH] drm/amd/display: use div_s64() for 64-bit division

[Arnd Bergmann]

From: Arnd Bergmann 

The open-coded 64-bit division causes a link error on 32-bit
machines:

ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!

Use the div_s64() to perform the division here. One of them was an
unsigned division originally, but it looks like signed division was
intended, so use that to consistently allow a negative delay.

Fixes: ea7154d8d9fb ("drm/amd/display: Update 
dcn30_apply_idle_power_optimizations() code")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index dff83c6a142a..a133e399e76d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -772,8 +772,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, 
bool enable)
cursor_cache_enable ? 
_attr : NULL)) {
unsigned int v_total = 
stream->adjust.v_total_max ?
stream->adjust.v_total_max : 
stream->timing.v_total;
-   unsigned int refresh_hz = (unsigned long long) 
stream->timing.pix_clk_100hz *
-   100LL / (v_total * 
stream->timing.h_total);
+   unsigned int refresh_hz = div_s64((unsigned 
long long) stream->timing.pix_clk_100hz *
+   100LL, v_total * 
stream->timing.h_total);
 
/*
 * one frame time in microsec:
@@ -800,8 +800,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, 
bool enable)
unsigned int denom = refresh_hz * 6528;
unsigned int stutter_period = 
dc->current_state->perf_params.stutter_period_us;
 
-   tmr_delay = (((100LL + 2 * stutter_period * 
refresh_hz) *
-   (100LL + 
dc->debug.mall_additional_timer_percent) + denom - 1) /
+   tmr_delay = div_s64(((100LL + 2 * 
stutter_period * refresh_hz) *
+   (100LL + 
dc->debug.mall_additional_timer_percent) + denom - 1),
denom) - 64LL;
 
/* scale should be increased until it fits into 
6 bits */
@@ -815,8 +815,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, 
bool enable)
}
 
denom *= 2;
-   tmr_delay = (((100LL + 2 * 
stutter_period * refresh_hz) *
-   (100LL + 
dc->debug.mall_additional_timer_percent) + denom - 1) /
+   tmr_delay = div_s64(((100LL + 2 * 
stutter_period * refresh_hz) *
+   (100LL + 
dc->debug.mall_additional_timer_percent) + denom - 1),
denom) - 64LL;
}
 
-- 
2.29.2

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[PATCH] drm/amd/display: Fix a potential NULL dereference

[Dan Carpenter]

The debug printk dereferences "link->link_enc" before we have ensured
that it is non-NULL.  Fix this potential NULL derefence by moving the
printk after the check.

Fixes: 1975b95ad4e7 ("drm/amd/display: Log link/connector info provided in BIOS 
object table")
Signed-off-by: Dan Carpenter 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c16af3983fdb..4d31b2fae1f9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1525,13 +1525,13 @@ static bool dc_link_construct(struct dc_link *link,
link->link_enc =
link->dc->res_pool->funcs->link_enc_create(_init_data);
 
-   DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", 
link->link_enc->features.flags.bits.DP_IS_USB_C);
-
if (!link->link_enc) {
DC_ERROR("Failed to create link encoder!\n");
goto link_enc_create_fail;
}
 
+   DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", 
link->link_enc->features.flags.bits.DP_IS_USB_C);
+
link->link_enc_hw_inst = link->link_enc->transmitter;
 
for (i = 0; i < 4; i++) {
-- 
2.29.2

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[PATCH] drm/amdgpu: fix bitwise vs logical negate

[Dan Carpenter]

There was a mixup between logical and bitwise negate so it just sets
"data1" and "data2" to zero.

Fixes: 3c9a7b7d6e75 ("drm/amdgpu: update mmhub mgcg for mmhub_v2_3")
Signed-off-by: Dan Carpenter 
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index 1961745e89c7..ab9be5ad5a5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -531,12 +531,12 @@ mmhub_v2_3_update_medium_grain_light_sleep(struct 
amdgpu_device *adev,
 
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
data &= ~MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;
-   data1 &= !(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
+   data1 &= ~(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
-   data2 &= !(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
+   data2 &= ~(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
-- 
2.29.2

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RE: [PATCH] drm/amd/amdgpu: add error handling to amdgpu_virt_read_pf2vf_data

[Liu, Monk]

[AMD Official Use Only - Approved for External Use]

Reviewed-by: Monk Liu

Thanks 

--
Monk Liu | Cloud-GPU Core team
--

-Original Message-
From: Chen, JingWen  
Sent: Thursday, January 21, 2021 11:13 AM
To: amd-gfx@lists.freedesktop.org; Liu, Monk 
Cc: Chen, JingWen 
Subject: RE: [PATCH] drm/amd/amdgpu: add error handling to 
amdgpu_virt_read_pf2vf_data

[AMD Official Use Only - Approved for External Use]

Ping

Best Regards,
JingWen Chen

-Original Message-
From: Jingwen Chen  
Sent: Tuesday, January 19, 2021 5:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, JingWen ; Chen, JingWen 
Subject: [PATCH] drm/amd/amdgpu: add error handling to 
amdgpu_virt_read_pf2vf_data

[Why]
when vram lost happened in guest, try to write vram can lead to kernel stuck.

[How]
When the readback data is invalid, don't do write work, directly reschedule a 
new work.

Signed-off-by: Jingwen Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index c649944e49da..3dd7eec52344 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -558,10 +558,14 @@ static int amdgpu_virt_write_vf2pf_data(struct 
amdgpu_device *adev)  static void amdgpu_virt_update_vf2pf_work_item(struct 
work_struct *work)  {
struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 
virt.vf2pf_work.work);
+   int ret;
 
-   amdgpu_virt_read_pf2vf_data(adev);
+   ret = amdgpu_virt_read_pf2vf_data(adev);
+   if (ret)
+   goto out;
amdgpu_virt_write_vf2pf_data(adev);
 
+out:
schedule_delayed_work(&(adev->virt.vf2pf_work), 
adev->virt.vf2pf_update_interval_ms);
 }
 
--
2.25.1
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