date:20220721

[PATCH] drm/amdgpu: Fix the incomplete product number

2022-07-21 Thread Roy Sun

The comments say that the product number is a 16-digit HEX string so the
buffer needs to be at least 17 characters to hold the NUL terminator. Expand
the buffer size to 20 to avoid the alignment issues.

The comment:Product number should only be 16 characters. Any
more,and something could be wrong. Cap it at 16 to be safe

Signed-off-by: Roy Sun 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 9f729a648005..187e3dae3965 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1019,7 +1019,7 @@ struct amdgpu_device {
boolpsp_sysfs_en;
 
/* Chip product information */
-   charproduct_number[16];
+   charproduct_number[20];
charproduct_name[AMDGPU_PRODUCT_NAME_LEN];
charserial[20];
 
-- 
2.34.1

RE: [PATCH 1/6] drm/amdgpu: add CHIP_IP_DISCOVERY support for virtualization

2022-07-21 Thread Chen, Horace

[AMD Official Use Only - General]

Hi Alex,

By current design, we will keep this register same for all new asics.
Also, the amdgpu_detect_virtualization will be called before we read the IP 
discovery table (virtualization needs to send a message to host machine to 
request for the IP discovery table preparation). So we can't use any IP version 
to decide the register.

Regards,
Horace.

-Original Message-
From: Alex Deucher 
Sent: Thursday, July 21, 2022 10:37 PM
To: Chen, Horace 
Cc: amd-gfx@lists.freedesktop.org; Grodzovsky, Andrey 
; Xiao, Jack ; Xu, Feifei 
; Wang, Yang(Kevin) ; Xiaojie Yuan 
; Tuikov, Luben ; Deucher, 
Alexander ; Quan, Evan ; Koenig, 
Christian ; Liu, Monk ; Zhang, 
Hawking 
Subject: Re: [PATCH 1/6] drm/amdgpu: add CHIP_IP_DISCOVERY support for 
virtualization

On Thu, Jul 21, 2022 at 5:52 AM Horace Chen  wrote:
>
> For further chips we will use CHIP_IP_DISCOVERY, so add this support
> for virtualization

All current and future chips will use CHIP_IP_DISCOVERY.  If we plan to keep 
the register the same for all new aics, this should be fine.
If we might need to have it per asic I think you might want something more like 
this:

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 9be57389301b..0bdd71f9a8fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -709,6 +709,16 @@ void amdgpu_detect_virtualization(struct
amdgpu_device *adev)
case CHIP_ALDEBARAN:
reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
break;
+   case CHIP_IP_DISCOVERY:
+   switch (adev->ip_versions[GC_HWIP][0]) {
+   case IP_VERSION(11, 0, 0):
+   reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
+   break;
+   default:
+   reg = 0;
+   break;
+   }
+   break;
default: /* other chip doesn't support SRIOV */
reg = 0;
break;

Alex

>
> Signed-off-by: Horace Chen 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 7d7044e9de2f..ab55602ff534 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -705,6 +705,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device 
> *adev)
> case CHIP_SIENNA_CICHLID:
> case CHIP_ARCTURUS:
> case CHIP_ALDEBARAN:
> +   case CHIP_IP_DISCOVERY:
> reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
> break;
> default: /* other chip doesn't support SRIOV */ @@ -748,6
> +749,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)
> case CHIP_NAVI10:
> case CHIP_NAVI12:
> case CHIP_SIENNA_CICHLID:
> +   case CHIP_IP_DISCOVERY:
> nv_set_virt_ops(adev);
> /* try send GPU_INIT_DATA request to host */
> amdgpu_virt_request_init_data(adev);
> --
> 2.25.1
>

[PATCH] drm/amdgpu: enable swiotlb for gmc 10.0

2022-07-21 Thread Aaron Liu

Enable swiotlb for gmc 10.0.

Signed-off-by: Aaron Liu 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 6470290aaf7d..a1a98c7fe8e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -967,6 +967,8 @@ static int gmc_v10_0_sw_init(void *handle)
return r;
}
 
+   adev->need_swiotlb = drm_need_swiotlb(44);
+
r = gmc_v10_0_mc_init(adev);
if (r)
return r;
-- 
2.37.0

RE: [PATCH] drm/amd/pm: Add get_gfx_off_status interface

2022-07-21 Thread Liu, Aaron

[AMD Official Use Only - General]

Shikai,

Yellow carp's SMUIO is 13_0_1. 
#define regSMUIO_GFX_MISC_CNTL  
0x00c5

This register in your patch is from smuio_13_0_2_offset.h and this register's 
value is different to 13_0_1.
#define regSMUIO_GFX_MISC_CNTL  
0x00d1


> -Original Message-
> From: amd-gfx  On Behalf Of
> shikai@amd.com
> Sent: Thursday, July 21, 2022 4:58 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
> ; Quan, Evan ; Guo, Shikai
> 
> Subject: [PATCH] drm/amd/pm: Add get_gfx_off_status interface
> 
> From: Shikai Guo 
> 
> add get_gfx_off_status interface to yellow_carp_ppt_funcs structure.
> 
> Signed-off-by: Shikai Guo 
> ---
>  .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  | 30
> +++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index 70cbc46341a3..2e39b629e7e6 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -31,6 +31,7 @@
>  #include "smu_v13_0_1_ppsmc.h"
>  #include "smu_v13_0_1_pmfw.h"
>  #include "smu_cmn.h"
> +#include "asic_reg/smuio/smuio_13_0_2_offset.h"
> 
>  /*
>   * DO NOT use these for err/warn/info/debug messages.
> @@ -42,6 +43,9 @@
>  #undef pr_info
>  #undef pr_debug
> 
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
>   0x0006L
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT
>   0x1
> +
>  #define FEATURE_MASK(feature) (1ULL << feature)  #define
> SMC_DPM_FEATURE ( \
>   FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -587,6 +591,31
> @@ static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
>   return sizeof(struct gpu_metrics_v2_1);  }
> 
> +/**
> + * yellow_carp_get_gfxoff_status - get gfxoff status
> + *
> + * @smu: smu_context pointer
> + *
> + * This function will be used to get gfxoff status
> + *
> + * Returns 0=GFXOFF(default).
> + * Returns 1=Transition out of GFX State.
> + * Returns 2=Not in GFXOFF.
> + * Returns 3=Transition into GFXOFF.
> + */
> +static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
> +{
> + uint32_t reg;
> + uint32_t gfxOff_Status = 0;
> + struct amdgpu_device *adev = smu->adev;
> +
> + reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
> + gfxOff_Status = (reg &
> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
> + >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
> +
> + return gfxOff_Status;
> +}
> +
>  static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)  {
>   struct smu_table_context *smu_table = >smu_table; @@ -
> 1186,6 +1215,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs
> = {
>   .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
>   .set_driver_table_location = smu_v13_0_set_driver_table_location,
>   .gfx_off_control = smu_v13_0_gfx_off_control,
> + .get_gfx_off_status = yellow_carp_get_gfxoff_status,
>   .post_init = yellow_carp_post_smu_init,
>   .mode2_reset = yellow_carp_mode2_reset,
>   .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
> --
> 2.25.1

Re: [PATCH v2 01/29] ACPI: video: Add acpi_video_backlight_use_native() helper

2022-07-21 Thread Daniel Dadap




On 7/12/22 14:38, Hans de Goede wrote:

ATM on x86 laptops where we want userspace to use the acpi_video backlight
device we often register both the GPU's native backlight device and
acpi_video's firmware acpi_video# backlight device. This relies on
userspace preferring firmware type backlight devices over native ones, but
registering 2 backlight devices for a single display really is undesirable.

On x86 laptops where the native GPU backlight device should be used,
the registering of other backlight devices is avoided by their drivers
using acpi_video_get_backlight_type() and only registering their backlight
if the return value matches their type.

acpi_video_get_backlight_type() uses
backlight_device_get_by_type(BACKLIGHT_RAW) to determine if a native
driver is available and will never return native if this returns
false. This means that the GPU's native backlight registering code
cannot just call acpi_video_get_backlight_type() to determine if it
should register its backlight, since acpi_video_get_backlight_type() will
never return native until the native backlight has already registered.

To fix this add a new internal native function parameter to
acpi_video_get_backlight_type(), which when set to true will make
acpi_video_get_backlight_type() behave as if a native backlight has
already been registered.

And add a new acpi_video_backlight_use_native() helper, which sets this
to true, for use in native GPU backlight code.

Changes in v2:
- Replace adding a native parameter to acpi_video_get_backlight_type() with
   adding a new acpi_video_backlight_use_native() helper.

Signed-off-by: Hans de Goede 
---
  drivers/acpi/video_detect.c | 24 
  include/acpi/video.h|  5 +
  2 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c
index becc198e4c22..4346c990022d 100644
--- a/drivers/acpi/video_detect.c
+++ b/drivers/acpi/video_detect.c
@@ -17,8 +17,9 @@
   * Otherwise vendor specific drivers like thinkpad_acpi, asus-laptop,
   * sony_acpi,... can take care about backlight brightness.
   *
- * Backlight drivers can use acpi_video_get_backlight_type() to determine
- * which driver should handle the backlight.
+ * Backlight drivers can use acpi_video_get_backlight_type() to determine which
+ * driver should handle the backlight. RAW/GPU-driver backlight drivers must
+ * use the acpi_video_backlight_use_native() helper for this.
   *
   * If CONFIG_ACPI_VIDEO is neither set as "compiled in" (y) nor as a module 
(m)
   * this file will not be compiled and acpi_video_get_backlight_type() will
@@ -548,9 +549,10 @@ static int acpi_video_backlight_notify(struct 
notifier_block *nb,
   * Arguably the native on win8 check should be done first, but that would
   * be a behavior change, which may causes issues.
   */
-enum acpi_backlight_type acpi_video_get_backlight_type(void)
+static enum acpi_backlight_type __acpi_video_get_backlight_type(bool native)
  {
static DEFINE_MUTEX(init_mutex);
+   static bool native_available;
static bool init_done;
static long video_caps;
  
@@ -570,6 +572,8 @@ enum acpi_backlight_type acpi_video_get_backlight_type(void)

backlight_notifier_registered = true;
init_done = true;
}
+   if (native)
+   native_available = true;
mutex_unlock(_mutex);
  
  	if (acpi_backlight_cmdline != acpi_backlight_undef)

@@ -581,13 +585,25 @@ enum acpi_backlight_type 
acpi_video_get_backlight_type(void)
if (!(video_caps & ACPI_VIDEO_BACKLIGHT))
return acpi_backlight_vendor;
  
-	if (acpi_osi_is_win8() && backlight_device_get_by_type(BACKLIGHT_RAW))

+   if (acpi_osi_is_win8() &&
+   (native_available || backlight_device_get_by_type(BACKLIGHT_RAW)))
return acpi_backlight_native;
  
  	return acpi_backlight_video;



So I ran into a minor problem when testing the NVIDIA proprietary driver 
against this change set, after checking 
acpi_video_backlight_use_native() before registering the NVIDIA 
proprietary driver's backlight handler. Namely, for the case where a 
user installs the NVIDIA proprietary driver after the video.ko has 
already registered its backlight handler, we end up with both the 
firmware and native handlers registered simultaneously, since the ACPI 
video driver no longer unregisters its backlight handler. In this state, 
desktop environments end up preferring the registered but non-functional 
firmware handler from video.ko. (Manually twiddling the sysfs interface 
for the native NVIDIA handler works fine.) When rebooting the system 
after installing the NVIDIA proprietary driver, it is able to register 
its native handler before the delayed work to register the ACPI video 
backlight handler fires, so we end up with only one (native) handler, 
and userspace is happy.


Maybe this will be moot later on, when the existing sysfs interface is

Re: [PATCH v2 01/29] ACPI: video: Add acpi_video_backlight_use_native() helper

2022-07-21 Thread Daniel Dadap




On 7/21/22 16:24, Daniel Dadap wrote:


On 7/12/22 14:38, Hans de Goede wrote:
ATM on x86 laptops where we want userspace to use the acpi_video 
backlight

device we often register both the GPU's native backlight device and
acpi_video's firmware acpi_video# backlight device. This relies on
userspace preferring firmware type backlight devices over native 
ones, but
registering 2 backlight devices for a single display really is 
undesirable.


On x86 laptops where the native GPU backlight device should be used,
the registering of other backlight devices is avoided by their drivers
using acpi_video_get_backlight_type() and only registering their 
backlight

if the return value matches their type.

acpi_video_get_backlight_type() uses
backlight_device_get_by_type(BACKLIGHT_RAW) to determine if a native
driver is available and will never return native if this returns
false. This means that the GPU's native backlight registering code
cannot just call acpi_video_get_backlight_type() to determine if it
should register its backlight, since acpi_video_get_backlight_type() 
will

never return native until the native backlight has already registered.

To fix this add a new internal native function parameter to
acpi_video_get_backlight_type(), which when set to true will make
acpi_video_get_backlight_type() behave as if a native backlight has
already been registered.

And add a new acpi_video_backlight_use_native() helper, which sets this
to true, for use in native GPU backlight code.

Changes in v2:
- Replace adding a native parameter to 
acpi_video_get_backlight_type() with

   adding a new acpi_video_backlight_use_native() helper.

Signed-off-by: Hans de Goede 
---
  drivers/acpi/video_detect.c | 24 
  include/acpi/video.h    |  5 +
  2 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c
index becc198e4c22..4346c990022d 100644
--- a/drivers/acpi/video_detect.c
+++ b/drivers/acpi/video_detect.c
@@ -17,8 +17,9 @@
   * Otherwise vendor specific drivers like thinkpad_acpi, asus-laptop,
   * sony_acpi,... can take care about backlight brightness.
   *
- * Backlight drivers can use acpi_video_get_backlight_type() to 
determine

- * which driver should handle the backlight.
+ * Backlight drivers can use acpi_video_get_backlight_type() to 
determine which
+ * driver should handle the backlight. RAW/GPU-driver backlight 
drivers must

+ * use the acpi_video_backlight_use_native() helper for this.
   *
   * If CONFIG_ACPI_VIDEO is neither set as "compiled in" (y) nor as 
a module (m)
   * this file will not be compiled and 
acpi_video_get_backlight_type() will
@@ -548,9 +549,10 @@ static int acpi_video_backlight_notify(struct 
notifier_block *nb,
   * Arguably the native on win8 check should be done first, but that 
would

   * be a behavior change, which may causes issues.
   */
-enum acpi_backlight_type acpi_video_get_backlight_type(void)
+static enum acpi_backlight_type __acpi_video_get_backlight_type(bool 
native)

  {
  static DEFINE_MUTEX(init_mutex);
+    static bool native_available;
  static bool init_done;
  static long video_caps;
  @@ -570,6 +572,8 @@ enum acpi_backlight_type 
acpi_video_get_backlight_type(void)

  backlight_notifier_registered = true;
  init_done = true;
  }
+    if (native)
+    native_available = true;
  mutex_unlock(_mutex);
    if (acpi_backlight_cmdline != acpi_backlight_undef)
@@ -581,13 +585,25 @@ enum acpi_backlight_type 
acpi_video_get_backlight_type(void)

  if (!(video_caps & ACPI_VIDEO_BACKLIGHT))
  return acpi_backlight_vendor;
  -    if (acpi_osi_is_win8() && 
backlight_device_get_by_type(BACKLIGHT_RAW))

+    if (acpi_osi_is_win8() &&
+    (native_available || 
backlight_device_get_by_type(BACKLIGHT_RAW)))

  return acpi_backlight_native;
    return acpi_backlight_video;



So I ran into a minor problem when testing the NVIDIA proprietary 
driver against this change set, after checking 
acpi_video_backlight_use_native() before registering the NVIDIA 
proprietary driver's backlight handler. Namely, for the case where a 
user installs the NVIDIA proprietary driver after the video.ko has 
already registered its backlight handler, we end up with both the 
firmware and native handlers registered simultaneously, since the ACPI 
video driver no longer unregisters its backlight handler. In this 
state, desktop environments end up preferring the registered but 
non-functional firmware handler from video.ko. (Manually twiddling the 
sysfs interface for the native NVIDIA handler works fine.) When 
rebooting the system after installing the NVIDIA proprietary driver, 
it is able to register its native handler before the delayed work to 
register the ACPI video backlight handler fires, so we end up with 
only one (native) handler, and userspace is happy.


Maybe this will be moot later on, when the existing sysfs

Re: [PATCH 2/2] drm/amd/display: Specify supported modifiers for dcn314

2022-07-21 Thread Alex Deucher

Series is:
Reviewed-by: Alex Deucher 

On Thu, Jul 21, 2022 at 6:04 PM  wrote:

> From: Roman Li 
>
> Use same modifiers as for AMDGPU_FAMILY_GC_11_0_0
>
> Signed-off-by: Roman Li 
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> index e27621e11947..2b3de9d0d3f3 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> @@ -1404,6 +1404,7 @@ static bool dm_plane_format_mod_supported(struct
> drm_plane *plane,
> }
> break;
> case AMDGPU_FAMILY_GC_11_0_0:
> +   case AMDGPU_FAMILY_GC_11_0_2:
> switch (AMD_FMT_MOD_GET(TILE, modifier)) {
> case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
> case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
> --
> 2.17.1
>
>

[PATCH 1/2] drm/amd/display: Fix dc_version detect for dcn314

2022-07-21 Thread Roman.Li

From: Roman Li 

[Why]
While parsing dc_version redundant check leads to
invalid dc_version for dcn314.

[How]
Remove redundant check

Fixes: 923989c9cc31b ("drm/amd/display: Enable DCN314 in DC")

Signed-off-by: Roman Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index bdaad4ce4b2d..752ba4ab2b1e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -74,6 +74,7 @@
 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
 {
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
+
switch (asic_id.chip_family) {
 
 #if defined(CONFIG_DRM_AMD_DC_SI)
@@ -169,8 +170,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id 
asic_id)
dc_version = DCN_VERSION_3_21;
break;
case AMDGPU_FAMILY_GC_11_0_2:
-   if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev))
-   dc_version = DCN_VERSION_3_14;
+   dc_version = DCN_VERSION_3_14;
break;
default:
dc_version = DCE_VERSION_UNKNOWN;
-- 
2.17.1

[PATCH 2/2] drm/amd/display: Specify supported modifiers for dcn314

2022-07-21 Thread Roman.Li

From: Roman Li 

Use same modifiers as for AMDGPU_FAMILY_GC_11_0_0

Signed-off-by: Roman Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index e27621e11947..2b3de9d0d3f3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1404,6 +1404,7 @@ static bool dm_plane_format_mod_supported(struct 
drm_plane *plane,
}
break;
case AMDGPU_FAMILY_GC_11_0_0:
+   case AMDGPU_FAMILY_GC_11_0_2:
switch (AMD_FMT_MOD_GET(TILE, modifier)) {
case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
-- 
2.17.1

Re: [PATCH 5/5] drm/amd/display: move FPU code from dcn301 clk mgr to DML folder

2022-07-21 Thread Rodrigo Siqueira Jordao





On 2022-07-21 13:26, Maíra Canal wrote:

Hi Melissa,

On 7/20/22 16:32, Melissa Wen wrote:

The -mno-gnu-attribute option in dcn301 clk mgr makefile hides a soft vs
hard fp error for powerpc. After removing this flag, we can see some FPU
code remains there:

gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses
hard float,
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
uses soft float

Therefore, remove the -mno-gnu-attribute flag for dcn301/powerpc and
move FPU-associated code to DML folder.

Signed-off-by: Melissa Wen 
---
  .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |  6 --
  .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c| 86 ++-
  .../display/dc/clk_mgr/dcn301/vg_clk_mgr.h|  3 +
  .../amd/display/dc/dml/dcn301/dcn301_fpu.c| 74 
  4 files changed, 84 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 15b660a951a5..271d8e573181 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -123,12 +123,6 @@ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)
  
###
  CLK_MGR_DCN301 = vg_clk_mgr.o dcn301_smu.o
  
-# prevent build errors regarding soft-float vs hard-float FP ABI tags

-# this code is currently unused on ppc64, as it applies to VanGogh APUs only
-ifdef CONFIG_PPC64
-CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn301/vg_clk_mgr.o := $(call 
cc-option,-mno-gnu-attribute)
-endif
-
  AMD_DAL_CLK_MGR_DCN301 = $(addprefix 
$(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301))
  
  AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
index f310b0d25a07..65f224af03c0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -32,6 +32,10 @@
  // For dcn20_update_clocks_update_dpp_dto
  #include "dcn20/dcn20_clk_mgr.h"
  
+// For DML FPU code

+#include "dml/dcn20/dcn20_fpu.h"
+#include "dml/dcn301/dcn301_fpu.h"
+


I guess the "dml/dcn301/dcn301_fpu.h" header is not needed, as you only
use dcn21_clk_mgr_set_bw_params_wm_table and the structs are on the
source file.

Besides that, to the whole series:
Reviewed-by: Maíra Canal 

Best Regards,
- Maíra Canal


Nice catch!
I'll make this adjustment before I merge it.

Thanks
Siqueira




  #include "vg_clk_mgr.h"
  #include "dcn301_smu.h"
  #include "reg_helper.h"
@@ -526,81 +530,6 @@ static struct clk_bw_params vg_bw_params = {
  
  };
  
-static struct wm_table ddr4_wm_table = {

-   .entries = {
-   {
-   .wm_inst = WM_A,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 6.09,
-   .sr_enter_plus_exit_time_us = 7.14,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_B,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 10.12,
-   .sr_enter_plus_exit_time_us = 11.48,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_C,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 10.12,
-   .sr_enter_plus_exit_time_us = 11.48,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_D,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 10.12,
-   .sr_enter_plus_exit_time_us = 11.48,
-   .valid = true,
-   },
-   }
-};
-
-static struct wm_table lpddr5_wm_table = {
-   .entries = {
-   {
-   .wm_inst = WM_A,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 13.5,
-   .sr_enter_plus_exit_time_us = 16.5,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_B,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 13.5,
-   .sr_enter_plus_exit_time_us = 16.5,
-   .valid = true,
-   },
-   {
-

Re: [PATCH 0/5] drm/amd/display: FPU cleanup in clk_mgr files for powerpc

2022-07-21 Thread Rodrigo Siqueira Jordao





On 2022-07-20 15:32, Melissa Wen wrote:

An initial report from Guenter[1] shows some soft-fp vs hard-fp error
from DCN31 clk mgr for powerpc. I was not able to reproduce it
cross-compiling with gcc-powerpc-linux-gnu and gcc-11.3, but thanks to
Maíra tips, I can reproduce the issue using make.cross, as follows:

- wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross 
-O ~/bin/make.cross
- chmod +x ~/bin/make.cross
- mkdir build_dir
- COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 ~/make.cross O=build_dir 
ARCH=powerpc SHELL=/bin/bash


Hi Melissa,

I didn't know about these steps, I was trying to reproduce this issue by 
using the standard cross compile package provided by my distro (Debian 
testing and ArchLinux), and as a result, I was never able to see the 
problem. Anyway, I can now reproduce this issue, thanks a lot.



with a config file generate by allmodconfig

So, the first patch fix the issue reported by Guenter. The second is
just a cleanup in dcn31_resource file to remove useless DC_FP_ wrapper.
Finally, the last three patches I'm removing the -mno-gnu-attribute
option, that was just hiding FPU-associated code in clk mgr files of
dcn21/30/301, and moving them to DML folder. This series doesn't cover
recent drivers dcn32/314.


I validated this series in our internal CI by running multiple IGT tests 
in numerous ASICs. Tomorrow we will also send some extra patches 
associated with this FPU effort; hopefully, after that, we will finally 
have all the FPU code under DML. Again, thanks a lot for your effort!


Thanks
Siqueira


Thanks Guenter, Maíra, Siqueira and Alex for all inputs on this
debugging process. Let me know your thoughts on this approach.

Melissa

[1] https://lore.kernel.org/amd-gfx/20220618232737.2036722-1-li...@roeck-us.net/>> 
Melissa Wen (5):

   drm/amd/display: fix soft-fp vs hard-fp on DCN 3.1 family for powerpc
   drm/amd/display: remove useless FPU protection wrapper from
 dcn31_resource file
   drm/amd/display: move FPU code on dcn21 clk_mgr
   drm/amd/display: move FPU code from dcn30 clk mgr to DML folder
   drm/amd/display: move FPU code from dcn301 clk mgr to DML folder

  .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |  18 --
  .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 234 +
  .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h |   7 +
  .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c  |  63 +
  .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c|  86 +--
  .../display/dc/clk_mgr/dcn301/vg_clk_mgr.h|   3 +
  .../drm/amd/display/dc/dcn31/dcn31_resource.c |  11 +-
  .../amd/display/dc/dcn315/dcn315_resource.c   |   5 +-
  .../amd/display/dc/dcn316/dcn316_resource.c   |   5 +-
  .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 235 ++
  .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.h  |   2 +
  .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c  |  63 -
  .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.h  |   1 +
  .../amd/display/dc/dml/dcn301/dcn301_fpu.c|  74 ++
  .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c  |  11 +
  .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.h  |   3 +
  16 files changed, 423 insertions(+), 398 deletions(-)

Re: [PATCH v2 1/4] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl

2022-07-21 Thread André Almeida

Thank you for the quick revision!

Series is Reviewed-by: André Almeida 

Às 15:36 de 21/07/22, Maíra Canal escreveu:
> As the enum entries dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp
> are not used on the codebase, drop those entries from enum
> dm_swizzle_mode.
> 
> Signed-off-by: Maíra Canal 
> ---
> v1 -> v2:
> - Replace "enum" to "enum entries" (André Almeida).
> - Describe changes in imperative mood (André Almeida).
> ---
>  .../dc/dml/dcn20/display_mode_vba_20.c| 26 +-
>  .../dc/dml/dcn20/display_mode_vba_20v2.c  | 26 +-
>  .../dc/dml/dcn21/display_mode_vba_21.c| 27 +--
>  .../amd/display/dc/dml/display_mode_enums.h   |  2 --
>  .../display/dc/dml/dml_wrapper_translation.c  |  9 ---
>  5 files changed, 19 insertions(+), 71 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> index d3b5b6fedf04..4e4cb0927057 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> @@ -938,7 +938,7 @@ static unsigned int CalculateVMAndRowBytes(
>   *MetaRowByte = 0;
>   }
>  
> - if (SurfaceTiling == dm_sw_linear || SurfaceTiling == 
> dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
> + if (SurfaceTiling == dm_sw_linear) {
>   MacroTileSizeBytes = 256;
>   MacroTileHeight = BlockHeight256Bytes;
>   } else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == 
> dm_sw_4kb_s_x
> @@ -3347,26 +3347,12 @@ void 
> dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
>   
> == dm_420_8
>   || 
> mode_lib->vba.SourcePixelFormat[k]
>   
> == dm_420_10))
> - || (((mode_lib->vba.SurfaceTiling[k] == 
> dm_sw_gfx7_2d_thin_gl
> - || 
> mode_lib->vba.SurfaceTiling[k]
> - == 
> dm_sw_gfx7_2d_thin_l_vp)
> - && 
> !((mode_lib->vba.SourcePixelFormat[k]
> - == dm_444_64
> + || (mode_lib->vba.DCCEnable[k] == true
> + && 
> (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>   || 
> mode_lib->vba.SourcePixelFormat[k]
> - 
> == dm_444_32)
> - && 
> mode_lib->vba.SourceScan[k]
> - 
> == dm_horz
> - && 
> mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
> - 
> == true
> - && 
> mode_lib->vba.DCCEnable[k]
> - 
> == false))
> - || (mode_lib->vba.DCCEnable[k] 
> == true
> - && 
> (mode_lib->vba.SurfaceTiling[k]
> - 
> == dm_sw_linear
> - 
> || mode_lib->vba.SourcePixelFormat[k]
> - 
> == dm_420_8
> - 
> || mode_lib->vba.SourcePixelFormat[k]
> - 
> == dm_420_10 {
> + 
> == dm_420_8
> + || 
> mode_lib->vba.SourcePixelFormat[k]
> + 
> == dm_420_10))) {
>   mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>   }
>   }
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> index 63bbdf8b8678..eaa0cdb599ba 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> @@ -998,7 +998,7 @@

Re: [PATCH 5/5] drm/amd/display: move FPU code from dcn301 clk mgr to DML folder

2022-07-21 Thread Rodrigo Siqueira Jordao





On 2022-07-20 15:32, Melissa Wen wrote:

The -mno-gnu-attribute option in dcn301 clk mgr makefile hides a soft vs
hard fp error for powerpc. After removing this flag, we can see some FPU
code remains there:

gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses
hard float,
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
uses soft float

Therefore, remove the -mno-gnu-attribute flag for dcn301/powerpc and
move FPU-associated code to DML folder.

Signed-off-by: Melissa Wen 
---
  .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |  6 --
  .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c| 86 ++-
  .../display/dc/clk_mgr/dcn301/vg_clk_mgr.h|  3 +
  .../amd/display/dc/dml/dcn301/dcn301_fpu.c| 74 
  4 files changed, 84 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 15b660a951a5..271d8e573181 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -123,12 +123,6 @@ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)
  
###
  CLK_MGR_DCN301 = vg_clk_mgr.o dcn301_smu.o
  
-# prevent build errors regarding soft-float vs hard-float FP ABI tags

-# this code is currently unused on ppc64, as it applies to VanGogh APUs only
-ifdef CONFIG_PPC64
-CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn301/vg_clk_mgr.o := $(call 
cc-option,-mno-gnu-attribute)
-endif
-
  AMD_DAL_CLK_MGR_DCN301 = $(addprefix 
$(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301))
  
  AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
index f310b0d25a07..65f224af03c0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -32,6 +32,10 @@
  // For dcn20_update_clocks_update_dpp_dto
  #include "dcn20/dcn20_clk_mgr.h"
  
+// For DML FPU code

+#include "dml/dcn20/dcn20_fpu.h"
+#include "dml/dcn301/dcn301_fpu.h"
+
  #include "vg_clk_mgr.h"
  #include "dcn301_smu.h"
  #include "reg_helper.h"
@@ -526,81 +530,6 @@ static struct clk_bw_params vg_bw_params = {
  
  };
  
-static struct wm_table ddr4_wm_table = {

-   .entries = {
-   {
-   .wm_inst = WM_A,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 6.09,
-   .sr_enter_plus_exit_time_us = 7.14,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_B,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 10.12,
-   .sr_enter_plus_exit_time_us = 11.48,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_C,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 10.12,
-   .sr_enter_plus_exit_time_us = 11.48,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_D,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 10.12,
-   .sr_enter_plus_exit_time_us = 11.48,
-   .valid = true,
-   },
-   }
-};
-
-static struct wm_table lpddr5_wm_table = {
-   .entries = {
-   {
-   .wm_inst = WM_A,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 13.5,
-   .sr_enter_plus_exit_time_us = 16.5,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_B,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 13.5,
-   .sr_enter_plus_exit_time_us = 16.5,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_C,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 13.5,
-   .sr_enter_plus_exit_time_us = 16.5,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_D,
-

Re: [PATCH 4/5] drm/amd/display: move FPU code from dcn30 clk mgr to DML folder

2022-07-21 Thread Rodrigo Siqueira Jordao





On 2022-07-20 15:32, Melissa Wen wrote:

The -mno-gnu-attribute option in clk mgr makefile for dcn30 hides a soft
vs hard fp error for powerpc. After removing this flag, we can see some
FPU code remains there:

gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses
hard float,
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.o
uses soft float

Therefore, remove the -mno-gnu-attribute flag for dcn30/powerpc and move
FPU-associated code to DML folder.

Signed-off-by: Melissa Wen 
---
  .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |  6 --
  .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c  | 63 ++-
  .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c  | 63 ++-
  .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.h  |  1 +
  4 files changed, 68 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 66dc02c426e9..15b660a951a5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -115,12 +115,6 @@ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)
  
###
  CLK_MGR_DCN30 = dcn30_clk_mgr.o dcn30_clk_mgr_smu_msg.o
  
-# prevent build errors regarding soft-float vs hard-float FP ABI tags

-# this code is currently unused on ppc64, as it applies to VanGogh APUs only
-ifdef CONFIG_PPC64
-CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn30/dcn30_clk_mgr.o := $(call 
cc-option,-mno-gnu-attribute)
-endif
-
  AMD_DAL_CLK_MGR_DCN30 = $(addprefix 
$(AMDDALPATH)/dc/clk_mgr/dcn30/,$(CLK_MGR_DCN30))
  
  AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index 914708cefc79..3ce0ee0d012f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -29,6 +29,7 @@
  #include "dcn20/dcn20_clk_mgr.h"
  #include "dce100/dce_clk_mgr.h"
  #include "dcn30/dcn30_clk_mgr.h"
+#include "dml/dcn30/dcn30_fpu.h"
  #include "reg_helper.h"
  #include "core_types.h"
  #include "dm_helpers.h"
@@ -97,65 +98,11 @@ static void dcn3_init_single_clock(struct clk_mgr_internal 
*clk_mgr, uint32_t cl
}
  }
  
-static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)

+static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
  {
-   /* defaults */
-   double pstate_latency_us = 
clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
-   double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
-   double sr_enter_plus_exit_time_us = 
clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
-   uint16_t min_uclk_mhz = 
clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
-
-   /* Set A - Normal - default values*/
-   clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
-   
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us 
= pstate_latency_us;
-   
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = 
sr_exit_time_us;
-   
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us
 = sr_enter_plus_exit_time_us;
-   
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = 
WATERMARKS_CLOCK_RANGE;
-   
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 
0;
-   
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 
0x;
-   
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = 
min_uclk_mhz;
-   
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 
0x;
-
-   /* Set B - Performance - higher minimum clocks */
-// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
-// 
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us 
= pstate_latency_us;
-// 
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = 
sr_exit_time_us;
-// 
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us
 = sr_enter_plus_exit_time_us;
-// 
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = 
WATERMARKS_CLOCK_RANGE;
-// 
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = 
TUNED VALUE;
-// 
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 
0x;
-// 
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = 
TUNED VALUE;
-// 
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 
0x;
-
-   /* Set C - Dummy P-State - P-State latency set

Re: [PATCH 3/5] drm/amd/display: move FPU code on dcn21 clk_mgr

2022-07-21 Thread Rodrigo Siqueira Jordao





On 2022-07-20 15:32, Melissa Wen wrote:

The -mno-gnu-attribute option in dcn21 clk mgr makefile hides a soft vs
hard fp error for powerpc. After removing this flag, we can see some FPU
code remains there:

/gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses
hard float,
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.o uses
soft float

Therefore, remove the -mno-gnu-attribute flag for dcn21/powerpc and move
FPU-associated code to DML folder.

Signed-off-by: Melissa Wen 
---
  .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |   6 -
  .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 234 +
  .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h |   7 +
  .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 235 ++
  .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.h  |   2 +
  5 files changed, 248 insertions(+), 236 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index a48453612d10..66dc02c426e9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -107,12 +107,6 @@ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN201)
  
###
  CLK_MGR_DCN21 = rn_clk_mgr.o rn_clk_mgr_vbios_smu.o
  
-# prevent build errors regarding soft-float vs hard-float FP ABI tags

-# this code is currently unused on ppc64, as it applies to Renoir APUs only
-ifdef CONFIG_PPC64
-CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := $(call 
cc-option,-mno-gnu-attribute)
-endif
-
  AMD_DAL_CLK_MGR_DCN21 = $(addprefix 
$(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21))
  
  AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index cf1b5f354ae9..0202dc682682 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -26,10 +26,9 @@
  #include "dccg.h"
  #include "clk_mgr_internal.h"
  
-

  #include "dcn20/dcn20_clk_mgr.h"
  #include "rn_clk_mgr.h"
-
+#include "dml/dcn20/dcn20_fpu.h"
  
  #include "dce100/dce_clk_mgr.h"

  #include "rn_clk_mgr_vbios_smu.h"
@@ -45,7 +44,6 @@
  
  /* Constants */
  
-#define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */

  #define SMU_VER_55_51_0 0x373300 /* SMU Version that is able to set DISPCLK 
below 100MHz */
  
  /* Macros */

@@ -613,228 +611,6 @@ static struct clk_bw_params rn_bw_params = {
  
  };
  
-static struct wm_table ddr4_wm_table_gs = {

-   .entries = {
-   {
-   .wm_inst = WM_A,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 7.09,
-   .sr_enter_plus_exit_time_us = 8.14,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_B,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 10.12,
-   .sr_enter_plus_exit_time_us = 11.48,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_C,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 10.12,
-   .sr_enter_plus_exit_time_us = 11.48,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_D,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.72,
-   .sr_exit_time_us = 10.12,
-   .sr_enter_plus_exit_time_us = 11.48,
-   .valid = true,
-   },
-   }
-};
-
-static struct wm_table lpddr4_wm_table_gs = {
-   .entries = {
-   {
-   .wm_inst = WM_A,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 5.32,
-   .sr_enter_plus_exit_time_us = 6.38,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_B,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-   .pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 9.82,
-   .sr_enter_plus_exit_time_us = 11.196,
-   .valid = true,
-   },
-   {
-   .wm_inst = WM_C,
-   .wm_type = WM_TYPE_PSTATE_CHG,
-

Re: [PATCH 2/5] drm/amd/display: remove useless FPU protection wrapper from dcn31_resource file

2022-07-21 Thread Rodrigo Siqueira Jordao





On 2022-07-20 15:32, Melissa Wen wrote:

Many lines of code in dcn31_resource_construct are wrapped by DC_FP
macro to protect FPU operations; however, there is no FPU in this
region. Therefore, just remove the wrapper for clarity.

Signed-off-by: Melissa Wen 
---
  drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 6 --
  1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 929b712cbada..6d25fcf865bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1863,8 +1863,6 @@ static bool dcn31_resource_construct(
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
  
-	DC_FP_START();

-
ctx->dc_bios->regs = _regs;
  
  	pool->base.res_cap = _cap_dcn31;

@@ -2175,13 +2173,9 @@ static bool dcn31_resource_construct(
  
  	dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
  
-	DC_FP_END();

-
return true;
  
  create_fail:

-
-   DC_FP_END();
dcn31_resource_destruct(pool);
  
  	return false;


Very nice catch!

Reviewed-by: Rodrigo Siqueira

Re: [PATCH 1/5] drm/amd/display: fix soft-fp vs hard-fp on DCN 3.1 family for powerpc

2022-07-21 Thread Rodrigo Siqueira Jordao





On 2022-07-20 15:32, Melissa Wen wrote:

Move remaining FPU code to DML folder that caused compilation error for
powerpc. This patch depends on [1] to prevent the error below:

/gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: 
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses hard 
float, drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.o uses 
soft float
/gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: failed to merge 
target specific data of file 
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.o
/gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: 
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses hard 
float, drivers/gpu/drm/amd/amdgpu/../display/dc/dcn315/dcn315_resource.o uses 
soft float
/gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: failed to merge 
target specific data of file 
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn315/dcn315_resource.o
/gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: 
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses hard 
float, drivers/gpu/drm/amd/amdgpu/../display/dc/dcn316/dcn316_resource.o uses 
soft float
/gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: failed to merge 
target specific data of file 
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn316/dcn316_resource.o

[1] https://lore.kernel.org/amd-gfx/20220716195144.342960-1-m...@igalia.com/

Reported-by: Guenter Roeck 
Signed-off-by: Melissa Wen 
---
  drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c |  5 +++--
  .../gpu/drm/amd/display/dc/dcn315/dcn315_resource.c   |  5 +++--
  .../gpu/drm/amd/display/dc/dcn316/dcn316_resource.c   |  5 +++--
  drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c  | 11 +++
  drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h  |  3 +++
  5 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 178d40c0d70a..929b712cbada 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1663,11 +1663,12 @@ int dcn31_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.src.immediate_flip = true;
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
pipes[pipe_cnt].pipe.src.gpuvm = true;
-   pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
-   pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
pipes[pipe_cnt].pipe.src.dcc_rate = 3;
pipes[pipe_cnt].dout.dsc_input_bpc = 0;
+   DC_FP_START();
+   dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
+   DC_FP_END();
  
  		if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE)

pipes[pipe_cnt].pipe.src.hostvm = 
dc->res_pool->hubbub->riommu_active;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index df2abd8fe2eb..1a5f5977f962 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1658,11 +1658,12 @@ static int dcn315_populate_dml_pipes_from_context(
  
  		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

pipes[pipe_cnt].pipe.src.gpuvm = true;
-   pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
-   pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
pipes[pipe_cnt].pipe.src.dcc_rate = 3;
pipes[pipe_cnt].dout.dsc_input_bpc = 0;
+   DC_FP_START();
+   dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
+   DC_FP_END();
  
  		if (pipes[pipe_cnt].dout.dsc_enable) {

switch (timing->display_color_depth) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
index 070fe10a004e..53dea466348f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
@@ -1661,11 +1661,12 @@ static int dcn316_populate_dml_pipes_from_context(
  
  		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

pipes[pipe_cnt].pipe.src.gpuvm = true;
-   pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
-   pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
pipes[pipe_cnt].pipe.src.dcc_rate = 3;
pipes[pipe_cnt].dout.dsc_input_bpc = 0;
+   DC_FP_START();
+

[PATCH v2 4/4] drm/amd/display: Rewrite CalculateWriteBackDISPCLK function

2022-07-21 Thread Maíra Canal

Based on the dml30_CalculateWriteBackDISPCLK, it separates the
DISPCLK calculations on three variables, making no functional changes, in order
to make it more readable and better express that three values are being compared
on dml_max.

Signed-off-by: Maíra Canal 
Reviewed-by: André Almeida 
---
 .../drm/amd/display/dc/dml/display_mode_vba.c | 29 ---
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 503e7d984ff0..df80c79d8fbc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -1115,20 +1115,27 @@ double CalculateWriteBackDISPCLK(
unsigned int HTotal,
unsigned int WritebackChromaLineBufferWidth)
 {
-   double CalculateWriteBackDISPCLK = 1.01 * PixelClock * dml_max(
-   dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio,
-   dml_max((WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 
1) * dml_ceil(WritebackDestinationWidth / 4.0, 1)
+   double DISPCLK_H, DISPCLK_V, DISPCLK_HB, CalculateWriteBackDISPCLK;
+
+   DISPCLK_H = dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio;
+   DISPCLK_V = (WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) * 
dml_ceil(WritebackDestinationWidth / 4.0, 1)
+ dml_ceil(WritebackDestinationWidth / 4.0, 1)) / 
(double) HTotal + dml_ceil(1.0 / WritebackVRatio, 1)
-   * (dml_ceil(WritebackLumaVTaps / 4.0, 1) + 4.0) / 
(double) HTotal,
-   dml_ceil(1.0 / WritebackVRatio, 1) * 
WritebackDestinationWidth / (double) HTotal));
+   * (dml_ceil(WritebackLumaVTaps / 4.0, 1) + 4.0) / 
(double) HTotal;
+   DISPCLK_HB = dml_ceil(1.0 / WritebackVRatio, 1) * 
WritebackDestinationWidth / (double) HTotal;
+
+   CalculateWriteBackDISPCLK = 1.01 * PixelClock * dml_max3(DISPCLK_H, 
DISPCLK_V, DISPCLK_HB);
+
if (WritebackPixelFormat != dm_444_32) {
-   CalculateWriteBackDISPCLK = dml_max(CalculateWriteBackDISPCLK, 
1.01 * PixelClock * dml_max(
-   dml_ceil(WritebackChromaHTaps / 2.0, 1) / (2 * 
WritebackHRatio),
-   dml_max((WritebackChromaVTaps * dml_ceil(1 / (2 * 
WritebackVRatio), 1) * dml_ceil(WritebackDestinationWidth / 2.0 / 2.0, 1)
-   + dml_ceil(WritebackDestinationWidth / 2.0 / 
WritebackChromaLineBufferWidth, 1)) / HTotal
-   + dml_ceil(1 / (2 * WritebackVRatio), 1) * 
(dml_ceil(WritebackChromaVTaps / 4.0, 1) + 4) / HTotal,
-   dml_ceil(1.0 / (2 * WritebackVRatio), 1) * 
WritebackDestinationWidth / 2.0 / HTotal)));
+   DISPCLK_H = dml_ceil(WritebackChromaHTaps / 2.0, 1) / (2 * 
WritebackHRatio);
+   DISPCLK_V = (WritebackChromaVTaps * dml_ceil(1 / (2 * 
WritebackVRatio), 1) *
+   dml_ceil(WritebackDestinationWidth / 4.0, 1) +
+   dml_ceil(WritebackDestinationWidth / 2.0 / 
WritebackChromaLineBufferWidth, 1)) / HTotal +
+   dml_ceil(1 / (2 * WritebackVRatio), 1) 
*(dml_ceil(WritebackChromaVTaps / 4.0, 1) + 4) / HTotal;
+   DISPCLK_HB = dml_ceil(1.0 / (2 * WritebackVRatio), 1) * 
WritebackDestinationWidth / 2.0 / HTotal;
+   CalculateWriteBackDISPCLK = dml_max(CalculateWriteBackDISPCLK,
+   1.01 * PixelClock * dml_max3(DISPCLK_H, 
DISPCLK_V, DISPCLK_HB));
}
+
return CalculateWriteBackDISPCLK;
 }
 
-- 
2.36.1

[PATCH v2 3/4] drm/amd/display: Remove parameters from rq_dlg_get_dlg_reg

2022-07-21 Thread Maíra Canal

Across all DCN's (except DCN32, that has a separate
rq_dlg_get_dlg_reg), the parameters const bool vm_en, const bool
ignore_viewport_pos, and const bool immediate_flip_support are not used
on the function. Therefore, change the rq_dlg_get_dlg_reg signature
by deleting those parameters.

Signed-off-by: Maíra Canal 
---
v1 -> v2:
- Replace "enum" to "enum entries" (André Almeida).
---
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  |  3 +--
 .../dc/dml/dcn20/display_rq_dlg_calc_20.c |  5 +
 .../dc/dml/dcn20/display_rq_dlg_calc_20.h |  5 +
 .../dc/dml/dcn20/display_rq_dlg_calc_20v2.c   |  5 +
 .../dc/dml/dcn20/display_rq_dlg_calc_20v2.h   |  5 +
 .../dc/dml/dcn21/display_rq_dlg_calc_21.c |  5 +
 .../dc/dml/dcn21/display_rq_dlg_calc_21.h |  5 +
 .../dc/dml/dcn30/display_rq_dlg_calc_30.c | 18 +++---
 .../dc/dml/dcn30/display_rq_dlg_calc_30.h |  5 +
 .../dc/dml/dcn31/display_rq_dlg_calc_31.c | 19 +++
 .../dc/dml/dcn31/display_rq_dlg_calc_31.h |  5 +
 .../dc/dml/dcn314/display_rq_dlg_calc_314.c   | 15 ++-
 .../dc/dml/dcn314/display_rq_dlg_calc_314.h   |  5 +
 .../drm/amd/display/dc/dml/display_mode_lib.h |  5 +
 .../gpu/drm/amd/display/dc/dml/dml_wrapper.c  |  3 +--
 15 files changed, 20 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index dc60b835e938..d9cfb29a2651 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -857,8 +857,7 @@ void dcn20_calculate_dlg_params(
pipe_cnt,
pipe_idx,
cstate_en,
-   
context->bw_ctx.bw.dcn.clk.p_state_change_support,
-   false, false, true);
+   
context->bw_ctx.bw.dcn.clk.p_state_change_support);
 

context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(>bw_ctx.dml,
>res_ctx.pipe_ctx[i].rq_regs,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
index 548cdef8a8ad..d0a4c69b47c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
@@ -1553,10 +1553,7 @@ void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib 
*mode_lib,
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
-   const bool pstate_en,
-   const bool vm_en,
-   const bool ignore_viewport_pos,
-   const bool immediate_flip_support)
+   const bool pstate_en)
 {
display_rq_params_st rq_param = {0};
display_dlg_sys_params_st dlg_sys_param = {0};
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
index 8b23867e97c1..36c3692e53b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
@@ -65,9 +65,6 @@ void dml20_rq_dlg_get_dlg_reg(
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
-   const bool pstate_en,
-   const bool vm_en,
-   const bool ignore_viewport_pos,
-   const bool immediate_flip_support);
+   const bool pstate_en);
 
 #endif
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
index 0fc9f3e3ffae..17df9d31c11f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
@@ -1554,10 +1554,7 @@ void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib 
*mode_lib,
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
-   const bool pstate_en,
-   const bool vm_en,
-   const bool ignore_viewport_pos,
-   const bool immediate_flip_support)
+   const bool pstate_en)
 {
display_rq_params_st rq_param = {0};
display_dlg_sys_params_st dlg_sys_param = {0};
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
index 2b4e46ea1c3d..f524f1ccfe41 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
@@ -65,9 +65,6 @@ void

[PATCH v2 2/4] drm/amd/display: Remove duplicated CalculateWriteBackDISPCLK

2022-07-21 Thread Maíra Canal

The functions dml30_CalculateWriteBackDISPCLK and
dml31_CalculateWriteBackDISPCLK are identical. Therefor, to avoid code
duplication, replace dml31_CalculateWriteBackDISPCLK by
dml30_CalculateWriteBackDISPCLK

Signed-off-by: Maíra Canal 
---
v1 -> v2:
- Describe changes in imperative mood (André Almeida).
---
 .../dc/dml/dcn31/display_mode_vba_31.c| 24 ++-
 .../dc/dml/dcn31/display_mode_vba_31.h| 11 -
 2 files changed, 2 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 3fab19134480..3bc529f0b0fc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -2085,7 +2085,7 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
if (v->WritebackEnable[k]) {
v->WritebackDISPCLK = dml_max(
v->WritebackDISPCLK,
-   dml31_CalculateWriteBackDISPCLK(
+   dml30_CalculateWriteBackDISPCLK(

v->WritebackPixelFormat[k],
v->PixelClock[k],
v->WritebackHRatio[k],
@@ -3470,26 +3470,6 @@ static double CalculateTWait(unsigned int PrefetchMode, 
double DRAMClockChangeLa
}
 }
 
-double dml31_CalculateWriteBackDISPCLK(
-   enum source_format_class WritebackPixelFormat,
-   double PixelClock,
-   double WritebackHRatio,
-   double WritebackVRatio,
-   unsigned int WritebackHTaps,
-   unsigned int WritebackVTaps,
-   long WritebackSourceWidth,
-   long WritebackDestinationWidth,
-   unsigned int HTotal,
-   unsigned int WritebackLineBufferSize)
-{
-   double DISPCLK_H, DISPCLK_V, DISPCLK_HB;
-
-   DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / 
WritebackHRatio;
-   DISPCLK_V = PixelClock * (WritebackVTaps * 
dml_ceil(WritebackDestinationWidth / 6.0, 1) + 8.0) / HTotal;
-   DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth * 
WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / WritebackSourceWidth;
-   return dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB);
-}
-
 static double CalculateWriteBackDelay(
enum source_format_class WritebackPixelFormat,
double WritebackHRatio,
@@ -4055,7 +4035,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
if (v->WritebackEnable[k] == true) {
v->WritebackRequiredDISPCLK = dml_max(
v->WritebackRequiredDISPCLK,
-   dml31_CalculateWriteBackDISPCLK(
+   dml30_CalculateWriteBackDISPCLK(

v->WritebackPixelFormat[k],
v->PixelClock[k],
v->WritebackHRatio[k],
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h
index 90be612f26b2..654362adcaa9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h
@@ -28,16 +28,5 @@
 
 void dml31_recalculate(struct display_mode_lib *mode_lib);
 void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib 
*mode_lib);
-double dml31_CalculateWriteBackDISPCLK(
-   enum source_format_class WritebackPixelFormat,
-   double PixelClock,
-   double WritebackHRatio,
-   double WritebackVRatio,
-   unsigned int WritebackHTaps,
-   unsigned int WritebackVTaps,
-   long   WritebackSourceWidth,
-   long   WritebackDestinationWidth,
-   unsigned int HTotal,
-   unsigned int WritebackLineBufferSize);
 
 #endif /* __DML31_DISPLAY_MODE_VBA_H__ */
-- 
2.36.1

[PATCH v2 1/4] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl

2022-07-21 Thread Maíra Canal

As the enum entries dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp
are not used on the codebase, drop those entries from enum
dm_swizzle_mode.

Signed-off-by: Maíra Canal 
---
v1 -> v2:
- Replace "enum" to "enum entries" (André Almeida).
- Describe changes in imperative mood (André Almeida).
---
 .../dc/dml/dcn20/display_mode_vba_20.c| 26 +-
 .../dc/dml/dcn20/display_mode_vba_20v2.c  | 26 +-
 .../dc/dml/dcn21/display_mode_vba_21.c| 27 +--
 .../amd/display/dc/dml/display_mode_enums.h   |  2 --
 .../display/dc/dml/dml_wrapper_translation.c  |  9 ---
 5 files changed, 19 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index d3b5b6fedf04..4e4cb0927057 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -938,7 +938,7 @@ static unsigned int CalculateVMAndRowBytes(
*MetaRowByte = 0;
}
 
-   if (SurfaceTiling == dm_sw_linear || SurfaceTiling == 
dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
+   if (SurfaceTiling == dm_sw_linear) {
MacroTileSizeBytes = 256;
MacroTileHeight = BlockHeight256Bytes;
} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == 
dm_sw_4kb_s_x
@@ -3347,26 +3347,12 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l

== dm_420_8
|| 
mode_lib->vba.SourcePixelFormat[k]

== dm_420_10))
-   || (((mode_lib->vba.SurfaceTiling[k] == 
dm_sw_gfx7_2d_thin_gl
-   || 
mode_lib->vba.SurfaceTiling[k]
-   == 
dm_sw_gfx7_2d_thin_l_vp)
-   && 
!((mode_lib->vba.SourcePixelFormat[k]
-   == dm_444_64
+   || (mode_lib->vba.DCCEnable[k] == true
+   && 
(mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
|| 
mode_lib->vba.SourcePixelFormat[k]
-   
== dm_444_32)
-   && 
mode_lib->vba.SourceScan[k]
-   
== dm_horz
-   && 
mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
-   
== true
-   && 
mode_lib->vba.DCCEnable[k]
-   
== false))
-   || (mode_lib->vba.DCCEnable[k] 
== true
-   && 
(mode_lib->vba.SurfaceTiling[k]
-   
== dm_sw_linear
-   
|| mode_lib->vba.SourcePixelFormat[k]
-   
== dm_420_8
-   
|| mode_lib->vba.SourcePixelFormat[k]
-   
== dm_420_10 {
+   
== dm_420_8
+   || 
mode_lib->vba.SourcePixelFormat[k]
+   
== dm_420_10))) {
mode_lib->vba.SourceFormatPixelAndScanSupport = false;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 63bbdf8b8678..eaa0cdb599ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -998,7 +998,7 @@ static unsigned int CalculateVMAndRowBytes(
*MetaRowByte = 0;
}
 
-   if (SurfaceTiling == dm_sw_linear || SurfaceTiling == 
dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
+   if

Re: [PATCH 1/4] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl

2022-07-21 Thread Maíra Canal




On 7/21/22 10:31, André Almeida wrote:
> Às 15:22 de 20/07/22, Maíra Canal escreveu:
>> As the enum dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp are not
>> used on the codebase, this commit drops those entries from enum
>> dm_swizzle_mode.
>>
> 
> dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp are not enums, but
> rather enum items or enum entries.
> 
> And, as per Linux documentation
> 
> Describe your changes in imperative mood, e.g. “make xyzzy do frotz”
> instead of “[This patch] makes xyzzy do frotz”
> 
> So replace /this commit drops/drop/
> 

Thank you for the feedback, André! I will address them on a v2.

Best Regards,
- Maíra Canal

>> Signed-off-by: Maíra Canal 
>> ---
>>  .../dc/dml/dcn20/display_mode_vba_20.c| 26 +-
>>  .../dc/dml/dcn20/display_mode_vba_20v2.c  | 26 +-
>>  .../dc/dml/dcn21/display_mode_vba_21.c| 27 +--
>>  .../amd/display/dc/dml/display_mode_enums.h   |  2 --
>>  .../display/dc/dml/dml_wrapper_translation.c  |  9 ---
>>  5 files changed, 19 insertions(+), 71 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
>> index d3b5b6fedf04..4e4cb0927057 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
>> @@ -938,7 +938,7 @@ static unsigned int CalculateVMAndRowBytes(
>>  *MetaRowByte = 0;
>>  }
>>  
>> -if (SurfaceTiling == dm_sw_linear || SurfaceTiling == 
>> dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
>> +if (SurfaceTiling == dm_sw_linear) {
>>  MacroTileSizeBytes = 256;
>>  MacroTileHeight = BlockHeight256Bytes;
>>  } else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == 
>> dm_sw_4kb_s_x
>> @@ -3347,26 +3347,12 @@ void 
>> dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
>>  
>> == dm_420_8
>>  || 
>> mode_lib->vba.SourcePixelFormat[k]
>>  
>> == dm_420_10))
>> -|| (((mode_lib->vba.SurfaceTiling[k] == 
>> dm_sw_gfx7_2d_thin_gl
>> -|| 
>> mode_lib->vba.SurfaceTiling[k]
>> -== 
>> dm_sw_gfx7_2d_thin_l_vp)
>> -&& 
>> !((mode_lib->vba.SourcePixelFormat[k]
>> -== dm_444_64
>> +|| (mode_lib->vba.DCCEnable[k] == true
>> +&& 
>> (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>>  || 
>> mode_lib->vba.SourcePixelFormat[k]
>> -
>> == dm_444_32)
>> -&& 
>> mode_lib->vba.SourceScan[k]
>> -
>> == dm_horz
>> -&& 
>> mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
>> -
>> == true
>> -&& 
>> mode_lib->vba.DCCEnable[k]
>> -
>> == false))
>> -|| (mode_lib->vba.DCCEnable[k] 
>> == true
>> -&& 
>> (mode_lib->vba.SurfaceTiling[k]
>> -
>> == dm_sw_linear
>> -
>> || mode_lib->vba.SourcePixelFormat[k]
>> -
>> == dm_420_8
>> -
>> || mode_lib->vba.SourcePixelFormat[k]
>> -
>> == dm_420_10 {
>> +
>> == dm_420_8
>> +|| 
>> mode_lib->vba.SourcePixelFormat[k]
>> +
>> == dm_420_10))) {
>>  mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>>  }
>>  }
>> diff --git 
>>

Re: [drm] 39dec70a06: leaking-addresses.proc._dyndbg_classes.

2022-07-21 Thread jim . cromie

On Wed, Jul 20, 2022 at 7:05 PM kernel test robot 
wrote:

>
>
> Greeting,
>
> FYI, we noticed the following commit (built with gcc-11):
>
> commit: 39dec70a061e581e60adb416031948ecd2dcd5d0 ("drm: POC drm on dyndbg
> - use in core, 2 helpers, 3 drivers.")
> https://github.com/jimc/linux.git dyn-drm-trc
>
> in testcase: leaking-addresses
> version: leaking-addresses-x86_64-4f19048-1_20220518
> with following parameters:
>
> ucode: 0x28
>
>
>
> on test machine: 8 threads 1 sockets Intel(R) Core(TM) i7-4770 CPU @
> 3.40GHz with 16G memory
>
> caused below changes (please refer to attached dmesg/kmsg for entire
> log/backtrace):
>
>
>
>
> If you fix the issue, kindly add following tag
> Reported-by: kernel test robot 
>
>
> below (1) is not observed on parent tests:
>




>
>
> 2022-07-18 02:55:06 ./leaking_addresses.pl --output-raw result/scan.out
> 2022-07-18 02:55:30 ./leaking_addresses.pl --input-raw result/scan.out
> --squash-by-filename
>
> Total number of results from scan (incl dmesg): 168569
>
> dmesg output:
> [2.186392] mapped IOAPIC to ff5fb000 (fec0)
>
> Results squashed by filename (excl dmesg). Displaying [
> ], 
>

new section, populated by macro invocations in this patch

[3 __dyndbg_classes] 0xc08dad00<- (1)
> [18 __dyndbg] 0xc01fd4e0
>

So I think this is All-good.


>

[PATCH 5/5] drm/amdgpu: enable VCN cg and JPEG cg/pg i

2022-07-21 Thread Sonny Jiang

Not enable VCN pg because encode issue

Signed-off-by: Sonny Jiang 
Reviewed-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 68e78983f956..52816de5e17b 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -585,8 +585,11 @@ static int soc21_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x10;
break;
case IP_VERSION(11, 0, 1):
-   adev->cg_flags = 0;
-   adev->pg_flags = 0;
+   adev->cg_flags =
+   AMD_CG_SUPPORT_VCN_MGCG |
+   AMD_CG_SUPPORT_JPEG_MGCG;
+   adev->pg_flags =
+   AMD_PG_SUPPORT_JPEG;
adev->external_rev_id = adev->rev_id + 0x1;
break;
default:
-- 
2.36.1

[PATCH 1/5] drm/amdgpu: fix a vcn4 boot poll bug in emulation mode

2022-07-21 Thread Sonny Jiang

The return value should be set in vcn4 boot poll.

Signed-off-by: Sonny Jiang 
Reviewed-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index a91ffbf902d4..3a16588024d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1041,6 +1041,7 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
}
 
if (amdgpu_emu_mode==1) {
+   r = -1;
if (status & 2) {
r = 0;
break;
-- 
2.36.1

[PATCH 4/5] drm/amdgpu: vcn_4_0_2 video codec query

2022-07-21 Thread Sonny Jiang

Enable support for vcn_4_0_2 video codec

Signed-off-by: Sonny Jiang 
Reviewed-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 00e9b7089feb..68e78983f956 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -80,6 +80,7 @@ static int soc21_query_video_codecs(struct amdgpu_device 
*adev, bool encode,
switch (adev->ip_versions[UVD_HWIP][0]) {
 
case IP_VERSION(4, 0, 0):
+   case IP_VERSION(4, 0, 2):
if (encode)
*codecs = _4_0_0_video_codecs_encode;
else
-- 
2.36.1

[PATCH 3/5] drm/amdgpu: add VCN_4_0_2 firmware support i

2022-07-21 Thread Sonny Jiang

Add VCN_4_0_2 firmware support

Signed-off-by: Sonny Jiang 
Reviewed-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 1bfdfb9207ac..f36e4f08db6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -54,6 +54,7 @@
 #define FIRMWARE_YELLOW_CARP   "amdgpu/yellow_carp_vcn.bin"
 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin"
 #define FIRMWARE_VCN4_0_0  "amdgpu/vcn_4_0_0.bin"
+#define FIRMWARE_VCN4_0_2  "amdgpu/vcn_4_0_2.bin"
 #define FIRMWARE_VCN4_0_4  "amdgpu/vcn_4_0_4.bin"
 
 MODULE_FIRMWARE(FIRMWARE_RAVEN);
@@ -74,6 +75,7 @@ MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
+MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
 
 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
@@ -185,6 +187,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
+   case IP_VERSION(4, 0, 2):
+   fw_name = FIRMWARE_VCN4_0_2;
+   if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+   (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+   adev->vcn.indirect_sram = false;
+   break;
case IP_VERSION(4, 0, 4):
fw_name = FIRMWARE_VCN4_0_4;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
-- 
2.36.1

[PATCH 2/5] drm/amdgpu: add VCN function in NBIO v7.7

2022-07-21 Thread Sonny Jiang

Add function to support VCN_4_0_2 doorbell

Signed-off-by: Sonny Jiang 
Reviewed-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
index e786b825cea9..01e8288d09a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
@@ -83,6 +83,26 @@ static void nbio_v7_7_sdma_doorbell_range(struct 
amdgpu_device *adev, int instan
WREG32_PCIE_PORT(reg, doorbell_range);
 }
 
+static void nbio_v7_7_vcn_doorbell_range(struct amdgpu_device *adev, bool 
use_doorbell,
+   int doorbell_index, int instance)
+{
+   u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
+   u32 doorbell_range = RREG32_PCIE_PORT(reg);
+
+   if (use_doorbell) {
+   doorbell_range = REG_SET_FIELD(doorbell_range,
+  GDC0_BIF_VCN0_DOORBELL_RANGE, 
OFFSET,
+  doorbell_index);
+   doorbell_range = REG_SET_FIELD(doorbell_range,
+  GDC0_BIF_VCN0_DOORBELL_RANGE, 
SIZE, 8);
+   } else {
+   doorbell_range = REG_SET_FIELD(doorbell_range,
+  GDC0_BIF_VCN0_DOORBELL_RANGE, 
SIZE, 0);
+   }
+
+   WREG32_PCIE_PORT(reg, doorbell_range);
+}
+
 static void nbio_v7_7_enable_doorbell_aperture(struct amdgpu_device *adev,
   bool enable)
 {
@@ -238,6 +258,7 @@ const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
.mc_access_enable = nbio_v7_7_mc_access_enable,
.get_memsize = nbio_v7_7_get_memsize,
.sdma_doorbell_range = nbio_v7_7_sdma_doorbell_range,
+   .vcn_doorbell_range = nbio_v7_7_vcn_doorbell_range,
.enable_doorbell_aperture = nbio_v7_7_enable_doorbell_aperture,
.enable_doorbell_selfring_aperture = 
nbio_v7_7_enable_doorbell_selfring_aperture,
.ih_doorbell_range = nbio_v7_7_ih_doorbell_range,
-- 
2.36.1

Re: [PATCH 5/5] drm/amd/display: move FPU code from dcn301 clk mgr to DML folder

2022-07-21 Thread Maíra Canal

Hi Melissa,

On 7/20/22 16:32, Melissa Wen wrote:
> The -mno-gnu-attribute option in dcn301 clk mgr makefile hides a soft vs
> hard fp error for powerpc. After removing this flag, we can see some FPU
> code remains there:
> 
> gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld:
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses
> hard float,
> drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
> uses soft float
> 
> Therefore, remove the -mno-gnu-attribute flag for dcn301/powerpc and
> move FPU-associated code to DML folder.
> 
> Signed-off-by: Melissa Wen 
> ---
>  .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |  6 --
>  .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c| 86 ++-
>  .../display/dc/clk_mgr/dcn301/vg_clk_mgr.h|  3 +
>  .../amd/display/dc/dml/dcn301/dcn301_fpu.c| 74 
>  4 files changed, 84 insertions(+), 85 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile 
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> index 15b660a951a5..271d8e573181 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> @@ -123,12 +123,6 @@ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)
>  
> ###
>  CLK_MGR_DCN301 = vg_clk_mgr.o dcn301_smu.o
>  
> -# prevent build errors regarding soft-float vs hard-float FP ABI tags
> -# this code is currently unused on ppc64, as it applies to VanGogh APUs only
> -ifdef CONFIG_PPC64
> -CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn301/vg_clk_mgr.o := $(call 
> cc-option,-mno-gnu-attribute)
> -endif
> -
>  AMD_DAL_CLK_MGR_DCN301 = $(addprefix 
> $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301))
>  
>  AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c 
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> index f310b0d25a07..65f224af03c0 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> @@ -32,6 +32,10 @@
>  // For dcn20_update_clocks_update_dpp_dto
>  #include "dcn20/dcn20_clk_mgr.h"
>  
> +// For DML FPU code
> +#include "dml/dcn20/dcn20_fpu.h"
> +#include "dml/dcn301/dcn301_fpu.h"
> +

I guess the "dml/dcn301/dcn301_fpu.h" header is not needed, as you only
use dcn21_clk_mgr_set_bw_params_wm_table and the structs are on the
source file.

Besides that, to the whole series:
Reviewed-by: Maíra Canal 

Best Regards,
- Maíra Canal

>  #include "vg_clk_mgr.h"
>  #include "dcn301_smu.h"
>  #include "reg_helper.h"
> @@ -526,81 +530,6 @@ static struct clk_bw_params vg_bw_params = {
>  
>  };
>  
> -static struct wm_table ddr4_wm_table = {
> - .entries = {
> - {
> - .wm_inst = WM_A,
> - .wm_type = WM_TYPE_PSTATE_CHG,
> - .pstate_latency_us = 11.72,
> - .sr_exit_time_us = 6.09,
> - .sr_enter_plus_exit_time_us = 7.14,
> - .valid = true,
> - },
> - {
> - .wm_inst = WM_B,
> - .wm_type = WM_TYPE_PSTATE_CHG,
> - .pstate_latency_us = 11.72,
> - .sr_exit_time_us = 10.12,
> - .sr_enter_plus_exit_time_us = 11.48,
> - .valid = true,
> - },
> - {
> - .wm_inst = WM_C,
> - .wm_type = WM_TYPE_PSTATE_CHG,
> - .pstate_latency_us = 11.72,
> - .sr_exit_time_us = 10.12,
> - .sr_enter_plus_exit_time_us = 11.48,
> - .valid = true,
> - },
> - {
> - .wm_inst = WM_D,
> - .wm_type = WM_TYPE_PSTATE_CHG,
> - .pstate_latency_us = 11.72,
> - .sr_exit_time_us = 10.12,
> - .sr_enter_plus_exit_time_us = 11.48,
> - .valid = true,
> - },
> - }
> -};
> -
> -static struct wm_table lpddr5_wm_table = {
> - .entries = {
> - {
> - .wm_inst = WM_A,
> - .wm_type = WM_TYPE_PSTATE_CHG,
> - .pstate_latency_us = 11.65333,
> - .sr_exit_time_us = 13.5,
> - .sr_enter_plus_exit_time_us = 16.5,
> - .valid = true,
> - },
> - {
> - .wm_inst = WM_B,
> - .wm_type = WM_TYPE_PSTATE_CHG,
> - .pstate_latency_us = 11.65333,
> - .sr_exit_time_us = 13.5,
> - .sr_enter_plus_exit_time_us = 16.5,
> - .valid = true,
> - },
> - {
> - .wm_inst = WM_C,
> -

Re: [PATCH 1/1] drm/amdkfd: Correct mmu_notifier_get failure handling

2022-07-21 Thread Felix Kuehling


Am 2022-07-21 um 09:44 schrieb Philip Yang:

If process has signal pending, mmu_notifier_get_locked fails and calls
ops->free_notifier, kfd_process_free_notifier will schedule
kfd_process_wq_release as process refcount is 1, but process structure
is already freed. This use after free bug causes system crash with
different backtrace.

The fix is to increase process refcount and then decrease the refcount
after mmu_notifier_get success.

Signed-off-by: Philip Yang 


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index fc38a4d81420..d8591721270b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -1405,6 +1405,11 @@ static struct kfd_process *create_process(const struct 
task_struct *thread)
hash_add_rcu(kfd_processes_table, >kfd_processes,
(uintptr_t)process->mm);
  
+	/* Avoid free_notifier to start kfd_process_wq_release if

+* mmu_notifier_get failed because of pending signal.
+*/
+   kref_get(>ref);
+
/* MMU notifier registration must be the last call that can fail
 * because after this point we cannot unwind the process creation.
 * After this point, mmu_notifier_put will trigger the cleanup by
@@ -1417,6 +1422,7 @@ static struct kfd_process *create_process(const struct 
task_struct *thread)
}
BUG_ON(mn != >mmu_notifier);
  
+	kfd_unref_process(process);

get_task_struct(process->lead_thread);
  
  	return process;

Re: [PATCH 1/6] drm/amdgpu: add CHIP_IP_DISCOVERY support for virtualization

2022-07-21 Thread Alex Deucher

On Thu, Jul 21, 2022 at 5:52 AM Horace Chen  wrote:
>
> For further chips we will use CHIP_IP_DISCOVERY, so add this
> support for virtualization

All current and future chips will use CHIP_IP_DISCOVERY.  If we plan
to keep the register the same for all new aics, this should be fine.
If we might need to have it per asic I think you might want something
more like this:

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 9be57389301b..0bdd71f9a8fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -709,6 +709,16 @@ void amdgpu_detect_virtualization(struct
amdgpu_device *adev)
case CHIP_ALDEBARAN:
reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
break;
+   case CHIP_IP_DISCOVERY:
+   switch (adev->ip_versions[GC_HWIP][0]) {
+   case IP_VERSION(11, 0, 0):
+   reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
+   break;
+   default:
+   reg = 0;
+   break;
+   }
+   break;
default: /* other chip doesn't support SRIOV */
reg = 0;
break;

Alex

>
> Signed-off-by: Horace Chen 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 7d7044e9de2f..ab55602ff534 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -705,6 +705,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device 
> *adev)
> case CHIP_SIENNA_CICHLID:
> case CHIP_ARCTURUS:
> case CHIP_ALDEBARAN:
> +   case CHIP_IP_DISCOVERY:
> reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
> break;
> default: /* other chip doesn't support SRIOV */
> @@ -748,6 +749,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device 
> *adev)
> case CHIP_NAVI10:
> case CHIP_NAVI12:
> case CHIP_SIENNA_CICHLID:
> +   case CHIP_IP_DISCOVERY:
> nv_set_virt_ops(adev);
> /* try send GPU_INIT_DATA request to host */
> amdgpu_virt_request_init_data(adev);
> --
> 2.25.1
>

[PATCH 1/1] drm/amdkfd: Correct mmu_notifier_get failure handling

2022-07-21 Thread Philip Yang

If process has signal pending, mmu_notifier_get_locked fails and calls
ops->free_notifier, kfd_process_free_notifier will schedule
kfd_process_wq_release as process refcount is 1, but process structure
is already freed. This use after free bug causes system crash with
different backtrace.

The fix is to increase process refcount and then decrease the refcount
after mmu_notifier_get success.

Signed-off-by: Philip Yang 
---
 drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index fc38a4d81420..d8591721270b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -1405,6 +1405,11 @@ static struct kfd_process *create_process(const struct 
task_struct *thread)
hash_add_rcu(kfd_processes_table, >kfd_processes,
(uintptr_t)process->mm);
 
+   /* Avoid free_notifier to start kfd_process_wq_release if
+* mmu_notifier_get failed because of pending signal.
+*/
+   kref_get(>ref);
+
/* MMU notifier registration must be the last call that can fail
 * because after this point we cannot unwind the process creation.
 * After this point, mmu_notifier_put will trigger the cleanup by
@@ -1417,6 +1422,7 @@ static struct kfd_process *create_process(const struct 
task_struct *thread)
}
BUG_ON(mn != >mmu_notifier);
 
+   kfd_unref_process(process);
get_task_struct(process->lead_thread);
 
return process;
-- 
2.35.1

Re: [PATCH] mm/gup.c: Fix formating in check_and_migrate_movable_page()

2022-07-21 Thread David Hildenbrand

On 21.07.22 04:05, Alistair Popple wrote:
> Commit b05a79d4377f ("mm/gup: migrate device coherent pages when pinning
> instead of failing") added a badly formatted if statement. Fix it.
> 
> Signed-off-by: Alistair Popple 
> Reported-by: David Hildenbrand 
> ---
> 
> Apologies Andrew for missing this. Hopefully this fixes things.
> 
>  mm/gup.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/mm/gup.c b/mm/gup.c
> index 364b274a10c2..c6d060dee9e0 100644
> --- a/mm/gup.c
> +++ b/mm/gup.c
> @@ -1980,8 +1980,8 @@ static long check_and_migrate_movable_pages(unsigned 
> long nr_pages,
>   folio_nr_pages(folio));
>   }
>  
> - if (!list_empty(_page_list) || isolation_error_count
> - || coherent_pages)
> + if (!list_empty(_page_list) || isolation_error_count ||
> + coherent_pages)
>   goto unpin_pages;
>  
>   /*

Happy to see the series go upstream soon.

Reviewed-by: David Hildenbrand 

-- 
Thanks,

David / dhildenb

Re: [PATCH 2/4] drm/amd/display: Remove duplicated CalculateWriteBackDISPCLK

2022-07-21 Thread André Almeida

Às 15:22 de 20/07/22, Maíra Canal escreveu:
> The functions dml30_CalculateWriteBackDISPCLK and
> dml31_CalculateWriteBackDISPCLK are identical. Therefor, to avoid
> code duplication, dml31_CalculateWriteBackDISPCLK is removed and
> replaced by dml30_CalculateWriteBackDISPCLK.
> 

The message should be in imperative mood:

"to avoid code duplication, dml31_CalculateWriteBackDISPCLK is removed
and replaced by dml30_CalculateWriteBackDISPCLK." -> "to avoid code
duplication, replace dml31_CalculateWriteBackDISPCLK by
dml30_CalculateWriteBackDISPCLK"

> Signed-off-by: Maíra Canal 
> ---

Re: [PATCH 1/4] drm/amd/display: Drop dm_sw_gfx7_2d_thin_l_vp and dm_sw_gfx7_2d_thin_gl

2022-07-21 Thread André Almeida

Às 15:22 de 20/07/22, Maíra Canal escreveu:
> As the enum dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp are not
> used on the codebase, this commit drops those entries from enum
> dm_swizzle_mode.
> 

dm_sw_gfx7_2d_thin_gl and dm_sw_gfx7_2d_thin_l_vp are not enums, but
rather enum items or enum entries.

And, as per Linux documentation

Describe your changes in imperative mood, e.g. “make xyzzy do frotz”
instead of “[This patch] makes xyzzy do frotz”

So replace /this commit drops/drop/

> Signed-off-by: Maíra Canal 
> ---
>  .../dc/dml/dcn20/display_mode_vba_20.c| 26 +-
>  .../dc/dml/dcn20/display_mode_vba_20v2.c  | 26 +-
>  .../dc/dml/dcn21/display_mode_vba_21.c| 27 +--
>  .../amd/display/dc/dml/display_mode_enums.h   |  2 --
>  .../display/dc/dml/dml_wrapper_translation.c  |  9 ---
>  5 files changed, 19 insertions(+), 71 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> index d3b5b6fedf04..4e4cb0927057 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> @@ -938,7 +938,7 @@ static unsigned int CalculateVMAndRowBytes(
>   *MetaRowByte = 0;
>   }
>  
> - if (SurfaceTiling == dm_sw_linear || SurfaceTiling == 
> dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {
> + if (SurfaceTiling == dm_sw_linear) {
>   MacroTileSizeBytes = 256;
>   MacroTileHeight = BlockHeight256Bytes;
>   } else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == 
> dm_sw_4kb_s_x
> @@ -3347,26 +3347,12 @@ void 
> dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
>   
> == dm_420_8
>   || 
> mode_lib->vba.SourcePixelFormat[k]
>   
> == dm_420_10))
> - || (((mode_lib->vba.SurfaceTiling[k] == 
> dm_sw_gfx7_2d_thin_gl
> - || 
> mode_lib->vba.SurfaceTiling[k]
> - == 
> dm_sw_gfx7_2d_thin_l_vp)
> - && 
> !((mode_lib->vba.SourcePixelFormat[k]
> - == dm_444_64
> + || (mode_lib->vba.DCCEnable[k] == true
> + && 
> (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>   || 
> mode_lib->vba.SourcePixelFormat[k]
> - 
> == dm_444_32)
> - && 
> mode_lib->vba.SourceScan[k]
> - 
> == dm_horz
> - && 
> mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
> - 
> == true
> - && 
> mode_lib->vba.DCCEnable[k]
> - 
> == false))
> - || (mode_lib->vba.DCCEnable[k] 
> == true
> - && 
> (mode_lib->vba.SurfaceTiling[k]
> - 
> == dm_sw_linear
> - 
> || mode_lib->vba.SourcePixelFormat[k]
> - 
> == dm_420_8
> - 
> || mode_lib->vba.SourcePixelFormat[k]
> - 
> == dm_420_10 {
> + 
> == dm_420_8
> + || 
> mode_lib->vba.SourcePixelFormat[k]
> + 
> == dm_420_10))) {
>   mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>   }
>   }
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> index 63bbdf8b8678..eaa0cdb599ba 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

Re: [PATCH] drm/amd/pm: Add get_gfx_off_status interface

2022-07-21 Thread André Almeida

Hi Shikai,

Could you change the commit message to

 drm/amd/pm: Add get_gfx_off_status interface for yellow carp

Otherwise, we are going to have duplicated commit messages for each new
architecture supporting get_gfx_off_status.

Also, giving that this is the second version of your patch, the subject
should be [PATCH v2], and the patch should contain a changelog compared
to the previous patch version.

Às 05:57 de 21/07/22, shikai@amd.com escreveu:
> From: Shikai Guo 
> 
> add get_gfx_off_status interface to yellow_carp_ppt_funcs structure.
> 
> Signed-off-by: Shikai Guo 


Thanks,
André

Re: [PATCH] drm/amd/pm: Add get_gfx_off_status interface

2022-07-21 Thread Lazar, Lijo





On 7/21/2022 2:27 PM, shikai@amd.com wrote:

From: Shikai Guo 

add get_gfx_off_status interface to yellow_carp_ppt_funcs structure.

Signed-off-by: Shikai Guo 
---
  .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  | 30 +++
  1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 70cbc46341a3..2e39b629e7e6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -31,6 +31,7 @@
  #include "smu_v13_0_1_ppsmc.h"
  #include "smu_v13_0_1_pmfw.h"
  #include "smu_cmn.h"
+#include "asic_reg/smuio/smuio_13_0_2_offset.h"
  
  /*

   * DO NOT use these for err/warn/info/debug messages.
@@ -42,6 +43,9 @@
  #undef pr_info
  #undef pr_debug
  
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK		0x0006L

+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT  0x1
+
  #define FEATURE_MASK(feature) (1ULL << feature)
  #define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -587,6 +591,31 @@ static ssize_t yellow_carp_get_gpu_metrics(struct 
smu_context *smu,
return sizeof(struct gpu_metrics_v2_1);
  }
  
+/**

+ * yellow_carp_get_gfxoff_status - get gfxoff status
+ *
+ * @smu: smu_context pointer
+ *
+ * This function will be used to get gfxoff status
+ *
+ * Returns 0=GFXOFF(default).
+ * Returns 1=Transition out of GFX State.
+ * Returns 2=Not in GFXOFF.
+ * Returns 3=Transition into GFXOFF.
+ */


This is a public API (amdgpu_dpm). Hope the final status is consistent 
with whatever is already defined for other ASICs.



+static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
+{
+   uint32_t reg;
+   uint32_t gfxOff_Status = 0;


Mixed-case names are not part of coding style.

With that change
Reviewed-by: Lijo Lazar 

Thanks,
Lijo


+   struct amdgpu_device *adev = smu->adev;
+
+   reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
+   gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
+   >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
+
+   return gfxOff_Status;
+}
+
  static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)
  {
struct smu_table_context *smu_table = >smu_table;
@@ -1186,6 +1215,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = 
{
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_driver_table_location = smu_v13_0_set_driver_table_location,
.gfx_off_control = smu_v13_0_gfx_off_control,
+   .get_gfx_off_status = yellow_carp_get_gfxoff_status,
.post_init = yellow_carp_post_smu_init,
.mode2_reset = yellow_carp_mode2_reset,
.get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,

[PATCH 6/6] drm/amdgpu: sriov remove vcn_4_0 and jpeg_4_0

2022-07-21 Thread Horace Chen

SRIOV needs to initialize mmsch instead of multimedia engines
directly. So currently remove them for SR-IOV until the code and
firmwares are ready.

Signed-off-by: Horace Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index f559fda2811f..3f7e1d683df3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1900,8 +1900,10 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct 
amdgpu_device *adev)
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 2):
case IP_VERSION(4, 0, 4):
-   amdgpu_device_ip_block_add(adev, _v4_0_ip_block);
-   amdgpu_device_ip_block_add(adev, _v4_0_ip_block);
+   if (!amdgpu_sriov_vf(adev)) {
+   amdgpu_device_ip_block_add(adev, 
_v4_0_ip_block);
+   amdgpu_device_ip_block_add(adev, 
_v4_0_ip_block);
+   }
break;
default:
dev_err(adev->dev,
-- 
2.25.1

[PATCH 5/6] drm/amdgpu: refine virtualization psp fw skip check

2022-07-21 Thread Horace Chen

SR-IOV may need to load different firmwares for different ASIC inside
VF.
So create a new function in amdgpu_virt to check whether FW load needs
to be skipped.

Signed-off-by: Horace Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c  | 17 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 29 
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h |  2 ++
 3 files changed, 34 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 6540582ecbf8..a601d0f67b1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -334,11 +334,12 @@ static int psp_init_sriov_microcode(struct psp_context 
*psp)
ret = psp_init_cap_microcode(psp, "aldebaran");
ret &= psp_init_ta_microcode(psp, "aldebaran");
break;
+   case IP_VERSION(13, 0, 0):
+   break;
default:
BUG();
break;
}
-
return ret;
 }
 
@@ -2389,19 +2390,7 @@ static bool fw_load_skip_check(struct psp_context *psp,
return true;
 
if (amdgpu_sriov_vf(psp->adev) &&
-  (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
-   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
-   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
-   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
-   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
-   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
-   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
-   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
-   || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
-   || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
-   || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
-   || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
-   || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
+   amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
/*skip ucode loading in SRIOV VF */
return true;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index ab55602ff534..ba367799d087 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -807,6 +807,35 @@ enum amdgpu_sriov_vf_mode 
amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad
return mode;
 }
 
+bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t 
ucode_id)
+{
+   /* this version doesn't support sriov autoload */
+   if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 0)) {
+   if (ucode_id == AMDGPU_UCODE_ID_VCN1 ||
+   ucode_id == AMDGPU_UCODE_ID_VCN)
+   return false;
+   else
+   return true;
+   }
+
+   if (ucode_id == AMDGPU_UCODE_ID_SDMA0
+   || ucode_id == AMDGPU_UCODE_ID_SDMA1
+   || ucode_id == AMDGPU_UCODE_ID_SDMA2
+   || ucode_id == AMDGPU_UCODE_ID_SDMA3
+   || ucode_id == AMDGPU_UCODE_ID_SDMA4
+   || ucode_id == AMDGPU_UCODE_ID_SDMA5
+   || ucode_id == AMDGPU_UCODE_ID_SDMA6
+   || ucode_id == AMDGPU_UCODE_ID_SDMA7
+   || ucode_id == AMDGPU_UCODE_ID_RLC_G
+   || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
+   || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
+   || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
+   || ucode_id == AMDGPU_UCODE_ID_SMC)
+   return true;
+
+   return false;
+}
+
 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
struct amdgpu_video_codec_info *encode, uint32_t 
encode_array_size,
struct amdgpu_video_codec_info *decode, uint32_t 
decode_array_size)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 239f232f9c02..cd6fce05978f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -343,4 +343,6 @@ void amdgpu_sriov_wreg(struct amdgpu_device *adev,
   u32 acc_flags, u32 hwip);
 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
  u32 offset, u32 acc_flags, u32 hwip);
+bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
+   uint32_t ucode_id);
 #endif
-- 
2.25.1

[PATCH 4/6] drm/amdgpu: enable WPTR_POLL_ENABLE for sriov on sdma_v6_0

2022-07-21 Thread Horace Chen

[Why]
Under SR-IOV, if VF is switched out then its doorbell will be disabled,
SDMA rely on WPTR_POLL to get doorbells which was sent during VF
switched-out time.

[How]
For SR-IOV, set SDMA WPTR_POLL_ENABLE to 1.

Signed-off-by: Horace Chen 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 0200cb3a31a4..23b01b121492 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -593,7 +593,10 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
   lower_32_bits(ring->rptr_gpu_addr) & 0xFFFC);
 
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 
RPTR_WRITEBACK_ENABLE, 1);
-   rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 
WPTR_POLL_ENABLE, 0);
+   if (amdgpu_sriov_vf(adev))
+   rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 
WPTR_POLL_ENABLE, 1);
+   else
+   rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 
WPTR_POLL_ENABLE, 0);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 
F32_WPTR_POLL_ENABLE, 1);
 
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, 
regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
-- 
2.25.1

[PATCH 3/6] drm/amdgpu: add a compute pipe reset for SR-IOV

2022-07-21 Thread Horace Chen

[Why]
Under SR-IOV, we are not sure whether pipe status is
good or not when doing initialization. The compute engine
maybe fail to bringup if pipe status is bad.

[How]
For SR-IOV, disable the compute engine to do a pipe reset
before we do initialization.

Signed-off-by: Horace Chen 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 0d8193b30fc5..b8f197a5ee84 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4586,8 +4586,12 @@ static int gfx_v11_0_hw_init(void *handle)
DRM_WARN("Invalid gb_addr_config !\n");
 
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
-   adev->gfx.rs64_enable)
+   adev->gfx.rs64_enable) {
+   if (amdgpu_sriov_vf(adev))
+   gfx_v11_0_cp_compute_enable(adev, false);
+
gfx_v11_0_config_gfx_rs64(adev);
+   }
 
r = gfx_v11_0_gfxhub_enable(adev);
if (r)
-- 
2.25.1

[PATCH 2/6] drm/amdgpu: add sriov nbio callback structure

2022-07-21 Thread Horace Chen

[Why]
under SR-IOV, the nbio doorbell range will be defined by PF. So VF
nbio doorbell range registers will be blocked. It will cause violation
if VF access those registers directly.

[How]
create an nbio_v4_3_sriov_funcs for sriov nbio_v4_3 initialization to
skip the setting for the doorbell range registers.

Signed-off-by: Horace Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |  5 ++-
 drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c| 44 +++
 drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h|  1 +
 3 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 242d1847c4aa..f559fda2811f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2232,7 +2232,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device 
*adev)
break;
case IP_VERSION(4, 3, 0):
case IP_VERSION(4, 3, 1):
-   adev->nbio.funcs = _v4_3_funcs;
+   if (amdgpu_sriov_vf(adev))
+   adev->nbio.funcs = _v4_3_sriov_funcs;
+   else
+   adev->nbio.funcs = _v4_3_funcs;
adev->nbio.hdp_flush_reg = _v4_3_hdp_flush_reg;
break;
case IP_VERSION(7, 7, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
index 982a89f841d5..15eb3658d70e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
@@ -488,3 +488,47 @@ const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
.get_rom_offset = nbio_v4_3_get_rom_offset,
.program_aspm = nbio_v4_3_program_aspm,
 };
+
+
+static void nbio_v4_3_sriov_ih_doorbell_range(struct amdgpu_device *adev,
+   bool use_doorbell, int doorbell_index)
+{
+}
+
+static void nbio_v4_3_sriov_sdma_doorbell_range(struct amdgpu_device *adev, 
int instance,
+ bool use_doorbell, int doorbell_index,
+ int doorbell_size)
+{
+}
+
+static void nbio_v4_3_sriov_vcn_doorbell_range(struct amdgpu_device *adev, 
bool use_doorbell,
+int doorbell_index, int instance)
+{
+}
+
+static void nbio_v4_3_sriov_gc_doorbell_init(struct amdgpu_device *adev)
+{
+}
+
+const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs = {
+   .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,
+   .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,
+   .get_pcie_index_offset = nbio_v4_3_get_pcie_index_offset,
+   .get_pcie_data_offset = nbio_v4_3_get_pcie_data_offset,
+   .get_rev_id = nbio_v4_3_get_rev_id,
+   .mc_access_enable = nbio_v4_3_mc_access_enable,
+   .get_memsize = nbio_v4_3_get_memsize,
+   .sdma_doorbell_range = nbio_v4_3_sriov_sdma_doorbell_range,
+   .vcn_doorbell_range = nbio_v4_3_sriov_vcn_doorbell_range,
+   .gc_doorbell_init = nbio_v4_3_sriov_gc_doorbell_init,
+   .enable_doorbell_aperture = nbio_v4_3_enable_doorbell_aperture,
+   .enable_doorbell_selfring_aperture = 
nbio_v4_3_enable_doorbell_selfring_aperture,
+   .ih_doorbell_range = nbio_v4_3_sriov_ih_doorbell_range,
+   .update_medium_grain_clock_gating = 
nbio_v4_3_update_medium_grain_clock_gating,
+   .update_medium_grain_light_sleep = 
nbio_v4_3_update_medium_grain_light_sleep,
+   .get_clockgating_state = nbio_v4_3_get_clockgating_state,
+   .ih_control = nbio_v4_3_ih_control,
+   .init_registers = nbio_v4_3_init_registers,
+   .remap_hdp_registers = nbio_v4_3_remap_hdp_registers,
+   .get_rom_offset = nbio_v4_3_get_rom_offset,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h 
b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h
index ade43661d7a9..711999ceedf4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h
@@ -28,5 +28,6 @@
 
 extern const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg;
 extern const struct amdgpu_nbio_funcs nbio_v4_3_funcs;
+extern const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs;
 
 #endif
-- 
2.25.1

[PATCH 1/6] drm/amdgpu: add CHIP_IP_DISCOVERY support for virtualization

2022-07-21 Thread Horace Chen

For further chips we will use CHIP_IP_DISCOVERY, so add this
support for virtualization

Signed-off-by: Horace Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 7d7044e9de2f..ab55602ff534 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -705,6 +705,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device 
*adev)
case CHIP_SIENNA_CICHLID:
case CHIP_ARCTURUS:
case CHIP_ALDEBARAN:
+   case CHIP_IP_DISCOVERY:
reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
break;
default: /* other chip doesn't support SRIOV */
@@ -748,6 +749,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device 
*adev)
case CHIP_NAVI10:
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
+   case CHIP_IP_DISCOVERY:
nv_set_virt_ops(adev);
/* try send GPU_INIT_DATA request to host */
amdgpu_virt_request_init_data(adev);
-- 
2.25.1

[PATCH] drm/amd/pm: Add get_gfx_off_status interface

2022-07-21 Thread shikai.guo

From: Shikai Guo 

add get_gfx_off_status interface to yellow_carp_ppt_funcs structure.

Signed-off-by: Shikai Guo 
---
 .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  | 30 +++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 70cbc46341a3..2e39b629e7e6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -31,6 +31,7 @@
 #include "smu_v13_0_1_ppsmc.h"
 #include "smu_v13_0_1_pmfw.h"
 #include "smu_cmn.h"
+#include "asic_reg/smuio/smuio_13_0_2_offset.h"
 
 /*
  * DO NOT use these for err/warn/info/debug messages.
@@ -42,6 +43,9 @@
 #undef pr_info
 #undef pr_debug
 
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK0x0006L
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT  0x1
+
 #define FEATURE_MASK(feature) (1ULL << feature)
 #define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -587,6 +591,31 @@ static ssize_t yellow_carp_get_gpu_metrics(struct 
smu_context *smu,
return sizeof(struct gpu_metrics_v2_1);
 }
 
+/**
+ * yellow_carp_get_gfxoff_status - get gfxoff status
+ *
+ * @smu: smu_context pointer
+ *
+ * This function will be used to get gfxoff status
+ *
+ * Returns 0=GFXOFF(default).
+ * Returns 1=Transition out of GFX State.
+ * Returns 2=Not in GFXOFF.
+ * Returns 3=Transition into GFXOFF.
+ */
+static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
+{
+   uint32_t reg;
+   uint32_t gfxOff_Status = 0;
+   struct amdgpu_device *adev = smu->adev;
+
+   reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
+   gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
+   >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
+
+   return gfxOff_Status;
+}
+
 static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)
 {
struct smu_table_context *smu_table = >smu_table;
@@ -1186,6 +1215,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = 
{
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_driver_table_location = smu_v13_0_set_driver_table_location,
.gfx_off_control = smu_v13_0_gfx_off_control,
+   .get_gfx_off_status = yellow_carp_get_gfxoff_status,
.post_init = yellow_carp_post_smu_init,
.mode2_reset = yellow_carp_mode2_reset,
.get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
-- 
2.25.1

[PATCH] drm/amd: Fix typo 'the the' in comment

2022-07-21 Thread Slark Xiao

Replace 'the the' with 'the' in the comment.

Signed-off-by: Slark Xiao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
 drivers/gpu/drm/amd/include/atombios.h| 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index ff659d4f772b..8adeb7469f1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -47,7 +47,7 @@
  * for GPU/CPU synchronization.  When the fence is written,
  * it is expected that all buffers associated with that fence
  * are no longer in use by the associated ring on the GPU and
- * that the the relevant GPU caches have been flushed.
+ * that the relevant GPU caches have been flushed.
  */
 
 struct amdgpu_fence {
diff --git a/drivers/gpu/drm/amd/include/atombios.h 
b/drivers/gpu/drm/amd/include/atombios.h
index 1f9df4e7509b..15943bc21bc5 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -3255,8 +3255,8 @@ ucMaxNBVoltageHigh: Voltage regulator dependent PWM 
value. High 8 bits of  t
 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of 
the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC 
at all.
 
 
-usInterNBVoltageLow:Voltage regulator dependent PWM value. The value makes 
the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x 
if VC without PWM or no VC at all.
-usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes 
the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x if 
VC without PWM or no VC at all.
+usInterNBVoltageLow:Voltage regulator dependent PWM value. The value makes 
the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x if VC 
without PWM or no VC at all.
+usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes 
the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x if VC 
without PWM or no VC at all.
 */
 
 
-- 
2.25.1

RE: [PATCH] drm/admdgpu: Add get_gfx_off_status interface

2022-07-21 Thread Liang, Prike

[Public]

It looks like the amdgpu_device pointer declaration is useless, please clean it 
up.
Meanwhile need correct the patch subject prefix to drm/amd/pm: instead of 
drm/admdgpu.

With the above fixed the patch is Reviewed-by: Prike Liang 

> -Original Message-
> From: Guo, Shikai 
> Sent: Thursday, July 21, 2022 2:20 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan ; Deucher, Alexander
> ; Liang, Prike ; Guo,
> Shikai ; Guo, Shikai 
> Subject: [PATCH] drm/admdgpu: Add get_gfx_off_status interface
>
> From: Shikai Guo 
>
> add get_gfx_off_status interface to yellow_carp_ppt_funcs structure.
>
> Signed-off-by: Shikai Guo 
> ---
>  .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  | 30
> +++
>  1 file changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index 70cbc46341a3..cac48121d72b 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -31,6 +31,7 @@
>  #include "smu_v13_0_1_ppsmc.h"
>  #include "smu_v13_0_1_pmfw.h"
>  #include "smu_cmn.h"
> +#include "asic_reg/smuio/smuio_13_0_2_offset.h"
>
>  /*
>   * DO NOT use these for err/warn/info/debug messages.
> @@ -42,6 +43,9 @@
>  #undef pr_info
>  #undef pr_debug
>
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
>   0x0006L
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT
>   0x1
> +
>  #define FEATURE_MASK(feature) (1ULL << feature)  #define
> SMC_DPM_FEATURE ( \
>   FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -587,6 +591,31
> @@ static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
>   return sizeof(struct gpu_metrics_v2_1);  }
>
> +/**
> + * yellow_carp_get_gfxoff_status - get gfxoff status
> + *
> + * @smu: amdgpu_device pointer
> + *
> + * This function will be used to get gfxoff status
> + *
> + * Returns 0=GFXOFF(default).
> + * Returns 1=Transition out of GFX State.
> + * Returns 2=Not in GFXOFF.
> + * Returns 3=Transition into GFXOFF.
> + */
> +static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
> +{
> + uint32_t reg;
> + uint32_t gfxOff_Status = 0;
> + struct amdgpu_device *adev = smu->adev;
> +
> + reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
> + gfxOff_Status = (reg &
> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
> + >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
> +
> + return gfxOff_Status;
> +}
> +
>  static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)  {
>   struct smu_table_context *smu_table = >smu_table; @@ -
> 1186,6 +1215,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs
> = {
>   .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
>   .set_driver_table_location = smu_v13_0_set_driver_table_location,
>   .gfx_off_control = smu_v13_0_gfx_off_control,
> + .get_gfx_off_status = yellow_carp_get_gfxoff_status,
>   .post_init = yellow_carp_post_smu_init,
>   .mode2_reset = yellow_carp_mode2_reset,
>   .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
> --
> 2.25.1

RE: [PATCH] drm/admdgpu: Add get_gfx_off_status interface

2022-07-21 Thread Chen, Guchun

*@smu: amdgpu_device pointer

I guess a typo here, smu is not amdgpu device pointer.

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of 
shikai@amd.com
Sent: Thursday, July 21, 2022 2:20 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Liang, Prike 
; Quan, Evan ; Guo, Shikai 

Subject: [PATCH] drm/admdgpu: Add get_gfx_off_status interface

From: Shikai Guo 

add get_gfx_off_status interface to yellow_carp_ppt_funcs structure.

Signed-off-by: Shikai Guo 
---
 .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  | 30 +++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 70cbc46341a3..cac48121d72b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -31,6 +31,7 @@
 #include "smu_v13_0_1_ppsmc.h"
 #include "smu_v13_0_1_pmfw.h"
 #include "smu_cmn.h"
+#include "asic_reg/smuio/smuio_13_0_2_offset.h"
 
 /*
  * DO NOT use these for err/warn/info/debug messages.
@@ -42,6 +43,9 @@
 #undef pr_info
 #undef pr_debug
 
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK0x0006L
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT  0x1
+
 #define FEATURE_MASK(feature) (1ULL << feature)  #define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -587,6 +591,31 @@ static 
ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
return sizeof(struct gpu_metrics_v2_1);  }
 
+/**
+ * yellow_carp_get_gfxoff_status - get gfxoff status
+ *
+ * @smu: amdgpu_device pointer
+ *
+ * This function will be used to get gfxoff status
+ *
+ * Returns 0=GFXOFF(default).
+ * Returns 1=Transition out of GFX State.
+ * Returns 2=Not in GFXOFF.
+ * Returns 3=Transition into GFXOFF.
+ */
+static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu) 
+{
+   uint32_t reg;
+   uint32_t gfxOff_Status = 0;
+   struct amdgpu_device *adev = smu->adev;
+
+   reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
+   gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
+   >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
+
+   return gfxOff_Status;
+}
+
 static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)  {
struct smu_table_context *smu_table = >smu_table; @@ -1186,6 
+1215,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = {
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_driver_table_location = smu_v13_0_set_driver_table_location,
.gfx_off_control = smu_v13_0_gfx_off_control,
+   .get_gfx_off_status = yellow_carp_get_gfxoff_status,
.post_init = yellow_carp_post_smu_init,
.mode2_reset = yellow_carp_mode2_reset,
.get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
--
2.25.1

RE: [PATCH] drm/admdgpu: Add get_gfx_off_status interface

2022-07-21 Thread Quan, Evan

[AMD Official Use Only - General]

Reviewed-by: Evan Quan 

> -Original Message-
> From: Guo, Shikai 
> Sent: Thursday, July 21, 2022 2:20 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan ; Deucher, Alexander
> ; Liang, Prike ; Guo,
> Shikai ; Guo, Shikai 
> Subject: [PATCH] drm/admdgpu: Add get_gfx_off_status interface
> 
> From: Shikai Guo 
> 
> add get_gfx_off_status interface to yellow_carp_ppt_funcs structure.
> 
> Signed-off-by: Shikai Guo 
> ---
>  .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  | 30
> +++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index 70cbc46341a3..cac48121d72b 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -31,6 +31,7 @@
>  #include "smu_v13_0_1_ppsmc.h"
>  #include "smu_v13_0_1_pmfw.h"
>  #include "smu_cmn.h"
> +#include "asic_reg/smuio/smuio_13_0_2_offset.h"
> 
>  /*
>   * DO NOT use these for err/warn/info/debug messages.
> @@ -42,6 +43,9 @@
>  #undef pr_info
>  #undef pr_debug
> 
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
>   0x0006L
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT
>   0x1
> +
>  #define FEATURE_MASK(feature) (1ULL << feature)
>  #define SMC_DPM_FEATURE ( \
>   FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
> @@ -587,6 +591,31 @@ static ssize_t yellow_carp_get_gpu_metrics(struct
> smu_context *smu,
>   return sizeof(struct gpu_metrics_v2_1);
>  }
> 
> +/**
> + * yellow_carp_get_gfxoff_status - get gfxoff status
> + *
> + * @smu: amdgpu_device pointer
> + *
> + * This function will be used to get gfxoff status
> + *
> + * Returns 0=GFXOFF(default).
> + * Returns 1=Transition out of GFX State.
> + * Returns 2=Not in GFXOFF.
> + * Returns 3=Transition into GFXOFF.
> + */
> +static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
> +{
> + uint32_t reg;
> + uint32_t gfxOff_Status = 0;
> + struct amdgpu_device *adev = smu->adev;
> +
> + reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
> + gfxOff_Status = (reg &
> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
> + >>
> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
> +
> + return gfxOff_Status;
> +}
> +
>  static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)
>  {
>   struct smu_table_context *smu_table = >smu_table;
> @@ -1186,6 +1215,7 @@ static const struct pptable_funcs
> yellow_carp_ppt_funcs = {
>   .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
>   .set_driver_table_location = smu_v13_0_set_driver_table_location,
>   .gfx_off_control = smu_v13_0_gfx_off_control,
> + .get_gfx_off_status = yellow_carp_get_gfxoff_status,
>   .post_init = yellow_carp_post_smu_init,
>   .mode2_reset = yellow_carp_mode2_reset,
>   .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
> --
> 2.25.1

[PATCH] drm/admdgpu: Add get_gfx_off_status interface

2022-07-21 Thread shikai.guo

From: Shikai Guo 

add get_gfx_off_status interface to yellow_carp_ppt_funcs structure.

Signed-off-by: Shikai Guo 
---
 .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  | 30 +++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 70cbc46341a3..cac48121d72b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -31,6 +31,7 @@
 #include "smu_v13_0_1_ppsmc.h"
 #include "smu_v13_0_1_pmfw.h"
 #include "smu_cmn.h"
+#include "asic_reg/smuio/smuio_13_0_2_offset.h"
 
 /*
  * DO NOT use these for err/warn/info/debug messages.
@@ -42,6 +43,9 @@
 #undef pr_info
 #undef pr_debug
 
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK0x0006L
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT  0x1
+
 #define FEATURE_MASK(feature) (1ULL << feature)
 #define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -587,6 +591,31 @@ static ssize_t yellow_carp_get_gpu_metrics(struct 
smu_context *smu,
return sizeof(struct gpu_metrics_v2_1);
 }
 
+/**
+ * yellow_carp_get_gfxoff_status - get gfxoff status
+ *
+ * @smu: amdgpu_device pointer
+ *
+ * This function will be used to get gfxoff status
+ *
+ * Returns 0=GFXOFF(default).
+ * Returns 1=Transition out of GFX State.
+ * Returns 2=Not in GFXOFF.
+ * Returns 3=Transition into GFXOFF.
+ */
+static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
+{
+   uint32_t reg;
+   uint32_t gfxOff_Status = 0;
+   struct amdgpu_device *adev = smu->adev;
+
+   reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
+   gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
+   >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
+
+   return gfxOff_Status;
+}
+
 static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)
 {
struct smu_table_context *smu_table = >smu_table;
@@ -1186,6 +1215,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = 
{
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_driver_table_location = smu_v13_0_set_driver_table_location,
.gfx_off_control = smu_v13_0_gfx_off_control,
+   .get_gfx_off_status = yellow_carp_get_gfxoff_status,
.post_init = yellow_carp_post_smu_init,
.mode2_reset = yellow_carp_mode2_reset,
.get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
-- 
2.25.1

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