Re: [bug report] drm/amdgpu: create I2S platform devices for Jadeite platform
On 7/26/22 8:47 PM, Dan Carpenter wrote:
> Hello Vijendar Mukunda,
>
> The patch 4c33e5179ff1: "drm/amdgpu: create I2S platform devices for
> Jadeite platform" from Jun 30, 2022, leads to the following Smatch
> static checker warning:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:393 acp_hw_init()
> error: buffer overflow 'i2s_pdata' 3 <= 3
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:396 acp_hw_init()
> error: buffer overflow 'i2s_pdata' 3 <= 3
will fix it and provide a patch.
--
Vijendar
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> 225 static int acp_hw_init(void *handle)
> 226 {
> 227 int r;
> 228 u64 acp_base;
> 229 u32 val = 0;
> 230 u32 count = 0;
> 231 struct i2s_platform_data *i2s_pdata = NULL;
> 232
> 233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 234
> 235 const struct amdgpu_ip_block *ip_block =
> 236 amdgpu_device_ip_get_ip_block(adev,
> AMD_IP_BLOCK_TYPE_ACP);
> 237
> 238 if (!ip_block)
> 239 return -EINVAL;
> 240
> 241 r = amd_acp_hw_init(adev->acp.cgs_device,
> 242 ip_block->version->major,
> ip_block->version->minor);
> 243 /* -ENODEV means board uses AZ rather than ACP */
> 244 if (r == -ENODEV) {
> 245 amdgpu_dpm_set_powergating_by_smu(adev,
> AMD_IP_BLOCK_TYPE_ACP, true);
> 246 return 0;
> 247 } else if (r) {
> 248 return r;
> 249 }
> 250
> 251 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
> 252 return -EINVAL;
> 253
> 254 acp_base = adev->rmmio_base;
> 255 adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain),
> GFP_KERNEL);
> 256 if (!adev->acp.acp_genpd)
> 257 return -ENOMEM;
> 258
> 259 adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
> 260 adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
> 261 adev->acp.acp_genpd->gpd.power_on = acp_poweron;
> 262 adev->acp.acp_genpd->adev = adev;
> 263
> 264 pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
> 265 dmi_check_system(acp_quirk_table);
> 266 switch (acp_machine_id) {
> 267 case ST_JADEITE:
> 268 {
> 269 adev->acp.acp_cell = kcalloc(2, sizeof(struct
> mfd_cell),
> 270 GFP_KERNEL);
> 271 if (!adev->acp.acp_cell) {
> 272 r = -ENOMEM;
> 273 goto failure;
> 274 }
> 275
> 276 adev->acp.acp_res = kcalloc(3, sizeof(struct
> resource), GFP_KERNEL);
> 277 if (!adev->acp.acp_res) {
> 278 r = -ENOMEM;
> 279 goto failure;
> 280 }
> 281
> 282 i2s_pdata = kcalloc(1, sizeof(struct
> i2s_platform_data), GFP_KERNEL);
> 283 if (!i2s_pdata) {
> 284 r = -ENOMEM;
> 285 goto failure;
> 286 }
> 287
> 288 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
> 289 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
> 290 i2s_pdata[0].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
> 291 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
> 292 i2s_pdata[0].i2s_reg_comp1 =
> ACP_I2S_COMP1_CAP_REG_OFFSET;
> 293 i2s_pdata[0].i2s_reg_comp2 =
> ACP_I2S_COMP2_CAP_REG_OFFSET;
> 294
> 295 adev->acp.acp_res[0].name = "acp2x_dma";
> 296 adev->acp.acp_res[0].flags = IORESOURCE_MEM;
> 297 adev->acp.acp_res[0].start = acp_base;
> 298 adev->acp.acp_res[0].end = acp_base +
> ACP_DMA_REGS_END;
> 299
> 300 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play_cap";
> 301 adev->acp.acp_res[1].flags = IORESOURCE_MEM;
> 302 adev->acp.acp_res[1].start = acp_base +
> ACP_I2S_CAP_REGS_START;
> 303 adev->acp.acp_res[1].end = acp_base +
> ACP_I2S_CAP_REGS_END;
> 304
> 305 adev->acp.acp_res[2].name = "acp2x_dma_irq";
> 306 adev->acp.acp_res[2].flags = IORESOURCE_IRQ;
> 307 adev->acp.acp_res[2].start =
> amdgpu_irq_create_mapping(adev, 162);
> 308 adev->acp.acp_res[2].end = adev->acp.acp_res[2].start;
> 309
> 310 adev->acp.acp_cell[0].name = "acp_audio_dma";
> 311 adev->acp.acp_cell[0].num_resources
[PATCH v2] drm/ttm: Fix dummy res NULL ptr deref bug
Check the bo->resource value before accessing the resource mem_type. v2: Fix commit description unwrapped warning [ 40.191227][ T184] general protection fault, probably for non-canonical address 0xdc02: [#1] SMP KASAN PTI [ 40.192995][ T184] KASAN: null-ptr-deref in range [0x0010-0x0017] [ 40.194411][ T184] CPU: 1 PID: 184 Comm: systemd-udevd Not tainted 5.19.0-rc4-00721-gb297c22b7070 #1 [ 40.196063][ T184] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.16.0-debian-1.16.0-4 04/01/2014 [ 40.199605][ T184] RIP: 0010:ttm_bo_validate+0x1b3/0x240 [ttm] [ 40.200754][ T184] Code: e8 72 c5 ff ff 83 f8 b8 74 d4 85 c0 75 54 49 8b 9e 58 01 00 00 48 b8 00 00 00 00 00 fc ff df 48 8d 7b 10 48 89 fa 48 c1 ea 03 <0f> b6 04 02 84 c0 74 04 3c 03 7e 44 8b 53 10 31 c0 85 d2 0f 85 58 [ 40.203685][ T184] RSP: 0018:c96df0c8 EFLAGS: 00010202 [ 40.204630][ T184] RAX: dc00 RBX: RCX: 11102f4bb71b [ 40.205864][ T184] RDX: 0002 RSI: c96df208 RDI: 0010 [ 40.207102][ T184] RBP: 192dbe1a R08: c96df208 R09: [ 40.208394][ T184] R10: 88817a5f R11: 0001 R12: c96df110 [ 40.209692][ T184] R13: c96df0f0 R14: 88817a5db800 R15: c96df208 [ 40.210862][ T184] FS: 7f6b1d16e8c0() GS:88839d70() knlGS: [ 40.212250][ T184] CS: 0010 DS: ES: CR0: 80050033 [ 40.213275][ T184] CR2: 55a1001d4ff0 CR3: 0001700f4000 CR4: 06e0 [ 40.214469][ T184] Call Trace: [ 40.214974][ T184] [ 40.215438][ T184] ? ttm_bo_bounce_temp_buffer+0x140/0x140 [ttm] [ 40.216572][ T184] ? mutex_spin_on_owner+0x240/0x240 [ 40.217456][ T184] ? drm_vma_offset_add+0xaa/0x100 [drm] [ 40.218457][ T184] ttm_bo_init_reserved+0x3d6/0x540 [ttm] [ 40.219410][ T184] ? shmem_get_inode+0x744/0x980 [ 40.220231][ T184] ttm_bo_init_validate+0xb1/0x200 [ttm] [ 40.221172][ T184] ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper] [ 40.222530][ T184] ? ttm_bo_init_reserved+0x540/0x540 [ttm] [ 40.223643][ T184] ? __do_sys_finit_module+0x11a/0x1c0 [ 40.224654][ T184] ? __shmem_file_setup+0x102/0x280 [ 40.234764][ T184] drm_gem_vram_create+0x305/0x480 [drm_vram_helper] [ 40.235766][ T184] ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper] [ 40.236846][ T184] ? __kasan_slab_free+0x108/0x180 [ 40.237650][ T184] drm_gem_vram_fill_create_dumb+0x134/0x340 [drm_vram_helper] [ 40.238864][ T184] ? local_pci_probe+0xdf/0x180 [ 40.239674][ T184] ? drmm_vram_helper_init+0x400/0x400 [drm_vram_helper] [ 40.240826][ T184] drm_client_framebuffer_create+0x19c/0x400 [drm] [ 40.241955][ T184] ? drm_client_buffer_delete+0x200/0x200 [drm] [ 40.243001][ T184] ? drm_client_pick_crtcs+0x554/0xb80 [drm] [ 40.244030][ T184] drm_fb_helper_generic_probe+0x23f/0x940 [drm_kms_helper] [ 40.245226][ T184] ? __cond_resched+0x1c/0xc0 [ 40.245987][ T184] ? drm_fb_helper_memory_range_to_clip+0x180/0x180 [drm_kms_helper] [ 40.247316][ T184] ? mutex_unlock+0x80/0x100 [ 40.248005][ T184] ? __mutex_unlock_slowpath+0x2c0/0x2c0 [ 40.249083][ T184] drm_fb_helper_single_fb_probe+0x907/0xf00 [drm_kms_helper] [ 40.250314][ T184] ? drm_fb_helper_check_var+0x1180/0x1180 [drm_kms_helper] [ 40.251540][ T184] ? __cond_resched+0x1c/0xc0 [ 40.252321][ T184] ? mutex_lock+0x9f/0x100 [ 40.253062][ T184] __drm_fb_helper_initial_config_and_unlock+0xb9/0x2c0 [drm_kms_helper] [ 40.254394][ T184] drm_fbdev_client_hotplug+0x56f/0x840 [drm_kms_helper] [ 40.255477][ T184] drm_fbdev_generic_setup+0x165/0x3c0 [drm_kms_helper] [ 40.256607][ T184] bochs_pci_probe+0x6b7/0x900 [bochs] [ 40.257515][ T184] ? _raw_spin_lock_irqsave+0x87/0x100 [ 40.258312][ T184] ? bochs_hw_init+0x480/0x480 [bochs] [ 40.259244][ T184] ? bochs_hw_init+0x480/0x480 [bochs] [ 40.260186][ T184] local_pci_probe+0xdf/0x180 [ 40.260928][ T184] pci_call_probe+0x15f/0x500 [ 40.265798][ T184] ? _raw_spin_lock+0x81/0x100 [ 40.266508][ T184] ? pci_pm_suspend_noirq+0x980/0x980 [ 40.267322][ T184] ? pci_assign_irq+0x81/0x280 [ 40.268096][ T184] ? pci_match_device+0x351/0x6c0 [ 40.268883][ T184] ? kernfs_put+0x18/0x40 [ 40.269611][ T184] pci_device_probe+0xee/0x240 [ 40.270352][ T184] really_probe+0x435/0xa80 [ 40.271021][ T184] __driver_probe_device+0x2ab/0x480 [ 40.271828][ T184] driver_probe_device+0x49/0x140 [ 40.272627][ T184] __driver_attach+0x1bd/0x4c0 [ 40.273372][ T184] ? __device_attach_driver+0x240/0x240 [ 40.274273][ T184] bus_for_each_dev+0x11e/0x1c0 [ 40.275080][ T184] ? subsys_dev_iter_exit+0x40/0x40 [ 40.275951][ T184] ? klist_add_tail+0x132/0x280 [ 40.276767][ T184] bus_add_driver+0x39b/0x580 [ 40.277574][ T184] driver_register+0x20
[PATCH 2/2] drm/amd/pm: enable GFX ULV feature support for SMU13.0.0
The feature is ready with latest firmwares. Signed-off-by: Evan Quan Reviewed-by: Hawking Zhang Change-Id: I4907ef8c96eb8933db01818d7431afb3778d1afd --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 931c775fe27e..1bbeceeb9e3c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -313,6 +313,9 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); + if (adev->pm.pp_feature & PP_ULV_MASK) + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); + return 0; } -- 2.29.0
[PATCH 1/2] drm/amd/pm: update driver if header for SMU 13.0.0
And get the version bumped to 0x2C to match the latest PMFW. Signed-off-by: Evan Quan Reviewed-by: Hawking Zhang Change-Id: Ie4bc8fa0831ae6d1735c2dca27331ff6f6229e30 --- .../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 2 +- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h index 2b672d102c96..78620b0bd279 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h @@ -97,7 +97,7 @@ #define FEATURE_MEM_TEMP_READ_BIT 47 #define FEATURE_ATHUB_MMHUB_PG_BIT48 #define FEATURE_SOC_PCC_BIT 49 -#define FEATURE_SPARE_50_BIT 50 +#define FEATURE_EDC_PWRBRK_BIT50 #define FEATURE_SPARE_51_BIT 51 #define FEATURE_SPARE_52_BIT 52 #define FEATURE_SPARE_53_BIT 53 diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index 72b553618116..c02e5e576728 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -30,7 +30,7 @@ #define SMU13_DRIVER_IF_VERSION_ALDE 0x08 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x04 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04 -#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2B +#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2C #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2C #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms -- 2.29.0
Re: [PATCH 1/2] drm/amd/display: change variables type
On 07/26, Magali Lemes wrote:
> On 7/25/22 20:38, Melissa Wen wrote:
>
> > On 07/25, Magali Lemes wrote:
> > > On 7/25/22 16:42, André Almeida wrote:
> > > > Hi Magali,
> > > >
> > > > Às 15:15 de 25/07/22, Magali Lemes escreveu:
> > > > > As "dcn3_15_soc" and "dcn3_16_soc" are of type "struct
> > > > > _vcs_dpi_soc_bounding_box_st", change their types accordingly.
> > > > >
> > > > I can see that indeed this type change sense for those variables, but
> > > > isn't a bit strange that the type was wrong in the first place? I wonder
> > > > if this variable is even used, given that it would very likely throw a
> > > > compiler error when using the wrong type and trying to access struct
> > > > members that aren't defined.
> > >
> > > A compilation error would be thrown if either
> > > "dc/dcn315/dcn315_resource.h"
> > > or "dc/dcn316/dcn316_resource.h" were included in the files where
> > > "dcn3_15_soc" and "dcn3_16_soc" are initialized. Since they are not
> > > included, the wrong variable type error is not shown.
> > > To solve the sparse warning in the second patch of this series, those
> > > variables need to be declared first, but they are already declared, we're
> > > only missing the headers. If I only add the headers, then those variables
> > > will be seen, and I get the expected incompatible variables types error.
> > > So,
> > > fixing the types here is a preliminary work for the next patch.
> > >
> > Hi Magali,
> >
> > Thanks for inspecting it. What you say makes sense, but André pointed
> > out something that makes sense to me too.
> >
> > As fas as I checked, dcn3_15_soc and dcn16_soc is not used outside their
> > respective FPU files. Maybe the proper solution is removing those
> > declarations (and make the struct static). Can you take a look at it?
> >
> > Best Regards,
> >
> > Melissa
>
> Hi, Melissa. Thank you for the suggestion!
> My sole reason not to make those structs static was to keep some sort of
> consistency with the rest of the dcn*_resource.h files, since that is where
> all the other structs are first declared. I'm not sure, though, if that's a
> good enough reason not to turn these variables into static. Let me know what
> you think.
I don't see any other file using dcn3_15_soc, it's only in dcn30_fpu, so
better make it static. Also, I see that doing this will ring a bell
for some misuse of the struct outside FPU protection, in the future.
With those points addressed, you can add in the next version:
Reviewed-by: Melissa Wen
Thanks,
Melissa
>
> Magali
>
>
>
> > Magali
> >
> >
> > > > > Signed-off-by: Magali Lemes
> > > > > ---
> > > > >drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h | 2 +-
> > > > >drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h | 2 +-
> > > > >2 files changed, 2 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
> > > > > b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
> > > > > index 39929fa67a51..45276317c057 100644
> > > > > --- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
> > > > > +++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
> > > > > @@ -32,7 +32,7 @@
> > > > > container_of(pool, struct dcn315_resource_pool, base)
> > > > >extern struct _vcs_dpi_ip_params_st dcn3_15_ip;
> > > > > -extern struct _vcs_dpi_ip_params_st dcn3_15_soc;
> > > > > +extern struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc;
> > > > >struct dcn315_resource_pool {
> > > > > struct resource_pool base;
> > > > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
> > > > > b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
> > > > > index 0dc5a6c13ae7..d2234aac5449 100644
> > > > > --- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
> > > > > +++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
> > > > > @@ -32,7 +32,7 @@
> > > > > container_of(pool, struct dcn316_resource_pool, base)
> > > > >extern struct _vcs_dpi_ip_params_st dcn3_16_ip;
> > > > > -extern struct _vcs_dpi_ip_params_st dcn3_16_soc;
> > > > > +extern struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc;
> > > > >struct dcn316_resource_pool {
> > > > > struct resource_pool base;
signature.asc
Description: PGP signature
Re: [PATCH] drm/amdgpu: Avoid direct cast to amdgpu_ttm_tt
Am 2022-07-26 um 19:43 schrieb Rajneesh Bhardwaj:
For typesafety, use container_of() instead of implicit cast from struct
ttm_tt to struct amdgpu_ttm_tt.
Cc: Christian König
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 44 ++---
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index be0efaae79a9..cd6aa206a59e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -637,6 +637,8 @@ struct amdgpu_ttm_tt {
#endif
};
+#define ttm_to_amdgpu_ttm_tt(ttm) container_of(ttm, struct amdgpu_ttm_tt, ttm)
+
#ifdef CONFIG_DRM_AMDGPU_USERPTR
/*
* amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
@@ -648,7 +650,7 @@ struct amdgpu_ttm_tt {
int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
{
struct ttm_tt *ttm = bo->tbo.ttm;
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
unsigned long start = gtt->userptr;
struct vm_area_struct *vma;
struct mm_struct *mm;
@@ -702,7 +704,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
struct page **pages)
*/
bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
{
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
bool r = false;
if (!gtt || !gtt->userptr)
@@ -751,7 +753,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_device
*bdev,
struct ttm_tt *ttm)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
enum dma_data_direction direction = write ?
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
@@ -788,7 +790,7 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device
*bdev,
struct ttm_tt *ttm)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
enum dma_data_direction direction = write ?
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
@@ -822,7 +824,7 @@ static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
{
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
struct ttm_tt *ttm = tbo->ttm;
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
if (amdgpu_bo_encrypted(abo))
flags |= AMDGPU_PTE_TMZ;
@@ -860,7 +862,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
struct ttm_resource *bo_mem)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void*)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
uint64_t flags;
int r;
@@ -927,7 +929,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct ttm_operation_ctx ctx = { false, false };
- struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
+ struct ttm_tt *ttm = bo->ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
Is the extra ttm local variable really needed? It's only used once in
this function, right here.
struct ttm_placement placement;
struct ttm_place placements;
struct ttm_resource *tmp;
@@ -998,7 +1001,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device
*bdev,
struct ttm_tt *ttm)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
/* if the pages have userptr pinning then clear that first */
if (gtt->userptr) {
@@ -1025,7 +1028,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device
*bdev,
static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
struct ttm_tt *ttm)
{
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
if (gtt->usertask)
put_task_struct(gtt->usertask);
@@ -1079,7 +1082,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
struct ttm_operation_ctx *ctx)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
pgoff_t i;
[PATCH] drm/amdgpu: Avoid direct cast to amdgpu_ttm_tt
For typesafety, use container_of() instead of implicit cast from struct
ttm_tt to struct amdgpu_ttm_tt.
Cc: Christian König
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 44 ++---
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index be0efaae79a9..cd6aa206a59e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -637,6 +637,8 @@ struct amdgpu_ttm_tt {
#endif
};
+#define ttm_to_amdgpu_ttm_tt(ttm) container_of(ttm, struct amdgpu_ttm_tt,
ttm)
+
#ifdef CONFIG_DRM_AMDGPU_USERPTR
/*
* amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
@@ -648,7 +650,7 @@ struct amdgpu_ttm_tt {
int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
{
struct ttm_tt *ttm = bo->tbo.ttm;
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
unsigned long start = gtt->userptr;
struct vm_area_struct *vma;
struct mm_struct *mm;
@@ -702,7 +704,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
struct page **pages)
*/
bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
{
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
bool r = false;
if (!gtt || !gtt->userptr)
@@ -751,7 +753,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_device
*bdev,
struct ttm_tt *ttm)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
enum dma_data_direction direction = write ?
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
@@ -788,7 +790,7 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device
*bdev,
struct ttm_tt *ttm)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
enum dma_data_direction direction = write ?
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
@@ -822,7 +824,7 @@ static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
{
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
struct ttm_tt *ttm = tbo->ttm;
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
if (amdgpu_bo_encrypted(abo))
flags |= AMDGPU_PTE_TMZ;
@@ -860,7 +862,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
struct ttm_resource *bo_mem)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void*)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
uint64_t flags;
int r;
@@ -927,7 +929,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct ttm_operation_ctx ctx = { false, false };
- struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
+ struct ttm_tt *ttm = bo->ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
struct ttm_placement placement;
struct ttm_place placements;
struct ttm_resource *tmp;
@@ -998,7 +1001,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device
*bdev,
struct ttm_tt *ttm)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
/* if the pages have userptr pinning then clear that first */
if (gtt->userptr) {
@@ -1025,7 +1028,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device
*bdev,
static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
struct ttm_tt *ttm)
{
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
if (gtt->usertask)
put_task_struct(gtt->usertask);
@@ -1079,7 +1082,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
struct ttm_operation_ctx *ctx)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
- struct amdgpu_ttm_tt *gtt = (void *)ttm;
+ struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
pgoff_t i;
int ret;
@@ -1113,7 +1116,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
Re: amdgpu: misc ugliness and inconsistency
Hi Dan, Às 12:52 de 26/07/22, Dan Carpenter escreveu: > Hi AMD devs, > > I guess there was a big merge in linux-next the other day? Anyway, it > generated a lot of Smatch warnings. I reported some of them but there > is just a lot so I'm mass reporting these. > > Inconsistent NULL checking can be harmless. Part of the function > assumes that the pointer can be NULL and part assumes that it cannot. > It does not make sense, but it is often harmless and the correct > response is just to remove the NULL check. > > The other class of reports is inconsistent indenting. There were two > bugs but I already fixed one and reported the other so these should be > harmless. For this class, I believe this series fixes most of them: https://lore.kernel.org/amd-gfx/20220726072555.91323-1-jiapeng.ch...@linux.alibaba.com/ > > regards, > dan carpenter > > Inconsistent NULL checks: > > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1271 > handle_cursor_update() error: we previously assumed 'afb' could be null (see > line 1230) > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:1017 > dcn201_acquire_idle_pipe_for_layer() error: we previously assumed 'head_pipe' > could be null (see line 1011) > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.c:222 > dcn21_set_backlight_level() error: we previously assumed 'panel_cntl' could > be null (see line 213) > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 > dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' > could be null (see line 749) > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:767 > dcn30_apply_idle_power_optimizations() error: we previously assumed 'plane' > could be null (see line 749) > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hwseq.c:284 > dcn31_init_hw() error: we previously assumed 'dc->clk_mgr' could be null (see > line 117) > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:896 > dcn32_init_hw() error: we previously assumed 'dc->clk_mgr' could be null (see > line 738) > drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:777 > subvp_drr_schedulable() error: we previously assumed 'pipe->stream' could be > null (see line 768) > drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:868 > subvp_vblank_schedulable() error: we previously assumed 'subvp_pipe' could be > null (see line 860) > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hwseq.c:250 > dcn201_init_hw() warn: variable dereferenced before check 'res_pool->dccg' > (see line 227) > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:782 > dcn20_enable_stream_timing() warn: variable dereferenced before check > 'pipe_ctx->stream_res.tg' (see line 698) > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hwseq.c:157 > dcn31_init_hw() warn: variable dereferenced before check 'res_pool->dccg' > (see line 147) > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:765 > dcn32_init_hw() warn: variable dereferenced before check 'res_pool->dccg' > (see line 742) > > Bad indenting: > > drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:107 > dcn201_update_clocks() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c:716 > dcn314_clk_mgr_construct() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c:655 > dcn315_clk_mgr_construct() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c:683 > dcn316_clk_mgr_construct() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c:726 > dcn31_clk_mgr_construct() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2152 > dcn10_align_pixel_clocks() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:854 > dcn301_hubbub_create() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:618 > dcn32_set_output_transfer_func() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:910 > dcn32_init_hw() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mpc.c:306 > mpc32_get_shaper_current() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource.c:1979 > dcn32_resource_construct() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource.c:2319 > dcn32_resource_construct() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:205 > dcn303_fpu_update_bw_bounding_box() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:355 > dcn303_fpu_init_soc_bounding_box() warn: inconsistent indenting > drivers
[PATCH 2/2] drm/amd/display: Fix indentation in commit_planes_for_stream()
No functional change. Just update whitespace.
Signed-off-by: Alex Deucher
Cc: Alvin Lee
Cc: Martin Leung
Cc: Harry Wentland
Cc: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 62
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7be3ad1c717c..8c97abd3bc5b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3365,8 +3365,8 @@ static void commit_planes_for_stream(struct dc *dc,
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (!pipe_ctx->top_pipe &&
- !pipe_ctx->prev_odm_pipe &&
- should_update_pipe_for_stream(context, pipe_ctx,
stream)) {
+ !pipe_ctx->prev_odm_pipe &&
+ should_update_pipe_for_stream(context, pipe_ctx, stream)) {
struct dc_stream_status *stream_status = NULL;
if (!pipe_ctx->plane_state)
@@ -3455,27 +3455,27 @@ static void commit_planes_for_stream(struct dc *dc,
}
- if (update_type != UPDATE_TYPE_FAST)
- if (dc->hwss.commit_subvp_config)
- dc->hwss.commit_subvp_config(dc, context);
+ if (update_type != UPDATE_TYPE_FAST)
+ if (dc->hwss.commit_subvp_config)
+ dc->hwss.commit_subvp_config(dc, context);
- if (should_lock_all_pipes &&
dc->hwss.interdependent_update_lock) {
- dc->hwss.interdependent_update_lock(dc, context, false);
- } else {
- dc->hwss.pipe_control_lock(dc, top_pipe_to_program,
false);
- }
+ if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
+ dc->hwss.interdependent_update_lock(dc, context, false);
+ } else {
+ dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
+ }
- if ((update_type != UPDATE_TYPE_FAST) &&
stream->update_flags.bits.dsc_changed)
- if
(top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
-
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
- top_pipe_to_program->stream_res.tg,
- CRTC_STATE_VACTIVE);
-
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
- top_pipe_to_program->stream_res.tg,
- CRTC_STATE_VBLANK);
-
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
- top_pipe_to_program->stream_res.tg,
- CRTC_STATE_VACTIVE);
+ if ((update_type != UPDATE_TYPE_FAST) &&
stream->update_flags.bits.dsc_changed)
+ if
(top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
+
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
+ top_pipe_to_program->stream_res.tg,
+ CRTC_STATE_VACTIVE);
+
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
+ top_pipe_to_program->stream_res.tg,
+ CRTC_STATE_VBLANK);
+
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
+ top_pipe_to_program->stream_res.tg,
+ CRTC_STATE_VACTIVE);
if (should_use_dmub_lock(stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
@@ -3485,9 +3485,9 @@ static void commit_planes_for_stream(struct dc *dc,
inst_flags.dig_inst =
top_pipe_to_program->stream_res.tg->inst;
dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
- false,
- &hw_locks,
- &inst_flags);
+false,
+&hw_locks,
+&inst_flags);
} else
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
top_pipe_to_program->stream_res.tg);
@@ -3499,13 +3499,13 @@ static void commit_planes_for_stream(struct dc *dc,
/* Since phantom pipe programming is moved to
post_unlock_program_front_end,
* move the SubVP lock to after the phantom pipes have been
[PATCH 1/2] Revert "drm/amd/display: attempt to fix the logic in commit_planes_for_stream()"
This reverts commit a0d10c437c1c9859d24a16b90abf85120603b4ff.
This caused a regression in the DC team testing.
Signed-off-by: Alex Deucher
Cc: Alvin Lee
Cc: Martin Leung
Cc: Harry Wentland
Cc: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 45 +++-
1 file changed, 21 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e42f44fc1c08..7be3ad1c717c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3229,7 +3229,7 @@ static void commit_planes_for_stream(struct dc *dc,
odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
}
- if ((update_type != UPDATE_TYPE_FAST) &&
stream->update_flags.bits.dsc_changed) {
+ if ((update_type != UPDATE_TYPE_FAST) &&
stream->update_flags.bits.dsc_changed)
if (top_pipe_to_program &&
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
if (should_use_dmub_lock(stream->link)) {
@@ -3247,7 +3247,6 @@ static void commit_planes_for_stream(struct dc *dc,
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
top_pipe_to_program->stream_res.tg);
}
- }
if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
if (dc->hwss.subvp_pipe_control_lock)
@@ -3456,27 +3455,27 @@ static void commit_planes_for_stream(struct dc *dc,
}
- if (update_type != UPDATE_TYPE_FAST)
- if (dc->hwss.commit_subvp_config)
- dc->hwss.commit_subvp_config(dc, context);
+ if (update_type != UPDATE_TYPE_FAST)
+ if (dc->hwss.commit_subvp_config)
+ dc->hwss.commit_subvp_config(dc, context);
- if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
- dc->hwss.interdependent_update_lock(dc, context, false);
- } else {
- dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
- }
+ if (should_lock_all_pipes &&
dc->hwss.interdependent_update_lock) {
+ dc->hwss.interdependent_update_lock(dc, context, false);
+ } else {
+ dc->hwss.pipe_control_lock(dc, top_pipe_to_program,
false);
+ }
- if ((update_type != UPDATE_TYPE_FAST) &&
stream->update_flags.bits.dsc_changed) {
- if
(top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
-
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
- top_pipe_to_program->stream_res.tg,
- CRTC_STATE_VACTIVE);
-
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
- top_pipe_to_program->stream_res.tg,
- CRTC_STATE_VBLANK);
-
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
- top_pipe_to_program->stream_res.tg,
- CRTC_STATE_VACTIVE);
+ if ((update_type != UPDATE_TYPE_FAST) &&
stream->update_flags.bits.dsc_changed)
+ if
(top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
+
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
+ top_pipe_to_program->stream_res.tg,
+ CRTC_STATE_VACTIVE);
+
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
+ top_pipe_to_program->stream_res.tg,
+ CRTC_STATE_VBLANK);
+
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
+ top_pipe_to_program->stream_res.tg,
+ CRTC_STATE_VACTIVE);
if (should_use_dmub_lock(stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
@@ -3493,9 +3492,8 @@ static void commit_planes_for_stream(struct dc *dc,
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
top_pipe_to_program->stream_res.tg);
}
- }
- if (update_type != UPDATE_TYPE_FAST) {
+ if (update_type != UPDATE_TYPE_FAST)
dc->hwss.post_unlock_program_front_end(dc, context);
/* Since phantom pipe programming is moved to
post_unlock_program_front_end,
@@ -3508,7 +3506,6 @@ static void commit_planes_for_stream(struct dc *dc,
if
Re: [PATCH 1/2] drm/amd/display: change variables type
Às 17:47 de 25/07/22, Magali Lemes escreveu:
>
> On 7/25/22 16:42, André Almeida wrote:
>> Hi Magali,
>>
>> Às 15:15 de 25/07/22, Magali Lemes escreveu:
>>> As "dcn3_15_soc" and "dcn3_16_soc" are of type "struct
>>> _vcs_dpi_soc_bounding_box_st", change their types accordingly.
>>>
>> I can see that indeed this type change sense for those variables, but
>> isn't a bit strange that the type was wrong in the first place? I wonder
>> if this variable is even used, given that it would very likely throw a
>> compiler error when using the wrong type and trying to access struct
>> members that aren't defined.
>
>
> A compilation error would be thrown if either
> "dc/dcn315/dcn315_resource.h" or "dc/dcn316/dcn316_resource.h" were
> included in the files where "dcn3_15_soc" and "dcn3_16_soc" are
> initialized. Since they are not included, the wrong variable type error
> is not shown.
> To solve the sparse warning in the second patch of this series, those
> variables need to be declared first, but they are already declared,
> we're only missing the headers. If I only add the headers, then those
> variables will be seen, and I get the expected incompatible variables
> types error. So, fixing the types here is a preliminary work for the
> next patch.
>
And what happens if you just drop this declaration? It still not clear
to me why this belongs to this header, giving that AFAIK this var is
only used at drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
Note that this kind of information you explained to me would be very
useful if you had included it in a cover letter to add more context for
your patches :)
>
> Magali
>
>
>>
>>> Signed-off-by: Magali Lemes
>>> ---
>>> drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h | 2 +-
>>> drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h | 2 +-
>>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
>>> b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
>>> index 39929fa67a51..45276317c057 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
>>> +++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
>>> @@ -32,7 +32,7 @@
>>> container_of(pool, struct dcn315_resource_pool, base)
>>> extern struct _vcs_dpi_ip_params_st dcn3_15_ip;
>>> -extern struct _vcs_dpi_ip_params_st dcn3_15_soc;
>>> +extern struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc;
>>> struct dcn315_resource_pool {
>>> struct resource_pool base;
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
>>> b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
>>> index 0dc5a6c13ae7..d2234aac5449 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
>>> +++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
>>> @@ -32,7 +32,7 @@
>>> container_of(pool, struct dcn316_resource_pool, base)
>>> extern struct _vcs_dpi_ip_params_st dcn3_16_ip;
>>> -extern struct _vcs_dpi_ip_params_st dcn3_16_soc;
>>> +extern struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc;
>>> struct dcn316_resource_pool {
>>> struct resource_pool base;
Re: [PATCH v9 06/14] mm/gup: migrate device coherent pages when pinning instead of failing
On Mon, 25 Jul 2022 21:22:06 -0500 "Sierra Guiza, Alejandro (Alex)" wrote: > >> a) add the || to the end of the previous line > >> b) indent such the we have a nice-to-read alignment > >> > >> if (!list_empty(&movable_page_list) || isolation_error_count || > >> coherent_pages) > >> > > I missed that. This series is now in mm-stable so any fix will need to > > be a standalone followup patch, please. > Hi Andrew, > Just wanted to make sure nothing is missing from our side to merge this > patch series. It's queued in mm-stable and all looks good for a 5.20-rc1 merge.
[PATCH v2 4/4] drm/amdgpu: Document gfx_off members of struct amdgpu_gfx
Add comments to document gfx_off related members of struct amdgpu_gfx.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 1b8b4a5270c9..8abdf41d0f83 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -332,12 +332,12 @@ struct amdgpu_gfx {
uint32_tsrbm_soft_reset;
/* gfx off */
- boolgfx_off_state; /* true: enabled, false:
disabled */
- struct mutexgfx_off_mutex;
- uint32_tgfx_off_req_count; /* default 1, enable
gfx off: dec 1, disable gfx off: add 1 */
- struct delayed_work gfx_off_delay_work;
- uint32_tgfx_off_residency;
- uint64_tgfx_off_entrycount;
+ boolgfx_off_state; /* true: enabled,
false: disabled */
+ struct mutexgfx_off_mutex; /* mutex to change
gfxoff state */
+ uint32_tgfx_off_req_count; /* default 1,
enable gfx off: dec 1, disable gfx off: add 1 */
+ struct delayed_work gfx_off_delay_work; /* async work to
set gfx block off */
+ uint32_tgfx_off_residency; /* last logged
residency */
+ uint64_tgfx_off_entrycount; /* count of times
GPU has get into GFXOFF state */
/* pipe reservation */
struct mutexpipe_reserve_mutex;
--
2.37.1
[PATCH v2 0/4] drm/amd: Add more GFXOFF stats for vangogh
This series adds new logging features for GFXOFF available for vangogh and documentation for it. I've created a small userspace program to interact with this new debugfs interface and it can be found at: https://gitlab.freedesktop.org/andrealmeid/gfxoff_tool Changelog: v2: - Make entrycount uint64_t - Add a note in docs about data types and overflow André Almeida (4): drm/amd: Add detailed GFXOFF stats to debugfs drm/amd/pm: Implement GFXOFF's entry count and residency for vangogh Documentation/gpu: Document GFXOFF's count and residency drm/amdgpu: Document gfx_off members of struct amdgpu_gfx Documentation/gpu/amdgpu/thermal.rst | 18 +- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 168 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 39 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 14 +- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 45 + drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 35 +++- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 22 +++ .../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 5 +- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 5 +- .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 92 ++ drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 3 + 13 files changed, 443 insertions(+), 8 deletions(-) -- 2.37.1
[PATCH v2 3/4] Documentation/gpu: Document GFXOFF's count and residency
Add documentation explaining those two new files. While here, add a note about the value type. Signed-off-by: André Almeida --- Documentation/gpu/amdgpu/thermal.rst | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/gpu/amdgpu/thermal.rst b/Documentation/gpu/amdgpu/thermal.rst index 997231b6adcf..5e27e4eb3959 100644 --- a/Documentation/gpu/amdgpu/thermal.rst +++ b/Documentation/gpu/amdgpu/thermal.rst @@ -72,7 +72,8 @@ card's RLC (RunList Controller) firmware powers off the gfx engine dynamically when there is no workload on gfx or compute pipes. GFXOFF is on by default on supported GPUs. -Userspace can interact with GFXOFF through a debugfs interface: +Userspace can interact with GFXOFF through a debugfs interface (all values in +`uint32_t`, unless otherwise noted): ``amdgpu_gfxoff`` - @@ -104,3 +105,18 @@ Read it to check current GFXOFF's status of a GPU:: If GFXOFF is enabled, the value will be transitioning around [0, 3], always getting into 0 when possible. When it's disabled, it's always at 2. Returns ``-EINVAL`` if it's not supported. + +``amdgpu_gfxoff_count`` +--- + +Read it to get the total GFXOFF entry count at the time of query since system +power-up. The value is an `uint64_t` type, however, due to firmware limitations, +it can currently overflow as an `uint32_t`. *Only supported in vangogh* + +``amdgpu_gfxoff_residency`` +--- + +Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop. Read it to +get average GFXOFF residency % multiplied by 100 during the last logging +interval. E.g. a value of 7854 means 78.54% of the time in the last logging +interval the GPU was in GFXOFF mode. *Only supported in vangogh* -- 2.37.1
[PATCH v2 2/4] drm/amd/pm: Implement GFXOFF's entry count and residency for vangogh
Implement functions to get and set GFXOFF's entry count and residency
for vangogh.
Signed-off-by: André Almeida
---
.../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 5 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 5 +-
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 92 +++
3 files changed, 100 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
index fe130a497d6c..7471e2df2828 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
@@ -108,7 +108,10 @@
#define PPSMC_MSG_SetSlowPPTLimit 0x4A
#define PPSMC_MSG_GetFastPPTLimit 0x4B
#define PPSMC_MSG_GetSlowPPTLimit 0x4C
-#define PPSMC_Message_Count0x4D
+#define PPSMC_MSG_GetGfxOffStatus 0x50
+#define PPSMC_MSG_GetGfxOffEntryCount 0x51
+#define PPSMC_MSG_LogGfxOffResidency 0x52
+#define PPSMC_Message_Count0x53
//Argument for PPSMC_MSG_GfxDeviceDriverReset
enum {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index 19084a4fcb2b..76fb6cbbc09c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -235,7 +235,10 @@
__SMU_DUMMY_MAP(UnforceGfxVid), \
__SMU_DUMMY_MAP(HeavySBR), \
__SMU_DUMMY_MAP(SetBadHBMPagesRetiredFlagsPerChannel), \
- __SMU_DUMMY_MAP(EnableGfxImu),
+ __SMU_DUMMY_MAP(EnableGfxImu), \
+ __SMU_DUMMY_MAP(GetGfxOffStatus),\
+ __SMU_DUMMY_MAP(GetGfxOffEntryCount),\
+ __SMU_DUMMY_MAP(LogGfxOffResidency),
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 89504ff8e9ed..4e547573698b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -138,6 +138,9 @@ static struct cmn2asic_msg_mapping
vangogh_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(SetSlowPPTLimit,PPSMC_MSG_SetSlowPPTLimit,
0),
MSG_MAP(GetFastPPTLimit,PPSMC_MSG_GetFastPPTLimit,
0),
MSG_MAP(GetSlowPPTLimit,PPSMC_MSG_GetSlowPPTLimit,
0),
+ MSG_MAP(GetGfxOffStatus,PPSMC_MSG_GetGfxOffStatus,
0),
+ MSG_MAP(GetGfxOffEntryCount,
PPSMC_MSG_GetGfxOffEntryCount, 0),
+ MSG_MAP(LogGfxOffResidency,
PPSMC_MSG_LogGfxOffResidency, 0),
};
static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
@@ -2200,6 +2203,92 @@ static int vangogh_set_power_limit(struct smu_context
*smu,
return ret;
}
+/**
+ * vangogh_set_gfxoff_residency
+ *
+ * @smu: amdgpu_device pointer
+ * @start: start/stop residency log
+ *
+ * This function will be used to log gfxoff residency
+ *
+ *
+ * Returns standard response codes.
+ */
+static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
+{
+ int ret = 0;
+ u32 residency;
+ struct amdgpu_device *adev = smu->adev;
+
+ switch (adev->ip_versions[MP1_HWIP][0]) {
+ case IP_VERSION(11, 5, 0):
+ if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
+ return 0;
+ ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_LogGfxOffResidency,
+ start, &residency);
+ if (!start)
+ adev->gfx.gfx_off_residency = residency;
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * vangogh_get_gfxoff_residency
+ *
+ * @smu: amdgpu_device pointer
+ *
+ * This function will be used to get gfxoff residency.
+ *
+ * Returns standard response codes.
+ */
+static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t
*residency)
+{
+ int ret = 0;
+ struct amdgpu_device *adev = smu->adev;
+
+ switch (adev->ip_versions[MP1_HWIP][0]) {
+ case IP_VERSION(11, 5, 0):
+ *residency = adev->gfx.gfx_off_residency;
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * vangogh_get_gfxoff_entrycount - get gfxoff entry count
+ *
+ * @smu: amdgpu_device pointer
+ *
+ * This function will be used to get gfxoff entry count
+ *
+ * Returns st
[PATCH v2 1/4] drm/amd: Add detailed GFXOFF stats to debugfs
Add debugfs interface to log GFXOFF statistics:
- Read amdgpu_gfxoff_count to get the total GFXOFF entry count at the
time of query since system power-up
- Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop.
Read it to get average GFXOFF residency % multiplied by 100
during the last logging interval.
Both features are designed to be keep the values persistent between
suspends.
Signed-off-by: André Almeida
---
Changes from v1: make entrycount u64
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 168 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 39
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 +
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 45 +
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 33
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 22 +++
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 3 +
9 files changed, 321 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index e2eec985adb3..e0eed087dba4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1042,6 +1042,157 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f,
char __user *buf,
return r;
}
+/**
+ * amdgpu_debugfs_gfxoff_residency_read - Read GFXOFF residency
+ *
+ * @f: open file handle
+ * @buf: User buffer to store read data in
+ * @size: Number of bytes to read
+ * @pos: Offset to seek to
+ *
+ * Read the last residency value logged. It doesn't auto update, one needs to
+ * stop logging before getting the current value.
+ */
+static ssize_t amdgpu_debugfs_gfxoff_residency_read(struct file *f, char
__user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return r;
+ }
+
+ while (size) {
+ uint32_t value;
+
+ r = amdgpu_get_gfx_off_residency(adev, &value);
+ if (r)
+ goto out;
+
+ r = put_user(value, (uint32_t *)buf);
+ if (r)
+ goto out;
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ r = result;
+out:
+ pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+
+ return r;
+}
+
+/**
+ * amdgpu_debugfs_gfxoff_residency_write - Log GFXOFF Residency
+ *
+ * @f: open file handle
+ * @buf: User buffer to write data from
+ * @size: Number of bytes to write
+ * @pos: Offset to seek to
+ *
+ * Write a 32-bit non-zero to start logging; write a 32-bit zero to stop
+ */
+static ssize_t amdgpu_debugfs_gfxoff_residency_write(struct file *f, const
char __user *buf,
+size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return r;
+ }
+
+ while (size) {
+ u32 value;
+
+ r = get_user(value, (uint32_t *)buf);
+ if (r)
+ goto out;
+
+ amdgpu_set_gfx_off_residency(adev, value ? true : false);
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ r = result;
+out:
+ pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+
+ return r;
+}
+
+
+/**
+ * amdgpu_debugfs_gfxoff_count_read - Read GFXOFF entry count
+ *
+ * @f: open file handle
+ * @buf: User buffer to store read data in
+ * @size: Number of bytes to read
+ * @pos: Offset to seek to
+ */
+static ssize_t amdgpu_debugfs_gfxoff_count_read(struct file *f, char __user
*buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return r;
+ }
+
+ while (size) {
+
[pull] amdgpu, amdkfd drm-next-5.20
Hi Dave, Daniel, Bug fixes for 5.20 and a few new things. I know it's a bit late for new stuff, but this is mainly fixes for new IPs that were just added in 5.20 and more DC cleanup which is just code shuffling to group FP code into separate code objects and spliting up the DC DM code into more files. The following changes since commit 891ce1c9623f36194587d02774ac3d8c30c3ca72: Merge tag 'drm-misc-next-fixes-2022-07-14' of git://anongit.freedesktop.org/drm/drm-misc into drm-next (2022-07-15 15:35:33 +1000) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-next-5.20-2022-07-26 for you to fetch changes up to 1b54a0121dba12af268fb75c413feabdb9f573d4: drm/amd/display: Reduce stack size in the mode support function (2022-07-25 17:23:30 -0400) amdgpu: - VCN4 fixes - RAS support for UMC 8.10 - ACP support for jadeite platforms - NBIO HDP flush fixes - Misc spelling and grammar fixes - Runtime PM fixes - Non-DC HPD fix - Clean up amdgpu DM code - DSC fixes - Expose some additional GFXOFF data via debugfs - More FP clean up for new DCN blocks - PPC DC FP fixes - DCN 3.1.4 fixes - DC DML stack usage fixes - GMC fixes - SPM fixes for RDNA2 amdkfd: - MMU notifier fix - Mutex fix UAPI: - Add a comment about VCN4 unified queues - IP version information for UMDs Proposed mesa change: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411/diffs?commit_id=c8a63590dfd0d64e6e6a634dcfed993f135dd075 Aaron Liu (2): drm/amdgpu: enable swiotlb for gmc 10.0 (V2) drm/amdgpu: enable swiotlb for gmc 11.0 Alex Deucher (10): drm/amdgpu: use the same HDP flush registers for all nbio 7.4.x drm/amdgpu: use the same HDP flush registers for all nbio 2.3.x drm/amdgpu: restore original stable pstate on ctx fini drm/amdgpu: add the IP discovery IP versions for HW INFO data drm/amdgpu: bump driver version for IP discovery info in HW INFO drm/amd/display: reduce stack size in dcn32 dml (v2) drm/amd/display: reduce stack for dml32_CalculateSwathAndDETConfiguration drm/amd/display: reduce stack for dml32_CalculateVMRowAndSwath drm/amd/display: reduce stack for dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport drm/amd/display: reduce stack for dml32_CalculatePrefetchSchedule Alex Sierra (1): drm/amdgpu: remove acc_size from reserve/unreserve mem Alvin Lee (8): drm/amd/display: Update in dml drm/amd/display: Don't set dram clock change requirement for SubVP drm/amd/display: Updates SubVP and SubVP DRR cases drm/amd/display: Calculate MALL cache lines based on Mblks required drm/amd/display: Fallback to SW cursor if SubVP + cursor too big drm/amd/display: Update DCN32 and DCN321 SR latencies drm/amd/display: Disable MPC split for DCN32/321 drm/amd/display: Add debug option for idle optimizations on cursor updates Andrey Grodzovsky (1): drm/amdgpu: Get rid of amdgpu_job->external_hw_fence André Almeida (3): drm/amdgpu: Clarify asics naming in Kconfig options drm/amd/debugfs: Expose GFXOFF state to userspace Documentation/gpu: Add GFXOFF section Anthony Koo (2): drm/amd/display: Add support for manual DMUB FAMS trigger drm/amd/display: 3.2.196 Aric Cyr (2): drm/amd/display: 3.2.195 drm/amd/display: Avoid MPC infinite loop Aurabindo Pillai (2): drm/amd/display: Revert "drm/amd/display: disable idle optimizations" drm/amd/display: Add dc_ctx to link_enc_create() parameters Chengming Gui (1): drm/amd/amdgpu: add TAP_DELAYS upload support for gfx10 Chris Park (2): drm/amd/display: Update Cursor Attribute MALL cache drm/amd/display: Cache cursor when cursor exceeds 64x64 Colin Ian King (1): drm/amd/display: Fix spelling mistake "supporing" -> "supporting" Dan Carpenter (1): drm/amd/display: Remove unnecessary NULL check in commit_planes_for_stream() Evan Quan (4): drm/amd/pm: enable GPO feature support for SMU13.0.0 drm/amd/pm: update SMU13.0.0 driver_if header drm/amd/pm: correct smu 13.0.0/7 mp1 state setup drm/amd/pm: revise the driver reloading fix for SMU 13.0.0 and 13.0.7 Gavin Wan (1): drm/amdgpu: fix scratch register access method in SRIOV Guchun Chen (4): drm/amdgpu: introduce runtime pm mode drm/amdgpu: skip SMU FW reloading in runpm BACO case drm/amdgpu: drop runtime pm disablement quirk on several sienna cichlid cards drm/amdgpu: drop runpm from amdgpu_device structure Guenter Roeck (1): drm/amd/display: Enable building new display engine with KCOV enabled Hawking Zhang (1): drm/amdgpu: correct the PSP_BL_CMD enum Jason Wang (2): drm/radeon: Fix comment typo drm/amdgpu: Fix comment typo Jun Lei (2): drm/amd/displ
Re: [bug report] drm/amd/display: use FB pitch to fill dc_cursor_attributes
On Tuesday, July 26th, 2022 at 17:47, Dan Carpenter wrote: > On Tue, Jul 26, 2022 at 03:27:54PM +, Simon Ser wrote: > > > plane->state->fb is NULL iff afb is NULL. There is an early return to > > make sure the dereferences don't cause a segfault. > > > Are you talking about this: > > if (!plane->state->fb && !old_plane_state->fb) > > return; > > Should the && be ||? Ah, sorry, the reason why this doesn't segfault is different: get_cursor_position() will leave position.enable = false if there is no FB, and we have an early return for that. This also guards crtc_state.
Re: Crash on resume from S3
The stack trace is expected part of reset procedure so that ok. The issue you are having is a hang on one of GPU jobs during resume which triggers a GPU reset attempt. You can open a ticket with this issue here https://gitlab.freedesktop.org/drm/amd/-/issues, please attach full dmesg log. Andrey On 2022-07-26 05:06, Tom Cook wrote: I have a Ryzen 7 3700U in an HP laptop. lspci describes the GPU in this way: 04:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Picasso/Raven 2 [Radeon Vega Series / Radeon Vega Mobile Series] (rev c1) This laptop has never successfully resumed from suspend (I have tried every 5.x kernel). Currently on 5.18.0, the system appears to be okay after resume apart from the gpu which is usually giving a blank screen, occasionally a scrambled output. After rebooting, I see this in syslog: Jul 25 11:02:18 frog kernel: [240782.968674] amdgpu :04:00.0: amdgpu: GPU reset begin! Jul 25 11:02:19 frog kernel: [240783.974891] amdgpu :04:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_2.1.0 test failed (-110) Jul 25 11:02:19 frog kernel: [240783.988650] [drm] free PSP TMR buffer Jul 25 11:02:19 frog kernel: [240784.019057] CPU: 4 PID: 305612 Comm: kworker/u32:17 Not tainted 5.18.0 #1 Jul 25 11:02:19 frog kernel: [240784.019063] Hardware name: HP HP ENVY x360 Convertible 15-ds0xxx/85DD, BIOS F.20 05/28/2020 Jul 25 11:02:19 frog kernel: [240784.019067] Workqueue: amdgpu-reset-dev drm_sched_job_timedout [gpu_sched] Jul 25 11:02:19 frog kernel: [240784.019079] Call Trace: Jul 25 11:02:19 frog kernel: [240784.019082] Jul 25 11:02:19 frog kernel: [240784.019085] dump_stack_lvl+0x49/0x5f Jul 25 11:02:19 frog kernel: [240784.019095] dump_stack+0x10/0x12 Jul 25 11:02:19 frog kernel: [240784.019099] amdgpu_do_asic_reset+0x2f/0x4e0 [amdgpu] Jul 25 11:02:19 frog kernel: [240784.019278] amdgpu_device_gpu_recover_imp+0x41e/0xb50 [amdgpu] Jul 25 11:02:19 frog kernel: [240784.019452] amdgpu_job_timedout+0x155/0x1b0 [amdgpu] Jul 25 11:02:19 frog kernel: [240784.019674] drm_sched_job_timedout+0x74/0xf0 [gpu_sched] Jul 25 11:02:19 frog kernel: [240784.019681] ? amdgpu_cgs_destroy_device+0x10/0x10 [amdgpu] Jul 25 11:02:19 frog kernel: [240784.019896] ? drm_sched_job_timedout+0x74/0xf0 [gpu_sched] Jul 25 11:02:19 frog kernel: [240784.019903] process_one_work+0x227/0x440 Jul 25 11:02:19 frog kernel: [240784.019908] worker_thread+0x31/0x3d0 Jul 25 11:02:19 frog kernel: [240784.019912] ? process_one_work+0x440/0x440 Jul 25 11:02:19 frog kernel: [240784.019914] kthread+0xfe/0x130 Jul 25 11:02:19 frog kernel: [240784.019918] ? kthread_complete_and_exit+0x20/0x20 Jul 25 11:02:19 frog kernel: [240784.019923] ret_from_fork+0x22/0x30 Jul 25 11:02:19 frog kernel: [240784.019930] Jul 25 11:02:19 frog kernel: [240784.019934] amdgpu :04:00.0: amdgpu: MODE2 reset Jul 25 11:02:19 frog kernel: [240784.020178] amdgpu :04:00.0: amdgpu: GPU reset succeeded, trying to resume Jul 25 11:02:19 frog kernel: [240784.020552] [drm] PCIE GART of 1024M enabled. Jul 25 11:02:19 frog kernel: [240784.020555] [drm] PTB located at 0x00F40090 Jul 25 11:02:19 frog kernel: [240784.020577] [drm] VRAM is lost due to GPU reset! Jul 25 11:02:19 frog kernel: [240784.020579] [drm] PSP is resuming... Jul 25 11:02:19 frog kernel: [240784.040465] [drm] reserve 0x40 from 0xf47fc0 for PSP TMR I'm running the latest BIOS from HP. Is there anything I can do to work around this? Or anything I can do to help debug it? Regards, Tom Cook
Re: [PATCH 4/5] drm/amdgpu: revert context to stop engine before mode2 reset
Got it
Acked-by: Andrey Grodzovsky
Andrey
On 2022-07-26 06:01, Zhao, Victor wrote:
[AMD Official Use Only - General]
Hi Andrey,
For slow tests I mean the slow hang tests by quark tool.
An example here:
hang_vm_gfx_dispatch_slow.lua - This script runs on a graphics engine using
compute engine and has a hacked CS program which is massive and duplicates
standard CS program move code hundreds of thousands of times. The effect is a
very slowly executing CS program.
It's not a bad job but just need a very long time to finish. I suppose we don’t
have a way to stop shader here. And the running apps will be affected when
reset is done.
Thanks,
Victor
-Original Message-
From: Grodzovsky, Andrey
Sent: Tuesday, July 26, 2022 5:20 AM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Deng, Emily ;
Koenig, Christian
Subject: Re: [PATCH 4/5] drm/amdgpu: revert context to stop engine before mode2
reset
On 2022-07-22 03:34, Victor Zhao wrote:
For some hang caused by slow tests, engine cannot be stopped which may
cause resume failure after reset. In this case, force halt engine by
reverting context addresses
Can you maybe explain a bit more what exactly you mean by slow test and why
engine cannot be stopped in this case ?
Andrey
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c| 36 +
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 2 ++
4 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5498fda8617f..833dc5e224d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5037,6 +5037,7 @@ static void amdgpu_device_recheck_guilty_jobs(
/* set guilty */
drm_sched_increase_karma(s_job);
+ amdgpu_reset_prepare_hwcontext(adev, reset_context);
retry:
/* do hw reset */
if (amdgpu_sriov_vf(adev)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
index f8036f2b100e..c7b44aeb671b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
@@ -37,6 +37,7 @@ struct amdgpu_gfxhub_funcs {
void (*utcl2_harvest)(struct amdgpu_device *adev);
void (*mode2_save_regs)(struct amdgpu_device *adev);
void (*mode2_restore_regs)(struct amdgpu_device *adev);
+ void (*halt)(struct amdgpu_device *adev);
};
struct amdgpu_gfxhub {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 51cf8acd2d79..8cf53e039c11 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -646,6 +646,41 @@ static void gfxhub_v2_1_restore_regs(struct amdgpu_device
*adev)
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL,
adev->gmc.MC_VM_MX_L1_TLB_CNTL);
}
+static void gfxhub_v2_1_halt(struct amdgpu_device *adev) {
+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
+ int i;
+ uint32_t tmp;
+ int time = 1000;
+
+ gfxhub_v2_1_set_fault_enable_default(adev, false);
+
+ for (i = 0; i <= 14; i++) {
+ WREG32_SOC15_OFFSET(GC, 0,
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
+ i * hub->ctx_addr_distance, ~0);
+ WREG32_SOC15_OFFSET(GC, 0,
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
+ i * hub->ctx_addr_distance, ~0);
+ WREG32_SOC15_OFFSET(GC, 0,
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
+ i * hub->ctx_addr_distance,
+ 0);
+ WREG32_SOC15_OFFSET(GC, 0,
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
+ i * hub->ctx_addr_distance,
+ 0);
+ }
+ tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
+ while ((tmp & (GRBM_STATUS2__EA_BUSY_MASK |
+ GRBM_STATUS2__EA_LINK_BUSY_MASK)) != 0 &&
+ time) {
+ udelay(100);
+ time--;
+ tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
+ }
+
+ if (!time) {
+ DRM_WARN("failed to wait for GRBM(EA) idle\n");
+ }
+}
+
const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
.get_fb_location = gfxhub_v2_1_get_fb_location,
.get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset, @@ -658,4 +693,5
@@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
.utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
.mode2_save_regs = gfxhub_v2_1_save_regs,
.mode2_restore_regs = gfxhub_v2_1_restore_regs,
+ .halt = gfxhub_v2_1_halt,
};
Re: [PATCH 5/5] drm/amdgpu: reduce reset time
On 2022-07-26 05:40, Zhao, Victor wrote:
[AMD Official Use Only - General]
Hi Andrey,
Reply inline.
Thanks,
Victor
-Original Message-
From: Grodzovsky, Andrey
Sent: Tuesday, July 26, 2022 5:18 AM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Deng, Emily ;
Koenig, Christian
Subject: Re: [PATCH 5/5] drm/amdgpu: reduce reset time
On 2022-07-22 03:34, Victor Zhao wrote:
In multi container use case, reset time is important, so skip ring
tests and cp halt wait during ip suspending for reset as they are
going to fail and cost more time on reset
Why are they failing in this case ? Skipping ring tests is not the best idea as
you loose important indicator of system's sanity. Is there any way to make them
work ?
[Victor]: I've seen gfx ring test fail every time after a gfx engine hang. I
thought it should be expected as gfx is in a bad state. Do you know the reason
we have ring tests before reset? As we are going to reset the asic anyway.
Another approach could be to make the skip mode2 only or reduce the wait time
here.
I dug down in history and according to commit 'drm/amdgpu:unmap KCQ in
gfx hw_fini(v2)' you need to write to scratch register for completion of
queue unmap operation so you defently don't want to just skip it. I
agree in case
that the ring is hung this has no point but remember that GPU reset can
happen not only to a hunged ring but for other reasons (RAS, manual
reset e.t.c.) in which case you probably want to shut down gracefully here ?
I see we have adev->ip_blocks[i].status.hang flag which you maybe can
use here instead ?
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +++--
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 222d3d7ea076..f872495ccc3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -477,7 +477,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
RESET_QUEUES, 0, 0);
- if (adev->gfx.kiq.ring.sched.ready)
+ if (adev->gfx.kiq.ring.sched.ready && !amdgpu_in_reset(adev))
r = amdgpu_ring_test_helper(kiq_ring);
spin_unlock(&adev->gfx.kiq.ring_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index fafbad3cf08d..9ae29023e38f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5971,16 +5971,19 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device
*adev, bool enable)
WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
}
- for (i = 0; i < adev->usec_timeout; i++) {
- if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
- break;
- udelay(1);
- }
-
- if (i >= adev->usec_timeout)
- DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
+ if (!amdgpu_in_reset(adev)) {
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
+ break;
+ udelay(1);
+ }
+ if (i >= adev->usec_timeout)
+ DRM_ERROR("failed to %s cp gfx\n",
+ enable ? "unhalt" : "halt");
+ }
return 0;
+
}
This change has impact beyond container case no ? We had no issue with this
code during regular reset cases so why we would give up on this code which
confirms CP is idle ? What is the side effect of skipping this during all GPU
resets ?
Andrey
[Victor]: I see "failed to halt cp gfx" with regular reset cases as well when
doing a gfx hang test using quark. I haven't seen a side effect with Mode1 reset yet but
maybe shorten the wait time could be better?
Same as above i guess, it would indeed time out for a hung ring but GPU
reset happens not only because of hung rings but for other reasons.
Andrey
static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device
*adev) @@ -7569,8 +7572,10 @@ static int gfx_v10_0_kiq_disable_kgq(struct
amdgpu_device *adev)
for (i = 0; i < adev->gfx.num_gfx_rings; i++)
kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
PREEMPT_QUEUES, 0, 0);
-
- return amdgpu_ring_test_helper(kiq_ring);
+ if (!amdgpu_in_reset(adev))
+ return amdgpu_ring_test_helper(kiq_ring);
+ else
+ return 0;
}
#endif
@@ -7610,6 +7615,7 @@ static int gfx_v10_0_hw_fini(void *handle)
return 0;
}
+
gfx_v10_0_cp_enable(adev, false);
gfx_v10_0_
[PATCH] drm/ttm: Fix dummy res NULL ptr deref bug
Check the bo->resource value before accessing the resource mem_type. [ 40.191227][ T184] general protection fault, probably for non-canonical address 0xdc02: [#1] SMP KASAN PTI [ 40.192995][ T184] KASAN: null-ptr-deref in range [0x0010-0x0017] [ 40.194411][ T184] CPU: 1 PID: 184 Comm: systemd-udevd Not tainted 5.19.0-rc4-00721-gb297c22b7070 #1 [ 40.196063][ T184] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.16.0-debian-1.16.0-4 04/01/2014 [ 40.199605][ T184] RIP: 0010:ttm_bo_validate+0x1b3/0x240 [ttm] [ 40.200754][ T184] Code: e8 72 c5 ff ff 83 f8 b8 74 d4 85 c0 75 54 49 8b 9e 58 01 00 00 48 b8 00 00 00 00 00 fc ff df 48 8d 7b 10 48 89 fa 48 c1 ea 03 <0f> b6 04 02 84 c0 74 04 3c 03 7e 44 8b 53 10 31 c0 85 d2 0f 85 58 [ 40.203685][ T184] RSP: 0018:c96df0c8 EFLAGS: 00010202 [ 40.204630][ T184] RAX: dc00 RBX: RCX: 11102f4bb71b [ 40.205864][ T184] RDX: 0002 RSI: c96df208 RDI: 0010 [ 40.207102][ T184] RBP: 192dbe1a R08: c96df208 R09: [ 40.208394][ T184] R10: 88817a5f R11: 0001 R12: c96df110 [ 40.209692][ T184] R13: c96df0f0 R14: 88817a5db800 R15: c96df208 [ 40.210862][ T184] FS: 7f6b1d16e8c0() GS:88839d70() knlGS: [ 40.212250][ T184] CS: 0010 DS: ES: CR0: 80050033 [ 40.213275][ T184] CR2: 55a1001d4ff0 CR3: 0001700f4000 CR4: 06e0 [ 40.214469][ T184] Call Trace: [ 40.214974][ T184] [ 40.215438][ T184] ? ttm_bo_bounce_temp_buffer+0x140/0x140 [ttm] [ 40.216572][ T184] ? mutex_spin_on_owner+0x240/0x240 [ 40.217456][ T184] ? drm_vma_offset_add+0xaa/0x100 [drm] [ 40.218457][ T184] ttm_bo_init_reserved+0x3d6/0x540 [ttm] [ 40.219410][ T184] ? shmem_get_inode+0x744/0x980 [ 40.220231][ T184] ttm_bo_init_validate+0xb1/0x200 [ttm] [ 40.221172][ T184] ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper] [ 40.222530][ T184] ? ttm_bo_init_reserved+0x540/0x540 [ttm] [ 40.223643][ T184] ? __do_sys_finit_module+0x11a/0x1c0 [ 40.224654][ T184] ? __shmem_file_setup+0x102/0x280 [ 40.234764][ T184] drm_gem_vram_create+0x305/0x480 [drm_vram_helper] [ 40.235766][ T184] ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper] [ 40.236846][ T184] ? __kasan_slab_free+0x108/0x180 [ 40.237650][ T184] drm_gem_vram_fill_create_dumb+0x134/0x340 [drm_vram_helper] [ 40.238864][ T184] ? local_pci_probe+0xdf/0x180 [ 40.239674][ T184] ? drmm_vram_helper_init+0x400/0x400 [drm_vram_helper] [ 40.240826][ T184] drm_client_framebuffer_create+0x19c/0x400 [drm] [ 40.241955][ T184] ? drm_client_buffer_delete+0x200/0x200 [drm] [ 40.243001][ T184] ? drm_client_pick_crtcs+0x554/0xb80 [drm] [ 40.244030][ T184] drm_fb_helper_generic_probe+0x23f/0x940 [drm_kms_helper] [ 40.245226][ T184] ? __cond_resched+0x1c/0xc0 [ 40.245987][ T184] ? drm_fb_helper_memory_range_to_clip+0x180/0x180 [drm_kms_helper] [ 40.247316][ T184] ? mutex_unlock+0x80/0x100 [ 40.248005][ T184] ? __mutex_unlock_slowpath+0x2c0/0x2c0 [ 40.249083][ T184] drm_fb_helper_single_fb_probe+0x907/0xf00 [drm_kms_helper] [ 40.250314][ T184] ? drm_fb_helper_check_var+0x1180/0x1180 [drm_kms_helper] [ 40.251540][ T184] ? __cond_resched+0x1c/0xc0 [ 40.252321][ T184] ? mutex_lock+0x9f/0x100 [ 40.253062][ T184] __drm_fb_helper_initial_config_and_unlock+0xb9/0x2c0 [drm_kms_helper] [ 40.254394][ T184] drm_fbdev_client_hotplug+0x56f/0x840 [drm_kms_helper] [ 40.255477][ T184] drm_fbdev_generic_setup+0x165/0x3c0 [drm_kms_helper] [ 40.256607][ T184] bochs_pci_probe+0x6b7/0x900 [bochs] [ 40.257515][ T184] ? _raw_spin_lock_irqsave+0x87/0x100 [ 40.258312][ T184] ? bochs_hw_init+0x480/0x480 [bochs] [ 40.259244][ T184] ? bochs_hw_init+0x480/0x480 [bochs] [ 40.260186][ T184] local_pci_probe+0xdf/0x180 [ 40.260928][ T184] pci_call_probe+0x15f/0x500 [ 40.265798][ T184] ? _raw_spin_lock+0x81/0x100 [ 40.266508][ T184] ? pci_pm_suspend_noirq+0x980/0x980 [ 40.267322][ T184] ? pci_assign_irq+0x81/0x280 [ 40.268096][ T184] ? pci_match_device+0x351/0x6c0 [ 40.268883][ T184] ? kernfs_put+0x18/0x40 [ 40.269611][ T184] pci_device_probe+0xee/0x240 [ 40.270352][ T184] really_probe+0x435/0xa80 [ 40.271021][ T184] __driver_probe_device+0x2ab/0x480 [ 40.271828][ T184] driver_probe_device+0x49/0x140 [ 40.272627][ T184] __driver_attach+0x1bd/0x4c0 [ 40.273372][ T184] ? __device_attach_driver+0x240/0x240 [ 40.274273][ T184] bus_for_each_dev+0x11e/0x1c0 [ 40.275080][ T184] ? subsys_dev_iter_exit+0x40/0x40 [ 40.275951][ T184] ? klist_add_tail+0x132/0x280 [ 40.276767][ T184] bus_add_driver+0x39b/0x580 [ 40.277574][ T184] driver_register+0x20f/0x3c0 [ 40.278281][ T184] ? 0xc0
amdgpu: misc ugliness and inconsistency
Hi AMD devs, I guess there was a big merge in linux-next the other day? Anyway, it generated a lot of Smatch warnings. I reported some of them but there is just a lot so I'm mass reporting these. Inconsistent NULL checking can be harmless. Part of the function assumes that the pointer can be NULL and part assumes that it cannot. It does not make sense, but it is often harmless and the correct response is just to remove the NULL check. The other class of reports is inconsistent indenting. There were two bugs but I already fixed one and reported the other so these should be harmless. regards, dan carpenter Inconsistent NULL checks: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1271 handle_cursor_update() error: we previously assumed 'afb' could be null (see line 1230) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:1017 dcn201_acquire_idle_pipe_for_layer() error: we previously assumed 'head_pipe' could be null (see line 1011) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.c:222 dcn21_set_backlight_level() error: we previously assumed 'panel_cntl' could be null (see line 213) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:765 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 749) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:767 dcn30_apply_idle_power_optimizations() error: we previously assumed 'plane' could be null (see line 749) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hwseq.c:284 dcn31_init_hw() error: we previously assumed 'dc->clk_mgr' could be null (see line 117) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:896 dcn32_init_hw() error: we previously assumed 'dc->clk_mgr' could be null (see line 738) drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:777 subvp_drr_schedulable() error: we previously assumed 'pipe->stream' could be null (see line 768) drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:868 subvp_vblank_schedulable() error: we previously assumed 'subvp_pipe' could be null (see line 860) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hwseq.c:250 dcn201_init_hw() warn: variable dereferenced before check 'res_pool->dccg' (see line 227) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:782 dcn20_enable_stream_timing() warn: variable dereferenced before check 'pipe_ctx->stream_res.tg' (see line 698) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hwseq.c:157 dcn31_init_hw() warn: variable dereferenced before check 'res_pool->dccg' (see line 147) drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:765 dcn32_init_hw() warn: variable dereferenced before check 'res_pool->dccg' (see line 742) Bad indenting: drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:107 dcn201_update_clocks() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c:716 dcn314_clk_mgr_construct() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c:655 dcn315_clk_mgr_construct() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c:683 dcn316_clk_mgr_construct() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c:726 dcn31_clk_mgr_construct() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2152 dcn10_align_pixel_clocks() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:854 dcn301_hubbub_create() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:618 dcn32_set_output_transfer_func() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:910 dcn32_init_hw() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mpc.c:306 mpc32_get_shaper_current() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource.c:1979 dcn32_resource_construct() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource.c:2319 dcn32_resource_construct() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:205 dcn303_fpu_update_bw_bounding_box() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:355 dcn303_fpu_init_soc_bounding_box() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.c:185 optc3_fpu_set_vrr_m_const() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.c:355 dcn30_fpu_set_mcif_arb_params() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.c:384 dcn30_fpu_calculate_wm_and_dlg() warn: inconsistent indenting drivers/g
Re: [bug report] drm/amd/display: use FB pitch to fill dc_cursor_attributes
On Tue, Jul 26, 2022 at 03:27:54PM +, Simon Ser wrote: > Hi, > > plane->state->fb is NULL iff afb is NULL. There is an early return to > make sure the dereferences don't cause a segfault. > Are you talking about this: if (!plane->state->fb && !old_plane_state->fb) return; Should the && be ||? regards, dan carpenter
Re: [bug report] drm/amd/display: use FB pitch to fill dc_cursor_attributes
Hi, plane->state->fb is NULL iff afb is NULL. There is an early return to make sure the dereferences don't cause a segfault. Simon
[bug report] drm/amd/display: DML changes for DCN32/321
Hello Aurabindo Pillai,
The patch dda4fb85e433: "drm/amd/display: DML changes for DCN32/321"
from Feb 21, 2022, leads to the following Smatch static checker
warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:1631
dml32_TruncToValidBPP() error: uninitialized symbol 'NonDSCBPP3'.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:1644
dml32_TruncToValidBPP() error: uninitialized symbol 'NonDSCBPP3'.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:1651
dml32_TruncToValidBPP() warn: ignoring unreachable code.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:713
dml32_CalculateSwathWidth() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c
1540 double dml32_TruncToValidBPP(
1541 double LinkBitRate,
1542 unsigned int Lanes,
1543 unsigned int HTotal,
1544 unsigned int HActive,
1545 double PixelClock,
1546 double DesiredBPP,
1547 bool DSCEnable,
1548 enum output_encoder_class Output,
1549 enum output_format_class Format,
1550 unsigned int DSCInputBitPerComponent,
1551 unsigned int DSCSlices,
1552 unsigned int AudioRate,
1553 unsigned int AudioLayout,
1554 enum odm_combine_mode ODMModeNoDSC,
1555 enum odm_combine_mode ODMModeDSC,
1556 /* Output */
1557 unsigned int *RequiredSlots)
1558 {
1559 doubleMaxLinkBPP;
1560 unsigned int MinDSCBPP;
1561 doubleMaxDSCBPP;
1562 unsigned int NonDSCBPP0;
1563 unsigned int NonDSCBPP1;
1564 unsigned int NonDSCBPP2;
1565 unsigned int NonDSCBPP3;
1566
1567 if (Format == dm_420) {
1568 NonDSCBPP0 = 12;
1569 NonDSCBPP1 = 15;
1570 NonDSCBPP2 = 18;
1571 MinDSCBPP = 6;
1572 MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16;
1573 } else if (Format == dm_444) {
1574 NonDSCBPP0 = 18;
1575 NonDSCBPP1 = 24;
1576 NonDSCBPP2 = 30;
1577 NonDSCBPP3 = 36;
NonDSCBPP3 is initialized here but not on other paths.
1578 MinDSCBPP = 8;
1579 MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16;
1580 } else {
1581 if (Output == dm_hdmi) {
1582 NonDSCBPP0 = 24;
1583 NonDSCBPP1 = 24;
1584 NonDSCBPP2 = 24;
1585 } else {
1586 NonDSCBPP0 = 16;
1587 NonDSCBPP1 = 20;
1588 NonDSCBPP2 = 24;
1589 }
1590 if (Format == dm_n422) {
1591 MinDSCBPP = 7;
1592 MaxDSCBPP = 2 * DSCInputBitPerComponent - 1.0
/ 16.0;
1593 } else {
1594 MinDSCBPP = 8;
1595 MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0
/ 16.0;
1596 }
1597 }
1598 if (Output == dm_dp2p0) {
1599 MaxLinkBPP = LinkBitRate * Lanes / PixelClock * 128 /
132 * 383 / 384 * 65536 / 65540;
1600 } else if (DSCEnable && Output == dm_dp) {
1601 MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock
* (1 - 2.4 / 100);
1602 } else {
1603 MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock;
1604 }
1605
1606 if (DSCEnable) {
1607 if (ODMModeDSC == dm_odm_combine_mode_4to1)
1608 MaxLinkBPP = dml_min(MaxLinkBPP, 16);
1609 else if (ODMModeDSC == dm_odm_combine_mode_2to1)
1610 MaxLinkBPP = dml_min(MaxLinkBPP, 32);
1611 else if (ODMModeDSC == dm_odm_split_mode_1to2)
1612 MaxLinkBPP = 2 * MaxLinkBPP;
1613 } else {
1614 if (ODMModeNoDSC == dm_odm_combine_mode_4to1)
1615 MaxLinkBPP = dml_min(MaxLinkBPP, 16);
1616 else if (ODMModeNoDSC == dm_odm_combine_mode_2to1)
1617 MaxLinkBPP = dml_min(MaxLinkBPP, 32);
1618 else if (ODMModeNoDSC == dm_odm_split_mode_1to2)
1619 MaxLinkBPP = 2 * MaxLinkBPP;
1620 }
1621
1622 if (DesiredBPP == 0) {
1623
[PATCH] drm/amd/display: Fix apply_synaptics_fifo_reset_wa()
There is a stray return which accidentally turns the last part of the
function into dead code.
Fixes: 2ca97adccdc9 ("drm/amd/display: Add Synaptics Fifo Reset Workaround")
Signed-off-by: Dan Carpenter
---
>From static analysis. Untested.
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index a0154a5f7183..0d200e276e67 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -671,7 +671,6 @@ static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux
*aux)
return;
data[0] |= (1 << 1); // set bit 1 to 1
- return;
if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
return;
--
2.35.1
[bug report] drm/amd/display: Synchronize displays with different timings
Hello Vladimir Stempen,
The patch 77a2b7265f20: "drm/amd/display: Synchronize displays with
different timings" from Dec 29, 2020, leads to the following Smatch
static checker warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2199
dcn10_enable_vblanks_synchronization() warn: if statement not indented
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2207
dcn10_enable_vblanks_synchronization() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c
2191 DC_SYNC_INFO("Aligning DP DTOs\n");
2192
2193 master = dcn10_align_pixel_clocks(dc, group_size,
grouped_pipes);
2194
2195 DC_SYNC_INFO("Synchronizing VBlanks\n");
2196
2197 if (master >= 0) {
2198 for (i = 0; i < group_size; i++) {
2199 if (i != master &&
!grouped_pipes[i]->stream->has_non_synchronizable_pclk)
2200
grouped_pipes[i]->stream_res.tg->funcs->align_vblanks(
2201 grouped_pipes[master]->stream_res.tg,
2202 grouped_pipes[i]->stream_res.tg,
2203
grouped_pipes[master]->stream->timing.pix_clk_100hz,
2204
grouped_pipes[i]->stream->timing.pix_clk_100hz,
2205
get_clock_divider(grouped_pipes[master], false),
2206 get_clock_divider(grouped_pipes[i],
false));
--> 2207
grouped_pipes[i]->stream->vblank_synchronized = true;
It looks like this is supposed to have curly braces (this code is buggy).
2208 }
2209 grouped_pipes[master]->stream->vblank_synchronized =
true;
2210 DC_SYNC_INFO("Sync complete\n");
2211 }
2212
2213 for (i = 1; i < group_size; i++) {
2214 opp = grouped_pipes[i]->stream_res.opp;
2215 tg = grouped_pipes[i]->stream_res.tg;
2216 tg->funcs->get_otg_active_size(tg, &width, &height);
2217 if (opp->funcs->opp_program_dpg_dimensions)
2218 opp->funcs->opp_program_dpg_dimensions(opp,
width, height);
2219 }
2220 }
regards,
dan carpenter
Re: [PATCH] drm/amd/display: fix signedness bug in execute_synaptics_rc_command()
Applied. Thanks!
Alex
On Tue, Jul 26, 2022 at 11:16 AM Dan Carpenter wrote:
>
> The "ret" variable needs to be signed for the error handling to work.
>
> Fixes: 2ca97adccdc9 ("drm/amd/display: Add Synaptics Fifo Reset Workaround")
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index d66e3cd64ebd..a0154a5f7183 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -569,7 +569,7 @@ static bool execute_synaptics_rc_command(struct
> drm_dp_aux *aux,
> unsigned char rc_cmd = 0;
> unsigned char rc_result = 0xFF;
> unsigned char i = 0;
> - uint8_t ret = 0;
> + int ret;
>
> if (is_write_cmd) {
> // write rc data
> --
> 2.35.1
>
[bug report] drm/amd/display: use FB pitch to fill dc_cursor_attributes
Hello Simon Ser,
The patch 03a663673063: "drm/amd/display: use FB pitch to fill
dc_cursor_attributes" from Dec 2, 2020, leads to the following Smatch
static checker warning:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1271
handle_cursor_update()
error: we previously assumed 'afb' could be null (see line 1230)
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c
1222 void handle_cursor_update(struct drm_plane *plane,
1223 struct drm_plane_state
*old_plane_state)
1224 {
1225 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1226 struct amdgpu_framebuffer *afb =
to_amdgpu_framebuffer(plane->state->fb);
1227 struct drm_crtc *crtc = afb ? plane->state->crtc :
old_plane_state->crtc;
afb is container_of() but it's basically a cast in this case. I would
always prefer to check "plane->state->fb" for NULL instead of the
container_of(), but that's sort of a style debate, I guess. Some people
really like checking the returned pointer and add build time asserts to
ensure that the container_of() is a no-op.
1228 struct dm_crtc_state *crtc_state = crtc ?
to_dm_crtc_state(crtc->state) : NULL;
1229 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1230 uint64_t address = afb ? afb->address : 0;
1231 struct dc_cursor_position position = {0};
1232 struct dc_cursor_attributes attributes;
1233 int ret;
1234
1235 if (!plane->state->fb && !old_plane_state->fb)
1236 return;
1237
1238 DC_LOG_CURSOR("%s: crtc_id=%d with size %d to %d\n",
1239 __func__,
1240 amdgpu_crtc->crtc_id,
1241 plane->state->crtc_w,
1242 plane->state->crtc_h);
1243
1244 ret = get_cursor_position(plane, crtc, &position);
1245 if (ret)
1246 return;
1247
1248 if (!position.enable) {
1249 /* turn off cursor */
1250 if (crtc_state && crtc_state->stream) {
1251 mutex_lock(&adev->dm.dc_lock);
1252
dc_stream_set_cursor_position(crtc_state->stream,
1253 &position);
1254 mutex_unlock(&adev->dm.dc_lock);
1255 }
1256 return;
1257 }
1258
1259 amdgpu_crtc->cursor_width = plane->state->crtc_w;
1260 amdgpu_crtc->cursor_height = plane->state->crtc_h;
1261
1262 memset(&attributes, 0, sizeof(attributes));
1263 attributes.address.high_part = upper_32_bits(address);
1264 attributes.address.low_part = lower_32_bits(address);
1265 attributes.width = plane->state->crtc_w;
1266 attributes.height= plane->state->crtc_h;
1267 attributes.color_format =
CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
1268 attributes.rotation_angle= 0;
1269 attributes.attribute_flags.value = 0;
1270
--> 1271 attributes.pitch = afb->base.pitches[0] /
afb->base.format->cpp[0];
^ ^
Unchecked dereferences.
1272
1273 if (crtc_state->stream) {
1274 mutex_lock(&adev->dm.dc_lock);
1275 if
(!dc_stream_set_cursor_attributes(crtc_state->stream,
1276 &attributes))
1277 DRM_ERROR("DC failed to set cursor
attributes\n");
1278
1279 if (!dc_stream_set_cursor_position(crtc_state->stream,
1280&position))
1281 DRM_ERROR("DC failed to set cursor
position\n");
1282 mutex_unlock(&adev->dm.dc_lock);
1283 }
1284 }
regards,
dan carpenter
[bug report] drm/amd/display: Add dcn3.01 support to DC (v2)
[ It's not clear to me why Smatch is complaining about 2 year old code
but that seems like the buggy commit? ]
Hello Roman Li,
The patch 3a83e4e64bb1: "drm/amd/display: Add dcn3.01 support to DC
(v2)" from Sep 29, 2020, leads to the following Smatch static checker
warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.c:539
find_dcfclk_for_voltage()
error: buffer overflow 'clock_table->DcfClocks' 7 <= 7
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.c
532 static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks
*clock_table,
533 unsigned int voltage)
534 {
535 int i;
536
537 for (i = 0; i < VG_NUM_SOC_VOLTAGE_LEVELS; i++) {
538 if (clock_table->SocVoltage[i] == voltage)
--> 539 return clock_table->DcfClocks[i];
^
The ->SocVoltage[] array has 8 elements but the ->DcfClocks[] array
only has 7 and the mismatch leads to an out of bounds.
540 }
541
542 ASSERT(0);
543 return 0;
544 }
regards,
dan carpenter
[bug report] drm/amd/display: Initial DC support for Beige Goby
Hello Aurabindo Pillai,
The patch cd6d421e3d1a: "drm/amd/display: Initial DC support for
Beige Goby" from Mar 15, 2021, leads to the following Smatch static
checker warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c:392
dcn303_stream_encoder_create()
error: buffer overflow 'stream_enc_regs' 2 <= 4
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1024
dcn301_stream_encoder_create() error: buffer overflow 'stream_enc_regs' 4
<= 5
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn303/dcn303_resource.c
366 static struct stream_encoder *dcn303_stream_encoder_create(enum
engine_id eng_id, struct dc_context *ctx)
367 {
368 struct dcn10_stream_encoder *enc1;
369 struct vpg *vpg;
370 struct afmt *afmt;
371 int vpg_inst;
372 int afmt_inst;
373
374 /* Mapping of VPG, AFMT, DME register blocks to DIO block
instance */
375 if (eng_id <= ENGINE_ID_DIGE) {
This tells us that eng_id can be <= 4.
376 vpg_inst = eng_id;
377 afmt_inst = eng_id;
378 } else
379 return NULL;
380
381 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
382 vpg = dcn303_vpg_create(ctx, vpg_inst);
383 afmt = dcn303_afmt_create(ctx, afmt_inst);
384
385 if (!enc1 || !vpg || !afmt) {
386 kfree(enc1);
387 kfree(vpg);
388 kfree(afmt);
389 return NULL;
390 }
391
--> 392 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
eng_id, vpg, afmt, &stream_enc_regs[eng_id],
^^^
But anything more than 1 is out of bounds. The dcn301 code is basically
the same.
393 &se_shift, &se_mask);
394
395 return &enc1->base;
396 }
regards,
dan carpenter
[bug report] drm/amdgpu: create I2S platform devices for Jadeite platform
Hello Vijendar Mukunda,
The patch 4c33e5179ff1: "drm/amdgpu: create I2S platform devices for
Jadeite platform" from Jun 30, 2022, leads to the following Smatch
static checker warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:393 acp_hw_init()
error: buffer overflow 'i2s_pdata' 3 <= 3
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:396 acp_hw_init()
error: buffer overflow 'i2s_pdata' 3 <= 3
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
225 static int acp_hw_init(void *handle)
226 {
227 int r;
228 u64 acp_base;
229 u32 val = 0;
230 u32 count = 0;
231 struct i2s_platform_data *i2s_pdata = NULL;
232
233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
234
235 const struct amdgpu_ip_block *ip_block =
236 amdgpu_device_ip_get_ip_block(adev,
AMD_IP_BLOCK_TYPE_ACP);
237
238 if (!ip_block)
239 return -EINVAL;
240
241 r = amd_acp_hw_init(adev->acp.cgs_device,
242 ip_block->version->major,
ip_block->version->minor);
243 /* -ENODEV means board uses AZ rather than ACP */
244 if (r == -ENODEV) {
245 amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_ACP, true);
246 return 0;
247 } else if (r) {
248 return r;
249 }
250
251 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
252 return -EINVAL;
253
254 acp_base = adev->rmmio_base;
255 adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain),
GFP_KERNEL);
256 if (!adev->acp.acp_genpd)
257 return -ENOMEM;
258
259 adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
260 adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
261 adev->acp.acp_genpd->gpd.power_on = acp_poweron;
262 adev->acp.acp_genpd->adev = adev;
263
264 pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
265 dmi_check_system(acp_quirk_table);
266 switch (acp_machine_id) {
267 case ST_JADEITE:
268 {
269 adev->acp.acp_cell = kcalloc(2, sizeof(struct mfd_cell),
270 GFP_KERNEL);
271 if (!adev->acp.acp_cell) {
272 r = -ENOMEM;
273 goto failure;
274 }
275
276 adev->acp.acp_res = kcalloc(3, sizeof(struct resource),
GFP_KERNEL);
277 if (!adev->acp.acp_res) {
278 r = -ENOMEM;
279 goto failure;
280 }
281
282 i2s_pdata = kcalloc(1, sizeof(struct
i2s_platform_data), GFP_KERNEL);
283 if (!i2s_pdata) {
284 r = -ENOMEM;
285 goto failure;
286 }
287
288 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
289 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
290 i2s_pdata[0].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
291 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
292 i2s_pdata[0].i2s_reg_comp1 =
ACP_I2S_COMP1_CAP_REG_OFFSET;
293 i2s_pdata[0].i2s_reg_comp2 =
ACP_I2S_COMP2_CAP_REG_OFFSET;
294
295 adev->acp.acp_res[0].name = "acp2x_dma";
296 adev->acp.acp_res[0].flags = IORESOURCE_MEM;
297 adev->acp.acp_res[0].start = acp_base;
298 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
299
300 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play_cap";
301 adev->acp.acp_res[1].flags = IORESOURCE_MEM;
302 adev->acp.acp_res[1].start = acp_base +
ACP_I2S_CAP_REGS_START;
303 adev->acp.acp_res[1].end = acp_base +
ACP_I2S_CAP_REGS_END;
304
305 adev->acp.acp_res[2].name = "acp2x_dma_irq";
306 adev->acp.acp_res[2].flags = IORESOURCE_IRQ;
307 adev->acp.acp_res[2].start =
amdgpu_irq_create_mapping(adev, 162);
308 adev->acp.acp_res[2].end = adev->acp.acp_res[2].start;
309
310 adev->acp.acp_cell[0].name = "acp_audio_dma";
311 adev->acp.acp_cell[0].num_resources = 3;
312 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
313 adev->acp.acp_cell[0].platform_data = &adev->asic_type;
314 adev->acp.acp_cell[0].pdata_size =
sizeof(adev->asic_type);
315
316 adev->acp.acp_cell[1].name =
[PATCH] drm/amd/display: fix signedness bug in execute_synaptics_rc_command()
The "ret" variable needs to be signed for the error handling to work.
Fixes: 2ca97adccdc9 ("drm/amd/display: Add Synaptics Fifo Reset Workaround")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index d66e3cd64ebd..a0154a5f7183 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -569,7 +569,7 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux
*aux,
unsigned char rc_cmd = 0;
unsigned char rc_result = 0xFF;
unsigned char i = 0;
- uint8_t ret = 0;
+ int ret;
if (is_write_cmd) {
// write rc data
--
2.35.1
Re: [PATCH 01/20] drm/amd/display: Clean up some inconsistent indenting
Applied the series. Thanks!
Alex
On Tue, Jul 26, 2022 at 3:26 AM Jiapeng Chong
wrote:
>
> No functional modification involved.
>
> smatch warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:910
> dcn32_init_hw() warn: inconsistent indenting.
>
> Reported-by: Abaci Robot
> Signed-off-by: Jiapeng Chong
> ---
> drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
> b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
> index b6bada383958..201516a62b4b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
> @@ -907,10 +907,10 @@ void dcn32_init_hw(struct dc *dc)
> dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
>
> // Get DMCUB capabilities
> -if (dc->ctx->dmub_srv) {
> - dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
> - dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
> -}
> + if (dc->ctx->dmub_srv) {
> + dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
> + dc->caps.dmub_caps.psr =
> dc->ctx->dmub_srv->dmub->feature_caps.psr;
> + }
> }
>
> static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
> --
> 2.20.1.7.g153144c
>
Re: [PATCH v3 2/3] drm/amdkfd: Set svm range max pages
Am 2022-07-25 um 17:17 schrieb Philip Yang:
This will be used to split giant svm range into smaller ranges, to
support VRAM overcommitment by giant range and improve GPU retry fault
recover on giant range.
Signed-off-by: Philip Yang
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 21 +
drivers/gpu/drm/amd/amdkfd/kfd_svm.h | 3 +++
3 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 9667015a6cbc..b1f87aa6138b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -1019,6 +1019,8 @@ int svm_migrate_init(struct amdgpu_device *adev)
amdgpu_amdkfd_reserve_system_mem(SVM_HMM_PAGE_STRUCT_SIZE(size));
+ svm_range_set_max_pages(adev);
+
pr_info("HMM registered %ldMB device memory\n", size >> 20);
return 0;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index b592aee6d9d6..9d855890658e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -46,6 +46,12 @@
*/
#define AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING (2UL * NSEC_PER_MSEC)
+/* Giant svm range split into smaller ranges based on this, it is decided using
+ * minimum of all dGPU/APU 1/32 VRAM size, between 2MB to 1GB and alignment to
+ * power of 2MB.
+ */
+uint64_t max_svm_range_pages;
+
struct criu_svm_metadata {
struct list_head list;
struct kfd_criu_svm_range_priv_data data;
@@ -1870,6 +1876,21 @@ static struct svm_range *svm_range_clone(struct
svm_range *old)
return new;
}
+void svm_range_set_max_pages(struct amdgpu_device *adev)
+{
+ uint64_t max_pages;
+ uint64_t pages, _pages;
+
+ /* 1/32 VRAM size in pages */
+ pages = adev->gmc.real_vram_size >> 17;
+ pages = clamp(pages, 1ULL << 9, 1ULL << 18);
+ pages = rounddown_pow_of_two(pages);
+ do {
+ max_pages = READ_ONCE(max_svm_range_pages);
+ _pages = min_not_zero(max_pages, pages);
+ } while (cmpxchg(&max_svm_range_pages, max_pages, _pages) != max_pages);
+}
+
/**
* svm_range_add - add svm range and handle overlap
* @p: the range add to this process svms
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
index eab7f6d3b13c..9156b041ef17 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
@@ -204,6 +204,9 @@ void svm_range_list_lock_and_flush_work(struct
svm_range_list *svms, struct mm_s
#define KFD_IS_SVM_API_SUPPORTED(dev) ((dev)->pgmap.type != 0)
void svm_range_bo_unref_async(struct svm_range_bo *svm_bo);
+
+void svm_range_set_max_pages(struct amdgpu_device *adev);
+
#else
struct kfd_process;
Re: [PATCH] drm/amdkfd: fix kgd_mem memory leak when importing dmabuf
Am 2022-07-26 um 07:15 schrieb Lang Yu:
The kgd_mem memory allocated in amdgpu_amdkfd_gpuvm_import_dmabuf()
is not freed properly.
Explicitly free it in amdgpu_amdkfd_gpuvm_free_memory_of_gpu()
under condition "mem->bo->kfd_bo != mem".
Suggested-by: Felix Kuehling
Signed-off-by: Lang Yu
Some suggestions inline to make the code more readable. Other than that,
the patch is
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 6bba6961eee7..086bed40cf34 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1803,6 +1803,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
uint64_t *size)
{
struct amdkfd_process_info *process_info = mem->process_info;
+ struct kgd_mem *tmp_mem = mem->bo->kfd_bo;
Right, you need this because using mem after drm_gem_object_put would be
a potential use-after-free. Instead of saving this pointer with some
obscure variable name, you could just save a bool with a more meaningful
name. E.g.:
bool use_release_notifier = (mem->bo->kfd_bo == mem);
This way you have the entire condition in one place, and the variable
name explains the meaning.
unsigned long bo_size = mem->bo->tbo.base.size;
struct kfd_mem_attachment *entry, *tmp;
struct bo_vm_reservation_context ctx;
@@ -1895,6 +1896,13 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
*/
drm_gem_object_put(&mem->bo->tbo.base);
+ /*
+* For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
+* explicitly free it here.
+*/
+ if (mem != tmp_mem)
if (!use_release_notifier)
kfree(mem);
Regards,
Felix
+ kfree(mem);
+
return ret;
}
Re: [PATCH v2] drm/amd/pm: Add get_gfx_off_status interface for yellow carp
Às 03:29 de 26/07/22, shikai@amd.com escreveu: > From: Shikai Guo > > add get_gfx_off_status interface to yellow_carp_ppt_funcs structure. > > Signed-off-by: Shikai Guo > --- Reviewed-by: André Almeida
RE: [PATCH v2] drm/amd/pm: Add get_gfx_off_status interface for yellow carp
[Public]
Reviewed-by: Prike Liang
> -Original Message-
> From: amd-gfx On Behalf Of
> shikai@amd.com
> Sent: Tuesday, July 26, 2022 2:29 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
> ; Quan, Evan ; Liu, Aaron
>
> Subject: [PATCH v2] drm/amd/pm: Add get_gfx_off_status interface for
> yellow carp
>
> From: Shikai Guo
>
> add get_gfx_off_status interface to yellow_carp_ppt_funcs structure.
>
> Signed-off-by: Shikai Guo
> ---
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 31
> +++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index 70cbc46341a3..04e56b0b3033 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -42,6 +42,11 @@
> #undef pr_info
> #undef pr_debug
>
> +#define regSMUIO_GFX_MISC_CNTL
> 0x00c5
> +#define regSMUIO_GFX_MISC_CNTL_BASE_IDX
> 0
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
> 0x0006L
> +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1L
> +
> #define FEATURE_MASK(feature) (1ULL << feature) #define
> SMC_DPM_FEATURE ( \
> FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -587,6 +592,31
> @@ static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
> return sizeof(struct gpu_metrics_v2_1); }
>
> +/**
> + * yellow_carp_get_gfxoff_status - get gfxoff status
> + *
> + * @smu: smu_context pointer
> + *
> + * This function will be used to get gfxoff status
> + *
> + * Returns 0=GFXOFF(default).
> + * Returns 1=Transition out of GFX State.
> + * Returns 2=Not in GFXOFF.
> + * Returns 3=Transition into GFXOFF.
> + */
> +static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
> +{
> + uint32_t reg;
> + uint32_t gfxoff_status = 0;
> + struct amdgpu_device *adev = smu->adev;
> +
> + reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
> + gfxoff_status = (reg &
> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
> + >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
> +
> + return gfxoff_status;
> +}
> +
> static int yellow_carp_set_default_dpm_tables(struct smu_context *smu) {
> struct smu_table_context *smu_table = &smu->smu_table; @@ -
> 1186,6 +1216,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs
> = {
> .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
> .set_driver_table_location = smu_v13_0_set_driver_table_location,
> .gfx_off_control = smu_v13_0_gfx_off_control,
> + .get_gfx_off_status = yellow_carp_get_gfxoff_status,
> .post_init = yellow_carp_post_smu_init,
> .mode2_reset = yellow_carp_mode2_reset,
> .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
> --
> 2.25.1
Re: [PATCH 1/4] drm/amd: Add detailed GFXOFF stats to debugfs
On Mon, Jul 25, 2022 at 11:03 PM Quan, Evan wrote:
>
> [AMD Official Use Only - General]
>
>
>
> > -Original Message-
> > From: André Almeida
> > Sent: Tuesday, July 26, 2022 12:15 AM
> > To: Quan, Evan ; Deucher, Alexander
> > ; Koenig, Christian
> > ; Pan, Xinhui ; David
> > Airlie ; Daniel Vetter ; Zhang, Hawking
> > ; Zhou1, Tao ; Kuehling,
> > Felix ; Xiao, Jack ; amd-
> > g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> > ker...@vger.kernel.org; StDenis, Tom ; Siqueira,
> > Rodrigo
> > Cc: kernel-...@igalia.com
> > Subject: Re: [PATCH 1/4] drm/amd: Add detailed GFXOFF stats to debugfs
> >
> > Às 10:04 de 25/07/22, André Almeida escreveu:
> > > Às 07:27 de 25/07/22, Quan, Evan escreveu:
> > >> [AMD Official Use Only - General]
> > >>
> > >> Using "uint64_t" instead of "uint32_t" for entry counter may be better.
> > >>
> > >
> > > Indeed, it's a good idea. I'll send a v2 with that change, thanks.
> > >
> >
> > However, SMU messaging reads a 32bit register to get the entrycount from
> > the pwfw, so would keep with with the risk of overflow anyway right?
> [Quan, Evan] Yes, that makes sense. Better to document that(the risk of
> overflow).
Still might be better to use a 64 bit number for the external
interface to be more future proof. Then we can either document the
behavior for specific chips or handle the wrap around in the driver.
Alex
> Anyway, the series seems fine to me.
> Series is acked-by: Evan Quan
> >
> > >> BR
> > >> Evan
> > >>> -Original Message-
> > >>> From: amd-gfx On Behalf Of
> > >>> André Almeida
> > >>> Sent: Saturday, July 23, 2022 4:34 AM
> > >>> To: Deucher, Alexander ; Koenig,
> > >>> Christian ; Pan, Xinhui
> > >>> ; David Airlie ; Daniel Vetter
> > >>> ; Zhang, Hawking ; Zhou1,
> > >>> Tao ; Kuehling, Felix
> > ;
> > >>> Xiao, Jack ; amd- g...@lists.freedesktop.org;
> > >>> dri-de...@lists.freedesktop.org; linux- ker...@vger.kernel.org;
> > >>> StDenis, Tom ; Siqueira, Rodrigo
> > >>>
> > >>> Cc: André Almeida ; kernel-...@igalia.com
> > >>> Subject: [PATCH 1/4] drm/amd: Add detailed GFXOFF stats to debugfs
> > >>>
> > >>> Add debugfs interface to log GFXOFF statistics:
> > >>>
> > >>> - Read amdgpu_gfxoff_count to get the total GFXOFF entry count at the
> > >>> time of query since system power-up
> > >>>
> > >>> - Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop.
> > >>> Read it to get average GFXOFF residency % multiplied by 100
> > >>> during the last logging interval.
> > >>>
> > >>> Both features are designed to be keep the values persistent between
> > >>> suspends.
> > >>>
> > >>> Signed-off-by: André Almeida
> > >>> ---
> > >>> drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 168
> > >>> ++
> > >>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 +
> > >>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 39
> > >>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 +
> > >>> drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 45 +
> > >>> drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 +
> > >>> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 +++-
> > >>> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 22 +++
> > >>> drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 3 +
> > >>> 9 files changed, 321 insertions(+), 1 deletion(-)
> > >>>
> > >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > >>> index e2eec985adb3..edf90a9ba980 100644
> > >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> > >>> @@ -1042,6 +1042,157 @@ static ssize_t
> > >>> amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
> > >>> return r;
> > >>> }
> > >>>
> > >>> +/**
> > >>> + * amdgpu_debugfs_gfxoff_residency_read - Read GFXOFF residency
> > >>> + *
> > >>> + * @f: open file handle
> > >>> + * @buf: User buffer to store read data in
> > >>> + * @size: Number of bytes to read
> > >>> + * @pos: Offset to seek to
> > >>> + *
> > >>> + * Read the last residency value logged. It doesn't auto update,
> > >>> +one needs
> > >>> to
> > >>> + * stop logging before getting the current value.
> > >>> + */
> > >>> +static ssize_t amdgpu_debugfs_gfxoff_residency_read(struct file *f,
> > >>> +char
> > >>> __user *buf,
> > >>> + size_t size, loff_t *pos)
> > >>> {
> > >>> + struct amdgpu_device *adev = file_inode(f)->i_private;
> > >>> + ssize_t result = 0;
> > >>> + int r;
> > >>> +
> > >>> + if (size & 0x3 || *pos & 0x3)
> > >>> + return -EINVAL;
> > >>> +
> > >>> + r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
> > >>> + if (r < 0) {
> > >>> + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> > >>> + return r;
> > >>> + }
> > >>> +
> > >>> + while (size) {
> > >>> + uint32_t value;
> > >>> +
> > >>> + r = amdgpu_get_gfx_off_residency(adev, &value);
> > >>> + i
Re: [PATCH] drm/amdgpu: Re-enable DCN for 64-bit powerpc
Linus Torvalds writes: > On Mon, Jul 25, 2022 at 5:39 AM Michael Ellerman wrote: >> >> Further digging shows that the build failures only occur with compilers >> that default to 64-bit long double. > > Where the heck do we have 'long double' things anywhere in the kernel? There's one or two uses, but not in any code that's relevant to this issue AFAICS. > I tried to grep for it, and failed miserably. I found some constants > that would qualify, but they were in the v4l colorspaces-details.rst > doc file. > > Strange. It doesn't seem to matter if you use long double or not. It's just that if the long double size is 64-bits the linker refuses to link a mixture of soft/hard-float objects. The 64-bit ABI says long double is 128-bits, so the compilers that are using 64-bit long double are either not built correctly, or we are not passing the correct flags to them. There's an -mlong-double-128 flag which we can pass at build time which seems to do the right thing, I will probably add that to the kernel CFLAGS, but I want that to get a bit more testing. cheers
[PATCH 20/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1372
dp_dsc_clock_en_read() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1478
dp_dsc_clock_en_write() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1563
dp_dsc_slice_width_read() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1667
dp_dsc_slice_width_write() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1752
dp_dsc_slice_height_read() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1856
dp_dsc_slice_height_write() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1937
dp_dsc_bits_per_pixel_read() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2038
dp_dsc_bits_per_pixel_write() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2117
dp_dsc_pic_width_read() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2178
dp_dsc_pic_height_read() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2254
dp_dsc_chunk_size_read() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2330
dp_dsc_slice_bpg_offset_read() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 72 +--
1 file changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index aa4edf182095..0e48824f55e3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1369,9 +1369,9 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char
__user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx =
&aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
- if (pipe_ctx && pipe_ctx->stream &&
- pipe_ctx->stream->link == aconnector->dc_link)
- break;
+ if (pipe_ctx && pipe_ctx->stream &&
+ pipe_ctx->stream->link == aconnector->dc_link)
+ break;
}
if (!pipe_ctx) {
@@ -1475,9 +1475,9 @@ static ssize_t dp_dsc_clock_en_write(struct file *f,
const char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx =
&aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
- if (pipe_ctx && pipe_ctx->stream &&
- pipe_ctx->stream->link == aconnector->dc_link)
- break;
+ if (pipe_ctx && pipe_ctx->stream &&
+ pipe_ctx->stream->link == aconnector->dc_link)
+ break;
}
if (!pipe_ctx || !pipe_ctx->stream)
@@ -1560,9 +1560,9 @@ static ssize_t dp_dsc_slice_width_read(struct file *f,
char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx =
&aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
- if (pipe_ctx && pipe_ctx->stream &&
- pipe_ctx->stream->link == aconnector->dc_link)
- break;
+ if (pipe_ctx && pipe_ctx->stream &&
+ pipe_ctx->stream->link == aconnector->dc_link)
+ break;
}
if (!pipe_ctx) {
@@ -1664,9 +1664,9 @@ static ssize_t dp_dsc_slice_width_write(struct file *f,
const char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx =
&aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
- if (pipe_ctx && pipe_ctx->stream &&
- pipe_ctx->stream->link == aconnector->dc_link)
- break;
+ if (pipe_ctx && pipe_ctx->stream &&
+ pipe_ctx->stream->link == aconnector->dc_link)
+ break;
}
if (!pipe_ctx || !pipe_ctx->stream)
@@ -1749,9 +1749,9 @@ static ssize_t dp_dsc_slice_height_read(struct file *f,
char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx =
&aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
- if (pipe_ctx && pipe_ctx->stream &&
- pipe_ctx->stream->link == aconnector->dc_link)
- break;
+ if (pipe_ctx && pipe_ctx->stream &&
+ pipe
[PATCH 14/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp_cm.c:450
dpp20_get_blndgam_current() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp_cm.c:543
dpp20_get_shaper_current() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../drm/amd/display/dc/dcn20/dcn20_dpp_cm.c | 68 +--
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
index 2feb051a2002..598caa508d43 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
@@ -444,24 +444,24 @@ static enum dc_lut_mode dpp20_get_blndgam_current(struct
dpp *dpp_base)
uint32_t state_mode;
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
- REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK,
- CM_BLNDGAM_CONFIG_STATUS, &state_mode);
+ REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS,
&state_mode);
- switch (state_mode) {
- case 0:
- mode = LUT_BYPASS;
- break;
- case 1:
- mode = LUT_RAM_A;
- break;
- case 2:
- mode = LUT_RAM_B;
- break;
- default:
- mode = LUT_BYPASS;
- break;
- }
- return mode;
+ switch (state_mode) {
+ case 0:
+ mode = LUT_BYPASS;
+ break;
+ case 1:
+ mode = LUT_RAM_A;
+ break;
+ case 2:
+ mode = LUT_RAM_B;
+ break;
+ default:
+ mode = LUT_BYPASS;
+ break;
+ }
+
+ return mode;
}
bool dpp20_program_blnd_lut(
@@ -537,24 +537,24 @@ static enum dc_lut_mode dpp20_get_shaper_current(struct
dpp *dpp_base)
uint32_t state_mode;
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
- REG_GET(CM_SHAPER_LUT_WRITE_EN_MASK,
- CM_SHAPER_CONFIG_STATUS, &state_mode);
+ REG_GET(CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_CONFIG_STATUS,
&state_mode);
- switch (state_mode) {
- case 0:
- mode = LUT_BYPASS;
- break;
- case 1:
- mode = LUT_RAM_A;
- break;
- case 2:
- mode = LUT_RAM_B;
- break;
- default:
- mode = LUT_BYPASS;
- break;
- }
- return mode;
+ switch (state_mode) {
+ case 0:
+ mode = LUT_BYPASS;
+ break;
+ case 1:
+ mode = LUT_RAM_A;
+ break;
+ case 2:
+ mode = LUT_RAM_B;
+ break;
+ default:
+ mode = LUT_BYPASS;
+ break;
+ }
+
+ return mode;
}
static void dpp20_configure_shaper_lut(
--
2.20.1.7.g153144c
[PATCH 11/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:186
optc3_set_dsc_config() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index 80136b5d7e48..d072997477dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -180,11 +180,8 @@ void optc3_set_dsc_config(struct timing_generator *optc,
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
- optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel,
- dsc_slice_width);
-
- REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
-
+ optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel,
dsc_slice_width);
+ REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
}
void optc3_set_vrr_m_const(struct timing_generator *optc,
--
2.20.1.7.g153144c
[PATCH 08/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dpp_cm.c:67
dpp30_get_gamcor_current() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../drm/amd/display/dc/dcn30/dcn30_dpp_cm.c | 25 ---
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c
index 87dbeca18984..e43f77c11c00 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c
@@ -61,23 +61,20 @@ static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp
*dpp_base)
uint32_t lut_mode;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
- REG_GET(CM_GAMCOR_CONTROL,
- CM_GAMCOR_MODE_CURRENT, &state_mode);
+ REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &state_mode);
- if (state_mode == 0)
- mode = LUT_BYPASS;
+ if (state_mode == 0)
+ mode = LUT_BYPASS;
- if (state_mode == 2) {//Programmable RAM LUT
- REG_GET(CM_GAMCOR_CONTROL,
- CM_GAMCOR_SELECT_CURRENT, &lut_mode);
-
- if (lut_mode == 0)
- mode = LUT_RAM_A;
- else
- mode = LUT_RAM_B;
- }
+ if (state_mode == 2) {//Programmable RAM LUT
+ REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &lut_mode);
+ if (lut_mode == 0)
+ mode = LUT_RAM_A;
+ else
+ mode = LUT_RAM_B;
+ }
- return mode;
+ return mode;
}
static void dpp3_program_gammcor_lut(
--
2.20.1.7.g153144c
[PATCH 17/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:713
dml32_CalculateSwathWidth() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 4b010b1b8aed..07f8f3b8626b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -710,10 +710,10 @@ void dml32_CalculateSwathWidth(
unsigned int k, j;
enum odm_combine_mode MainSurfaceODMMode;
-unsigned int surface_width_ub_l;
-unsigned int surface_height_ub_l;
-unsigned int surface_width_ub_c;
-unsigned int surface_height_ub_c;
+ unsigned int surface_width_ub_l;
+ unsigned int surface_height_ub_l;
+ unsigned int surface_width_ub_c;
+ unsigned int surface_height_ub_c;
#ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP);
--
2.20.1.7.g153144c
[PATCH 06/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved. smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c:655 dcn315_clk_mgr_construct() warn: inconsistent indenting. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index 36b0cd47c1c7..cc076621f5e6 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -652,7 +652,8 @@ void dcn315_clk_mgr_construct( dcn315_bw_params.wm_table = ddr5_wm_table; } /* Saved clocks configured at boot for debug purposes */ -dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); + dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, + &clk_mgr->base.base, &log_info); } -- 2.20.1.7.g153144c
[PATCH 07/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved. smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c:726 dcn31_clk_mgr_construct() warn: inconsistent indenting. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c index bca5f01da763..c09be3f15fe6 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c @@ -723,7 +723,8 @@ void dcn31_clk_mgr_construct( dcn31_bw_params.wm_table = ddr5_wm_table; } /* Saved clocks configured at boot for debug purposes */ -dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); + dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, +&clk_mgr->base.base, &log_info); } -- 2.20.1.7.g153144c
[PATCH 05/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved. smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c:683 dcn316_clk_mgr_construct() warn: inconsistent indenting. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c index e4bb9c6193b5..0cd3d2eb7ac7 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c @@ -680,7 +680,8 @@ void dcn316_clk_mgr_construct( dcn316_bw_params.wm_table = ddr4_wm_table; } /* Saved clocks configured at boot for debug purposes */ -dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); + dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, + &clk_mgr->base.base, &log_info); } -- 2.20.1.7.g153144c
[PATCH 19/20] drm/amd/display: Clean up some inconsistent indenting
Clean up some inconsistent indenting, replace sizeof(x) / sizeof((x)[0]))
with ARRAY_SIZE(x).
smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.c:185
optc3_fpu_set_vrr_m_const() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.c:355
dcn30_fpu_set_mcif_arb_params() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.c:384
dcn30_fpu_calculate_wm_and_dlg() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.c:390
dcn30_fpu_calculate_wm_and_dlg() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index c00f759fdded..060426916998 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -181,7 +181,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
void optc3_fpu_set_vrr_m_const(struct timing_generator *optc,
double vtotal_avg)
{
-struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
double vtotal_min, vtotal_max;
double ratio, modulo, phase;
uint32_t vblank_start;
@@ -350,24 +350,24 @@ void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params
*wb_arb_params,
int pipe_cnt,
int cur_pipe)
{
-int i;
+ int i;
dc_assert_fp_enabled();
-for (i = 0; i <
sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]);
i++) {
+ for (i = 0; i < ARRAY_SIZE(wb_arb_params->cli_watermark); i++) {
wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml,
pipes, pipe_cnt) * 1000;
wb_arb_params->pstate_watermark[i] =
get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
-}
+ }
-wb_arb_params->dram_speed_change_duration =
dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] *
pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
+ wb_arb_params->dram_speed_change_duration =
dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] *
pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
}
void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
{
-dc_assert_fp_enabled();
+ dc_assert_fp_enabled();
-if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
+ if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
context->bw_ctx.dml.soc.sr_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
@@ -380,12 +380,12 @@ void dcn30_fpu_calculate_wm_and_dlg(
int pipe_cnt,
int vlevel)
{
-int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
+ int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
int i, pipe_idx;
double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];
bool pstate_en =
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] !=
dm_dram_clock_change_unsupported;
-dc_assert_fp_enabled();
+ dc_assert_fp_enabled();
if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
--
2.20.1.7.g153144c
[PATCH 16/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.c:51
dml32_rq_dlg_get_rq_reg() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.c:68
dml32_rq_dlg_get_rq_reg() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.c:220
dml32_rq_dlg_get_dlg_reg() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.c:224
dml32_rq_dlg_get_dlg_reg() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.c:235
dml32_rq_dlg_get_dlg_reg() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.c:240
dml32_rq_dlg_get_dlg_reg() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../dc/dml/dcn32/display_rq_dlg_calc_32.c | 81 +--
1 file changed, 40 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
index 269bdfc4bc40..a1276f6b9581 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
@@ -48,9 +48,9 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
{
const display_pipe_source_params_st *src =
&e2e_pipe_param[pipe_idx].pipe.src;
bool dual_plane = is_dual_plane((enum source_format_class)
(src->source_format));
-double stored_swath_l_bytes;
-double stored_swath_c_bytes;
-bool is_phantom_pipe;
+ double stored_swath_l_bytes;
+ double stored_swath_c_bytes;
+ bool is_phantom_pipe;
uint32_t pixel_chunk_bytes = 0;
uint32_t min_pixel_chunk_bytes = 0;
uint32_t meta_chunk_bytes = 0;
@@ -65,9 +65,9 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
uint32_t p1_dpte_group_bytes = 0;
uint32_t p1_mpte_group_bytes = 0;
-unsigned int detile_buf_size_in_bytes;
-unsigned int detile_buf_plane1_addr;
-unsigned int pte_row_height_linear;
+ unsigned int detile_buf_size_in_bytes;
+ unsigned int detile_buf_plane1_addr;
+ unsigned int pte_row_height_linear;
memset(rq_regs, 0, sizeof(*rq_regs));
@@ -217,52 +217,51 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib
*mode_lib,
double refcyc_per_req_delivery_cur0 = 0.;
double refcyc_per_req_delivery_pre_c = 0.;
double refcyc_per_req_delivery_c = 0.;
-double refcyc_per_req_delivery_pre_l;
-double refcyc_per_req_delivery_l;
+ double refcyc_per_req_delivery_pre_l;
+ double refcyc_per_req_delivery_l;
double refcyc_per_line_delivery_pre_c = 0.;
double refcyc_per_line_delivery_c = 0.;
-double refcyc_per_line_delivery_pre_l;
-double refcyc_per_line_delivery_l;
-double min_ttu_vblank;
-double vratio_pre_l;
-double vratio_pre_c;
-unsigned int min_dst_y_next_start;
+ double refcyc_per_line_delivery_pre_l;
+ double refcyc_per_line_delivery_l;
+ double min_ttu_vblank;
+ double vratio_pre_l;
+ double vratio_pre_c;
+ unsigned int min_dst_y_next_start;
unsigned int htotal = dst->htotal;
unsigned int hblank_end = dst->hblank_end;
unsigned int vblank_end = dst->vblank_end;
bool interlaced = dst->interlaced;
double pclk_freq_in_mhz = dst->pixel_rate_mhz;
-unsigned int vready_after_vcount0;
+ unsigned int vready_after_vcount0;
double refclk_freq_in_mhz = clks->refclk_mhz;
double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
bool dual_plane = 0;
unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX];
-int unsigned dst_x_after_scaler;
-int unsigned dst_y_after_scaler;
-double dst_y_prefetch;
-double dst_y_per_vm_vblank;
-double dst_y_per_row_vblank;
-double dst_y_per_vm_flip;
-double dst_y_per_row_flip;
-double max_dst_y_per_vm_vblank = 32.0;
-double max_dst_y_per_row_vblank = 16.0;
-
-double dst_y_per_pte_row_nom_l;
-double dst_y_per_pte_row_nom_c;
-double dst_y_per_meta_row_nom_l;
-double dst_y_per_meta_row_nom_c;
-double refcyc_per_pte_group_nom_l;
-double refcyc_per_pte_group_nom_c;
-double refcyc_per_pte_group_vblank_l;
-double refcyc_per_pte_group_vblank_c;
-double refcyc_per_pte_group_flip_l;
-double refcyc_per_pte_group_flip_c;
-double refcyc_per_meta_chunk_nom_l;
-double refcyc_per_meta_chunk_nom_c;
-double refcyc_per_meta_chunk_vblank_l;
-double refcyc_per_meta_chunk_vblank_c;
-double refcyc_per_meta_chunk_flip_l;
-double refcyc_per_meta_chunk_flip_c;
+ unsigned int dst_x_after_scaler;
+ unsigned int dst_y_after_scaler;
+
[PATCH 03/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved. smatch warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c:716 dcn314_clk_mgr_construct() warn: inconsistent indenting. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index df6dd8465272..ee99974b3b62 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -713,7 +713,8 @@ void dcn314_clk_mgr_construct( dcn314_bw_params.wm_table = ddr5_wm_table; /* Saved clocks configured at boot for debug purposes */ -dcn314_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); + dcn314_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, + &clk_mgr->base.base, &log_info); } -- 2.20.1.7.g153144c
[PATCH 15/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:1728
dcn20_program_front_end_for_ctx() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 3b26962637d0..68690e2118cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1715,15 +1715,13 @@ void dcn20_program_front_end_for_ctx(
DC_LOGGER_INIT(dc->ctx->logger);
/* Carry over GSL groups in case the context is changing. */
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- struct pipe_ctx *old_pipe_ctx =
- &dc->current_state->res_ctx.pipe_ctx[i];
-
- if (pipe_ctx->stream == old_pipe_ctx->stream)
- pipe_ctx->stream_res.gsl_group =
- old_pipe_ctx->stream_res.gsl_group;
- }
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *old_pipe_ctx =
&dc->current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe_ctx->stream == old_pipe_ctx->stream)
+ pipe_ctx->stream_res.gsl_group =
old_pipe_ctx->stream_res.gsl_group;
+ }
if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
--
2.20.1.7.g153144c
Re: [PATCH] drm/amdgpu: Re-enable DCN for 64-bit powerpc
Hi! On Mon, Jul 25, 2022 at 03:40:40PM -0700, Guenter Roeck wrote: > On 7/25/22 13:42, Segher Boessenkool wrote: > >>What I'm wondering is if the compiler is getting confused between > >>standard and long doubles when they are both the same bit length... > > > >The compiler emits the same code (DFmode things, double precision float) > >in both cases, and it itself does not see any difference anymore fairly > >early in the pipeline. Compare to int and long on most 32-bit targets, > >both are SImode, the compiler will not see different types anymore: > >there *are* no types, except in the compiler frontend. > > > >It only happens for powerpc64le things, and not for powerpc64 builds. > > > >It is probably a GCC problem. I don't see what forces the GCC build > >here to use 64-bit long double either btw? Compilers build via buildall > >have all kinds of unnecessary things disabled, but not that, not > >directly at least. > > From what little documentation I can find, there appears to be > "--with-long-double-128" and "--with-long-double-format=ieee". > That looks like something that would need to be enabled, not disabled. Look in the GCC toplevel configure.ac for (some of!) the actual rules (and some more in config.gcc, and there are more at different levels). If your target is not *-linux* you likely end up with a 64-bit long double by default, and if it is, you do. But it depends on various things configure can determine about your C library. buildall uses --without-headers, but something makes GCC still use 128-bit long double on powerpc64-linux, but it uses 64-bit on powerpc64le-linux. Curious. I suppose things work better on Linux userland when you do not use the spartan build flags buildall uses :-) If you set it explicitly (--with-long-double-128) it just works. > FWIW, depending on compiler build options such as the above for kernel > builds seems to be a little odd to me, Yes. It should be (and was!) possible to build the kernel with pretty much any compiler. Usual were *-linux* compilers of course, but *-elf also works, and for powerpc in particular any kind of biarch or not "just works". > and I am not sure I'd want to > blame gcc if the kernel wants to be built with 128-bit floating point > as default. At the very least, that should be documented somewhere, > and if possible the kernel should refuse to build if the compiler build > options don't meet the requirements. It always was the rule that the kernel did not use floating point at all. If that is changed it can no longer be built on targets that use soft float for example (they need libgcc, which the kernel build is allergic to for some reason). It is non-trivial to handle floating point in the kernel itself as well of course (mostly arch stuff). The problem here was that some objects are built with soft float and some with hard float, incompatible ABIs that ld does not want to link together (without further coercing). Segher
Re: [PATCH] drm/amdgpu: Re-enable DCN for 64-bit powerpc
On 7/25/22 13:42, Segher Boessenkool wrote: On Mon, Jul 25, 2022 at 02:34:08PM -0500, Timothy Pearson wrote: Further digging shows that the build failures only occur with compilers that default to 64-bit long double. Where the heck do we have 'long double' things anywhere in the kernel? I tried to grep for it, and failed miserably. I found some constants that would qualify, but they were in the v4l colorspaces-details.rst doc file. Strange. We don't, at least not that I can see. The affected code uses standard doubles. What I'm wondering is if the compiler is getting confused between standard and long doubles when they are both the same bit length... The compiler emits the same code (DFmode things, double precision float) in both cases, and it itself does not see any difference anymore fairly early in the pipeline. Compare to int and long on most 32-bit targets, both are SImode, the compiler will not see different types anymore: there *are* no types, except in the compiler frontend. It only happens for powerpc64le things, and not for powerpc64 builds. It is probably a GCC problem. I don't see what forces the GCC build here to use 64-bit long double either btw? Compilers build via buildall have all kinds of unnecessary things disabled, but not that, not directly at least. From what little documentation I can find, there appears to be "--with-long-double-128" and "--with-long-double-format=ieee". That looks like something that would need to be enabled, not disabled. FWIW, depending on compiler build options such as the above for kernel builds seems to be a little odd to me, and I am not sure I'd want to blame gcc if the kernel wants to be built with 128-bit floating point as default. At the very least, that should be documented somewhere, and if possible the kernel should refuse to build if the compiler build options don't meet the requirements. Guenter
[PATCH 09/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dpp.c:724
dpp3_get_blndgam_current() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dpp.c:823
dpp3_get_shaper_current() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 77 +--
1 file changed, 38 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index 787b852eeaf2..77b00f86c216 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -716,28 +716,27 @@ static enum dc_lut_mode dpp3_get_blndgam_current(struct
dpp *dpp_base)
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
- REG_GET(CM_BLNDGAM_CONTROL,
- CM_BLNDGAM_MODE_CURRENT, &mode_current);
- REG_GET(CM_BLNDGAM_CONTROL,
- CM_BLNDGAM_SELECT_CURRENT, &in_use);
-
- switch (mode_current) {
- case 0:
- case 1:
- mode = LUT_BYPASS;
- break;
-
- case 2:
- if (in_use == 0)
- mode = LUT_RAM_A;
- else
- mode = LUT_RAM_B;
- break;
- default:
- mode = LUT_BYPASS;
- break;
- }
- return mode;
+ REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &mode_current);
+ REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &in_use);
+
+ switch (mode_current) {
+ case 0:
+ case 1:
+ mode = LUT_BYPASS;
+ break;
+
+ case 2:
+ if (in_use == 0)
+ mode = LUT_RAM_A;
+ else
+ mode = LUT_RAM_B;
+ break;
+ default:
+ mode = LUT_BYPASS;
+ break;
+ }
+
+ return mode;
}
static bool dpp3_program_blnd_lut(struct dpp *dpp_base,
@@ -817,24 +816,24 @@ static enum dc_lut_mode dpp3_get_shaper_current(struct
dpp *dpp_base)
uint32_t state_mode;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
- REG_GET(CM_SHAPER_CONTROL,
- CM_SHAPER_MODE_CURRENT, &state_mode);
+ REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &state_mode);
- switch (state_mode) {
- case 0:
- mode = LUT_BYPASS;
- break;
- case 1:
- mode = LUT_RAM_A;
- break;
- case 2:
- mode = LUT_RAM_B;
- break;
- default:
- mode = LUT_BYPASS;
- break;
- }
- return mode;
+ switch (state_mode) {
+ case 0:
+ mode = LUT_BYPASS;
+ break;
+ case 1:
+ mode = LUT_RAM_A;
+ break;
+ case 2:
+ mode = LUT_RAM_B;
+ break;
+ default:
+ mode = LUT_BYPASS;
+ break;
+ }
+
+ return mode;
}
static void dpp3_configure_shaper_lut(
--
2.20.1.7.g153144c
[PATCH 01/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:910
dcn32_init_hw() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index b6bada383958..201516a62b4b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -907,10 +907,10 @@ void dcn32_init_hw(struct dc *dc)
dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
// Get DMCUB capabilities
-if (dc->ctx->dmub_srv) {
- dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
- dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
-}
+ if (dc->ctx->dmub_srv) {
+ dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
+ dc->caps.dmub_caps.psr =
dc->ctx->dmub_srv->dmub->feature_caps.psr;
+ }
}
static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
--
2.20.1.7.g153144c
[PATCH 10/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_mpc.c:116
mpc3_get_ogam_current() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_mpc.c:445
mpc3_get_shaper_current() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 70 +--
1 file changed, 35 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index 1981a71b961b..ad1c1b703874 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -109,32 +109,32 @@ enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc,
int mpcc_id)
uint32_t state_ram_lut_in_use;
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
- REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id],
- MPCC_OGAM_MODE_CURRENT, &state_mode,
- MPCC_OGAM_SELECT_CURRENT, &state_ram_lut_in_use);
+ REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id], MPCC_OGAM_MODE_CURRENT,
&state_mode,
+ MPCC_OGAM_SELECT_CURRENT, &state_ram_lut_in_use);
- switch (state_mode) {
+ switch (state_mode) {
+ case 0:
+ mode = LUT_BYPASS;
+ break;
+ case 2:
+ switch (state_ram_lut_in_use) {
case 0:
- mode = LUT_BYPASS;
+ mode = LUT_RAM_A;
break;
- case 2:
- switch (state_ram_lut_in_use) {
- case 0:
- mode = LUT_RAM_A;
- break;
- case 1:
- mode = LUT_RAM_B;
- break;
- default:
- mode = LUT_BYPASS;
- break;
- }
+ case 1:
+ mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
- return mode;
+ break;
+ default:
+ mode = LUT_BYPASS;
+ break;
+ }
+
+ return mode;
}
void mpc3_power_on_ogam_lut(
@@ -439,24 +439,24 @@ static enum dc_lut_mode mpc3_get_shaper_current(struct
mpc *mpc, uint32_t rmu_id
uint32_t state_mode;
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
- REG_GET(SHAPER_CONTROL[rmu_idx],
- MPC_RMU_SHAPER_LUT_MODE_CURRENT, &state_mode);
+ REG_GET(SHAPER_CONTROL[rmu_idx], MPC_RMU_SHAPER_LUT_MODE_CURRENT,
&state_mode);
- switch (state_mode) {
- case 0:
- mode = LUT_BYPASS;
- break;
- case 1:
- mode = LUT_RAM_A;
- break;
- case 2:
- mode = LUT_RAM_B;
- break;
- default:
- mode = LUT_BYPASS;
- break;
- }
- return mode;
+ switch (state_mode) {
+ case 0:
+ mode = LUT_BYPASS;
+ break;
+ case 1:
+ mode = LUT_RAM_A;
+ break;
+ case 2:
+ mode = LUT_RAM_B;
+ break;
+ default:
+ mode = LUT_BYPASS;
+ break;
+ }
+
+ return mode;
}
static void mpc3_configure_shaper_lut(
--
2.20.1.7.g153144c
Re: [PATCH] drm/amdgpu: Re-enable DCN for 64-bit powerpc
Guenter Roeck writes: > On 7/25/22 13:42, Segher Boessenkool wrote: >> On Mon, Jul 25, 2022 at 02:34:08PM -0500, Timothy Pearson wrote: > Further digging shows that the build failures only occur with compilers > that default to 64-bit long double. Where the heck do we have 'long double' things anywhere in the kernel? I tried to grep for it, and failed miserably. I found some constants that would qualify, but they were in the v4l colorspaces-details.rst doc file. Strange. >>> >>> We don't, at least not that I can see. The affected code uses standard >>> doubles. >>> >>> What I'm wondering is if the compiler is getting confused between standard >>> and long doubles when they are both the same bit length... >> >> The compiler emits the same code (DFmode things, double precision float) >> in both cases, and it itself does not see any difference anymore fairly >> early in the pipeline. Compare to int and long on most 32-bit targets, >> both are SImode, the compiler will not see different types anymore: >> there *are* no types, except in the compiler frontend. >> >> It only happens for powerpc64le things, and not for powerpc64 builds. >> >> It is probably a GCC problem. I don't see what forces the GCC build >> here to use 64-bit long double either btw? Compilers build via buildall >> have all kinds of unnecessary things disabled, but not that, not >> directly at least. >> > > From what little documentation I can find, there appears to be > "--with-long-double-128" and "--with-long-double-format=ieee". > That looks like something that would need to be enabled, not disabled. > > FWIW, depending on compiler build options such as the above for kernel > builds seems to be a little odd to me, and I am not sure I'd want to > blame gcc if the kernel wants to be built with 128-bit floating point > as default. The kernel doesn't care what the size is, but ld refuses to link objects built with soft/hard float if the long double size is 64-bits. > At the very least, that should be documented somewhere, > and if possible the kernel should refuse to build if the compiler build > options don't meet the requirements. The ABI says long double is 128-bits. So it's documented there :) The kernel expects that passing `-m64 -mlittle-endian -mabi=elfv2` will produce code that conforms to the 64-bit Little Endian ELFv2 ABI :D But it seems those flags are not sufficient. There is an -mlong-double-128 flag, which appears to do the right thing regardless of how the compiler was built. I will probably add that to the kernel CFLAGS, but that's not a change I want to do just before the v5.19 release. cheers
[PATCH 02/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mpc.c:306
mpc32_get_shaper_current() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c | 36 +--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
index 94141f5e6994..357bd2461bc9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
@@ -300,24 +300,24 @@ static enum dc_lut_mode mpc32_get_shaper_current(struct
mpc *mpc, uint32_t mpcc_
uint32_t state_mode;
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
- REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id],
- MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
-
- switch (state_mode) {
- case 0:
- mode = LUT_BYPASS;
- break;
- case 1:
- mode = LUT_RAM_A;
- break;
- case 2:
- mode = LUT_RAM_B;
- break;
- default:
- mode = LUT_BYPASS;
- break;
- }
- return mode;
+ REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_MODE_CURRENT,
&state_mode);
+
+ switch (state_mode) {
+ case 0:
+ mode = LUT_BYPASS;
+ break;
+ case 1:
+ mode = LUT_RAM_A;
+ break;
+ case 2:
+ mode = LUT_RAM_B;
+ break;
+ default:
+ mode = LUT_BYPASS;
+ break;
+ }
+
+ return mode;
}
--
2.20.1.7.g153144c
[PATCH 18/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved. smatch warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:205 dcn303_fpu_update_bw_bounding_box() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:355 dcn303_fpu_init_soc_bounding_box() warn: inconsistent indenting. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong --- .../drm/amd/display/dc/dml/dcn303/dcn303_fpu.c| 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c index 8fb14baed208..3eb3a021ab7d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c @@ -202,7 +202,7 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p unsigned int num_dcfclk_sta_targets = 4; unsigned int num_uclk_states; -dc_assert_fp_enabled(); + dc_assert_fp_enabled(); if (dc->ctx->dc_bios->vram_info.num_chans) dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; @@ -349,14 +349,11 @@ void dcn303_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info) dc_assert_fp_enabled(); if (bb_info.dram_clock_change_latency_100ns > 0) - dcn3_03_soc.dram_clock_change_latency_us = - bb_info.dram_clock_change_latency_100ns * 10; + dcn3_03_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; - if (bb_info.dram_sr_enter_exit_latency_100ns > 0) - dcn3_03_soc.sr_enter_plus_exit_time_us = - bb_info.dram_sr_enter_exit_latency_100ns * 10; + if (bb_info.dram_sr_enter_exit_latency_100ns > 0) + dcn3_03_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; - if (bb_info.dram_sr_exit_latency_100ns > 0) - dcn3_03_soc.sr_exit_time_us = - bb_info.dram_sr_exit_latency_100ns * 10; + if (bb_info.dram_sr_exit_latency_100ns > 0) + dcn3_03_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; } -- 2.20.1.7.g153144c
[PATCH 12/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dwb.c:104 dwb2_enable()
warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
index 8d3884b306dd..f1490e97b6ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
@@ -101,8 +101,8 @@ static bool dwb2_enable(struct dwbc *dwbc, struct
dc_dwb_params *params)
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
/* Only chroma scaling (sub-sampling) is supported in DCN2 */
-if ((params->cnv_params.src_width != params->dest_width) ||
- (params->cnv_params.src_height != params->dest_height)) {
+ if ((params->cnv_params.src_width != params->dest_width) ||
+ (params->cnv_params.src_height != params->dest_height)) {
DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED",
__func__, dwbc20->base.inst);
return false;
--
2.20.1.7.g153144c
[PATCH 13/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_mpc.c:305
mpc20_get_ogam_current() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 36 +--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
index 15734db0cdea..3d307dd58e9a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
@@ -299,24 +299,24 @@ static enum dc_lut_mode mpc20_get_ogam_current(struct mpc
*mpc, int mpcc_id)
uint32_t state_mode;
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
- REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id],
- MPCC_OGAM_CONFIG_STATUS, &state_mode);
-
- switch (state_mode) {
- case 0:
- mode = LUT_BYPASS;
- break;
- case 1:
- mode = LUT_RAM_A;
- break;
- case 2:
- mode = LUT_RAM_B;
- break;
- default:
- mode = LUT_BYPASS;
- break;
- }
- return mode;
+ REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], MPCC_OGAM_CONFIG_STATUS,
&state_mode);
+
+ switch (state_mode) {
+ case 0:
+ mode = LUT_BYPASS;
+ break;
+ case 1:
+ mode = LUT_RAM_A;
+ break;
+ case 2:
+ mode = LUT_RAM_B;
+ break;
+ default:
+ mode = LUT_BYPASS;
+ break;
+ }
+
+ return mode;
}
static void mpc2_program_lutb(struct mpc *mpc, int mpcc_id,
--
2.20.1.7.g153144c
[PATCH 04/20] drm/amd/display: Clean up some inconsistent indenting
No functional modification involved.
smatch warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:107
dcn201_update_clocks() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c| 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
index 451e8d6cd8bd..f0577dcd1af6 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
@@ -101,8 +101,8 @@ static void dcn201_update_clocks(struct clk_mgr
*clk_mgr_base,
return;
if (clk_mgr_base->clks.dispclk_khz == 0 ||
- dc->debug.force_clock_mode & 0x1) {
- force_reset = true;
+ dc->debug.force_clock_mode & 0x1) {
+ force_reset = true;
dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
}
--
2.20.1.7.g153144c
Re: [PATCH 1/2] drm/amd/display: change variables type
On 7/25/22 20:38, Melissa Wen wrote:
On 07/25, Magali Lemes wrote:
On 7/25/22 16:42, André Almeida wrote:
Hi Magali,
Às 15:15 de 25/07/22, Magali Lemes escreveu:
As "dcn3_15_soc" and "dcn3_16_soc" are of type "struct
_vcs_dpi_soc_bounding_box_st", change their types accordingly.
I can see that indeed this type change sense for those variables, but
isn't a bit strange that the type was wrong in the first place? I wonder
if this variable is even used, given that it would very likely throw a
compiler error when using the wrong type and trying to access struct
members that aren't defined.
A compilation error would be thrown if either "dc/dcn315/dcn315_resource.h"
or "dc/dcn316/dcn316_resource.h" were included in the files where
"dcn3_15_soc" and "dcn3_16_soc" are initialized. Since they are not
included, the wrong variable type error is not shown.
To solve the sparse warning in the second patch of this series, those
variables need to be declared first, but they are already declared, we're
only missing the headers. If I only add the headers, then those variables
will be seen, and I get the expected incompatible variables types error. So,
fixing the types here is a preliminary work for the next patch.
Hi Magali,
Thanks for inspecting it. What you say makes sense, but André pointed
out something that makes sense to me too.
As fas as I checked, dcn3_15_soc and dcn16_soc is not used outside their
respective FPU files. Maybe the proper solution is removing those
declarations (and make the struct static). Can you take a look at it?
Best Regards,
Melissa
Hi, Melissa. Thank you for the suggestion!
My sole reason not to make those structs static was to keep some sort of
consistency with the rest of the dcn*_resource.h files, since that is
where all the other structs are first declared. I'm not sure, though, if
that's a good enough reason not to turn these variables into static. Let
me know what you think.
Magali
Magali
Signed-off-by: Magali Lemes
---
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h | 2 +-
drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
index 39929fa67a51..45276317c057 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
@@ -32,7 +32,7 @@
container_of(pool, struct dcn315_resource_pool, base)
extern struct _vcs_dpi_ip_params_st dcn3_15_ip;
-extern struct _vcs_dpi_ip_params_st dcn3_15_soc;
+extern struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc;
struct dcn315_resource_pool {
struct resource_pool base;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
index 0dc5a6c13ae7..d2234aac5449 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
@@ -32,7 +32,7 @@
container_of(pool, struct dcn316_resource_pool, base)
extern struct _vcs_dpi_ip_params_st dcn3_16_ip;
-extern struct _vcs_dpi_ip_params_st dcn3_16_soc;
+extern struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc;
struct dcn316_resource_pool {
struct resource_pool base;
[PATCH] drm/amdkfd: fix kgd_mem memory leak when importing dmabuf
The kgd_mem memory allocated in amdgpu_amdkfd_gpuvm_import_dmabuf()
is not freed properly.
Explicitly free it in amdgpu_amdkfd_gpuvm_free_memory_of_gpu()
under condition "mem->bo->kfd_bo != mem".
Suggested-by: Felix Kuehling
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 6bba6961eee7..086bed40cf34 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1803,6 +1803,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
uint64_t *size)
{
struct amdkfd_process_info *process_info = mem->process_info;
+ struct kgd_mem *tmp_mem = mem->bo->kfd_bo;
unsigned long bo_size = mem->bo->tbo.base.size;
struct kfd_mem_attachment *entry, *tmp;
struct bo_vm_reservation_context ctx;
@@ -1895,6 +1896,13 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
*/
drm_gem_object_put(&mem->bo->tbo.base);
+ /*
+* For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
+* explicitly free it here.
+*/
+ if (mem != tmp_mem)
+ kfree(mem);
+
return ret;
}
--
2.25.1
Re: [PATCH v2 4/6] drm/i915: Implement intersect/compatible functions
On 25/07/2022 12:42, Arunpravin Paneer Selvam wrote:
Implemented a new intersect and compatible callback function
fetching start offset from drm buddy allocator.
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 43 +++
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index a5109548abc0..b5801c05bd41 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -178,6 +178,47 @@ static void i915_ttm_buddy_man_free(struct
ttm_resource_manager *man,
kfree(bman_res);
}
+static bool i915_ttm_buddy_man_intersect(struct ttm_resource_manager *man,
+struct ttm_resource *res,
+const struct ttm_place *place,
+size_t size)
+{
+ struct i915_ttm_buddy_resource *bman_res = to_ttm_buddy_resource(res);
+ u32 start, num_pages = PFN_UP(size);
+ struct drm_buddy_block *block;
+
+ /* Check each drm buddy block individually */
+ list_for_each_entry(block, &bman_res->blocks, link) {
+ start = drm_buddy_block_offset(block) >> PAGE_SHIFT;
+ /* Don't evict BOs outside of the requested placement range */
+ if (place->fpfn >= (start + num_pages) ||
+ (place->lpfn && place->lpfn <= start))
+ return false;
+ }
+
+ return true;
+}
This looks like a nice idea. We should be able to clean up
i915_ttm_eviction_valuable() a fair bit I think, if we now call
ttm_bo_eviction_valuable() at the end (like in amdgpu), and move the
bits that are specific to buddy_man here?
So something like:
if (!place->fpfn && !place->lpfn)
return true;
if (!place->fpfn &&
place->lpfn == i915_buddy_man_visible_size(man))
return bman_res->used_visible_size > 0;
/* Check each drm buddy block individually */
+
+static bool i915_ttm_buddy_man_compatible(struct ttm_resource_manager *man,
+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
Is it not possible to derive the size from res->num_pages?
+{
+ struct i915_ttm_buddy_resource *bman_res = to_ttm_buddy_resource(res);
+ u32 start, num_pages = PFN_UP(size);
+ struct drm_buddy_block *block;
+
+ /* Check each drm buddy block individually */
+ list_for_each_entry(block, &bman_res->blocks, link) {
+ start = drm_buddy_block_offset(block) >> PAGE_SHIFT;
+ if (start < place->fpfn ||
+ (place->lpfn && (start + num_pages) > place->lpfn))
+ return false;
+ }
if (!place->fpfn && !place->lpfn)
return true;
if (!place->fpfn &&
place->lpfn == i915_buddy_man_visible_size(man))
return bman_res->used_visible_size == res->num_pages;
/* Check each drm buddy block individually */
...
+
+ return true;
+}
+
static void i915_ttm_buddy_man_debug(struct ttm_resource_manager *man,
struct drm_printer *printer)
{
@@ -205,6 +246,8 @@ static void i915_ttm_buddy_man_debug(struct
ttm_resource_manager *man,
static const struct ttm_resource_manager_func i915_ttm_buddy_manager_func = {
.alloc = i915_ttm_buddy_man_alloc,
.free = i915_ttm_buddy_man_free,
+ .intersect = i915_ttm_buddy_man_intersect,
s/intersect/intersects/ ?
+ .compatible = i915_ttm_buddy_man_compatible,
.debug = i915_ttm_buddy_man_debug,
};
RE: [PATCH 1/5] drm/amdgpu: add mode2 reset for sienna_cichlid
[AMD Official Use Only - General]
Will do.
Thanks,
Victor
-Original Message-
From: Grodzovsky, Andrey
Sent: Tuesday, July 26, 2022 5:06 AM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Deng, Emily
; Koenig, Christian
Subject: Re: [PATCH 1/5] drm/amdgpu: add mode2 reset for sienna_cichlid
On 2022-07-22 03:33, Victor Zhao wrote:
> To meet the requirement for multi container usecase which needs a
> quicker reset and not causing VRAM lost, adding the Mode2 reset
> handler for sienna_cichlid. Adding a AMDGPU_SKIP_MODE2_RESET flag so
> driver can fallback to default reset method when mode2 reset failed
> and retry.
>
> - add mode2 reset handler for sienna_cichlid
Seems to me ASIC specific changes should be in a seperate patch
> - introduce AMDGPU_SKIP_MODE2_RESET flag
> - let mode2 reset fallback to default reset method if failed
>
> Signed-off-by: Victor Zhao
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 7 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 13 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 1 +
> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 1 +
> drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 1 +
> drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 1 +
> drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 297 ++
> drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h | 32 ++
> .../pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h | 4 +-
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 +-
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 54
> 15 files changed, 414 insertions(+), 5 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index c7d0cd15b5ef..7030ac2d7d2c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -75,7 +75,7 @@ amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
> vega10_reg_init.o \
> vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o
> mxgpu_nv.o \
> nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o
> soc21.o \
> - nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o
> + sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o
> +lsdma_v6_0.o
>
> # add DF block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index 5e53a5293935..091415a4abf0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -135,6 +135,7 @@ static void amdgpu_amdkfd_reset_work(struct work_struct
> *work)
> reset_context.method = AMD_RESET_METHOD_NONE;
> reset_context.reset_req_dev = adev;
> clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
> + clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
>
> amdgpu_device_gpu_recover(adev, NULL, &reset_context);
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index b79ee4ffb879..5498fda8617f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -5146,6 +5146,7 @@ int amdgpu_device_gpu_recover(struct
> amdgpu_device *adev,
>
> reset_context->job = job;
> reset_context->hive = hive;
> +
> /*
>* Build list of devices to reset.
>* In case we are in XGMI hive mode, resort the device list @@
> -5265,8 +5266,11 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
> amdgpu_ras_resume(adev);
> } else {
> r = amdgpu_do_asic_reset(device_list_handle, reset_context);
> - if (r && r == -EAGAIN)
> + if (r && r == -EAGAIN) {
> + set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags);
> + adev->asic_reset_res = 0;
See my question bellow related to this set
> goto retry;
> + }
> }
>
> skip_hw_reset:
> @@ -5694,6 +5698,7 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev
> *pdev)
> reset_context.reset_req_dev = adev;
> set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
> set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
> + set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
>
> adev->no_hw_access = true;
> r = amdgpu_device_pre_asic_reset(adev, &reset_context); diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> b/drivers/gpu/drm/amd
RE: [PATCH 4/5] drm/amdgpu: revert context to stop engine before mode2 reset
[AMD Official Use Only - General]
Hi Andrey,
For slow tests I mean the slow hang tests by quark tool.
An example here:
hang_vm_gfx_dispatch_slow.lua - This script runs on a graphics engine using
compute engine and has a hacked CS program which is massive and duplicates
standard CS program move code hundreds of thousands of times. The effect is a
very slowly executing CS program.
It's not a bad job but just need a very long time to finish. I suppose we don’t
have a way to stop shader here. And the running apps will be affected when
reset is done.
Thanks,
Victor
-Original Message-
From: Grodzovsky, Andrey
Sent: Tuesday, July 26, 2022 5:20 AM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Deng, Emily
; Koenig, Christian
Subject: Re: [PATCH 4/5] drm/amdgpu: revert context to stop engine before mode2
reset
On 2022-07-22 03:34, Victor Zhao wrote:
> For some hang caused by slow tests, engine cannot be stopped which may
> cause resume failure after reset. In this case, force halt engine by
> reverting context addresses
Can you maybe explain a bit more what exactly you mean by slow test and why
engine cannot be stopped in this case ?
Andrey
>
> Signed-off-by: Victor Zhao
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h | 1 +
> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c| 36 +
> drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 2 ++
> 4 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 5498fda8617f..833dc5e224d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -5037,6 +5037,7 @@ static void amdgpu_device_recheck_guilty_jobs(
>
> /* set guilty */
> drm_sched_increase_karma(s_job);
> + amdgpu_reset_prepare_hwcontext(adev, reset_context);
> retry:
> /* do hw reset */
> if (amdgpu_sriov_vf(adev)) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
> index f8036f2b100e..c7b44aeb671b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
> @@ -37,6 +37,7 @@ struct amdgpu_gfxhub_funcs {
> void (*utcl2_harvest)(struct amdgpu_device *adev);
> void (*mode2_save_regs)(struct amdgpu_device *adev);
> void (*mode2_restore_regs)(struct amdgpu_device *adev);
> + void (*halt)(struct amdgpu_device *adev);
> };
>
> struct amdgpu_gfxhub {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> index 51cf8acd2d79..8cf53e039c11 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> @@ -646,6 +646,41 @@ static void gfxhub_v2_1_restore_regs(struct
> amdgpu_device *adev)
> WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL,
> adev->gmc.MC_VM_MX_L1_TLB_CNTL);
> }
>
> +static void gfxhub_v2_1_halt(struct amdgpu_device *adev) {
> + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
> + int i;
> + uint32_t tmp;
> + int time = 1000;
> +
> + gfxhub_v2_1_set_fault_enable_default(adev, false);
> +
> + for (i = 0; i <= 14; i++) {
> + WREG32_SOC15_OFFSET(GC, 0,
> mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
> + i * hub->ctx_addr_distance, ~0);
> + WREG32_SOC15_OFFSET(GC, 0,
> mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
> + i * hub->ctx_addr_distance, ~0);
> + WREG32_SOC15_OFFSET(GC, 0,
> mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
> + i * hub->ctx_addr_distance,
> + 0);
> + WREG32_SOC15_OFFSET(GC, 0,
> mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> + i * hub->ctx_addr_distance,
> + 0);
> + }
> + tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
> + while ((tmp & (GRBM_STATUS2__EA_BUSY_MASK |
> + GRBM_STATUS2__EA_LINK_BUSY_MASK)) != 0 &&
> +time) {
> + udelay(100);
> + time--;
> + tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
> + }
> +
> + if (!time) {
> + DRM_WARN("failed to wait for GRBM(EA) idle\n");
> + }
> +}
> +
> const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
> .get_fb_location = gfxhub_v2_1_get_fb_location,
> .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset, @@ -658,4 +693,5
> @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
> .utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
> .mode2_save_regs = gfxhub_v2_1_save_regs,
> .mode2_restore_regs = gfxhub_v2_1_restore_regs,
> + .halt = gfxh
RE: [PATCH 5/5] drm/amdgpu: reduce reset time
[AMD Official Use Only - General]
Hi Andrey,
Reply inline.
Thanks,
Victor
-Original Message-
From: Grodzovsky, Andrey
Sent: Tuesday, July 26, 2022 5:18 AM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Deng, Emily
; Koenig, Christian
Subject: Re: [PATCH 5/5] drm/amdgpu: reduce reset time
On 2022-07-22 03:34, Victor Zhao wrote:
> In multi container use case, reset time is important, so skip ring
> tests and cp halt wait during ip suspending for reset as they are
> going to fail and cost more time on reset
Why are they failing in this case ? Skipping ring tests is not the best idea as
you loose important indicator of system's sanity. Is there any way to make them
work ?
[Victor]: I've seen gfx ring test fail every time after a gfx engine hang. I
thought it should be expected as gfx is in a bad state. Do you know the reason
we have ring tests before reset? As we are going to reset the asic anyway.
Another approach could be to make the skip mode2 only or reduce the wait time
here.
>
> Signed-off-by: Victor Zhao
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +++--
> 2 files changed, 17 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 222d3d7ea076..f872495ccc3a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -477,7 +477,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
> kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
> RESET_QUEUES, 0, 0);
>
> - if (adev->gfx.kiq.ring.sched.ready)
> + if (adev->gfx.kiq.ring.sched.ready && !amdgpu_in_reset(adev))
> r = amdgpu_ring_test_helper(kiq_ring);
> spin_unlock(&adev->gfx.kiq.ring_lock);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index fafbad3cf08d..9ae29023e38f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -5971,16 +5971,19 @@ static int gfx_v10_0_cp_gfx_enable(struct
> amdgpu_device *adev, bool enable)
> WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
> }
>
> - for (i = 0; i < adev->usec_timeout; i++) {
> - if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
> - break;
> - udelay(1);
> - }
> -
> - if (i >= adev->usec_timeout)
> - DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
> + if (!amdgpu_in_reset(adev)) {
> + for (i = 0; i < adev->usec_timeout; i++) {
> + if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
> + break;
> + udelay(1);
> + }
>
> + if (i >= adev->usec_timeout)
> + DRM_ERROR("failed to %s cp gfx\n",
> + enable ? "unhalt" : "halt");
> + }
> return 0;
> +
> }
This change has impact beyond container case no ? We had no issue with this
code during regular reset cases so why we would give up on this code which
confirms CP is idle ? What is the side effect of skipping this during all GPU
resets ?
Andrey
[Victor]: I see "failed to halt cp gfx" with regular reset cases as well when
doing a gfx hang test using quark. I haven't seen a side effect with Mode1
reset yet but maybe shorten the wait time could be better?
>
> static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device
> *adev) @@ -7569,8 +7572,10 @@ static int gfx_v10_0_kiq_disable_kgq(struct
> amdgpu_device *adev)
> for (i = 0; i < adev->gfx.num_gfx_rings; i++)
> kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
> PREEMPT_QUEUES, 0, 0);
> -
> - return amdgpu_ring_test_helper(kiq_ring);
> + if (!amdgpu_in_reset(adev))
> + return amdgpu_ring_test_helper(kiq_ring);
> + else
> + return 0;
> }
> #endif
>
> @@ -7610,6 +7615,7 @@ static int gfx_v10_0_hw_fini(void *handle)
>
> return 0;
> }
> +
> gfx_v10_0_cp_enable(adev, false);
> gfx_v10_0_enable_gui_idle_interrupt(adev, false);
>
Crash on resume from S3
I have a Ryzen 7 3700U in an HP laptop. lspci describes the GPU in this way: 04:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Picasso/Raven 2 [Radeon Vega Series / Radeon Vega Mobile Series] (rev c1) This laptop has never successfully resumed from suspend (I have tried every 5.x kernel). Currently on 5.18.0, the system appears to be okay after resume apart from the gpu which is usually giving a blank screen, occasionally a scrambled output. After rebooting, I see this in syslog: Jul 25 11:02:18 frog kernel: [240782.968674] amdgpu :04:00.0: amdgpu: GPU reset begin! Jul 25 11:02:19 frog kernel: [240783.974891] amdgpu :04:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_2.1.0 test failed (-110) Jul 25 11:02:19 frog kernel: [240783.988650] [drm] free PSP TMR buffer Jul 25 11:02:19 frog kernel: [240784.019057] CPU: 4 PID: 305612 Comm: kworker/u32:17 Not tainted 5.18.0 #1 Jul 25 11:02:19 frog kernel: [240784.019063] Hardware name: HP HP ENVY x360 Convertible 15-ds0xxx/85DD, BIOS F.20 05/28/2020 Jul 25 11:02:19 frog kernel: [240784.019067] Workqueue: amdgpu-reset-dev drm_sched_job_timedout [gpu_sched] Jul 25 11:02:19 frog kernel: [240784.019079] Call Trace: Jul 25 11:02:19 frog kernel: [240784.019082] Jul 25 11:02:19 frog kernel: [240784.019085] dump_stack_lvl+0x49/0x5f Jul 25 11:02:19 frog kernel: [240784.019095] dump_stack+0x10/0x12 Jul 25 11:02:19 frog kernel: [240784.019099] amdgpu_do_asic_reset+0x2f/0x4e0 [amdgpu] Jul 25 11:02:19 frog kernel: [240784.019278] amdgpu_device_gpu_recover_imp+0x41e/0xb50 [amdgpu] Jul 25 11:02:19 frog kernel: [240784.019452] amdgpu_job_timedout+0x155/0x1b0 [amdgpu] Jul 25 11:02:19 frog kernel: [240784.019674] drm_sched_job_timedout+0x74/0xf0 [gpu_sched] Jul 25 11:02:19 frog kernel: [240784.019681] ? amdgpu_cgs_destroy_device+0x10/0x10 [amdgpu] Jul 25 11:02:19 frog kernel: [240784.019896] ? drm_sched_job_timedout+0x74/0xf0 [gpu_sched] Jul 25 11:02:19 frog kernel: [240784.019903] process_one_work+0x227/0x440 Jul 25 11:02:19 frog kernel: [240784.019908] worker_thread+0x31/0x3d0 Jul 25 11:02:19 frog kernel: [240784.019912] ? process_one_work+0x440/0x440 Jul 25 11:02:19 frog kernel: [240784.019914] kthread+0xfe/0x130 Jul 25 11:02:19 frog kernel: [240784.019918] ? kthread_complete_and_exit+0x20/0x20 Jul 25 11:02:19 frog kernel: [240784.019923] ret_from_fork+0x22/0x30 Jul 25 11:02:19 frog kernel: [240784.019930] Jul 25 11:02:19 frog kernel: [240784.019934] amdgpu :04:00.0: amdgpu: MODE2 reset Jul 25 11:02:19 frog kernel: [240784.020178] amdgpu :04:00.0: amdgpu: GPU reset succeeded, trying to resume Jul 25 11:02:19 frog kernel: [240784.020552] [drm] PCIE GART of 1024M enabled. Jul 25 11:02:19 frog kernel: [240784.020555] [drm] PTB located at 0x00F40090 Jul 25 11:02:19 frog kernel: [240784.020577] [drm] VRAM is lost due to GPU reset! Jul 25 11:02:19 frog kernel: [240784.020579] [drm] PSP is resuming... Jul 25 11:02:19 frog kernel: [240784.040465] [drm] reserve 0x40 from 0xf47fc0 for PSP TMR I'm running the latest BIOS from HP. Is there anything I can do to work around this? Or anything I can do to help debug it? Regards, Tom Cook
Re: [PATCH 1/3] Revert "drm/amdgpu: move internal vram_mgr function into the C file"
On 26/07/2022 08:46, Thomas Zimmermann wrote: Hi Am 25.07.22 um 19:14 schrieb Christian König: Am 25.07.22 um 17:27 schrieb Tvrtko Ursulin: On 24/07/2022 19:28, Thomas Zimmermann wrote: Hi Am 22.07.22 um 17:47 schrieb Christian König: Hi Tvrtko, scratching my head what exactly is going on here. I've build tested drm-tip a couple of test in the last week and it always worked flawlessly. It looks like that some conflict resolution is sometimes not applied correctly, but I have no idea why. It worked last week, but must have been reintroduced meanhwile. Please fetch the latest drm-tip and rebuild. The attached config produces the error on my system. What is the status with this? I hit a conflict on an implicated file just now trying to rebuild drm-tip: Unmerged paths: (use "git add/rm ..." as appropriate to mark resolution) deleted by us: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h I had an other i915 conflict to solve and as grep amdgpu_vram_mgr.h drivers/gpu/drm/amd produced nothing I just did a git rm on it and pushed the resolution. Let me know if I broke something, re-broke something, or whatever.. Build of amdgpu certainly still looks broken on my end, both before and after me rebuilding drm-tip so maybe I just preserved the breakage. It looks like that somehow re-broke, but I'm not sure how. I've fetched drm-tip on Friday at around 1pm CET and build it and that worked perfectly fine. Essentially the status of drm-misc-next for the following files should be carried on in drm-tip: drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h I've reset these files to their state as in drm-misc-next and updated drm-tip. It appears to be working again from what I could test locally. Please try at your earliest convenience. Builds for me now - thank you! Regards, Tvrtko
Re: [PATCH 1/3] Revert "drm/amdgpu: move internal vram_mgr function into the C file"
Hi
Am 25.07.22 um 19:14 schrieb Christian König:
Am 25.07.22 um 17:27 schrieb Tvrtko Ursulin:
On 24/07/2022 19:28, Thomas Zimmermann wrote:
Hi
Am 22.07.22 um 17:47 schrieb Christian König:
Hi Tvrtko,
scratching my head what exactly is going on here.
I've build tested drm-tip a couple of test in the last week and it
always worked flawlessly.
It looks like that some conflict resolution is sometimes not applied
correctly, but I have no idea why.
It worked last week, but must have been reintroduced meanhwile.
Please fetch the latest drm-tip and rebuild. The attached config
produces the error on my system.
What is the status with this? I hit a conflict on an implicated file
just now trying to rebuild drm-tip:
Unmerged paths:
(use "git add/rm ..." as appropriate to mark resolution)
deleted by us: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
I had an other i915 conflict to solve and as grep amdgpu_vram_mgr.h
drivers/gpu/drm/amd produced nothing I just did a git rm on it and
pushed the resolution.
Let me know if I broke something, re-broke something, or whatever..
Build of amdgpu certainly still looks broken on my end, both before
and after me rebuilding drm-tip so maybe I just preserved the breakage.
It looks like that somehow re-broke, but I'm not sure how.
I've fetched drm-tip on Friday at around 1pm CET and build it and that
worked perfectly fine.
Essentially the status of drm-misc-next for the following files should
be carried on in drm-tip:
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
I've reset these files to their state as in drm-misc-next and updated
drm-tip. It appears to be working again from what I could test locally.
Please try at your earliest convenience.
Best regards
Thomas
Regards,
Christian.
Regards,
Tvrtko
Best regards
Thomas
Regards,
Christian.
Am 22.07.22 um 16:46 schrieb Tvrtko Ursulin:
On 14/07/2022 09:45, Thomas Zimmermann wrote:
Hi
Am 08.07.22 um 11:30 schrieb Arunpravin Paneer Selvam:
This reverts commit 708d19d9f362766147cab79eccae60912c6d3068.
This commit is only present in drm-misc-next. Should the revert be
cherry-picked into drm-misc-next-fixes?
Seemed like an appropriate thread to raise this, in case my pings
about it on #dri-devel and #radeon go un-noticed since it is Friday
after all.
So for me dri-tip today fails to build the amdgpu driver.
I had to revert 925b6e59138cefa47275c67891c65d48d3266d57 to make it
build. This conflicts a bit but seems trivial. Without this revert
code seems confused with different versions of struct
amdgpu_vram_mgr and build fails violently (increase your scroll
back buffers to see it all).
Regards,
Tvrtko
Best regards
Thomas
This is part of a revert of the following commits:
commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function
into the C file")
commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in
amdgpu_vram_mgr_new")
commit c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu")
[WHY]
Few users reported garbaged graphics as soon as x starts,
reverting until this can be resolved.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 29
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 27
++
2 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 7a5e8a7b4a1b..51d9d3a4456c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -50,35 +50,6 @@ to_amdgpu_device(struct amdgpu_vram_mgr *mgr)
return container_of(mgr, struct amdgpu_device, mman.vram_mgr);
}
-static inline struct drm_buddy_block *
-amdgpu_vram_mgr_first_block(struct list_head *list)
-{
- return list_first_entry_or_null(list, struct
drm_buddy_block, link);
-}
-
-static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct
list_head *head)
-{
- struct drm_buddy_block *block;
- u64 start, size;
-
- block = amdgpu_vram_mgr_first_block(head);
- if (!block)
- return false;
-
- while (head != block->link.next) {
- start = amdgpu_vram_mgr_block_start(block);
- size = amdgpu_vram_mgr_block_size(block);
-
- block = list_entry(block->link.next, struct
drm_buddy_block, link);
- if (start + size != amdgpu_vram_mgr_block_start(block))
- return false;
- }
-
- return true;
-}
-
-
-
/**
* DOC: mem_info_vram_total
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
index 4b267bf1c5db..9a2db87186c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
@@ -53,6 +53,33 @@ static inline u64
amdgpu_vram_mgr_block_size
