[PATCH 19/19] drm/amd/display: Promote DAL to 3.2.229
From: Aric Cyr This DC version brings along: - Enable FPO optimization - Support for 6.75 GBps link rate - Fixes to underflow, black screen and more Acked-by: Qingqing Zhuo Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1b77d50cfd89..e363a3c88250 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.228" +#define DC_VER "3.2.229" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.34.1
[PATCH 17/19] drm/amd/display: [FW Promotion] Release 0.0.160.0
From: Anthony Koo
- New parameter to define extra vblank stretch required when
doing FPO + Vactive
- Pass in pipe index for FPO
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 3175a4fe4d52..15d26222597a 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -95,6 +95,13 @@
/* Maximum number of SubVP streams */
#define DMUB_MAX_SUBVP_STREAMS 2
+/* Define max FPO streams as 4 for now. Current implementation today
+ * only supports 1, but could be more in the future. Reduce array
+ * size to ensure the command size remains less than 64 bytes if
+ * adding new fields.
+ */
+#define DMUB_MAX_FPO_STREAMS 4
+
/* Maximum number of streams on any ASIC. */
#define DMUB_MAX_STREAMS 6
@@ -3084,14 +3091,15 @@ struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
uint8_t max_ramp_step;
uint8_t pipes;
uint8_t min_refresh_in_hz;
- uint8_t padding[1];
+ uint8_t pipe_count;
+ uint8_t pipe_index[4];
};
struct dmub_cmd_fw_assisted_mclk_switch_config {
uint8_t fams_enabled;
uint8_t visual_confirm_enabled;
- uint8_t padding[2];
- struct dmub_cmd_fw_assisted_mclk_switch_pipe_data
pipe_data[DMUB_MAX_STREAMS];
+ uint16_t vactive_stretch_margin_us; // Extra vblank stretch required
when doing FPO + Vactive
+ struct dmub_cmd_fw_assisted_mclk_switch_pipe_data
pipe_data[DMUB_MAX_FPO_STREAMS];
};
struct dmub_rb_cmd_fw_assisted_mclk_switch {
--
2.34.1
[PATCH 18/19] drm/amd/display: Uncomment assignments after HW headers are promoted
From: Alvin Lee
[Description]
Assign the correct info now that FW headers are promoted
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 8f26f7245104..dd6f643254fe 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -307,19 +307,17 @@ static void dc_dmub_srv_populate_fams_pipe_info(struct dc
*dc, struct dc_state *
struct dmub_cmd_fw_assisted_mclk_switch_pipe_data
*fams_pipe_data)
{
int j;
+ int pipe_idx = 0;
- // TODO: Uncomment once FW headers are updated in driver
- //fams_pipe_data->pipe_index[pipe_idx++] =
head_pipe->plane_res.hubp->inst;
+ fams_pipe_data->pipe_index[pipe_idx++] =
head_pipe->plane_res.hubp->inst;
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
if (split_pipe->stream == head_pipe->stream &&
(split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
- // TODO: Uncomment once FW headers are updated in driver
- //fams_pipe_data->pipe_index[pipe_idx++] =
split_pipe->plane_res.hubp->inst;
+ fams_pipe_data->pipe_index[pipe_idx++] =
split_pipe->plane_res.hubp->inst;
}
}
- // TODO: Uncomment once FW headers are updated in driver
- //fams_pipe_data->pipe_count = pipe_idx;
+ fams_pipe_data->pipe_count = pipe_idx;
}
bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate,
struct dc_state *context)
--
2.34.1
[PATCH 16/19] drm/amd/display: skip ClearPayloadIdTable if device mst_en is 0
From: Peichen Huang
[Why]
Some dock and mst monitor don't like to receive ClearPayloadIdTable
when mst_en is set to 0. And it doesn't make sense to do so in source
side, either.
[How]
Not send ClearyPayloadIdTable if mst_en is 0
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
Signed-off-by: Peichen Huang
---
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index aa08925d54c9..f6c5ee2d639b 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -2160,6 +2160,7 @@ static enum dc_status enable_link_dp_mst(
struct pipe_ctx *pipe_ctx)
{
struct dc_link *link = pipe_ctx->stream->link;
+ unsigned char mstm_cntl;
/* sink signal type after MST branch is MST. Multiple MST sinks
* share one link. Link DP PHY is enable or training only once.
@@ -2168,7 +2169,9 @@ static enum dc_status enable_link_dp_mst(
return DC_OK;
/* clear payload table */
- dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
+ core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1);
+ if (mstm_cntl & DP_MST_EN)
+ dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx,
link);
/* to make sure the pending down rep can be processed
* before enabling the link
--
2.34.1
[PATCH 15/19] drm/amd/display: Enable FPO optimization
From: Alvin Lee
[Description]
Enable optimization for preferring FPO if it achieves
a lower voltage level
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index b8c1de357e5f..502f990346b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -725,7 +725,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.min_prefetch_in_strobe_ns = 6, // 60us
.disable_unbounded_requesting = false,
.override_dispclk_programming = true,
- .disable_fpo_optimizations = true,
+ .disable_fpo_optimizations = false,
};
static const struct dc_debug_options debug_defaults_diags = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 5e0b1484dc18..79664ba7e7af 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -723,7 +723,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.min_prefetch_in_strobe_ns = 6, // 60us
.disable_unbounded_requesting = false,
.override_dispclk_programming = true,
- .disable_fpo_optimizations = true,
+ .disable_fpo_optimizations = false,
};
static const struct dc_debug_options debug_defaults_diags = {
--
2.34.1
[PATCH 14/19] drm/amd/display: Only keep cursor p-state force for FPO
From: Alvin Lee
[Description]
If transitioning from an FPO config -> FPO config, we want
to keep cursor P-State force disallowed. Any other transition
from FPO config -> non FPO config should unforce the cursor
P-State disallow
Reviewed-by: Wesley Chalmers
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index b2919104ffc7..b3824287c224 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -591,6 +591,12 @@ void dcn32_update_force_pstate(struct dc *dc, struct
dc_state *context)
pipe->stream->fpo_in_use))) {
if (hubp &&
hubp->funcs->hubp_update_force_pstate_disallow)
hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
+ }
+
+ /* Today only FPO uses cursor P-State force. Only clear cursor
P-State force
+* if it's not FPO.
+*/
+ if (!pipe->stream || (pipe->stream &&
!pipe->stream->fpo_in_use)) {
if (hubp &&
hubp->funcs->hubp_update_force_cursor_pstate_disallow)
hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);
}
--
2.34.1
[PATCH 13/19] drm/amd/display: Conditionally enable 6.75 GBps link rate
From: Artem Grishin
[Why]
The 6.75 GBps link rate is part of the new eDP specification
version 1.5 is going to be supported in the future.
Since this standard is very new and there are no existing 6.75 GBps
panels on the market yet, we should put a condition in the driver
on enabling this feature until we can validate it with real hardware.
[How]
- Add boolean flag support_eDP1_5 in struct dc_debug_options.
- Enable the 6.75 link rate in reduce_link_rate(...) only when
the flag is true.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Artem Grishin
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../dc/link/protocols/link_dp_capability.c| 23 +++
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2d2621abf012..1b77d50cfd89 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -874,6 +874,7 @@ struct dc_debug_options {
bool temp_mst_deallocation_sequence;
bool override_dispclk_programming;
bool disable_fpo_optimizations;
+ bool support_eDP1_5;
};
struct gpu_info_soc_bounding_box_v1_0;
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 7d7edbb2cf52..c840ef17802e 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -447,8 +447,12 @@ static enum dc_lane_count reduce_lane_count(enum
dc_lane_count lane_count)
}
}
-static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
+static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum
dc_link_rate link_rate)
{
+ // NEEDSWORK: provide some details about why this function never
returns some of the
+ // obscure link rates such as 4.32 Gbps or 3.24 Gbps and if such
behavior is intended.
+ //
+
switch (link_rate) {
case LINK_RATE_UHBR20:
return LINK_RATE_UHBR13_5;
@@ -457,13 +461,22 @@ static enum dc_link_rate reduce_link_rate(enum
dc_link_rate link_rate)
case LINK_RATE_UHBR10:
return LINK_RATE_HIGH3;
case LINK_RATE_HIGH3:
+ if (link->connector_signal == SIGNAL_TYPE_EDP &&
link->dc->debug.support_eDP1_5)
+ return LINK_RATE_RATE_8;
+ return LINK_RATE_HIGH2;
+ case LINK_RATE_RATE_8:
return LINK_RATE_HIGH2;
case LINK_RATE_HIGH2:
return LINK_RATE_HIGH;
+ case LINK_RATE_RATE_6:
+ case LINK_RATE_RBR2:
+ return LINK_RATE_HIGH;
case LINK_RATE_HIGH:
return LINK_RATE_LOW;
+ case LINK_RATE_RATE_3:
+ case LINK_RATE_RATE_2:
+ return LINK_RATE_LOW;
case LINK_RATE_LOW:
- return LINK_RATE_UNKNOWN;
default:
return LINK_RATE_UNKNOWN;
}
@@ -586,7 +599,7 @@ bool decide_fallback_link_setting(
case LINK_TRAINING_LQA_FAIL:
{
if (!reached_minimum_link_rate(cur->link_rate)) {
- cur->link_rate = reduce_link_rate(cur->link_rate);
+ cur->link_rate = reduce_link_rate(link, cur->link_rate);
} else if (!reached_minimum_lane_count(cur->lane_count)) {
cur->link_rate = max->link_rate;
if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
@@ -608,7 +621,7 @@ bool decide_fallback_link_setting(
if (!reached_minimum_lane_count(cur->lane_count)) {
cur->lane_count = reduce_lane_count(cur->lane_count);
} else if (!reached_minimum_link_rate(cur->link_rate)) {
- cur->link_rate = reduce_link_rate(cur->link_rate);
+ cur->link_rate = reduce_link_rate(link, cur->link_rate);
/* Reduce max link rate to avoid potential infinite
loop.
* Needed so that any subsequent CR_FAIL fallback can't
* re-set the link rate higher than the link rate from
@@ -624,7 +637,7 @@ bool decide_fallback_link_setting(
case LINK_TRAINING_EQ_FAIL_CR:
{
if (!reached_minimum_link_rate(cur->link_rate)) {
- cur->link_rate = reduce_link_rate(cur->link_rate);
+ cur->link_rate = reduce_link_rate(link, cur->link_rate);
/* Reduce max link rate to avoid potential infinite
loop.
* Needed so that any subsequent CR_FAIL fallback can't
* re-set the link rate higher than the link rate from
--
2.34.1
[PATCH 10/19] drm/amd/display: Use per pipe P-State force for FPO
From: Alvin Lee
[Description]
* Pass in pipe index for FPO cmd to DMCUB
- This change will pass in the pipe index for each stream
that is using FPO
- This change is in preparation to enable FPO + VActive
* Use per pipe P-State force for FPO
- For FPO, instead of using max watermarks value for P-State disallow,
use per pipe p-state force instead
- This is in preparation to enable FPO + VActive
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 46 +++
drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 +
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 10
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +
.../gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c | 10
.../gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h | 2 +
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 41 ++---
.../drm/amd/display/dc/dcn32/dcn32_hwseq.h| 2 +-
.../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 2 +-
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 4 ++
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 8 ++--
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 1 +
.../amd/display/dc/inc/hw_sequencer_private.h | 2 +-
13 files changed, 88 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index b5c6501c28fc..8f26f7245104 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -302,27 +302,31 @@ static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc
*dc, struct dc_stream_
return pipes;
}
-static int dc_dmub_srv_get_timing_generator_offset(struct dc *dc, struct
dc_stream_state *stream)
+static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state
*context,
+ struct pipe_ctx *head_pipe,
+ struct dmub_cmd_fw_assisted_mclk_switch_pipe_data
*fams_pipe_data)
{
- int tg_inst = 0;
- int i = 0;
+ int j;
- for (i = 0; i < MAX_PIPES; i++) {
- struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+ // TODO: Uncomment once FW headers are updated in driver
+ //fams_pipe_data->pipe_index[pipe_idx++] =
head_pipe->plane_res.hubp->inst;
+ for (j = 0; j < dc->res_pool->pipe_count; j++) {
+ struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
- if (pipe->stream == stream && pipe->stream_res.tg) {
- tg_inst = pipe->stream_res.tg->inst;
- break;
+ if (split_pipe->stream == head_pipe->stream &&
(split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
+ // TODO: Uncomment once FW headers are updated in driver
+ //fams_pipe_data->pipe_index[pipe_idx++] =
split_pipe->plane_res.hubp->inst;
}
}
- return tg_inst;
+ // TODO: Uncomment once FW headers are updated in driver
+ //fams_pipe_data->pipe_count = pipe_idx;
}
bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate,
struct dc_state *context)
{
union dmub_rb_cmd cmd = { 0 };
struct dmub_cmd_fw_assisted_mclk_switch_config *config_data =
&cmd.fw_assisted_mclk_switch.config_data;
- int i = 0;
+ int i = 0, k = 0;
int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled.
Reenable it.
uint8_t visual_confirm_enabled;
@@ -337,17 +341,21 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool
should_manage_pstate, stru
cmd.fw_assisted_mclk_switch.config_data.fams_enabled =
should_manage_pstate;
cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled =
visual_confirm_enabled;
- for (i = 0; context && i < context->stream_count; i++) {
- struct dc_stream_state *stream = context->streams[i];
- uint8_t min_refresh_in_hz = (stream->timing.min_refresh_in_uhz
+ 99) / 100;
- int tg_inst = dc_dmub_srv_get_timing_generator_offset(dc,
stream);
+ for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
- config_data->pipe_data[tg_inst].pix_clk_100hz =
stream->timing.pix_clk_100hz;
- config_data->pipe_data[tg_inst].min_refresh_in_hz =
min_refresh_in_hz;
- config_data->pipe_data[tg_inst].max_ramp_step =
ramp_up_num_steps;
- config_data->pipe_data[tg_inst].pipes =
dc_dmub_srv_get_pipes_for_stream(dc, stream);
+ if (!pipe->top_pipe && !pipe->prev_odm_pipe && pipe->stream &&
pipe->stream->fpo_in_use) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ uint8_t min_refresh_in_hz =
(pipe->stream->timing.min_refresh_in_uhz + 99) / 100;
+
+ config_data->pipe_
[PATCH 12/19] drm/amd/display: Add support for 6.75 GBps link rate
From: Artem Grishin
[Why]
The latest eDP spec version 1.5 defines a new generic link
rate of 6.75 Gbps/Lane, which needs to be supported in the driver.
[How]
Added new element to the dc_link_rate enum
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Artem Grishin
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h| 17 +
.../dc/link/protocols/link_dp_capability.c | 5 -
.../dc/link/protocols/link_dp_training.c| 3 +++
3 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index af53278662ec..49aab1924665 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -47,14 +47,15 @@ enum dc_lane_count {
*/
enum dc_link_rate {
LINK_RATE_UNKNOWN = 0,
- LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
- LINK_RATE_RATE_2 = 0x08,// Rate_2 - 2.16 Gbps/Lane
- LINK_RATE_RATE_3 = 0x09,// Rate_3 - 2.43 Gbps/Lane
- LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
- LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane
- LINK_RATE_RATE_6 = 0x10,// Rate_6 - 4.32 Gbps/Lane
- LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane
- LINK_RATE_HIGH3 = 0x1E, // Rate_8 (HBR3)- 8.10 Gbps/Lane
+ LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
+ LINK_RATE_RATE_2 = 0x08,// Rate_2- 2.16 Gbps/Lane
+ LINK_RATE_RATE_3 = 0x09,// Rate_3- 2.43 Gbps/Lane
+ LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
+ LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
+ LINK_RATE_RATE_6 = 0x10,// Rate_6- 4.32 Gbps/Lane
+ LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
+ LINK_RATE_RATE_8 = 0x19,// Rate_8- 6.75 Gbps/Lane
+ LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
/* Starting from DP2.0 link rate enum directly represents actual
* link rate value in unit of 10 mbps
*/
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 2a2443535b67..7d7edbb2cf52 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -203,8 +203,11 @@ static enum dc_link_rate
linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in
case 540:
link_rate = LINK_RATE_HIGH2;// Rate_7 (HBR2)- 5.40 Gbps/Lane
break;
+ case 675:
+ link_rate = LINK_RATE_RATE_8; // Rate_8 - 6.75 Gbps/Lane
+ break;
case 810:
- link_rate = LINK_RATE_HIGH3;// Rate_8 (HBR3)- 8.10 Gbps/Lane
+ link_rate = LINK_RATE_HIGH3;// Rate_9 (HBR3)- 8.10 Gbps/Lane
break;
default:
link_rate = LINK_RATE_UNKNOWN;
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
index 10261764a0ce..f301c9eaf2f9 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
@@ -86,6 +86,9 @@ void dp_log_training_result(
case LINK_RATE_HIGH2:
link_rate = "HBR2";
break;
+ case LINK_RATE_RATE_8:
+ link_rate = "R8";
+ break;
case LINK_RATE_HIGH3:
link_rate = "HBR3";
break;
--
2.34.1
[PATCH 11/19] drm/amd/display: fixed dcn30+ underflow issue
From: Ayush Gupta [Why] Observing underflow on dcn30+ system config at 4k144hz [How] We set the UCLK hardmax on AC/DC switch if softmax is enabled and also on boot. While booting up the UCLK Hardmax is set to softmax before the init sequence and the init sequence resets the hardmax to UCLK max which enables P-state switching. Just added a conditional check to avoid setting hardmax on init. Reviewed-by: Alvin Lee Reviewed-by: Martin Leung Acked-by: Qingqing Zhuo Signed-off-by: Ayush Gupta --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 3 ++- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index 6d328b7e07a8..0e071fbc9154 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -621,7 +621,8 @@ void dcn30_init_hw(struct dc *dc) if (dc->clk_mgr->funcs->notify_wm_ranges) dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); - if (dc->clk_mgr->funcs->set_hard_max_memclk) + //if softmax is enabled then hardmax will be set by a different call + if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled) dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); if (dc->res_pool->hubbub->funcs->force_pstate_change_control) diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c index 10e3cc17f71a..7ac6e69cff37 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c @@ -285,7 +285,7 @@ void dcn31_init_hw(struct dc *dc) if (dc->clk_mgr->funcs->notify_wm_ranges) dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); - if (dc->clk_mgr->funcs->set_hard_max_memclk) + if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled) dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); if (dc->res_pool->hubbub->funcs->force_pstate_change_control) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 5ee9c5a74ecb..b2919104ffc7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -909,7 +909,7 @@ void dcn32_init_hw(struct dc *dc) if (dc->clk_mgr->funcs->notify_wm_ranges) dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); - if (dc->clk_mgr->funcs->set_hard_max_memclk) + if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled) dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); if (dc->res_pool->hubbub->funcs->force_pstate_change_control) -- 2.34.1
[PATCH 09/19] drm/amd/display: Add infrastructure for enabling FAMS for DCN30
As part of the FAMS work, we need code infrastructure in DC.
dcn30_fpu.c changes went missing during previous upstream
activity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 53 ---
1 file changed, 46 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index 4fa636364793..ecfa395f5fa8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -384,9 +384,34 @@ void dcn30_fpu_calculate_wm_and_dlg(
int i, pipe_idx;
double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];
bool pstate_en =
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] !=
dm_dram_clock_change_unsupported;
+ unsigned int dummy_latency_index = 0;
dc_assert_fp_enabled();
+ context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
+
+ if (!pstate_en) {
+ /* only when the mclk switch can not be natural, is the fw
based vblank stretch attempted */
+ context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching =
+
dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);
+
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
+ dummy_latency_index =
dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
+ context, pipes, pipe_cnt, vlevel);
+
+ /* After calling
dcn30_find_dummy_latency_index_for_fw_based_mclk_switch
+* we reinstate the original
dram_clock_change_latency_us on the context
+* and all variables that may have changed up to this
point, except the
+* newly found dummy_latency_index
+*/
+ context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
+ dcn30_internal_validate_bw(dc, context, pipes,
&pipe_cnt, &vlevel, false, true);
+ maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
+ dcfclk =
context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+ pstate_en =
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] !=
dm_dram_clock_change_unsupported;
+ }
+ }
+
if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
@@ -449,15 +474,29 @@ void dcn30_fpu_calculate_wm_and_dlg(
unsigned int min_dram_speed_mts =
context->bw_ctx.dml.vba.DRAMSpeed;
unsigned int min_dram_speed_mts_margin = 160;
- if
(context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
== dm_dram_clock_change_unsupported)
- min_dram_speed_mts =
dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries
- 1].memclk_mhz * 16;
+ context->bw_ctx.dml.soc.dram_clock_change_latency_us =
+
dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;
- /* find largest table entry that is lower than dram speed, but
lower than DPM0 still uses DPM0 */
- for (i = 3; i > 0; i--)
- if (min_dram_speed_mts + min_dram_speed_mts_margin >
dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts)
- break;
+ if
(context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==
+ dm_dram_clock_change_unsupported) {
+ int min_dram_speed_mts_offset =
dc->clk_mgr->bw_params->clk_table.num_entries - 1;
- context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
+ min_dram_speed_mts =
+
dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz
* 16;
+ }
+
+ if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
+ /* find largest table entry that is lower than dram
speed,
+* but lower than DPM0 still uses DPM0
+*/
+ for (dummy_latency_index = 3; dummy_latency_index > 0;
dummy_latency_index--)
+ if (min_dram_speed_mts +
min_dram_speed_mts_margin >
+
dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)
+ break;
+ }
+
+
[PATCH 08/19] drm/amd/display: Add 90Mhz to video_optimized_pixel_rates
From: Taimur Hassan
[Why & How]
Needed to get certain EDID to light up during TMDS compliance.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 67e3df7e1b05..462c7a3ec3cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1157,6 +1157,7 @@ const struct pixel_rate_range_table_entry
video_optimized_pixel_rates[] = {
{25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17
{59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340
{74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758
+ {89910, 9, 9, 1000, 1001}, //90Mhz -> 89.91
{125870, 125880, 126000, 1000, 1001}, //126Mhz-> 125.87
{148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516
{167830, 167840, 168000, 1000, 1001}, //168Mhz-> 167.83
--
2.34.1
[PATCH 07/19] drm/amd/display: w/a for dcn315 inconsistent smu clock table
From: Dmytro Laktyushkin
[Why & How]
w/a for dcn315 inconsistent smu clock.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index a737782b2840..b737cbc468f5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -522,6 +522,11 @@ static void dcn315_clk_mgr_helper_populate_bw_params(
bw_params->clk_table.entries[i].dcfclk_mhz =
clock_table->DcfClocks[0];
bw_params->clk_table.entries[i].wck_ratio = 1;
i++;
+ } else if (clock_table->NumDcfClkLevelsEnabled !=
clock_table->NumSocClkLevelsEnabled) {
+ bw_params->clk_table.entries[i-1].voltage =
clock_table->SocVoltage[clock_table->NumSocClkLevelsEnabled - 1];
+ bw_params->clk_table.entries[i-1].socclk_mhz =
clock_table->SocClocks[clock_table->NumSocClkLevelsEnabled - 1];
+ bw_params->clk_table.entries[i-1].dispclk_mhz =
clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1];
+ bw_params->clk_table.entries[i-1].dppclk_mhz =
clock_table->DppClocks[clock_table->NumDispClkLevelsEnabled - 1];
}
bw_params->clk_table.num_entries = i;
--
2.34.1
[PATCH 06/19] drm/amd/display: update dig enable sequence
From: Charlene Liu
[why]
HW delta follow up
Reviewed-by: Chris Park
Reviewed-by: Jun Lei
Reviewed-by: Jerry Zuo
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
.../amd/display/dc/dcn32/dcn32_dio_stream_encoder.c | 10 +-
.../amd/display/dc/dcn32/dcn32_dio_stream_encoder.h | 8
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 11 ++-
3 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
index d05e7655f603..2fef1419ae91 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
@@ -274,10 +274,10 @@ static bool is_dp_dig_pixel_rate_div_policy(struct dc
*dc, const struct dc_crtc_
dc->debug.enable_dp_dig_pixel_rate_div_policy;
}
-static void enc32_stream_encoder_dp_unblank(
-struct dc_link *link,
- struct stream_encoder *enc,
- const struct encoder_unblank_param *param)
+void enc32_stream_encoder_dp_unblank(
+ struct dc_link *link,
+ struct stream_encoder *enc,
+ const struct encoder_unblank_param *param)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
struct dc *dc = enc->ctx->dc;
@@ -440,7 +440,7 @@ static void enc32_reset_fifo(struct stream_encoder *enc,
bool reset)
udelay(10);
}
-static void enc32_enable_fifo(struct stream_encoder *enc)
+void enc32_enable_fifo(struct stream_encoder *enc)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
index 875b1cd46056..1be5410cce97 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
@@ -194,4 +194,12 @@ void dcn32_dio_stream_encoder_construct(
const struct dcn10_stream_encoder_shift *se_shift,
const struct dcn10_stream_encoder_mask *se_mask);
+
+void enc32_enable_fifo(struct stream_encoder *enc);
+
+void enc32_stream_encoder_dp_unblank(
+ struct dc_link *link,
+ struct stream_encoder *enc,
+ const struct encoder_unblank_param *param);
+
#endif /* __DC_DIO_STREAM_ENCODER_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 020d668ce09e..aa08925d54c9 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -2477,11 +2477,12 @@ void link_set_dpms_on(
* from transmitter control.
*/
if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
- dp_is_128b_132b_signal(pipe_ctx)))
- if (link_enc)
- link_enc->funcs->setup(
- link_enc,
- pipe_ctx->stream->signal);
+ dp_is_128b_132b_signal(pipe_ctx))) {
+ if (link_enc)
+ link_enc->funcs->setup(
+ link_enc,
+ pipe_ctx->stream->signal);
+ }
dc->hwss.enable_stream(pipe_ctx);
--
2.34.1
[PATCH 05/19] drm/amd/display: fix double memory allocation
From: Martin Leung [Why & How] when trying to fix a nullptr dereference on VMs, accidentally doubly allocated memory for the non VM case. removed the extra link_srv creation since dc_construct_ctx is called in both VM and non VM cases Also added a proper fail check for if kzalloc fails Cc: sta...@vger.kernel.org Cc: Mario Limonciello Reviewed-by: Leo Ma Acked-by: Qingqing Zhuo Signed-off-by: Martin Leung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 40f2e174c524..52564b93f7eb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -887,7 +887,10 @@ static bool dc_construct_ctx(struct dc *dc, } dc->ctx = dc_ctx; + dc->link_srv = link_create_link_service(); + if (!dc->link_srv) + return false; return true; } @@ -986,8 +989,6 @@ static bool dc_construct(struct dc *dc, goto fail; } - dc->link_srv = link_create_link_service(); - dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version); if (!dc->res_pool) goto fail; -- 2.34.1
[PATCH 03/19] drm/amd/display: Update FCLK change latency
From: Alvin Lee
[Descrtipion]
- Driver hardcoded FCLK P-State latency was incorrect
- Use the value provided by PMFW header instead
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 4e17f2c8d2b7..6ab60facc091 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -131,7 +131,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
.urgent_latency_pixel_data_only_us = 4.0,
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
.urgent_latency_vm_data_only_us = 4.0,
- .fclk_change_latency_us = 20,
+ .fclk_change_latency_us = 25,
.usr_retraining_latency_us = 2,
.smn_latency_us = 2,
.mall_allocated_for_dcn_mbytes = 64,
--
2.34.1
[PATCH 04/19] drm/amd/display: Fix 4to1 MPC black screen with DPP RCO
From: Nicholas Kazlauskas
[Why]
DPP Root clock optimization when combined with 4to1 MPC combine results
in the screen turning black.
This is because the DPPCLK is stopped during the middle of an
optimize_bandwidth sequence during commit_minimal_transition without
going through plane power down/power up.
[How]
The intent of a 0Hz DPP clock through update_clocks is to disable the
DTO. This differs from the behavior of stopping the DPPCLK entirely
(utilizing a 0Hz clock on some ASIC) so it's better to move this logic
to reside next to plane power up/power down where we gate the HUBP/DPP
DOMAIN.
The new sequence should be:
Power down: PG enabled -> RCO on
Power up: RCO off -> PG disabled
Rename power_on_plane to power_on_plane_resources to reflect the
actual operation that's occurring.
Cc: sta...@vger.kernel.org
Cc: Mario Limonciello
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 ++--
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 8 --
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 13 ++---
.../drm/amd/display/dc/dcn314/dcn314_dccg.c | 23 +++
.../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 10 +++
.../drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 ++
.../drm/amd/display/dc/dcn314/dcn314_init.c | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 28 +++
.../amd/display/dc/inc/hw_sequencer_private.h | 4 +++
9 files changed, 74 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 46ca88741cb8..1c3b6f25a782 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -726,11 +726,15 @@ void dcn10_hubp_pg_control(
}
}
-static void power_on_plane(
+static void power_on_plane_resources(
struct dce_hwseq *hws,
int plane_id)
{
DC_LOGGER_INIT(hws->ctx->logger);
+
+ if (hws->funcs.dpp_root_clock_control)
+ hws->funcs.dpp_root_clock_control(hws, plane_id, true);
+
if (REG(DC_IP_REQUEST_CNTL)) {
REG_SET(DC_IP_REQUEST_CNTL, 0,
IP_REQUEST_EN, 1);
@@ -1237,11 +1241,15 @@ void dcn10_plane_atomic_power_down(struct dc *dc,
hws->funcs.hubp_pg_control(hws, hubp->inst, false);
dpp->funcs->dpp_reset(dpp);
+
REG_SET(DC_IP_REQUEST_CNTL, 0,
IP_REQUEST_EN, 0);
DC_LOG_DEBUG(
"Power gated front end %d\n", hubp->inst);
}
+
+ if (hws->funcs.dpp_root_clock_control)
+ hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);
}
/* disable HW used by plane.
@@ -2462,7 +2470,7 @@ static void dcn10_enable_plane(
undo_DEGVIDCN10_253_wa(dc);
- power_on_plane(dc->hwseq,
+ power_on_plane_resources(dc->hwseq,
pipe_ctx->plane_res.hubp->inst);
/* enable DCFCLK current DCHUB */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 69ea1f4ea749..9ca162ea0d07 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1130,11 +1130,15 @@ void dcn20_blank_pixel_data(
}
-static void dcn20_power_on_plane(
+static void dcn20_power_on_plane_resources(
struct dce_hwseq *hws,
struct pipe_ctx *pipe_ctx)
{
DC_LOGGER_INIT(hws->ctx->logger);
+
+ if (hws->funcs.dpp_root_clock_control)
+ hws->funcs.dpp_root_clock_control(hws,
pipe_ctx->plane_res.dpp->inst, true);
+
if (REG(DC_IP_REQUEST_CNTL)) {
REG_SET(DC_IP_REQUEST_CNTL, 0,
IP_REQUEST_EN, 1);
@@ -1158,7 +1162,7 @@ static void dcn20_enable_plane(struct dc *dc, struct
pipe_ctx *pipe_ctx,
//if (dc->debug.sanity_checks) {
// dcn10_verify_allow_pstate_change_high(dc);
//}
- dcn20_power_on_plane(dc->hwseq, pipe_ctx);
+ dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx);
/* enable DCFCLK current DCHUB */
pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 7f34418e6308..7d2b982506fd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -66,17 +66,8 @@ void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst,
int req_dppclk)
REG_UPDATE(DPPCLK_DTO_CTRL,
DPPCLK_DTO_ENABLE[dpp_inst], 1);
} else {
- //DTO must be enabled to generate a 0Hz clock output
- if
[PATCH 02/19] drm/amd/display: Enable FPO for configs that could reduce vlevel
From: Alvin Lee
[Description]
- On high refresh rate DRR displays that support VBLANK naturally,
UCLK could be idling at DPM1 instead of DPM0 since it doesn't use
FPO
- To achieve DPM0, enable FPO on these configs even though it can
support P-State without FPO
- Default disable for now, have debug option to enable
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
.../amd/display/dc/dcn321/dcn321_resource.c | 1 +
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 23 ++-
4 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 475128db02bb..2d2621abf012 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -873,6 +873,7 @@ struct dc_debug_options {
bool dig_fifo_off_in_blank;
bool temp_mst_deallocation_sequence;
bool override_dispclk_programming;
+ bool disable_fpo_optimizations;
};
struct gpu_info_soc_bounding_box_v1_0;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 1715909b1225..b8c1de357e5f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -725,6 +725,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.min_prefetch_in_strobe_ns = 6, // 60us
.disable_unbounded_requesting = false,
.override_dispclk_programming = true,
+ .disable_fpo_optimizations = true,
};
static const struct dc_debug_options debug_defaults_diags = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index c6a0e84885a2..5e0b1484dc18 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -723,6 +723,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.min_prefetch_in_strobe_ns = 6, // 60us
.disable_unbounded_requesting = false,
.override_dispclk_programming = true,
+ .disable_fpo_optimizations = true,
};
static const struct dc_debug_options debug_defaults_diags = {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 6b29d3a9520f..4e17f2c8d2b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1961,7 +1961,8 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct
dc_state *context,
context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
- if (!pstate_en) {
+ if (!pstate_en || (!dc->debug.disable_fpo_optimizations &&
+ pstate_en && vlevel != 0)) {
/* only when the mclk switch can not be natural, is the fw
based vblank stretch attempted */
context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching =
dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);
@@ -1985,11 +1986,21 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc,
struct dc_state *context,
context->bw_ctx.dml.soc.fclk_change_latency_us =
dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
}
- dcn32_internal_validate_bw(dc, context, pipes,
&pipe_cnt, &vlevel, false);
- maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
- dcfclk_from_fw_based_mclk_switching =
context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
- pstate_en =
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] !=
- dm_dram_clock_change_unsupported;
+ dcn32_internal_validate_bw(dc, context, pipes,
&pipe_cnt, &vlevel_temp, false);
+ if (vlevel_temp < vlevel) {
+ vlevel = vlevel_temp;
+ maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
+ dcfclk_from_fw_based_mclk_switching =
context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+ pstate_en = true;
+ } else {
+ /* Restore FCLK latency and re-run validation
to go back to original validation
+* output if we find that enabling FPO does not
give us any benefit (i.e. lower
+* voltage level)
+*/
+
[PATCH 01/19] drm/amd/display: Add NULL plane_state check for cursor disable logic
From: Nicholas Kazlauskas
[Why]
While scanning the top_pipe connections we can run into a case where
the bottom pipe is still connected to a top_pipe but with a NULL
plane_state.
[How]
Treat a NULL plane_state the same as the plane being invisible for
pipe cursor disable logic.
Cc: sta...@vger.kernel.org
Cc: Mario Limonciello
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7f9cceb49f4e..46ca88741cb8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3385,7 +3385,9 @@ static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx
*pipe_ctx)
for (test_pipe = pipe_ctx->top_pipe; test_pipe;
test_pipe = test_pipe->top_pipe) {
// Skip invisible layer and pipe-split plane on same layer
- if (!test_pipe->plane_state->visible ||
test_pipe->plane_state->layer_index == cur_layer)
+ if (!test_pipe->plane_state ||
+ !test_pipe->plane_state->visible ||
+ test_pipe->plane_state->layer_index == cur_layer)
continue;
r2 = test_pipe->plane_res.scl_data.recout;
--
2.34.1
[PATCH 00/19] DC Patches Mar 27th, 2023
This DC patchset brings improvements in multiple areas. In summary, we highlight: - Enable FPO optimization - Support for 6.75 GBps link rate - Fixes to underflow, black screen and more Cc: Daniel Wheeler --- Alvin Lee (6): drm/amd/display: Enable FPO for configs that could reduce vlevel drm/amd/display: Update FCLK change latency drm/amd/display: Use per pipe P-State force for FPO drm/amd/display: Only keep cursor p-state force for FPO drm/amd/display: Enable FPO optimization drm/amd/display: Uncomment assignments after HW headers are promoted Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.160.0 Aric Cyr (1): drm/amd/display: Promote DAL to 3.2.229 Artem Grishin (2): drm/amd/display: Add support for 6.75 GBps link rate drm/amd/display: Conditionally enable 6.75 GBps link rate Ayush Gupta (1): drm/amd/display: fixed dcn30+ underflow issue Charlene Liu (1): drm/amd/display: update dig enable sequence Dmytro Laktyushkin (1): drm/amd/display: w/a for dcn315 inconsistent smu clock table Martin Leung (1): drm/amd/display: fix double memory allocation Nicholas Kazlauskas (2): drm/amd/display: Add NULL plane_state check for cursor disable logic drm/amd/display: Fix 4to1 MPC black screen with DPP RCO Peichen Huang (1): drm/amd/display: skip ClearPayloadIdTable if device mst_en is 0 Qingqing Zhuo (1): drm/amd/display: Add infrastructure for enabling FAMS for DCN30 Taimur Hassan (1): drm/amd/display: Add 90Mhz to video_optimized_pixel_rates .../dc/clk_mgr/dcn315/dcn315_clk_mgr.c| 5 ++ drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +- drivers/gpu/drm/amd/display/dc/dc.h | 4 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 44 +++--- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 17 +++--- drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 + .../drm/amd/display/dc/dce/dce_clock_source.c | 1 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 18 +- .../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 3 +- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 2 + .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 13 + .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 2 +- .../drm/amd/display/dc/dcn314/dcn314_dccg.c | 23 .../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 10 .../drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 + .../drm/amd/display/dc/dcn314/dcn314_init.c | 1 + .../dc/dcn32/dcn32_dio_stream_encoder.c | 10 ++-- .../dc/dcn32/dcn32_dio_stream_encoder.h | 8 +++ .../gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c | 10 .../gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h | 2 + .../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 49 ++-- .../drm/amd/display/dc/dcn32/dcn32_hwseq.h| 2 +- .../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 2 +- .../drm/amd/display/dc/dcn32/dcn32_resource.c | 1 + .../amd/display/dc/dcn321/dcn321_resource.c | 1 + .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 57 --- .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 33 +++ drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 28 + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 1 + .../amd/display/dc/inc/hw_sequencer_private.h | 6 +- .../gpu/drm/amd/display/dc/link/link_dpms.c | 16 -- .../dc/link/protocols/link_dp_capability.c| 28 +++-- .../dc/link/protocols/link_dp_training.c | 3 + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 14 - 35 files changed, 319 insertions(+), 119 deletions(-) -- 2.34.1
Re: [v1,2/3] drm/amd/pm: send the SMT-enable message to pmfw
On 3/23/2023 11:36 PM, Limonciello, Mario wrote:
On 3/23/2023 12:41, Limonciello, Mario wrote:
On 3/22/2023 00:48, Wenyou Yang wrote:
When the CPU SMT status change in the fly, sent the SMT-enable
message to pmfw to notify it that the SMT status changed.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 +++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index b5d64749990e..5cd85a9d149d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -22,6 +22,7 @@
#define SWSMU_CODE_LAYER_L1
+#include
#include
#include
@@ -69,6 +70,14 @@ static int smu_set_fan_speed_rpm(void *handle,
uint32_t speed);
static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
static int smu_set_mp1_state(void *handle, enum pp_mp1_state
mp1_state);
+static int smt_notifier_callback(struct notifier_block *nb, unsigned
long action, void *data);
+
+extern struct raw_notifier_head smt_notifier_head;
+
+static struct notifier_block smt_notifier = {
+ .notifier_call = smt_notifier_callback,
+};
+
static int smu_sys_get_pp_feature_mask(void *handle,
char *buf)
{
@@ -625,6 +634,8 @@ static int smu_set_funcs(struct amdgpu_device *adev)
return 0;
}
+static struct smu_context *current_smu;
+
static int smu_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -645,6 +656,7 @@ static int smu_early_init(void *handle)
mutex_init(&smu->message_lock);
adev->powerplay.pp_handle = smu;
+ current_smu = smu;
Although this series is intended for the Van Gogh case right now, I
dont't think this would scale well for multiple GPUs in a system.
I think that instead you may want to move the notifier callback to be a
level "higher" in amdgpu. Perhaps amdgpu_device.c? Then when that
notifier call is received you'll want to walk through the PCI device
space to find any GPUs that are bound with AMDGPU a series of
wrappers/calls that end up calling smu_set_cpu_smt_enable with the
approriate arguments.
This is not required when the notifier is registered only within Vangogh
ppt function. Then follow Evan's suggestion of keeping the notifier
block inside smu. From the notifier block, it can find the smu block and
then call cpu_smt_enable/disable. That way notifier callback comes only
once even with multiple dGPUs + Vangogh and processed for the
corresponding smu.
This notifier doesn't need to be registered for platforms only with
dGPUs or APUs which don't need this.
Thanks,
Lijo
adev->powerplay.pp_funcs = &swsmu_pm_funcs;
r = smu_set_funcs(adev);
@@ -1105,6 +1117,8 @@ static int smu_sw_init(void *handle)
if (!smu->ppt_funcs->get_fan_control_mode)
smu->adev->pm.no_fan = true;
+ raw_notifier_chain_register(&smt_notifier_head, &smt_notifier);
+
return 0;
}
@@ -1122,6 +1136,8 @@ static int smu_sw_fini(void *handle)
smu_fini_microcode(smu);
+ raw_notifier_chain_unregister(&smt_notifier_head, &smt_notifier);
+
return 0;
}
@@ -3241,3 +3257,28 @@ int smu_send_hbm_bad_channel_flag(struct
smu_context *smu, uint32_t size)
return ret;
}
+
+static int smu_set_cpu_smt_enable(struct smu_context *smu, bool enable)
+{
+ int ret = -EINVAL;
+
+ if (smu->ppt_funcs && smu->ppt_funcs->set_cpu_smt_enable)
+ ret = smu->ppt_funcs->set_cpu_smt_enable(smu, enable);
+
+ return ret;
+}
+
+static int smt_notifier_callback(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct smu_context *smu = current_smu;
+ int ret = NOTIFY_OK;
This initialization is pointless, it's clobbered in the next line.
+
+ ret = (action == SMT_ENABLED) ?
+ smu_set_cpu_smt_enable(smu, true) :
+ smu_set_cpu_smt_enable(smu, false);
How about this instead, it should be more readable:
ret = smu_set_cpu_smt_enable(smu, action == SMT_ENABLED);
+ if (ret)
+ ret = NOTIFY_BAD;
+
+ return ret;
How about instead:
dev_dbg(adev->dev, "failed to %sable SMT: %d\n", action ==
SMT_ENABLED ? "en" : "dis", ret);
return ret ? NOTIFY_BAD : NOTIFY_OK;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 09469c750a96..7c6594bba796 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1354,6 +1354,11 @@ struct pptable_funcs {
* @init_pptable_microcode: Prepare the pptable microcode to
upload via PSP
*/
int (*init_pptable_microcode)(struct smu_context *smu);
+
+ /**
+ * @set_cpu_smt_enable: Set the CPU SMT status
+ */
+ int (*set_cpu_smt_enable)(struct smu_context *smu, bool enab
RE: [v1,2/3] drm/amd/pm: send the SMT-enable message to pmfw
[AMD Official Use Only - General]
> -Original Message-
> From: Limonciello, Mario
> Sent: Friday, March 24, 2023 1:42 AM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Li, Ying ; Liu, Kun ; amd-
> g...@lists.freedesktop.org; Liang, Richard qi
> Subject: Re: [v1,2/3] drm/amd/pm: send the SMT-enable message to pmfw
>
> On 3/22/2023 00:48, Wenyou Yang wrote:
> > When the CPU SMT status change in the fly, sent the SMT-enable message
> > to pmfw to notify it that the SMT status changed.
> >
> > Signed-off-by: Wenyou Yang
> > ---
> > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41
> +++
> > drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +++
> > 2 files changed, 46 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index b5d64749990e..5cd85a9d149d 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -22,6 +22,7 @@
> >
> > #define SWSMU_CODE_LAYER_L1
> >
> > +#include
> > #include
> > #include
> >
> > @@ -69,6 +70,14 @@ static int smu_set_fan_speed_rpm(void *handle,
> uint32_t speed);
> > static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
> > static int smu_set_mp1_state(void *handle, enum pp_mp1_state
> > mp1_state);
> >
> > +static int smt_notifier_callback(struct notifier_block *nb, unsigned
> > +long action, void *data);
> > +
> > +extern struct raw_notifier_head smt_notifier_head;
> > +
> > +static struct notifier_block smt_notifier = {
> > + .notifier_call = smt_notifier_callback, };
> > +
> > static int smu_sys_get_pp_feature_mask(void *handle,
> >char *buf)
> > {
> > @@ -625,6 +634,8 @@ static int smu_set_funcs(struct amdgpu_device
> *adev)
> > return 0;
> > }
> >
> > +static struct smu_context *current_smu;
> > +
> > static int smu_early_init(void *handle)
> > {
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> @@
> > -645,6 +656,7 @@ static int smu_early_init(void *handle)
> > mutex_init(&smu->message_lock);
> >
> > adev->powerplay.pp_handle = smu;
> > + current_smu = smu;
> > adev->powerplay.pp_funcs = &swsmu_pm_funcs;
> >
> > r = smu_set_funcs(adev);
> > @@ -1105,6 +1117,8 @@ static int smu_sw_init(void *handle)
> > if (!smu->ppt_funcs->get_fan_control_mode)
> > smu->adev->pm.no_fan = true;
> >
> > + raw_notifier_chain_register(&smt_notifier_head, &smt_notifier);
> > +
> > return 0;
> > }
> >
> > @@ -1122,6 +1136,8 @@ static int smu_sw_fini(void *handle)
> >
> > smu_fini_microcode(smu);
> >
> > + raw_notifier_chain_unregister(&smt_notifier_head, &smt_notifier);
> > +
> > return 0;
> > }
> >
> > @@ -3241,3 +3257,28 @@ int smu_send_hbm_bad_channel_flag(struct
> > smu_context *smu, uint32_t size)
> >
> > return ret;
> > }
> > +
> > +static int smu_set_cpu_smt_enable(struct smu_context *smu, bool
> > +enable) {
> > + int ret = -EINVAL;
> > +
> > + if (smu->ppt_funcs && smu->ppt_funcs->set_cpu_smt_enable)
> > + ret = smu->ppt_funcs->set_cpu_smt_enable(smu, enable);
> > +
> > + return ret;
> > +}
> > +
> > +static int smt_notifier_callback(struct notifier_block *nb,
> > +unsigned long action, void *data) {
> > + struct smu_context *smu = current_smu;
> > + int ret = NOTIFY_OK;
>
> This initialization is pointless, it's clobbered in the next line.
Yes, accept.
>
> > +
> > + ret = (action == SMT_ENABLED) ?
> > + smu_set_cpu_smt_enable(smu, true) :
> > + smu_set_cpu_smt_enable(smu, false);
>
> How about this instead, it should be more readable:
>
> ret = smu_set_cpu_smt_enable(smu, action == SMT_ENABLED);
Accept.
>
> > + if (ret)
> > + ret = NOTIFY_BAD;
> > +
> > + return ret;
>
> How about instead:
>
> dev_dbg(adev->dev, "failed to %sable SMT: %d\n", action ==
> SMT_ENABLED ? "en" : "dis", ret);
>
> return ret ? NOTIFY_BAD : NOTIFY_OK;
>
Accept.
Thanks
Wenyou
> > +}
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > index 09469c750a96..7c6594bba796 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > @@ -1354,6 +1354,11 @@ struct pptable_funcs {
> > * @init_pptable_microcode: Prepare the pptable microcode to
> upload via PSP
> > */
> > int (*init_pptable_microcode)(struct smu_context *smu);
> > +
> > + /**
> > +* @set_cpu_smt_enable: Set the CPU SMT status
> > +*/
> > + int (*set_cpu_smt_enable)(struct smu_context *smu, bool enable);
> > };
> >
> > typedef enum {
RE: [v1,3/3] drm/amd/pm: vangogh: support to send SMT enable message
[AMD Official Use Only - General]
> -Original Message-
> From: Limonciello, Mario
> Sent: Friday, March 24, 2023 1:15 AM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Li, Ying ; Liu, Kun ; amd-
> g...@lists.freedesktop.org; Liang, Richard qi
> Subject: Re: [v1,3/3] drm/amd/pm: vangogh: support to send SMT enable
> message
>
> On 3/22/2023 00:48, Wenyou Yang wrote:
> > Add the support to PPSMC_MSG_SetCClkSMTEnable(0x58) message to
> pmfw
> > for vangogh.
> >
> > Signed-off-by: Wenyou Yang
> > ---
> > .../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 3 ++-
> > drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
> > .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 19
> +++
> > 3 files changed, 23 insertions(+), 2 deletions(-)
> >
> > diff --git
> > a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > index 7471e2df2828..2b182dbc6f9c 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > +++
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > @@ -111,7 +111,8 @@
> > #define PPSMC_MSG_GetGfxOffStatus0x50
> > #define PPSMC_MSG_GetGfxOffEntryCount0x51
> > #define PPSMC_MSG_LogGfxOffResidency 0x52
> > -#define PPSMC_Message_Count0x53
> > +#define PPSMC_MSG_SetCClkSMTEnable0x58
> > +#define PPSMC_Message_Count0x54
>
> This doesn't make sense that the PPSMC_Message_Count would be smaller
> than the biggest message. This should be:
>
> #define PPSMC_Message_Count 0x59
>
Accepted.
Thanks
Wenyou
> >
> > //Argument for PPSMC_MSG_GfxDeviceDriverReset
> > enum {
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > index 297b70b9388f..820812d910bf 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > @@ -245,7 +245,8 @@
> > __SMU_DUMMY_MAP(AllowGpo), \
> > __SMU_DUMMY_MAP(Mode2Reset),\
> > __SMU_DUMMY_MAP(RequestI2cTransaction), \
> > - __SMU_DUMMY_MAP(GetMetricsTable),
> > + __SMU_DUMMY_MAP(GetMetricsTable), \
> > + __SMU_DUMMY_MAP(SetCClkSMTEnable),
> >
> > #undef __SMU_DUMMY_MAP
> > #define __SMU_DUMMY_MAP(type) SMU_MSG_##type
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > index 7433dcaa16e0..f0eeb42df96b 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > @@ -141,6 +141,7 @@ static struct cmn2asic_msg_mapping
> vangogh_message_map[SMU_MSG_MAX_COUNT] = {
> > MSG_MAP(GetGfxOffStatus,
> PPSMC_MSG_GetGfxOffStatus,
> 0),
> > MSG_MAP(GetGfxOffEntryCount,
> PPSMC_MSG_GetGfxOffEntryCount,0),
> > MSG_MAP(LogGfxOffResidency,
> PPSMC_MSG_LogGfxOffResidency, 0),
> > + MSG_MAP(SetCClkSMTEnable,
> PPSMC_MSG_SetCClkSMTEnable,
> 0),
> > };
> >
> > static struct cmn2asic_mapping
> > vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { @@ -2428,6
> +2429,23 @@ static u32 vangogh_get_gfxoff_entrycount(struct
> smu_context *smu, uint64_t *entr
> > return ret;
> > }
> >
> > +static int vangogh_set_cpu_smt_enable(struct smu_context *smu, bool
> > +enable) {
> > + int ret = 0;
> > +
> > + if (enable) {
> > + ret = smu_cmn_send_smc_msg_with_param(smu,
> > +
> SMU_MSG_SetCClkSMTEnable,
> > + 1, NULL);
> > + } else {
> > + ret = smu_cmn_send_smc_msg_with_param(smu,
> > +
> SMU_MSG_SetCClkSMTEnable,
> > + 0, NULL);
> > + }
> > +
> > + return ret;
> > +}
> > +
> > static const struct pptable_funcs vangogh_ppt_funcs = {
> >
> > .check_fw_status = smu_v11_0_check_fw_status, @@ -2474,6
> +2492,7 @@
> > static const struct pptable_funcs vangogh_ppt_funcs = {
> > .get_power_limit = vangogh_get_power_limit,
> > .set_power_limit = vangogh_set_power_limit,
> > .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
> > + .set_cpu_smt_enable = vangogh_set_cpu_smt_enable,
> > };
> >
> > void vangogh_set_ppt_funcs(struct smu_context *smu)
Re: [Resend PATCH v1 0/3] send message to pmfw when SMT changes
Hi Wenyou Yang, first of all thanks for the improvement! I'd like to ask you (and all CCed) if it would be possible to explain a bit the goal / functionality behind these patches. By reading the commit descriptions and code, I can understand code-wise what's going on and how this will message the FW on SMT changes. What I couldn't parse is the purpose of this, or in other words, what does it gain for us? Also, why only on Vangogh? Since I don't have the spec I couldn't read and learn myself - apologies if this is somewhat a silly question. Also, if for some reason you cannot respond (like a HW "NDA"), it's fine too. Thanks in advance, Guilherme
Re: [linux-next:master] BUILD REGRESSION 7c4a254d78f89546d0e74a40617ef24c6151c8d1
On Fri, Mar 24, 2023 at 05:34:18AM +0800, kernel test robot wrote: > tree/branch: > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master > branch HEAD: 7c4a254d78f89546d0e74a40617ef24c6151c8d1 Add linux-next > specific files for 20230323 > > Error/Warning reports: > > https://lore.kernel.org/oe-kbuild-all/202303161521.jbgbafjj-...@intel.com > https://lore.kernel.org/oe-kbuild-all/202303231302.iy6qifxa-...@intel.com > https://lore.kernel.org/oe-kbuild-all/202303232154.axoxawhg-...@intel.com > > Error/Warning: (recently discovered and may have been fixed) > > drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:351:13: > warning: variable 'bw_needed' set but not used [-Wunused-but-set-variable] > drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:352:25: > warning: variable 'link' set but not used [-Wunused-but-set-variable] > drivers/net/wireless/legacy/ray_cs.c:628:17: warning: 'strncpy' specified > bound 32 equals destination size [-Wstringop-truncation] > gpio.c:(.init.text+0xec): undefined reference to `of_mm_gpiochip_add_data' > include/linux/mmzone.h:1749:2: error: #error Allocator MAX_ORDER exceeds > SECTION_SIZE > > Unverified Error/Warning (likely false positive, please contact us if > interested): > > drivers/soc/fsl/qe/tsa.c:140:26: sparse: sparse: incorrect type in argument 2 > (different address spaces) > drivers/soc/fsl/qe/tsa.c:150:27: sparse: sparse: incorrect type in argument 1 > (different address spaces) > mm/mmap.c:962 vma_merge() error: uninitialized symbol 'next'. I hate to add noise, but just for completeness and clarity, this is an issue that was resolved in the patchset already whose fixes will be ported to -next on the next go around. https://lore.kernel.org/all/cover.1679516210.git.lstoa...@gmail.com has the latest version (v5), fix came in v3. > sound/soc/sof/ipc4-pcm.c:391 sof_ipc4_pcm_dai_link_fixup_rate() error: > uninitialized symbol 'be_rate'. > sound/soc/sof/ipc4-topology.c:1132 ipc4_copier_set_capture_fmt() error: > uninitialized symbol 'sample_valid_bits'. > > Error/Warning ids grouped by kconfigs: > > gcc_recent_errors > |-- alpha-allyesconfig > | `-- > drivers-net-wireless-legacy-ray_cs.c:warning:strncpy-specified-bound-equals-destination-size > |-- arm-allmodconfig > | |-- > drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used > | `-- > drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used > |-- i386-randconfig-m021 > | `-- mm-mmap.c-vma_merge()-error:uninitialized-symbol-next-. > |-- ia64-allmodconfig > | `-- > drivers-net-wireless-legacy-ray_cs.c:warning:strncpy-specified-bound-equals-destination-size > |-- loongarch-randconfig-r006-20230322 > | `-- > include-linux-mmzone.h:error:error-Allocator-MAX_ORDER-exceeds-SECTION_SIZE > |-- m68k-randconfig-s041-20230323 > | |-- > drivers-soc-fsl-qe-tsa.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-void-const-noderef-__iomem-got-void-noderef-__iomem-addr > | `-- > drivers-soc-fsl-qe-tsa.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-void-noderef-__iomem-got-void-noderef-__iomem-addr > |-- microblaze-buildonly-randconfig-r003-20230323 > | |-- > drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used > | `-- > drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used > |-- powerpc-allmodconfig > | |-- > drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used > | `-- > drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used > |-- powerpc-randconfig-s041-20230322 > | `-- gpio.c:(.init.text):undefined-reference-to-of_mm_gpiochip_add_data > |-- s390-randconfig-m031-20230321 > | |-- > sound-soc-sof-ipc4-pcm.c-sof_ipc4_pcm_dai_link_fixup_rate()-error:uninitialized-symbol-be_rate-. > | `-- > sound-soc-sof-ipc4-topology.c-ipc4_copier_set_capture_fmt()-error:uninitialized-symbol-sample_valid_bits-. > `-- sparc-allyesconfig > `-- > drivers-net-wireless-legacy-ray_cs.c:warning:strncpy-specified-bound-equals-destination-size > > elapsed time: 1022m > > configs tested: 95 > configs skipped: 4 > > tested configs: > alphaallyesconfig gcc > alpha defconfig gcc > alpharandconfig-r026-20230322 gcc > arc allyesconfig gcc > arc
[PATCH 13/13] drm/amdgpu: add debugfs interface for reading MQDs
Provide a debugfs interface to access the MQD. Useful for
debugging issues with the CP and MES hardware scheduler.
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 60 +++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index dc474b809604..4da67faef668 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -478,6 +478,59 @@ static const struct file_operations
amdgpu_debugfs_ring_fops = {
.llseek = default_llseek
};
+static ssize_t amdgpu_debugfs_mqd_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_ring *ring = file_inode(f)->i_private;
+ volatile u32 *mqd;
+ int r;
+ uint32_t value, result;
+
+ if (*pos & 3 || size & 3)
+ return -EINVAL;
+
+ result = 0;
+
+ r = amdgpu_bo_reserve(ring->mqd_obj, false);
+ if (unlikely(r != 0))
+ return r;
+
+ r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&mqd);
+ if (r) {
+ amdgpu_bo_unreserve(ring->mqd_obj);
+ return r;
+ }
+
+ while (size) {
+ if (*pos >= ring->mqd_size)
+ return result;
+
+ value = mqd[*pos/4];
+ r = put_user(value, (uint32_t *)buf);
+ if (r)
+ goto done;
+ buf += 4;
+ result += 4;
+ size -= 4;
+ *pos += 4;
+ }
+
+done:
+ amdgpu_bo_kunmap(ring->mqd_obj);
+ mqd = NULL;
+ amdgpu_bo_unreserve(ring->mqd_obj);
+ if (r)
+ return r;
+
+ return result;
+}
+
+static const struct file_operations amdgpu_debugfs_mqd_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_mqd_read,
+ .llseek = default_llseek
+};
+
#endif
void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
@@ -492,7 +545,12 @@ void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, ring,
&amdgpu_debugfs_ring_fops,
ring->ring_size + 12);
-
+ if (ring->mqd_obj) {
+ sprintf(name, "amdgpu_mqd_%s", ring->name);
+ debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, ring,
+&amdgpu_debugfs_mqd_fops,
+ring->mqd_size);
+ }
#endif
}
--
2.39.2
[PATCH 12/13] drm/amdgpu: track MQD size for gfx and compute
It varies by generation and we need to know the size
to expose this via debugfs.
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index c50d59855011..5435f41a3b7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -404,6 +404,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
return r;
}
+ ring->mqd_size = mqd_size;
/* prepare MQD backup */
adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size,
GFP_KERNEL);
if (!adev->gfx.me.mqd_backup[i])
@@ -424,6 +425,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
return r;
}
+ ring->mqd_size = mqd_size;
/* prepare MQD backup */
adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size,
GFP_KERNEL);
if (!adev->gfx.mec.mqd_backup[i])
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7942cb62e52c..deb9f7bead02 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -257,6 +257,7 @@ struct amdgpu_ring {
struct amdgpu_bo*mqd_obj;
uint64_tmqd_gpu_addr;
void*mqd_ptr;
+ unsignedmqd_size;
uint64_teop_gpu_addr;
u32 doorbell_index;
booluse_doorbell;
--
2.39.2
[PATCH 11/13] drm/amdgpu: bump driver version number for CP GFX shadow
So UMDs can determine whether the kernel supports this. Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986 Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 917926c8dc5f..c35baee082e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -111,9 +111,10 @@ * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: *tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, *gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi + * 3.53.0 - Support for GFX11 CP GFX shadowing */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 52 +#define KMS_DRIVER_MINOR 53 #define KMS_DRIVER_PATCHLEVEL 0 unsigned int amdgpu_vram_limit = UINT_MAX; -- 2.39.2
[PATCH 10/13] drm/amdgpu: add support for new GFX shadow size query
Use the new callback to fetch the data. Return an error if
not supported. UMDs should use this query to check whether
shadow buffers are supported and if so what size they
should be.
v2: return an error rather than a zerod structure.
v3: drop GDS, move into dev_info structure. Data will be
0 if not supported.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 0efb38539d70..90738024cc1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -876,6 +876,20 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
dev_info->mall_size = adev->gmc.mall_size;
+
+ if (adev->gfx.funcs->get_gfx_shadow_info) {
+ struct amdgpu_gfx_shadow_info shadow_info;
+ int r;
+
+ r = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info);
+ if (!r) {
+ dev_info->shadow_size = shadow_info.shadow_size;
+ dev_info->shadow_alignment =
shadow_info.shadow_alignment;
+ dev_info->csa_size = shadow_info.csa_size;
+ dev_info->csa_alignment =
shadow_info.csa_alignment;
+ }
+ }
+
ret = copy_to_user(out, dev_info,
min((size_t)size, sizeof(*dev_info))) ?
-EFAULT : 0;
kfree(dev_info);
--
2.39.2
[PATCH 08/13] drm/amdgpu: add gfx shadow callback
To provide IP specific shadow sizes. UMDs will use
this to query the kernel driver for the size of the
shadow buffers.
v2: make callback return an int (Alex)
v3: drop GDS (Alex)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 4ad9e225d6e6..62047a541c21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -219,6 +219,13 @@ struct amdgpu_gfx_ras {
struct amdgpu_iv_entry *entry);
};
+struct amdgpu_gfx_shadow_info {
+ u32 shadow_size;
+ u32 shadow_alignment;
+ u32 csa_size;
+ u32 csa_alignment;
+};
+
struct amdgpu_gfx_funcs {
/* get the gpu clock counter */
uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
@@ -236,6 +243,8 @@ struct amdgpu_gfx_funcs {
u32 queue, u32 vmid);
void (*init_spm_golden)(struct amdgpu_device *adev);
void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
+ int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
+ struct amdgpu_gfx_shadow_info *shadow_info);
};
struct sq_work {
@@ -372,6 +381,7 @@ struct amdgpu_gfx {
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance)
(adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid)
(adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
#define amdgpu_gfx_init_spm_golden(adev)
(adev)->gfx.funcs->init_spm_golden((adev))
+#define amdgpu_gfx_get_gfx_shadow_info(adev, si)
(adev)->gfx.funcs->get_gfx_shadow_info((adev), (si))
/**
* amdgpu_gfx_create_bitmask - create a bitmask
--
2.39.2
[PATCH 02/13] drm/amdgpu/gfx11: check the CP FW version CP GFX shadow support
Only set the supported flag if we have new enough CP FW. XXX: don't commit this until the CP FW versions are finalized! Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index a0d830dc0d01..4a50d0fbcdcf 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -469,6 +469,15 @@ static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 3): + /* XXX fix me! */ + if ((adev->gfx.me_fw_version >= 1498) && + (adev->gfx.me_feature_version >= 29) && + (adev->gfx.pfp_fw_version >= 1541) && + (adev->gfx.pfp_feature_version >= 29) && + (adev->gfx.mec_fw_version >= 507) && + (adev->gfx.mec_feature_version >= 29)) + adev->gfx.cp_gfx_shadow = true; + break; default: adev->gfx.cp_gfx_shadow = false; break; -- 2.39.2
[PATCH 09/13] drm/amdgpu: add get_gfx_shadow_info callback for gfx11
Used to get the size and alignment requirements for
the gfx shadow buffer for preemption.
v2: use FW version check to determine whether to
return a valid size here
return an error if not supported (Alex)
v3: drop GDS (Alex)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 1fc1e941f7df..df2eabf50e6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -822,6 +822,30 @@ static void gfx_v11_0_select_me_pipe_q(struct
amdgpu_device *adev,
soc21_grbm_select(adev, me, pipe, q, vm);
}
+/* all sizes are in bytes */
+#define MQD_SHADOW_BASE_SIZE 73728
+#define MQD_SHADOW_BASE_ALIGNMENT 256
+#define MQD_FWWORKAREA_SIZE 484
+#define MQD_FWWORKAREA_ALIGNMENT 256
+
+static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,
+struct amdgpu_gfx_shadow_info
*shadow_info)
+{
+ if (shadow_info) {
+ if (adev->gfx.cp_gfx_shadow) {
+ shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
+ shadow_info->shadow_alignment =
MQD_SHADOW_BASE_ALIGNMENT;
+ shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
+ shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
+ return 0;
+ } else {
+ memset(shadow_info, 0, sizeof(struct
amdgpu_gfx_shadow_info));
+ return -ENOTSUPP;
+ }
+ }
+ return -EINVAL;
+}
+
static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter,
.select_se_sh = &gfx_v11_0_select_se_sh,
@@ -830,6 +854,7 @@ static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
.read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
.select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
.update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
+ .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info,
};
static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
--
2.39.2
[PATCH 06/13] drm/amdgpu: don't require a job for cond_exec and shadow
We need to reset the shadow state every time we submit an IB and there needs to be a COND_EXEC packet after the SET_Q_PREEMPTION_MODE packet for it to work properly, so we should emit both of these packets regardless of whether there is a job present or not. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 7fb8e6691d13..3b35e21eb934 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -223,11 +223,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, amdgpu_ring_ib_begin(ring); - if (job && ring->funcs->emit_gfx_shadow) + if (ring->funcs->emit_gfx_shadow) amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va, init_shadow, vmid); - if (job && ring->funcs->init_cond_exec) + if (ring->funcs->init_cond_exec) patch_offset = amdgpu_ring_init_cond_exec(ring); amdgpu_device_flush_hdp(adev, ring); -- 2.39.2
[PATCH 03/13] drm/amdgpu/UAPI: add new CS chunk for GFX shadow buffers
For GFX11, the UMD needs to allocate some shadow buffers
to be used for preemption. The UMD allocates the buffers
and passes the GPU virtual address to the kernel since the
kernel will program the packet that specified these
addresses as part of its IB submission frame.
v2: UMD passes shadow init to tell kernel when to initialize
the shadow
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index b6eb90df5d05..3d9474af6566 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -592,6 +592,7 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT0x08
#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
+#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
@@ -708,6 +709,15 @@ struct drm_amdgpu_cs_chunk_data {
};
};
+#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1
+
+struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
+ __u64 shadow_va;
+ __u64 csa_va;
+ __u64 gds_va;
+ __u64 flags;
+};
+
/*
* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
*
--
2.39.2
[PATCH 07/13] drm/amdgpu: add UAPI to query GFX shadow sizes
Add UAPI to query the GFX shadow buffer requirements
for preemption on GFX11. UMDs need to specify the shadow
areas for preemption.
v2: move into existing asic info query
drop GDS as its use is determined by the UMD (Marek)
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 3d9474af6566..3563c69521b0 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -1136,6 +1136,14 @@ struct drm_amdgpu_info_device {
__u64 mall_size;/* AKA infinity cache */
/* high 32 bits of the rb pipes mask */
__u32 enabled_rb_pipes_mask_hi;
+ /* shadow area size for gfx11 */
+ __u32 shadow_size;
+ /* shadow area alignment for gfx11 */
+ __u32 shadow_alignment;
+ /* context save area size for gfx11 */
+ __u32 csa_size;
+ /* context save area alignment for gfx11 */
+ __u32 csa_alignment;
};
struct drm_amdgpu_info_hw_ip {
--
2.39.2
[PATCH 04/13] drm/amdgpu: add gfx shadow CS IOCTL support
From: Christian König
Add support for submitting the shadow update packet
when submitting an IB. Needed for MCBP on GFX11.
v2: update API for CSA (Alex)
v3: fix ordering; SET_Q_PREEMPTION_MODE most come before COND_EXEC
Add missing check for AMDGPU_CHUNK_ID_CP_GFX_SHADOW in
amdgpu_cs_pass1()
Only initialize shadow on first use
(Alex)
v4: Pass parameters rather than job to new ring callback (Alex)
Signed-off-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 26
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 17 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +++
4 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 47763ac0d14a..41bd3a1a1989 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -281,6 +281,7 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
+ case AMDGPU_CHUNK_ID_CP_GFX_SHADOW:
break;
default:
@@ -583,6 +584,26 @@ static int amdgpu_cs_p2_syncobj_timeline_signal(struct
amdgpu_cs_parser *p,
return 0;
}
+static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p,
+ struct amdgpu_cs_chunk *chunk)
+{
+ struct drm_amdgpu_cs_chunk_cp_gfx_shadow *shadow = chunk->kdata;
+ int i;
+
+ if (shadow->flags & ~AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW)
+ return -EINVAL;
+
+ for (i = 0; i < p->gang_size; ++i) {
+ p->jobs[i]->shadow_va = shadow->shadow_va;
+ p->jobs[i]->csa_va = shadow->csa_va;
+ p->jobs[i]->gds_va = shadow->gds_va;
+ p->jobs[i]->init_shadow =
+ shadow->flags &
AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW;
+ }
+
+ return 0;
+}
+
static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p)
{
unsigned int ce_preempt = 0, de_preempt = 0;
@@ -625,6 +646,11 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p)
if (r)
return r;
break;
+ case AMDGPU_CHUNK_ID_CP_GFX_SHADOW:
+ r = amdgpu_cs_p2_shadow(p, chunk);
+ if (r)
+ return r;
+ break;
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index b348dbe2..7fb8e6691d13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -136,7 +136,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
uint64_t fence_ctx;
uint32_t status = 0, alloc_size;
unsigned fence_flags = 0;
- bool secure;
+ bool secure, init_shadow;
+ u64 shadow_va, csa_va, gds_va;
+ int vmid = AMDGPU_JOB_GET_VMID(job);
unsigned i;
int r = 0;
@@ -150,9 +152,17 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
vm = job->vm;
fence_ctx = job->base.s_fence ?
job->base.s_fence->scheduled.context : 0;
+ shadow_va = job->shadow_va;
+ csa_va = job->csa_va;
+ gds_va = job->gds_va;
+ init_shadow = job->init_shadow;
} else {
vm = NULL;
fence_ctx = 0;
+ shadow_va = 0;
+ csa_va = 0;
+ gds_va = 0;
+ init_shadow = false;
}
if (!ring->sched.ready && !ring->is_mes_queue) {
@@ -212,6 +222,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
}
amdgpu_ring_ib_begin(ring);
+
+ if (job && ring->funcs->emit_gfx_shadow)
+ amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va,
+ init_shadow, vmid);
+
if (job && ring->funcs->init_cond_exec)
patch_offset = amdgpu_ring_init_cond_exec(ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index 52f2e313ea17..3f9804f956c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -67,6 +67,12 @@ struct amdgpu_job {
uint64_tuf_addr;
uint64_tuf_sequence;
+ /* virtual addresses for shadow/GDS/CSA */
+ uint64_tshadow_va;
+ uint64_tcsa_va;
+ uint64_tgds_va;
+ bool
[PATCH 01/13] drm/amdgpu/gfx11: add FW version check for new CP GFX shadow feature
Use this to determine if we support the new SET_Q_PREEMPTION_MODE
packet.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 13 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index de9e7a00bb15..4ad9e225d6e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -364,6 +364,8 @@ struct amdgpu_gfx {
struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
struct amdgpu_ring_mux muxer;
+
+ boolcp_gfx_shadow; /* for gfx11 */
};
#define amdgpu_gfx_get_gpu_clock_counter(adev)
(adev)->gfx.funcs->get_gpu_clock_counter((adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index ecf8ceb53311..a0d830dc0d01 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -463,6 +463,18 @@ static int gfx_v11_0_init_toc_microcode(struct
amdgpu_device *adev, const char *
return err;
}
+static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 2):
+ case IP_VERSION(11, 0, 3):
+ default:
+ adev->gfx.cp_gfx_shadow = false;
+ break;
+ }
+}
+
static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
{
char fw_name[40];
@@ -539,6 +551,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device
*adev)
/* only one MEC for gfx 11.0.0. */
adev->gfx.mec2_fw = NULL;
+ gfx_v11_0_check_fw_cp_gfx_shadow(adev);
out:
if (err) {
amdgpu_ucode_release(&adev->gfx.pfp_fw);
--
2.39.2
[PATCH 05/13] drm/amdgpu: add gfx11 emit shadow callback
From: Christian König
Add ring callback for gfx to update the CP firmware
with the new shadow information before we process the
IB.
v2: add implementation for new packet (Alex)
v3: add current FW version checks (Alex)
v4: only initialize shadow on first use
Only set IB_VMID when a valid shadow buffer is present
(Alex)
v5: Pass parameters rather than job to new ring callback (Alex)
Signed-off-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 25 +
drivers/gpu/drm/amd/amdgpu/nvd.h | 5 -
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 4a50d0fbcdcf..1fc1e941f7df 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5598,6 +5598,29 @@ static void gfx_v11_0_ring_emit_cntxcntl(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, 0);
}
+static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring,
+ u64 shadow_va, u64 csa_va,
+ u64 gds_va, bool init_shadow,
+ int vmid)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (!adev->gfx.cp_gfx_shadow)
+ return;
+
+ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7));
+ amdgpu_ring_write(ring, lower_32_bits(shadow_va));
+ amdgpu_ring_write(ring, upper_32_bits(shadow_va));
+ amdgpu_ring_write(ring, lower_32_bits(gds_va));
+ amdgpu_ring_write(ring, upper_32_bits(gds_va));
+ amdgpu_ring_write(ring, lower_32_bits(csa_va));
+ amdgpu_ring_write(ring, upper_32_bits(csa_va));
+ amdgpu_ring_write(ring, shadow_va ?
+ PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid): 0);
+ amdgpu_ring_write(ring, init_shadow ?
+ PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0);
+}
+
static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
{
unsigned ret;
@@ -6219,6 +6242,7 @@ static const struct amdgpu_ring_funcs
gfx_v11_0_ring_funcs_gfx = {
.set_wptr = gfx_v11_0_ring_set_wptr_gfx,
.emit_frame_size = /* totally 242 maximum if 16 IBs */
5 + /* COND_EXEC */
+ 9 + /* SET_Q_PREEMPTION_MODE */
7 + /* PIPELINE_SYNC */
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
@@ -6245,6 +6269,7 @@ static const struct amdgpu_ring_funcs
gfx_v11_0_ring_funcs_gfx = {
.insert_nop = amdgpu_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
.emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,
+ .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow,
.init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec,
.patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec,
.preempt_ib = gfx_v11_0_ring_preempt_ib,
diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h b/drivers/gpu/drm/amd/amdgpu/nvd.h
index fd6b58243b03..631dafb92299 100644
--- a/drivers/gpu/drm/amd/amdgpu/nvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/nvd.h
@@ -462,6 +462,9 @@
# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25)
#definePACKET3_RUN_LIST0xA5
#definePACKET3_MAP_PROCESS_VM 0xA6
-
+/* GFX11 */
+#definePACKET3_SET_Q_PREEMPTION_MODE 0xF0
+# define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x) ((x) << 0)
+# define PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM(1 << 0)
#endif
--
2.39.2
[PATCH V3 00/13] Enable FW assisted shadowing for GFX11
This patch set allows for FW assisted shadowing on supported platforms. A new enough CP FW is required. This feature is required for mid command buffer preemption and proper SR-IOV support. This also simplifies the UMDs by allowing persistent hardware state when the command submission executes. UMDs that use this will have their state retained across command submissions. The mesa MR to implement the user mode side of this is: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986 v2: Integrate feedback from V1. UMDs now need to specify init_shadow on first use. v3: Integrate feedback from V2. Drop GDS query, move query into dev info. Add MQD dumping for debug. Alex Deucher (11): drm/amdgpu/gfx11: add FW version check for new CP GFX shadow feature drm/amdgpu/gfx11: check the CP FW version CP GFX shadow support drm/amdgpu/UAPI: add new CS chunk for GFX shadow buffers drm/amdgpu: don't require a job for cond_exec and shadow drm/amdgpu: add UAPI to query GFX shadow sizes drm/amdgpu: add gfx shadow callback drm/amdgpu: add get_gfx_shadow_info callback for gfx11 drm/amdgpu: add support for new GFX shadow size query drm/amdgpu: bump driver version number for CP GFX shadow drm/amdgpu: track MQD size for gfx and compute drm/amdgpu: add debugfs interface for reading MQDs Christian König (2): drm/amdgpu: add gfx shadow CS IOCTL support drm/amdgpu: add gfx11 emit shadow callback drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 26 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 12 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 19 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 6 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 + drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 60 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 72 drivers/gpu/drm/amd/amdgpu/nvd.h | 5 +- include/uapi/drm/amdgpu_drm.h| 18 ++ 12 files changed, 236 insertions(+), 5 deletions(-) -- 2.39.2
[linux-next:master] BUILD REGRESSION 7c4a254d78f89546d0e74a40617ef24c6151c8d1
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 7c4a254d78f89546d0e74a40617ef24c6151c8d1 Add linux-next specific files for 20230323 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202303161521.jbgbafjj-...@intel.com https://lore.kernel.org/oe-kbuild-all/202303231302.iy6qifxa-...@intel.com https://lore.kernel.org/oe-kbuild-all/202303232154.axoxawhg-...@intel.com Error/Warning: (recently discovered and may have been fixed) drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:351:13: warning: variable 'bw_needed' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:352:25: warning: variable 'link' set but not used [-Wunused-but-set-variable] drivers/net/wireless/legacy/ray_cs.c:628:17: warning: 'strncpy' specified bound 32 equals destination size [-Wstringop-truncation] gpio.c:(.init.text+0xec): undefined reference to `of_mm_gpiochip_add_data' include/linux/mmzone.h:1749:2: error: #error Allocator MAX_ORDER exceeds SECTION_SIZE Unverified Error/Warning (likely false positive, please contact us if interested): drivers/soc/fsl/qe/tsa.c:140:26: sparse: sparse: incorrect type in argument 2 (different address spaces) drivers/soc/fsl/qe/tsa.c:150:27: sparse: sparse: incorrect type in argument 1 (different address spaces) mm/mmap.c:962 vma_merge() error: uninitialized symbol 'next'. sound/soc/sof/ipc4-pcm.c:391 sof_ipc4_pcm_dai_link_fixup_rate() error: uninitialized symbol 'be_rate'. sound/soc/sof/ipc4-topology.c:1132 ipc4_copier_set_capture_fmt() error: uninitialized symbol 'sample_valid_bits'. Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | `-- drivers-net-wireless-legacy-ray_cs.c:warning:strncpy-specified-bound-equals-destination-size |-- arm-allmodconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- i386-randconfig-m021 | `-- mm-mmap.c-vma_merge()-error:uninitialized-symbol-next-. |-- ia64-allmodconfig | `-- drivers-net-wireless-legacy-ray_cs.c:warning:strncpy-specified-bound-equals-destination-size |-- loongarch-randconfig-r006-20230322 | `-- include-linux-mmzone.h:error:error-Allocator-MAX_ORDER-exceeds-SECTION_SIZE |-- m68k-randconfig-s041-20230323 | |-- drivers-soc-fsl-qe-tsa.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-void-const-noderef-__iomem-got-void-noderef-__iomem-addr | `-- drivers-soc-fsl-qe-tsa.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-void-noderef-__iomem-got-void-noderef-__iomem-addr |-- microblaze-buildonly-randconfig-r003-20230323 | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- powerpc-allmodconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- powerpc-randconfig-s041-20230322 | `-- gpio.c:(.init.text):undefined-reference-to-of_mm_gpiochip_add_data |-- s390-randconfig-m031-20230321 | |-- sound-soc-sof-ipc4-pcm.c-sof_ipc4_pcm_dai_link_fixup_rate()-error:uninitialized-symbol-be_rate-. | `-- sound-soc-sof-ipc4-topology.c-ipc4_copier_set_capture_fmt()-error:uninitialized-symbol-sample_valid_bits-. `-- sparc-allyesconfig `-- drivers-net-wireless-legacy-ray_cs.c:warning:strncpy-specified-bound-equals-destination-size elapsed time: 1022m configs tested: 95 configs skipped: 4 tested configs: alphaallyesconfig gcc alpha defconfig gcc alpharandconfig-r026-20230322 gcc arc allyesconfig gcc arc defconfig gcc arc randconfig-r033-20230322 gcc arc randconfig-r043-20230322 gcc arm allmodconfig gcc arm allyesconfig gcc arm defconfig gcc arm randconfig-r023-20230322 clang arm randconfig-r046-20230322 clang arm vf610m4_defconfig gcc arm64allyesconfig gcc arm64 defconfig gcc cskydefconfig gcc hexagon randconfig-r041-20230322 clang hexagon randconfig-r045-20230322 clang i386 allyesconfig
Re: [PATCH 03/32] drm/amdkfd: prepare per-process debug enable and disable
Sorry, I think that was just a stray comment that I messed up while editing my response. You can ignore it. Regards, Felix Am 2023-03-23 um 15:12 schrieb Kim, Jonathan: index c06ada0844ba..a2ac98d06e71 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -979,6 +979,14 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm, goto out; pdd = qpd_to_pdd(qpd); + + /* The debugger creates processes that temporarily have not acquired +* all VMs for all devices and has no VMs itself. +* Skip queue eviction on process eviction. +*/ + if (!pdd->drm_priv) + goto out; + This should be before qpd-> Sorry I didn't quite catch what you were saying here (did your comment get cutoff?). Did you mean the pdd->drm_priv check needs to go before the if (qpd->evicted++ > 0) /* already evicted, do nothing */ check? Thanks, Jon
RE: [PATCH 19/32] drm/amdkfd: add runtime enable operation
[AMD Official Use Only - General]
> -Original Message-
> From: Kuehling, Felix
> Sent: Monday, March 20, 2023 8:31 PM
> To: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: Re: [PATCH 19/32] drm/amdkfd: add runtime enable operation
>
>
> On 2023-01-25 14:53, Jonathan Kim wrote:
> > The debugger can attach to a process prior to HSA enablement (i.e.
> > inferior is spawned by the debugger and attached to immediately before
> > target process has been enabled for HSA dispatches) or it
> > can attach to a running target that is already HSA enabled. Either
> > way, the debugger needs to know the enablement status to know when
> > it can inspect queues.
> >
> > For the scenario where the debugger spawns the target process,
> > it will have to wait for ROCr's runtime enable request from the target.
> > The runtime enable request will be able to see that its process has been
> > debug attached. ROCr raises an EC_PROCESS_RUNTIME signal to the
> > debugger then blocks the target process while waiting the debugger's
> > response. Once the debugger has received the runtime signal, it will
> > unblock the target process.
> >
> > For the scenario where the debugger attaches to a running target
> > process, ROCr will set the target process' runtime status as enabled so
> > that on an attach request, the debugger will be able to see this
> > status and will continue with debug enablement as normal.
> >
> > A secondary requirement is to conditionally enable the trap tempories
> only
> > if the user requests it (env var HSA_ENABLE_DEBUG=1) or if the debugger
> > attaches with HSA runtime enabled. This is because setting up the trap
> > temporaries incurs a performance overhead that is unacceptable for
> > microbench performance in normal mode for certain customers.
> >
> > In the scenario where the debugger spawns the target process, when ROCr
> > detects that the debugger has attached during the runtime enable
> > request, it will enable the trap temporaries before it blocks the target
> > process while waiting for the debugger to respond.
> >
> > In the scenario where the debugger attaches to a running target process,
> > it will enable to trap temporaries itself.
> >
> > Finally, there is an additional restriction that is required to be
> > enforced with runtime enable and HW debug mode setting. The debugger
> must
> > first ensure that HW debug mode has been enabled before permitting HW
> debug
> > mode operations.
> >
> > With single process debug devices, allowing the debugger to set debug
> > HW modes prior to trap activation means that debug HW mode setting can
> > occur before the KFD has reserved the debug VMID (0xf) from the hardware
> > scheduler's VMID allocation resource pool. This can result in the
> > hardware scheduler assigning VMID 0xf to a non-debugged process and
> > having that process inherit debug HW mode settings intended for the
> > debugged target process instead, which is both incorrect and potentially
> > fatal for normal mode operation.
> >
> > With multi process debug devices, allowing the debugger to set debug
> > HW modes prior to trap activation means that non-debugged processes
> > migrating to a new VMID could inherit unintended debug settings.
> >
> > All debug operations that touch HW settings must require trap activation
> > where trap activation is triggered by both debug attach and runtime
> > enablement (target has KFD opened and is ready to dispatch work).
> >
> > v2: fix up hierarchy of semantics in description.
> >
> > Signed-off-by: Jonathan Kim
> > ---
> > drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 150
> ++-
> > drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 6 +-
> > drivers/gpu/drm/amd/amdkfd/kfd_debug.h | 4 +
> > drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 1 +
> > 4 files changed, 157 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > index 09fe8576dc8c..46f9d453dc5e 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > @@ -2654,11 +2654,147 @@ static int kfd_ioctl_criu(struct file *filep,
> struct kfd_process *p, void *data)
> > return ret;
> > }
> >
> > -static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process
> > *p,
> void *data)
> > +static int runtime_enable(struct kfd_process *p, uint64_t r_debug,
> > + bool enable_ttmp_setup)
> > {
> > + int i = 0, ret = 0;
> > +
> > + if (p->is_runtime_retry)
> > + goto retry;
> > +
> > + if (p->runtime_info.runtime_state !=
> DEBUG_RUNTIME_STATE_DISABLED)
> > + return -EBUSY;
> > +
> > + for (i = 0; i < p->n_pdds; i++) {
> > + struct kfd_process_device *pdd = p->pdds[i];
> > +
> > + if (pdd->qpd.queue_count)
> > + return -EEXIST;
> > + }
> > +
> > + p->runtime_info.runtime_state =
>
RE: [PATCH] drm/display: Add missing OLED Vesa brightnesses definitions
[AMD Official Use Only - General] Hello Rodrigo and Harry, I would like to propose some changes to keep this patch consistent with the naming scheme and general organization of the drm_dp.h file. #define DP_EDP_OLED_VESA_BRIGHTNESS_ON 0x80 It would be better to use the (1<<7) representation for this bit to follow the pattern established by the other defines in the file. Also, a more generic name for this macro would be DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE. # define DP_EDP_OLED_VESA_CAP (1 << 4) A more generic name for this macro would be DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE In terms of the file structure, DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE should appear underneath the definition of DP_EDP_BACKLIGHT_MODE_SET_REGISTER. Similarly, DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE should appear underneath the definition of DP_EDP_GENERAL_CAP_2 For a complete definition of the millinit based brightness control specification the following should also be added: #define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734 Here is a suggested pseudo-patch with all these changes: #define DP_EDP_GENERAL_CAP_2 0x703 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) +# define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE (1<<7) # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ +# define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE (1<<7) #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 +#define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734 Thank you, Felipe -Original Message- From: Wentland, Harry Sent: Wednesday, March 22, 2023 2:01 PM To: Siqueira, Rodrigo ; airl...@gmail.com; dan...@ffwll.ch Cc: amd-gfx@lists.freedesktop.org; Koo, Anthony ; Nagulendran, Iswara ; Clark, Felipe ; dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org Subject: Re: [PATCH] drm/display: Add missing OLED Vesa brightnesses definitions On 3/22/23 12:05, Rodrigo Siqueira wrote: > Cc: Anthony Koo > Cc: Iswara Negulendran > Cc: Felipe Clark > Cc: Harry Wentland > Signed-off-by: Rodrigo Siqueira Reviewed-by: Harry Wentland Harry > --- > include/drm/display/drm_dp.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/drm/display/drm_dp.h > b/include/drm/display/drm_dp.h index 632376c291db..d30a9b2f450c 100644 > --- a/include/drm/display/drm_dp.h > +++ b/include/drm/display/drm_dp.h > @@ -977,6 +977,8 @@ > # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) > # define DP_EDP_DYNAMIC_BACKLIGHT_CAP(1 << 6) > # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) > +#define DP_EDP_OLED_VESA_BRIGHTNESS_ON 0x80 > +# define DP_EDP_OLED_VESA_CAP(1 << 4) > > #define DP_EDP_GENERAL_CAP_2 0x703 > # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
RE: [PATCH 03/32] drm/amdkfd: prepare per-process debug enable and disable
[Public]
> -Original Message-
> From: Kuehling, Felix
> Sent: Thursday, February 16, 2023 6:44 PM
> To: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: Re: [PATCH 03/32] drm/amdkfd: prepare per-process debug enable
> and disable
>
>
> On 2023-01-25 14:53, Jonathan Kim wrote:
> > The ROCm debugger will attach to a process to debug by PTRACE and will
> > expect the KFD to prepare a process for the target PID, whether the
> > target PID has opened the KFD device or not.
> >
> > This patch is to explicity handle this requirement. Further HW mode
> > setting and runtime coordination requirements will be handled in
> > following patches.
> >
> > In the case where the target process has not opened the KFD device,
> > a new KFD process must be created for the target PID.
> > The debugger as well as the target process for this case will have not
> > acquired any VMs so handle process restoration to correctly account for
> > this.
> >
> > To coordinate with HSA runtime, the debugger must be aware of the target
> > process' runtime enablement status and will copy the runtime status
> > information into the debugged KFD process for later query.
> >
> > On enablement, the debugger will subscribe to a set of exceptions where
> > each exception events will notify the debugger through a pollable FIFO
> > file descriptor that the debugger provides to the KFD to manage.
> > Some events will be synchronously raised while other are scheduled,
> > which is why a debug_event_workarea worker is initialized.
> >
> > Finally on process termination of either the debugger or the target,
> > debugging must be disabled if it has not been done so.
> >
> > v3: fix typo on debug trap disable and PTRACE ATTACH relax check.
> > remove unnecessary queue eviction counter reset when there's nothing
> > to evict.
> > change err code to EALREADY if attaching to an already attached process.
> > move debug disable to release worker to avoid race with disable from
> > ioctl call.
> >
> > v2: relax debug trap disable and PTRACE ATTACH requirement.
> >
> > Signed-off-by: Jonathan Kim
> > ---
> > drivers/gpu/drm/amd/amdkfd/Makefile | 3 +-
> > drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 88 -
> > drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 94
> +++
> > drivers/gpu/drm/amd/amdkfd/kfd_debug.h| 33 +++
> > .../drm/amd/amdkfd/kfd_device_queue_manager.c | 22 -
> > drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 34 ++-
> > drivers/gpu/drm/amd/amdkfd/kfd_process.c | 63 +
> > 7 files changed, 308 insertions(+), 29 deletions(-)
> > create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> > create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_debug.h
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile
> b/drivers/gpu/drm/amd/amdkfd/Makefile
> > index e758c2a24cd0..747754428073 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/Makefile
> > +++ b/drivers/gpu/drm/amd/amdkfd/Makefile
> > @@ -55,7 +55,8 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \
> > $(AMDKFD_PATH)/kfd_int_process_v9.o \
> > $(AMDKFD_PATH)/kfd_int_process_v11.o \
> > $(AMDKFD_PATH)/kfd_smi_events.o \
> > - $(AMDKFD_PATH)/kfd_crat.o
> > + $(AMDKFD_PATH)/kfd_crat.o \
> > + $(AMDKFD_PATH)/kfd_debug.o
> >
> > ifneq ($(CONFIG_AMD_IOMMU_V2),)
> > AMDKFD_FILES += $(AMDKFD_PATH)/kfd_iommu.o
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > index d3b019e64093..ee05c2e54ef6 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > @@ -44,6 +44,7 @@
> > #include "amdgpu_amdkfd.h"
> > #include "kfd_smi_events.h"
> > #include "amdgpu_dma_buf.h"
> > +#include "kfd_debug.h"
> >
> > static long kfd_ioctl(struct file *, unsigned int, unsigned long);
> > static int kfd_open(struct inode *, struct file *);
> > @@ -142,10 +143,15 @@ static int kfd_open(struct inode *inode, struct
> file *filep)
> > return -EPERM;
> > }
> >
> > - process = kfd_create_process(filep);
> > + process = kfd_create_process(current);
> > if (IS_ERR(process))
> > return PTR_ERR(process);
> >
> > + if (kfd_process_init_cwsr_apu(process, filep)) {
> > + kfd_unref_process(process);
> > + return -EFAULT;
> > + }
> > +
> > if (kfd_is_locked()) {
> > dev_dbg(kfd_device, "kfd is locked!\n"
> > "process %d unreferenced", process->pasid);
> > @@ -2653,6 +2659,9 @@ static int kfd_ioctl_runtime_enable(struct file
> *filep, struct kfd_process *p, v
> > static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process
> *p, void *data)
> > {
> > struct kfd_ioctl_dbg_trap_args *args = data;
> > + struct task_struct *thread = NULL;
> > + struct pid *pid = NULL;
> > + struct kfd
Re: BUG: KASAN: slab-use-after-free in drm_sched_get_cleanup_job+0x47b/0x5c0 [gpu_sched]
On Tue, Mar 21, 2023 at 11:47 PM Christian König wrote: > > Hi Mikhail, > > That looks like a reference counting issue to me. > > I'm going to take a look, but we have already fixed one of those recently. > > Probably best that you try this on drm-fixes, just to double check that > this isn't the same issue. > Hi Christian, you meant this branch? $ git clone -b drm-fixes git://anongit.freedesktop.org/drm/drm linux-drm If yes I just checked and unfortunately see this issue unfixed there. [ 1984.295833] == [ 1984.295876] BUG: KASAN: slab-use-after-free in drm_sched_get_cleanup_job+0x47b/0x5c0 [gpu_sched] [ 1984.295898] Read of size 8 at addr 88814cadc4c0 by task sdma1/764 [ 1984.295924] CPU: 12 PID: 764 Comm: sdma1 Tainted: GWL 6.3.0-rc3-drm-fixes+ #1 [ 1984.295937] Hardware name: System manufacturer System Product Name/ROG STRIX X570-I GAMING, BIOS 4601 02/02/2023 [ 1984.295951] Call Trace: [ 1984.295963] [ 1984.295975] dump_stack_lvl+0x72/0xc0 [ 1984.295991] print_report+0xcf/0x670 [ 1984.296007] ? drm_sched_get_cleanup_job+0x47b/0x5c0 [gpu_sched] [ 1984.296030] ? drm_sched_get_cleanup_job+0x47b/0x5c0 [gpu_sched] [ 1984.296047] kasan_report+0xa4/0xe0 [ 1984.296118] ? drm_sched_get_cleanup_job+0x47b/0x5c0 [gpu_sched] [ 1984.296149] drm_sched_get_cleanup_job+0x47b/0x5c0 [gpu_sched] [ 1984.296175] drm_sched_main+0x643/0x990 [gpu_sched] [ 1984.296204] ? __pfx_drm_sched_main+0x10/0x10 [gpu_sched] [ 1984.296222] ? __pfx_autoremove_wake_function+0x10/0x10 [ 1984.296290] ? __kthread_parkme+0xc1/0x1f0 [ 1984.296304] ? __pfx_drm_sched_main+0x10/0x10 [gpu_sched] [ 1984.296321] kthread+0x29e/0x340 [ 1984.296334] ? __pfx_kthread+0x10/0x10 [ 1984.296501] ret_from_fork+0x2c/0x50 [ 1984.296518] [ 1984.296539] Allocated by task 12194: [ 1984.296552] kasan_save_stack+0x2f/0x50 [ 1984.296566] kasan_set_track+0x21/0x30 [ 1984.296578] __kasan_kmalloc+0x8b/0x90 [ 1984.296590] amdgpu_driver_open_kms+0x10b/0x5a0 [amdgpu] [ 1984.297051] drm_file_alloc+0x46e/0x880 [ 1984.297064] drm_open_helper+0x161/0x460 [ 1984.297076] drm_open+0x1e7/0x5c0 [ 1984.297089] drm_stub_open+0x24d/0x400 [ 1984.297107] chrdev_open+0x215/0x620 [ 1984.297125] do_dentry_open+0x5f1/0x1000 [ 1984.297146] path_openat+0x1b3d/0x28a0 [ 1984.297164] do_filp_open+0x1bd/0x400 [ 1984.297180] do_sys_openat2+0x140/0x420 [ 1984.297197] __x64_sys_openat+0x11f/0x1d0 [ 1984.297213] do_syscall_64+0x5b/0x80 [ 1984.297231] entry_SYSCALL_64_after_hwframe+0x72/0xdc [ 1984.297266] Freed by task 12195: [ 1984.297284] kasan_save_stack+0x2f/0x50 [ 1984.297303] kasan_set_track+0x21/0x30 [ 1984.297323] kasan_save_free_info+0x2a/0x50 [ 1984.297343] __kasan_slab_free+0x107/0x1a0 [ 1984.297361] slab_free_freelist_hook+0x11e/0x1d0 [ 1984.297373] __kmem_cache_free+0xbc/0x2e0 [ 1984.297385] amdgpu_driver_postclose_kms+0x582/0x8d0 [amdgpu] [ 1984.297821] drm_file_free.part.0+0x638/0xb70 [ 1984.297834] drm_release+0x1ea/0x470 [ 1984.297845] __fput+0x213/0x9e0 [ 1984.297857] task_work_run+0x11b/0x200 [ 1984.297869] exit_to_user_mode_prepare+0x23a/0x260 [ 1984.297883] syscall_exit_to_user_mode+0x16/0x50 [ 1984.297896] do_syscall_64+0x67/0x80 [ 1984.297907] entry_SYSCALL_64_after_hwframe+0x72/0xdc [ 1984.298033] Last potentially related work creation: [ 1984.298044] kasan_save_stack+0x2f/0x50 [ 1984.298057] __kasan_record_aux_stack+0x97/0xb0 [ 1984.298075] __call_rcu_common.constprop.0+0xf8/0x1af0 [ 1984.298095] amdgpu_bo_list_put+0x1a4/0x1f0 [amdgpu] [ 1984.298557] amdgpu_cs_parser_fini+0x293/0x5a0 [amdgpu] [ 1984.299055] amdgpu_cs_ioctl+0x4f2a/0x5630 [amdgpu] [ 1984.299624] drm_ioctl_kernel+0x1f8/0x3d0 [ 1984.299637] drm_ioctl+0x4c1/0xaa0 [ 1984.299649] amdgpu_drm_ioctl+0xce/0x1b0 [amdgpu] [ 1984.300083] __x64_sys_ioctl+0x12d/0x1a0 [ 1984.300097] do_syscall_64+0x5b/0x80 [ 1984.300109] entry_SYSCALL_64_after_hwframe+0x72/0xdc [ 1984.300135] Second to last potentially related work creation: [ 1984.300149] kasan_save_stack+0x2f/0x50 [ 1984.300167] __kasan_record_aux_stack+0x97/0xb0 [ 1984.300185] __call_rcu_common.constprop.0+0xf8/0x1af0 [ 1984.300203] amdgpu_bo_list_put+0x1a4/0x1f0 [amdgpu] [ 1984.300692] amdgpu_cs_parser_fini+0x293/0x5a0 [amdgpu] [ 1984.301133] amdgpu_cs_ioctl+0x4f2a/0x5630 [amdgpu] [ 1984.301577] drm_ioctl_kernel+0x1f8/0x3d0 [ 1984.301598] drm_ioctl+0x4c1/0xaa0 [ 1984.301610] amdgpu_drm_ioctl+0xce/0x1b0 [amdgpu] [ 1984.302043] __x64_sys_ioctl+0x12d/0x1a0 [ 1984.302056] do_syscall_64+0x5b/0x80 [ 1984.302068] entry_SYSCALL_64_after_hwframe+0x72/0xdc [ 1984.302090] The buggy address belongs to the object at 88814cadc000 which belongs to the cache kmalloc-4k of size 4096 [ 1984.302103] The buggy address is located 1216 bytes inside of freed 4096-byte region [88814cadc000, 88814cadd000) [ 1984.302129] The buggy address belongs to the physical page: [ 1984.302141] page:
Re: [v1,2/3] drm/amd/pm: send the SMT-enable message to pmfw
On 3/23/2023 12:41, Limonciello, Mario wrote:
On 3/22/2023 00:48, Wenyou Yang wrote:
When the CPU SMT status change in the fly, sent the SMT-enable
message to pmfw to notify it that the SMT status changed.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 +++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index b5d64749990e..5cd85a9d149d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -22,6 +22,7 @@
#define SWSMU_CODE_LAYER_L1
+#include
#include
#include
@@ -69,6 +70,14 @@ static int smu_set_fan_speed_rpm(void *handle,
uint32_t speed);
static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
static int smu_set_mp1_state(void *handle, enum pp_mp1_state
mp1_state);
+static int smt_notifier_callback(struct notifier_block *nb, unsigned
long action, void *data);
+
+extern struct raw_notifier_head smt_notifier_head;
+
+static struct notifier_block smt_notifier = {
+ .notifier_call = smt_notifier_callback,
+};
+
static int smu_sys_get_pp_feature_mask(void *handle,
char *buf)
{
@@ -625,6 +634,8 @@ static int smu_set_funcs(struct amdgpu_device *adev)
return 0;
}
+static struct smu_context *current_smu;
+
static int smu_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -645,6 +656,7 @@ static int smu_early_init(void *handle)
mutex_init(&smu->message_lock);
adev->powerplay.pp_handle = smu;
+ current_smu = smu;
Although this series is intended for the Van Gogh case right now, I
dont't think this would scale well for multiple GPUs in a system.
I think that instead you may want to move the notifier callback to be a
level "higher" in amdgpu. Perhaps amdgpu_device.c? Then when that
notifier call is received you'll want to walk through the PCI device
space to find any GPUs that are bound with AMDGPU a series of
wrappers/calls that end up calling smu_set_cpu_smt_enable with the
approriate arguments.
adev->powerplay.pp_funcs = &swsmu_pm_funcs;
r = smu_set_funcs(adev);
@@ -1105,6 +1117,8 @@ static int smu_sw_init(void *handle)
if (!smu->ppt_funcs->get_fan_control_mode)
smu->adev->pm.no_fan = true;
+ raw_notifier_chain_register(&smt_notifier_head, &smt_notifier);
+
return 0;
}
@@ -1122,6 +1136,8 @@ static int smu_sw_fini(void *handle)
smu_fini_microcode(smu);
+ raw_notifier_chain_unregister(&smt_notifier_head, &smt_notifier);
+
return 0;
}
@@ -3241,3 +3257,28 @@ int smu_send_hbm_bad_channel_flag(struct
smu_context *smu, uint32_t size)
return ret;
}
+
+static int smu_set_cpu_smt_enable(struct smu_context *smu, bool enable)
+{
+ int ret = -EINVAL;
+
+ if (smu->ppt_funcs && smu->ppt_funcs->set_cpu_smt_enable)
+ ret = smu->ppt_funcs->set_cpu_smt_enable(smu, enable);
+
+ return ret;
+}
+
+static int smt_notifier_callback(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct smu_context *smu = current_smu;
+ int ret = NOTIFY_OK;
This initialization is pointless, it's clobbered in the next line.
+
+ ret = (action == SMT_ENABLED) ?
+ smu_set_cpu_smt_enable(smu, true) :
+ smu_set_cpu_smt_enable(smu, false);
How about this instead, it should be more readable:
ret = smu_set_cpu_smt_enable(smu, action == SMT_ENABLED);
+ if (ret)
+ ret = NOTIFY_BAD;
+
+ return ret;
How about instead:
dev_dbg(adev->dev, "failed to %sable SMT: %d\n", action ==
SMT_ENABLED ? "en" : "dis", ret);
return ret ? NOTIFY_BAD : NOTIFY_OK;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 09469c750a96..7c6594bba796 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1354,6 +1354,11 @@ struct pptable_funcs {
* @init_pptable_microcode: Prepare the pptable microcode to
upload via PSP
*/
int (*init_pptable_microcode)(struct smu_context *smu);
+
+ /**
+ * @set_cpu_smt_enable: Set the CPU SMT status
+ */
+ int (*set_cpu_smt_enable)(struct smu_context *smu, bool enable);
};
typedef enum {
Re: [v1,2/3] drm/amd/pm: send the SMT-enable message to pmfw
On 3/22/2023 00:48, Wenyou Yang wrote:
When the CPU SMT status change in the fly, sent the SMT-enable
message to pmfw to notify it that the SMT status changed.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 +++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index b5d64749990e..5cd85a9d149d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -22,6 +22,7 @@
#define SWSMU_CODE_LAYER_L1
+#include
#include
#include
@@ -69,6 +70,14 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
+static int smt_notifier_callback(struct notifier_block *nb, unsigned long action, void *data);
+
+extern struct raw_notifier_head smt_notifier_head;
+
+static struct notifier_block smt_notifier = {
+ .notifier_call = smt_notifier_callback,
+};
+
static int smu_sys_get_pp_feature_mask(void *handle,
char *buf)
{
@@ -625,6 +634,8 @@ static int smu_set_funcs(struct amdgpu_device *adev)
return 0;
}
+static struct smu_context *current_smu;
+
static int smu_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -645,6 +656,7 @@ static int smu_early_init(void *handle)
mutex_init(&smu->message_lock);
adev->powerplay.pp_handle = smu;
+ current_smu = smu;
adev->powerplay.pp_funcs = &swsmu_pm_funcs;
r = smu_set_funcs(adev);
@@ -1105,6 +1117,8 @@ static int smu_sw_init(void *handle)
if (!smu->ppt_funcs->get_fan_control_mode)
smu->adev->pm.no_fan = true;
+ raw_notifier_chain_register(&smt_notifier_head, &smt_notifier);
+
return 0;
}
@@ -1122,6 +1136,8 @@ static int smu_sw_fini(void *handle)
smu_fini_microcode(smu);
+ raw_notifier_chain_unregister(&smt_notifier_head, &smt_notifier);
+
return 0;
}
@@ -3241,3 +3257,28 @@ int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
return ret;
}
+
+static int smu_set_cpu_smt_enable(struct smu_context *smu, bool enable)
+{
+ int ret = -EINVAL;
+
+ if (smu->ppt_funcs && smu->ppt_funcs->set_cpu_smt_enable)
+ ret = smu->ppt_funcs->set_cpu_smt_enable(smu, enable);
+
+ return ret;
+}
+
+static int smt_notifier_callback(struct notifier_block *nb,
+unsigned long action, void *data)
+{
+ struct smu_context *smu = current_smu;
+ int ret = NOTIFY_OK;
This initialization is pointless, it's clobbered in the next line.
+
+ ret = (action == SMT_ENABLED) ?
+ smu_set_cpu_smt_enable(smu, true) :
+ smu_set_cpu_smt_enable(smu, false);
How about this instead, it should be more readable:
ret = smu_set_cpu_smt_enable(smu, action == SMT_ENABLED);
+ if (ret)
+ ret = NOTIFY_BAD;
+
+ return ret;
How about instead:
dev_dbg(adev->dev, "failed to %sable SMT: %d\n", action == SMT_ENABLED
? "en" : "dis", ret);
return ret ? NOTIFY_BAD : NOTIFY_OK;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 09469c750a96..7c6594bba796 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1354,6 +1354,11 @@ struct pptable_funcs {
* @init_pptable_microcode: Prepare the pptable microcode to upload via
PSP
*/
int (*init_pptable_microcode)(struct smu_context *smu);
+
+ /**
+* @set_cpu_smt_enable: Set the CPU SMT status
+*/
+ int (*set_cpu_smt_enable)(struct smu_context *smu, bool enable);
};
typedef enum {
Re: [v1,3/3] drm/amd/pm: vangogh: support to send SMT enable message
On 3/22/2023 00:48, Wenyou Yang wrote:
Add the support to PPSMC_MSG_SetCClkSMTEnable(0x58) message to pmfw
for vangogh.
Signed-off-by: Wenyou Yang
---
.../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 3 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 19 +++
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
index 7471e2df2828..2b182dbc6f9c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
@@ -111,7 +111,8 @@
#define PPSMC_MSG_GetGfxOffStatus0x50
#define PPSMC_MSG_GetGfxOffEntryCount0x51
#define PPSMC_MSG_LogGfxOffResidency 0x52
-#define PPSMC_Message_Count0x53
+#define PPSMC_MSG_SetCClkSMTEnable0x58
+#define PPSMC_Message_Count0x54
This doesn't make sense that the PPSMC_Message_Count would be smaller
than the biggest message. This should be:
#define PPSMC_Message_Count 0x59
//Argument for PPSMC_MSG_GfxDeviceDriverReset
enum {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index 297b70b9388f..820812d910bf 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -245,7 +245,8 @@
__SMU_DUMMY_MAP(AllowGpo), \
__SMU_DUMMY_MAP(Mode2Reset),\
__SMU_DUMMY_MAP(RequestI2cTransaction), \
- __SMU_DUMMY_MAP(GetMetricsTable),
+ __SMU_DUMMY_MAP(GetMetricsTable), \
+ __SMU_DUMMY_MAP(SetCClkSMTEnable),
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 7433dcaa16e0..f0eeb42df96b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -141,6 +141,7 @@ static struct cmn2asic_msg_mapping
vangogh_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(GetGfxOffStatus,PPSMC_MSG_GetGfxOffStatus,
0),
MSG_MAP(GetGfxOffEntryCount,
PPSMC_MSG_GetGfxOffEntryCount, 0),
MSG_MAP(LogGfxOffResidency,
PPSMC_MSG_LogGfxOffResidency, 0),
+ MSG_MAP(SetCClkSMTEnable, PPSMC_MSG_SetCClkSMTEnable,
0),
};
static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
@@ -2428,6 +2429,23 @@ static u32 vangogh_get_gfxoff_entrycount(struct
smu_context *smu, uint64_t *entr
return ret;
}
+static int vangogh_set_cpu_smt_enable(struct smu_context *smu, bool enable)
+{
+ int ret = 0;
+
+ if (enable) {
+ ret = smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_SetCClkSMTEnable,
+ 1, NULL);
+ } else {
+ ret = smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_SetCClkSMTEnable,
+ 0, NULL);
+ }
+
+ return ret;
+}
+
static const struct pptable_funcs vangogh_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status,
@@ -2474,6 +2492,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
.get_power_limit = vangogh_get_power_limit,
.set_power_limit = vangogh_set_power_limit,
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
+ .set_cpu_smt_enable = vangogh_set_cpu_smt_enable,
};
void vangogh_set_ppt_funcs(struct smu_context *smu)
[pull] amdgpu drm-fixes-6.3
Hi Dave, Daniel, Fixes for 6.3. The following changes since commit e8d018dd0257f744ca50a729e3d042cf2ec9da65: Linux 6.3-rc3 (2023-03-19 13:27:55 -0700) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-6.3-2023-03-23 for you to fetch changes up to f9537b1fa7fb51c2162bc15ce469cbbf1ca0fbfe: drm/amd/display: Set dcn32 caps.seamless_odm (2023-03-23 09:39:34 -0400) amd-drm-fixes-6.3-2023-03-23: amdgpu: - S4 fix - Soft reset fixes - SR-IOV fix - Remove an out of date comment in the DC code - ASPM fix - DCN 3.2 fixes Alex Hung (1): drm/amd/display: remove outdated 8bpc comments Hersen Wu (2): drm/amd/display: fix wrong index used in dccg32_set_dpstreamclk drm/amd/display: Set dcn32 caps.seamless_odm Jane Jian (1): drm/amdgpu/gfx: set cg flags to enter/exit safe mode Kai-Heng Feng (1): drm/amdgpu/nv: Apply ASPM quirk on Intel ADL + AMD Navi Tim Huang (2): drm/amdgpu: reposition the gpu reset checking for reuse drm/amdgpu: skip ASIC reset for APUs when go to S4 Tong Liu01 (1): drm/amdgpu: add mes resume when do gfx post soft reset YuBiao Wang (1): drm/amdgpu: Force signal hw_fences that are embedded in non-sched jobs drivers/gpu/drm/amd/amdgpu/amdgpu.h| 5 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 41 -- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 5 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 9 + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 14 drivers/gpu/drm/amd/amdgpu/nv.c| 2 +- drivers/gpu/drm/amd/amdgpu/vi.c| 17 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 3 +- .../gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 + 11 files changed, 72 insertions(+), 41 deletions(-)
Re: [PATCH 15/32] drm/amdkfd: prepare trap workaround for gfx11
Am 2023-03-23 um 09:50 schrieb Kim, Jonathan:
[Public]
-Original Message-
From: Kuehling, Felix
Sent: Monday, March 20, 2023 5:50 PM
To: Kim, Jonathan ; amd-
g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Subject: Re: [PATCH 15/32] drm/amdkfd: prepare trap workaround for gfx11
On 2023-01-25 14:53, Jonathan Kim wrote:
Due to a HW bug, waves in only half the shader arrays can enter trap.
When starting a debug session, relocate all waves to the first shader
array of each shader engine and mask off the 2nd shader array as
unavailable.
When ending a debug session, re-enable the 2nd shader array per
shader engine.
User CU masking per queue cannot be guaranteed to remain functional
if requested during debugging (e.g. user cu mask requests only 2nd shader
array as an available resource leading to zero HW resources available)
nor can runtime be alerted of any of these changes during execution.
Make user CU masking and debugging mutual exclusive with respect to
availability.
If the debugger tries to attach to a process with a user cu masked
queue, return the runtime status as enabled but busy.
If the debugger tries to attach and fails to reallocate queue waves to
the first shader array of each shader engine, return the runtime status
as enabled but with an error.
In addition, like any other mutli-process debug supported devices,
disable trap temporary setup per-process to avoid performance impact
from
setup overhead.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 2 +
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 7 +-
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 -
drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 64
+++
drivers/gpu/drm/amd/amdkfd/kfd_debug.h| 3 +-
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 7 ++
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 3 +-
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 3 +-
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 42
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 +-
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 3 +-
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +-
.../amd/amdkfd/kfd_process_queue_manager.c| 9 ++-
13 files changed, 124 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index d20df0cf0d88..b5f5eed2b5ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -219,6 +219,8 @@ struct mes_add_queue_input {
uint32_tgws_size;
uint64_ttba_addr;
uint64_ttma_addr;
+ uint32_ttrap_en;
+ uint32_tskip_process_ctx_clear;
uint32_tis_kfd_process;
uint32_tis_aql_queue;
uint32_tqueue_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index fbacdc42efac..38c7a0cbf264 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -197,17 +197,14 @@ static int mes_v11_0_add_hw_queue(struct
amdgpu_mes *mes,
mes_add_queue_pkt.gws_size = input->gws_size;
mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
mes_add_queue_pkt.tma_addr = input->tma_addr;
+ mes_add_queue_pkt.trap_en = input->trap_en;
+ mes_add_queue_pkt.skip_process_ctx_clear = input-
skip_process_ctx_clear;
mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
/* For KFD, gds_size is re-used for queue size (needed in MES for AQL
queues) */
mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
mes_add_queue_pkt.gds_size = input->queue_size;
- if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >=
4) &&
- (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
&&
- (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3
- mes_add_queue_pkt.trap_en = 1;
-
/* For KFD, gds_size is re-used for queue size (needed in MES for AQL
queues) */
mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
mes_add_queue_pkt.gds_size = input->queue_size;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index ee05c2e54ef6..f5f639de28f0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -530,8 +530,6 @@ static int kfd_ioctl_set_cu_mask(struct file *filp,
struct kfd_process *p,
goto out;
}
- minfo.update_flag = UPDATE_FLAG_CU_MASK;
-
mutex_lock(&p->mutex);
retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index f6ea6db266b4..6e99a0160275 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -37,6 +37,70 @@ void debug_event_write_work_handler(struct
work_
RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
[AMD Official Use Only - General] Thanks a lot Luben!, much appreciate for your help! -Original Message- From: Tuikov, Luben Sent: Thursday, March 23, 2023 7:24 PM To: Koenig, Christian ; SHANMUGAM, SRINIVASAN ; Deucher, Alexander ; Limonciello, Mario ; Zhang, Hawking Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling On 2023-03-23 09:29, Christian König wrote: > Am 23.03.23 um 13:04 schrieb Srinivasan Shanmugam: >> CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o >> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with >> non-zero value always evaluates to true >> [-Werror,-Wtautological-bitwise-compare] >>if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) >>~^~ >> >> Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit >> was set if ras is enabled, so that's what I'm changing the code to. >> Hopefully to do the right thing. > > That looks like a nice catch to me, but I don't really know the ras > code that well. > > Hawking, Luben or whoever is more familiar with that should probably > comment as well. Thanks Christian--yeah, it looks like a typo. Fix is already committed into amd-staging-drm-next. -- Regards, Luben
Re: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
On 2023-03-23 09:29, Christian König wrote: > Am 23.03.23 um 13:04 schrieb Srinivasan Shanmugam: >> CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o >> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with >> non-zero value always evaluates to true >> [-Werror,-Wtautological-bitwise-compare] >>if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) >>~^~ >> >> Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF >> bit was set if ras is enabled, so that's what I'm changing the >> code to. Hopefully to do the right thing. > > That looks like a nice catch to me, but I don't really know the ras code > that well. > > Hawking, Luben or whoever is more familiar with that should probably > comment as well. Thanks Christian--yeah, it looks like a typo. Fix is already committed into amd-staging-drm-next. -- Regards, Luben
RE: [PATCH 15/32] drm/amdkfd: prepare trap workaround for gfx11
[Public]
> -Original Message-
> From: Kuehling, Felix
> Sent: Monday, March 20, 2023 5:50 PM
> To: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: Re: [PATCH 15/32] drm/amdkfd: prepare trap workaround for gfx11
>
>
> On 2023-01-25 14:53, Jonathan Kim wrote:
> > Due to a HW bug, waves in only half the shader arrays can enter trap.
> >
> > When starting a debug session, relocate all waves to the first shader
> > array of each shader engine and mask off the 2nd shader array as
> > unavailable.
> >
> > When ending a debug session, re-enable the 2nd shader array per
> > shader engine.
> >
> > User CU masking per queue cannot be guaranteed to remain functional
> > if requested during debugging (e.g. user cu mask requests only 2nd shader
> > array as an available resource leading to zero HW resources available)
> > nor can runtime be alerted of any of these changes during execution.
> >
> > Make user CU masking and debugging mutual exclusive with respect to
> > availability.
> >
> > If the debugger tries to attach to a process with a user cu masked
> > queue, return the runtime status as enabled but busy.
> >
> > If the debugger tries to attach and fails to reallocate queue waves to
> > the first shader array of each shader engine, return the runtime status
> > as enabled but with an error.
> >
> > In addition, like any other mutli-process debug supported devices,
> > disable trap temporary setup per-process to avoid performance impact
> from
> > setup overhead.
> >
> > Signed-off-by: Jonathan Kim
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 2 +
> > drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 7 +-
> > drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 -
> > drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 64
> +++
> > drivers/gpu/drm/amd/amdkfd/kfd_debug.h| 3 +-
> > .../drm/amd/amdkfd/kfd_device_queue_manager.c | 7 ++
> > .../gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 3 +-
> > .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 3 +-
> > .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 42
> > .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 +-
> > .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 3 +-
> > drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +-
> > .../amd/amdkfd/kfd_process_queue_manager.c| 9 ++-
> > 13 files changed, 124 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > index d20df0cf0d88..b5f5eed2b5ef 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > @@ -219,6 +219,8 @@ struct mes_add_queue_input {
> > uint32_tgws_size;
> > uint64_ttba_addr;
> > uint64_ttma_addr;
> > + uint32_ttrap_en;
> > + uint32_tskip_process_ctx_clear;
> > uint32_tis_kfd_process;
> > uint32_tis_aql_queue;
> > uint32_tqueue_size;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> > index fbacdc42efac..38c7a0cbf264 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> > @@ -197,17 +197,14 @@ static int mes_v11_0_add_hw_queue(struct
> amdgpu_mes *mes,
> > mes_add_queue_pkt.gws_size = input->gws_size;
> > mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
> > mes_add_queue_pkt.tma_addr = input->tma_addr;
> > + mes_add_queue_pkt.trap_en = input->trap_en;
> > + mes_add_queue_pkt.skip_process_ctx_clear = input-
> >skip_process_ctx_clear;
> > mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
> >
> > /* For KFD, gds_size is re-used for queue size (needed in MES for AQL
> queues) */
> > mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
> > mes_add_queue_pkt.gds_size = input->queue_size;
> >
> > - if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >=
> 4) &&
> > - (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
> &&
> > - (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3
> > - mes_add_queue_pkt.trap_en = 1;
> > -
> > /* For KFD, gds_size is re-used for queue size (needed in MES for AQL
> queues) */
> > mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
> > mes_add_queue_pkt.gds_size = input->queue_size;
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > index ee05c2e54ef6..f5f639de28f0 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > @@ -530,8 +530,6 @@ static int kfd_ioctl_set_cu_mask(struct file *filp,
> struct kfd_process *p,
> > goto out;
> > }
> >
> > - minfo.update_flag = UPDATE_FLAG_CU_MASK;
> > -
> > mutex_lock(&p->mutex);
> >
> > retval = pqm_update_mqd(&p->pqm, args->queue_id, &m
RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
[Public]
Thanks a lot Mario!, much appreciate for your help in reviewing!
Best Regards,
Srini
-Original Message-
From: Limonciello, Mario
Sent: Thursday, March 23, 2023 6:09 PM
To: SHANMUGAM, SRINIVASAN ; Koenig, Christian
; Deucher, Alexander ; Li,
Candice ; Zhang, Hawking
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
[Public]
> -Original Message-
> From: SHANMUGAM, SRINIVASAN
>
> Sent: Thursday, March 23, 2023 07:37
> To: Limonciello, Mario ; Koenig, Christian
> ; Deucher, Alexander
> ; Li, Candice ; Zhang,
> Hawking
> Cc: amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error
> handling
>
> [Public]
>
> Hi Mario,
>
> Thanks for your comments, it was on " origin/amd-staging-drm-next"
>
Oh, it's a newer change just landed that I needed to update my local tree,
thanks.
Fixes: 5778b47626b51 ("drm/amdgpu: Add fatal error handling in nbio v4_3")
Reviewed-by: Mario Limonciello
>
> Best Regards,
> Srini
> -Original Message-
> From: Limonciello, Mario
> Sent: Thursday, March 23, 2023 6:03 PM
> To: SHANMUGAM, SRINIVASAN ; Koenig,
> Christian ; Deucher, Alexander
> ; Li, Candice ; Zhang,
> Hawking
> Cc: amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error
> handling
>
> [Public]
>
>
>
> > -Original Message-
> > From: SHANMUGAM, SRINIVASAN
> >
> > Sent: Thursday, March 23, 2023 07:32
> > To: Koenig, Christian ; Deucher, Alexander
> > ; Limonciello, Mario
> > ; Li, Candice ;
> Zhang,
> > Hawking
> > Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN
> >
> > Subject: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error
> > handling
> >
> > CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or
> > with non-zero value always evaluates to true
> > [-Werror,-Wtautological-bitwise- compare]
> > if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF)
> > ~^~
> >
> > Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit
> was
> > set if ras is enabled, so that's what I'm changing the code to.
> > Hopefully to do the right thing.
> >
> > Cc: Christian König
> > Cc: Alex Deucher
> > Cc: Mario Limonciello
> > Cc: Hawking Zhang
> > Cc: Candice Li
> > Signed-off-by: Srinivasan Shanmugam
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > index 5b17790218811..fac45f98145d8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device
> *adev)
> > adev->nbio.ras = &nbio_v7_4_ras;
> > break;
> > case IP_VERSION(4, 3, 0):
> > - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF)
> > + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF)
> > /* unlike other generation of nbio ras,
> > * nbio v4_3 only support fatal error interrupt
> > * to inform software that DF is freezed due to
> > --
> > 2.25.1
>
> This change generally makes sense for what you showed above, but what
> tree is this against? That doesn't look like amd-staging-drm-next,
> Linus' tree or even some recent tags.
RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
[AMD Official Use Only - General] Thanks a lot Hawking!, much appreciate for your help in reviewing! Best Regards, Srini -Original Message- From: Zhang, Hawking Sent: Thursday, March 23, 2023 7:15 PM To: Koenig, Christian ; SHANMUGAM, SRINIVASAN ; Deucher, Alexander ; Limonciello, Mario ; Tuikov, Luben Cc: amd-gfx@lists.freedesktop.org Subject: RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling [AMD Official Use Only - General] Good catch. This is a typo The change is Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: Koenig, Christian Sent: Thursday, March 23, 2023 21:29 To: SHANMUGAM, SRINIVASAN ; Deucher, Alexander ; Limonciello, Mario ; Zhang, Hawking ; Tuikov, Luben Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling Am 23.03.23 um 13:04 schrieb Srinivasan Shanmugam: > CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with > non-zero value always evaluates to true > [-Werror,-Wtautological-bitwise-compare] >if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) >~^~ > > Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit was > set if ras is enabled, so that's what I'm changing the code to. > Hopefully to do the right thing. That looks like a nice catch to me, but I don't really know the ras code that well. Hawking, Luben or whoever is more familiar with that should probably comment as well. Christian. > > Cc: Christian König > Cc: Alex Deucher > Cc: Mario Limonciello > Signed-off-by: Srinivasan Shanmugam > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index 5b17790218811..fac45f98145d8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) > adev->nbio.ras = &nbio_v7_4_ras; > break; > case IP_VERSION(4, 3, 0): > - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) > + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF) > /* unlike other generation of nbio ras, >* nbio v4_3 only support fatal error interrupt >* to inform software that DF is freezed due to
RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
[AMD Official Use Only - General] Thanks a lot Christian!, much appreciate for your help! Best Regards, Srini -Original Message- From: Koenig, Christian Sent: Thursday, March 23, 2023 6:59 PM To: SHANMUGAM, SRINIVASAN ; Deucher, Alexander ; Limonciello, Mario ; Zhang, Hawking ; Tuikov, Luben Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling Am 23.03.23 um 13:04 schrieb Srinivasan Shanmugam: > CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with > non-zero value always evaluates to true > [-Werror,-Wtautological-bitwise-compare] >if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) >~^~ > > Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit was > set if ras is enabled, so that's what I'm changing the code to. > Hopefully to do the right thing. That looks like a nice catch to me, but I don't really know the ras code that well. Hawking, Luben or whoever is more familiar with that should probably comment as well. Christian. > > Cc: Christian König > Cc: Alex Deucher > Cc: Mario Limonciello > Signed-off-by: Srinivasan Shanmugam > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index 5b17790218811..fac45f98145d8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) > adev->nbio.ras = &nbio_v7_4_ras; > break; > case IP_VERSION(4, 3, 0): > - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) > + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF) > /* unlike other generation of nbio ras, >* nbio v4_3 only support fatal error interrupt >* to inform software that DF is freezed due to
RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
[AMD Official Use Only - General] Good catch. This is a typo The change is Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: Koenig, Christian Sent: Thursday, March 23, 2023 21:29 To: SHANMUGAM, SRINIVASAN ; Deucher, Alexander ; Limonciello, Mario ; Zhang, Hawking ; Tuikov, Luben Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling Am 23.03.23 um 13:04 schrieb Srinivasan Shanmugam: > CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with > non-zero value always evaluates to true > [-Werror,-Wtautological-bitwise-compare] >if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) >~^~ > > Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit was > set if ras is enabled, so that's what I'm changing the code to. > Hopefully to do the right thing. That looks like a nice catch to me, but I don't really know the ras code that well. Hawking, Luben or whoever is more familiar with that should probably comment as well. Christian. > > Cc: Christian König > Cc: Alex Deucher > Cc: Mario Limonciello > Signed-off-by: Srinivasan Shanmugam > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index 5b17790218811..fac45f98145d8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) > adev->nbio.ras = &nbio_v7_4_ras; > break; > case IP_VERSION(4, 3, 0): > - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) > + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF) > /* unlike other generation of nbio ras, >* nbio v4_3 only support fatal error interrupt >* to inform software that DF is freezed due to
Re: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
Am 23.03.23 um 13:04 schrieb Srinivasan Shanmugam: CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with non-zero value always evaluates to true [-Werror,-Wtautological-bitwise-compare] if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) ~^~ Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit was set if ras is enabled, so that's what I'm changing the code to. Hopefully to do the right thing. That looks like a nice catch to me, but I don't really know the ras code that well. Hawking, Luben or whoever is more familiar with that should probably comment as well. Christian. Cc: Christian König Cc: Alex Deucher Cc: Mario Limonciello Signed-off-by: Srinivasan Shanmugam --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 5b17790218811..fac45f98145d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) adev->nbio.ras = &nbio_v7_4_ras; break; case IP_VERSION(4, 3, 0): - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF) /* unlike other generation of nbio ras, * nbio v4_3 only support fatal error interrupt * to inform software that DF is freezed due to
Re: [PATCH 2/2] drm/amdgpu: Return from switch early for EEPROM I2C address
Series is:
Reviewed-by: Alex Deucher
On Thu, Mar 23, 2023 at 2:06 AM Luben Tuikov wrote:
>
> As soon as control->i2c_address is set, return; remove the "break;" from the
> switch--it is unnecessary. This mimics what happens when for some cases in the
> switch, we call helper functions with "return ".
>
> Remove final function "return true;" to indicate that the switch is final and
> terminal, and that there should be no code after the switch.
>
> Cc: Candice Li
> Cc: Kent Russell
> Cc: Alex Deucher
> Signed-off-by: Luben Tuikov
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index 5c21480fff9c8b..3106fa8a15efef 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -181,14 +181,14 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device
> *adev,
> switch (adev->asic_type) {
> case CHIP_VEGA20:
> control->i2c_address = EEPROM_I2C_MADDR_0;
> - break;
> + return true;
>
> case CHIP_ARCTURUS:
> return __get_eeprom_i2c_addr_arct(adev, control);
>
> case CHIP_SIENNA_CICHLID:
> control->i2c_address = EEPROM_I2C_MADDR_0;
> - break;
> + return true;
>
> case CHIP_ALDEBARAN:
> if (strnstr(atom_ctx->vbios_version, "D673",
> @@ -196,7 +196,7 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device
> *adev,
> control->i2c_address = EEPROM_I2C_MADDR_4;
> else
> control->i2c_address = EEPROM_I2C_MADDR_0;
> - break;
> + return true;
>
> case CHIP_IP_DISCOVERY:
> return __get_eeprom_i2c_addr_ip_discovery(adev, control);
> @@ -204,8 +204,6 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device
> *adev,
> default:
> return false;
> }
> -
> - return true;
> }
>
> static void
> --
> 2.40.0
>
2023 X.Org Board of Directors Elections timeline extended, request for nominations
We are seeking nominations for candidates for election to the X.org Foundation Board of Directors. However, as we presently do not have enough nominations to start the election - the decision has been made to extend the timeline by 2 weeks. Note this is a fairly regular part of the elections process. The new deadline for nominations to the X.org Board of Directors is 23:59 UTC on April 2nd, 2023. The new deadline for membership application or renewals is April 9th, 2023. Membership is required to vote on the elections. The Board consists of directors elected from the membership. Each year, an election is held to bring the total number of directors to eight. The four members receiving the highest vote totals will serve as directors for two year terms. The directors who received two year terms starting in 2022 were Emma Anholt, Mark Filion, Alyssa Rosenzweig and Ricardo Garcia. They will continue to serve until their term ends in 2024. Current directors whose term expires in 2023 are Samuel Iglesias Gonsálvez, Manasi D Navare, Lyude Paul and Daniel Vetter. A director is expected to participate in the fortnightly IRC meeting to discuss current business and to attend the annual meeting of the X.Org Foundation, which will be held at a location determined in advance by the Board of Directors. A member may nominate themselves or any other member they feel is qualified. Nominations should be sent to the Election Committee at electi...@x.org. Nominees shall be required to be current members of the X.Org Foundation, and submit a personal statement of up to 200 words that will be provided to prospective voters. The collected statements, along with the statement of contribution to the X.Org Foundation in the member's account page on http://members.x.org, will be made available to all voters to help them make their voting decisions. Nominations, membership applications or renewals and completed personal statements must be received no later than 23:59 UTC on April 2nd, 2023. The slate of candidates will be published April 10th 2023 and candidate Q&A will begin then. The deadline for Xorg membership applications and renewals is April 9th, 2023. Cheers, Ricardo Garcia, on behalf of the X.Org BoD
RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
[Public]
> -Original Message-
> From: SHANMUGAM, SRINIVASAN
>
> Sent: Thursday, March 23, 2023 07:37
> To: Limonciello, Mario ; Koenig, Christian
> ; Deucher, Alexander
> ; Li, Candice ;
> Zhang, Hawking
> Cc: amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
>
> [Public]
>
> Hi Mario,
>
> Thanks for your comments, it was on " origin/amd-staging-drm-next"
>
Oh, it's a newer change just landed that I needed to update my local tree,
thanks.
Fixes: 5778b47626b51 ("drm/amdgpu: Add fatal error handling in nbio v4_3")
Reviewed-by: Mario Limonciello
>
> Best Regards,
> Srini
> -Original Message-
> From: Limonciello, Mario
> Sent: Thursday, March 23, 2023 6:03 PM
> To: SHANMUGAM, SRINIVASAN ;
> Koenig, Christian ; Deucher, Alexander
> ; Li, Candice ;
> Zhang, Hawking
> Cc: amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
>
> [Public]
>
>
>
> > -Original Message-
> > From: SHANMUGAM, SRINIVASAN
> >
> > Sent: Thursday, March 23, 2023 07:32
> > To: Koenig, Christian ; Deucher, Alexander
> > ; Limonciello, Mario
> > ; Li, Candice ;
> Zhang,
> > Hawking
> > Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN
> >
> > Subject: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
> >
> > CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or
> > with non-zero value always evaluates to true
> > [-Werror,-Wtautological-bitwise- compare]
> > if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF)
> > ~^~
> >
> > Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit
> was
> > set if ras is enabled, so that's what I'm changing the code to.
> > Hopefully to do the right thing.
> >
> > Cc: Christian König
> > Cc: Alex Deucher
> > Cc: Mario Limonciello
> > Cc: Hawking Zhang
> > Cc: Candice Li
> > Signed-off-by: Srinivasan Shanmugam
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > index 5b17790218811..fac45f98145d8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device
> *adev)
> > adev->nbio.ras = &nbio_v7_4_ras;
> > break;
> > case IP_VERSION(4, 3, 0):
> > - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF)
> > + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF)
> > /* unlike other generation of nbio ras,
> > * nbio v4_3 only support fatal error interrupt
> > * to inform software that DF is freezed due to
> > --
> > 2.25.1
>
> This change generally makes sense for what you showed above, but what
> tree is this against? That doesn't look like amd-staging-drm-next, Linus'
> tree
> or even some recent tags.
RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
[Public] Hi Mario, Thanks for your comments, it was on " origin/amd-staging-drm-next" Best Regards, Srini -Original Message- From: Limonciello, Mario Sent: Thursday, March 23, 2023 6:03 PM To: SHANMUGAM, SRINIVASAN ; Koenig, Christian ; Deucher, Alexander ; Li, Candice ; Zhang, Hawking Cc: amd-gfx@lists.freedesktop.org Subject: RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling [Public] > -Original Message- > From: SHANMUGAM, SRINIVASAN > > Sent: Thursday, March 23, 2023 07:32 > To: Koenig, Christian ; Deucher, Alexander > ; Limonciello, Mario > ; Li, Candice ; Zhang, > Hawking > Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN > > Subject: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling > > CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or > with non-zero value always evaluates to true > [-Werror,-Wtautological-bitwise- compare] > if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) > ~^~ > > Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit was > set if ras is enabled, so that's what I'm changing the code to. > Hopefully to do the right thing. > > Cc: Christian König > Cc: Alex Deucher > Cc: Mario Limonciello > Cc: Hawking Zhang > Cc: Candice Li > Signed-off-by: Srinivasan Shanmugam > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index 5b17790218811..fac45f98145d8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) > adev->nbio.ras = &nbio_v7_4_ras; > break; > case IP_VERSION(4, 3, 0): > - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) > + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF) > /* unlike other generation of nbio ras, >* nbio v4_3 only support fatal error interrupt >* to inform software that DF is freezed due to > -- > 2.25.1 This change generally makes sense for what you showed above, but what tree is this against? That doesn't look like amd-staging-drm-next, Linus' tree or even some recent tags.
RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
[Public] > -Original Message- > From: SHANMUGAM, SRINIVASAN > > Sent: Thursday, March 23, 2023 07:32 > To: Koenig, Christian ; Deucher, Alexander > ; Limonciello, Mario > ; Li, Candice ; Zhang, > Hawking > Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN > > Subject: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling > > CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with > non-zero value always evaluates to true [-Werror,-Wtautological-bitwise- > compare] > if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) > ~^~ > > Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF > bit was set if ras is enabled, so that's what I'm changing the > code to. Hopefully to do the right thing. > > Cc: Christian König > Cc: Alex Deucher > Cc: Mario Limonciello > Cc: Hawking Zhang > Cc: Candice Li > Signed-off-by: Srinivasan Shanmugam > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index 5b17790218811..fac45f98145d8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) > adev->nbio.ras = &nbio_v7_4_ras; > break; > case IP_VERSION(4, 3, 0): > - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) > + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF) > /* unlike other generation of nbio ras, >* nbio v4_3 only support fatal error interrupt >* to inform software that DF is freezed due to > -- > 2.25.1 This change generally makes sense for what you showed above, but what tree is this against? That doesn't look like amd-staging-drm-next, Linus' tree or even some recent tags.
[PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with non-zero value always evaluates to true [-Werror,-Wtautological-bitwise-compare] if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) ~^~ Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit was set if ras is enabled, so that's what I'm changing the code to. Hopefully to do the right thing. Cc: Christian König Cc: Alex Deucher Cc: Mario Limonciello Cc: Hawking Zhang Cc: Candice Li Signed-off-by: Srinivasan Shanmugam --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 5b17790218811..fac45f98145d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) adev->nbio.ras = &nbio_v7_4_ras; break; case IP_VERSION(4, 3, 0): - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF) /* unlike other generation of nbio ras, * nbio v4_3 only support fatal error interrupt * to inform software that DF is freezed due to -- 2.25.1
[PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling
CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with non-zero value always evaluates to true [-Werror,-Wtautological-bitwise-compare] if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) ~^~ Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit was set if ras is enabled, so that's what I'm changing the code to. Hopefully to do the right thing. Cc: Christian König Cc: Alex Deucher Cc: Mario Limonciello Signed-off-by: Srinivasan Shanmugam --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 5b17790218811..fac45f98145d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) adev->nbio.ras = &nbio_v7_4_ras; break; case IP_VERSION(4, 3, 0): - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF) /* unlike other generation of nbio ras, * nbio v4_3 only support fatal error interrupt * to inform software that DF is freezed due to -- 2.25.1
Re: [Resend PATCH v1 2/3] drm/amd/pm: send the SMT-enable message to pmfw
On 3/23/2023 3:04 PM, Yang, WenYou wrote:
[AMD Official Use Only - General]
-Original Message-
From: Lazar, Lijo
Sent: Thursday, March 23, 2023 4:29 PM
To: Yang, WenYou ; Deucher, Alexander
; Koenig, Christian
; Pan, Xinhui
Cc: Yuan, Perry ; Li, Ying ; amd-
g...@lists.freedesktop.org; Liu, Kun ; Liang, Richard qi
Subject: Re: [Resend PATCH v1 2/3] drm/amd/pm: send the SMT-enable
message to pmfw
On 3/22/2023 2:46 PM, Wenyou Yang wrote:
When the CPU SMT status change in the fly, sent the SMT-enable message
to pmfw to notify it that the SMT status changed.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41
+++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index b5d64749990e..5cd85a9d149d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -22,6 +22,7 @@
#define SWSMU_CODE_LAYER_L1
+#include
#include
#include
@@ -69,6 +70,14 @@ static int smu_set_fan_speed_rpm(void *handle,
uint32_t speed);
static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
static int smu_set_mp1_state(void *handle, enum pp_mp1_state
mp1_state);
+static int smt_notifier_callback(struct notifier_block *nb, unsigned
+long action, void *data);
+
+extern struct raw_notifier_head smt_notifier_head;
+
+static struct notifier_block smt_notifier = {
+ .notifier_call = smt_notifier_callback, };
+
static int smu_sys_get_pp_feature_mask(void *handle,
char *buf)
{
@@ -625,6 +634,8 @@ static int smu_set_funcs(struct amdgpu_device
*adev)
return 0;
}
+static struct smu_context *current_smu;
+
static int smu_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@
-645,6 +656,7 @@ static int smu_early_init(void *handle)
mutex_init(&smu->message_lock);
adev->powerplay.pp_handle = smu;
+ current_smu = smu;
adev->powerplay.pp_funcs = &swsmu_pm_funcs;
r = smu_set_funcs(adev);
@@ -1105,6 +1117,8 @@ static int smu_sw_init(void *handle)
if (!smu->ppt_funcs->get_fan_control_mode)
smu->adev->pm.no_fan = true;
+ raw_notifier_chain_register(&smt_notifier_head, &smt_notifier);
+
It is not required for every dGPU smu to register for and process this
notification regardless of the system they are in. It is only applicable for
vangogh and hence this and below should be moved to some ppt funcs used
in sw_init/sw_fini of amdgpu_smu for vangogh alone.
The fixed issue is common, it is possible to keep this interface for others. So
I think it is better to put the common code here.
No, this is not common at all. A Navi10 card sitting on an Intel system
or a Renoir platform is not bothered about an smt change and doesn't
need to register any notification callback.
All you have to do is to register for this notifier inside, say
vangogh_set_ppt_funcs or some other callback which happen during sw_init
of amdgpu_smu.
For unregister, you may keep it in smu_sw_fini call like below.
if (smu->nb.notifier != NULL)
unregister
Also, other/future APUs may be able handle the change internally (by
propagating through HW itself) without driver needing to notify the FW.
Thanks,
Lijo
Thanks,
Lijo
return 0;
}
@@ -1122,6 +1136,8 @@ static int smu_sw_fini(void *handle)
smu_fini_microcode(smu);
+ raw_notifier_chain_unregister(&smt_notifier_head, &smt_notifier);
+
return 0;
}
@@ -3241,3 +3257,28 @@ int smu_send_hbm_bad_channel_flag(struct
smu_context *smu, uint32_t size)
return ret;
}
+
+static int smu_set_cpu_smt_enable(struct smu_context *smu, bool
+enable) {
+ int ret = -EINVAL;
+
+ if (smu->ppt_funcs && smu->ppt_funcs->set_cpu_smt_enable)
+ ret = smu->ppt_funcs->set_cpu_smt_enable(smu, enable);
+
+ return ret;
+}
+
+static int smt_notifier_callback(struct notifier_block *nb,
+unsigned long action, void *data) {
+ struct smu_context *smu = current_smu;
+ int ret = NOTIFY_OK;
+
+ ret = (action == SMT_ENABLED) ?
+ smu_set_cpu_smt_enable(smu, true) :
+ smu_set_cpu_smt_enable(smu, false);
+ if (ret)
+ ret = NOTIFY_BAD;
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 09469c750a96..7c6594bba796 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1354,6 +1354,11 @@ struct pptable_funcs {
* @init_pptable_microcode: Prepare the pptable microcode to
upload via PSP
*/
int (*init_pptable_micr
RE: [Resend PATCH v1 3/3] drm/amd/pm: vangogh: support to send SMT enable message
[AMD Official Use Only - General]
> -Original Message-
> From: Yuan, Perry
> Sent: Thursday, March 23, 2023 10:21 AM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Liang, Richard qi ; Li, Ying
> ; Liu, Kun ; amd-
> g...@lists.freedesktop.org; Yang, WenYou
> Subject: RE: [Resend PATCH v1 3/3] drm/amd/pm: vangogh: support to send
> SMT enable message
>
> [AMD Official Use Only - General]
>
>
>
> > -Original Message-
> > From: Wenyou Yang
> > Sent: Wednesday, March 22, 2023 5:16 PM
> > To: Deucher, Alexander ; Koenig,
> Christian
> > ; Pan, Xinhui
> > Cc: Yuan, Perry ; Liang, Richard qi
> > ; Li, Ying ; Liu, Kun
> > ; amd-gfx@lists.freedesktop.org; Yang, WenYou
> >
> > Subject: [Resend PATCH v1 3/3] drm/amd/pm: vangogh: support to send
> > SMT enable message
> >
> > Add the support to PPSMC_MSG_SetCClkSMTEnable(0x58) message to
> pmfw
> > for vangogh.
> >
> > Signed-off-by: Wenyou Yang
> > ---
> > .../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 3 ++-
> > drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
> > .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 19
> > +++
> > 3 files changed, 23 insertions(+), 2 deletions(-)
> >
> > diff --git
> > a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > index 7471e2df2828..2b182dbc6f9c 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > +++
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > @@ -111,7 +111,8 @@
> > #define PPSMC_MSG_GetGfxOffStatus 0x50
> > #define PPSMC_MSG_GetGfxOffEntryCount 0x51
> > #define PPSMC_MSG_LogGfxOffResidency 0x52
> > -#define PPSMC_Message_Count0x53
> > +#define PPSMC_MSG_SetCClkSMTEnable0x58
> > +#define PPSMC_Message_Count0x54
> >
> > //Argument for PPSMC_MSG_GfxDeviceDriverReset enum { diff --git
> > a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > index 297b70b9388f..820812d910bf 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > @@ -245,7 +245,8 @@
> > __SMU_DUMMY_MAP(AllowGpo), \
> > __SMU_DUMMY_MAP(Mode2Reset),\
> > __SMU_DUMMY_MAP(RequestI2cTransaction), \
> > - __SMU_DUMMY_MAP(GetMetricsTable),
> > + __SMU_DUMMY_MAP(GetMetricsTable), \
> > + __SMU_DUMMY_MAP(SetCClkSMTEnable),
> >
> > #undef __SMU_DUMMY_MAP
> > #define __SMU_DUMMY_MAP(type) SMU_MSG_##type
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > index 7433dcaa16e0..f0eeb42df96b 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > @@ -141,6 +141,7 @@ static struct cmn2asic_msg_mapping
> > vangogh_message_map[SMU_MSG_MAX_COUNT] = {
> > MSG_MAP(GetGfxOffStatus,
> > PPSMC_MSG_GetGfxOffStatus,
> 0),
> > MSG_MAP(GetGfxOffEntryCount,
> > PPSMC_MSG_GetGfxOffEntryCount,
> 0),
> > MSG_MAP(LogGfxOffResidency,
> > PPSMC_MSG_LogGfxOffResidency, 0),
> > + MSG_MAP(SetCClkSMTEnable,
> > PPSMC_MSG_SetCClkSMTEnable,
> > 0),
> > };
> >
> > static struct cmn2asic_mapping
> > vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { @@ -2428,6
> > +2429,23 @@ static u32 vangogh_get_gfxoff_entrycount(struct
> > +smu_context
> > *smu, uint64_t *entr
> > return ret;
> > }
> >
> > +static int vangogh_set_cpu_smt_enable(struct smu_context *smu, bool
> > +enable) {
> > + int ret = 0;
> > +
> > + if (enable) {
> > + ret = smu_cmn_send_smc_msg_with_param(smu,
> > +
> > SMU_MSG_SetCClkSMTEnable,
> > + 1, NULL);
> > + } else {
> > + ret = smu_cmn_send_smc_msg_with_param(smu,
> > +
> > SMU_MSG_SetCClkSMTEnable,
> > + 0, NULL);
> > + }
> > +
> > + return ret;
> > +}
> > +
> > static const struct pptable_funcs vangogh_ppt_funcs = {
> >
> > .check_fw_status = smu_v11_0_check_fw_status, @@ -2474,6
> +2492,7 @@
> > static const struct pptable_funcs vangogh_ppt_funcs = {
> > .get_power_limit = vangogh_get_power_limit,
> > .set_power_limit = vangogh_set_power_limit,
> > .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
> > + .set_cpu_smt_enable = vangogh_set_cpu_smt_enable,
>
> Maybe we can rename the function with cclk dpm string?
> For example,
> .set_cclk_pd_limit = vangogh_set_cpu_smt_enable,
This interface is only to send the smt status to pmfw, it is not used for
configuring the Cclk_PD_Data_Limut value.
>
> Perry.
>
> > };
> >
> > void vangogh_set_ppt_funcs(struct smu_context *smu)
> > --
> > 2.39.2
RE: [Resend PATCH v1 2/3] drm/amd/pm: send the SMT-enable message to pmfw
[AMD Official Use Only - General]
> -Original Message-
> From: Lazar, Lijo
> Sent: Thursday, March 23, 2023 4:29 PM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Yuan, Perry ; Li, Ying ; amd-
> g...@lists.freedesktop.org; Liu, Kun ; Liang, Richard qi
>
> Subject: Re: [Resend PATCH v1 2/3] drm/amd/pm: send the SMT-enable
> message to pmfw
>
>
>
> On 3/22/2023 2:46 PM, Wenyou Yang wrote:
> > When the CPU SMT status change in the fly, sent the SMT-enable message
> > to pmfw to notify it that the SMT status changed.
> >
> > Signed-off-by: Wenyou Yang
> > ---
> > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41
> +++
> > drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +++
> > 2 files changed, 46 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index b5d64749990e..5cd85a9d149d 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -22,6 +22,7 @@
> >
> > #define SWSMU_CODE_LAYER_L1
> >
> > +#include
> > #include
> > #include
> >
> > @@ -69,6 +70,14 @@ static int smu_set_fan_speed_rpm(void *handle,
> uint32_t speed);
> > static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
> > static int smu_set_mp1_state(void *handle, enum pp_mp1_state
> > mp1_state);
> >
> > +static int smt_notifier_callback(struct notifier_block *nb, unsigned
> > +long action, void *data);
> > +
> > +extern struct raw_notifier_head smt_notifier_head;
> > +
> > +static struct notifier_block smt_notifier = {
> > + .notifier_call = smt_notifier_callback, };
> > +
> > static int smu_sys_get_pp_feature_mask(void *handle,
> >char *buf)
> > {
> > @@ -625,6 +634,8 @@ static int smu_set_funcs(struct amdgpu_device
> *adev)
> > return 0;
> > }
> >
> > +static struct smu_context *current_smu;
> > +
> > static int smu_early_init(void *handle)
> > {
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> @@
> > -645,6 +656,7 @@ static int smu_early_init(void *handle)
> > mutex_init(&smu->message_lock);
> >
> > adev->powerplay.pp_handle = smu;
> > + current_smu = smu;
> > adev->powerplay.pp_funcs = &swsmu_pm_funcs;
> >
> > r = smu_set_funcs(adev);
> > @@ -1105,6 +1117,8 @@ static int smu_sw_init(void *handle)
> > if (!smu->ppt_funcs->get_fan_control_mode)
> > smu->adev->pm.no_fan = true;
> >
> > + raw_notifier_chain_register(&smt_notifier_head, &smt_notifier);
> > +
>
> It is not required for every dGPU smu to register for and process this
> notification regardless of the system they are in. It is only applicable for
> vangogh and hence this and below should be moved to some ppt funcs used
> in sw_init/sw_fini of amdgpu_smu for vangogh alone.
The fixed issue is common, it is possible to keep this interface for others. So
I think it is better to put the common code here.
>
> Thanks,
> Lijo
>
> > return 0;
> > }
> >
> > @@ -1122,6 +1136,8 @@ static int smu_sw_fini(void *handle)
> >
> > smu_fini_microcode(smu);
> >
> > + raw_notifier_chain_unregister(&smt_notifier_head, &smt_notifier);
> > +
> > return 0;
> > }
> >
> > @@ -3241,3 +3257,28 @@ int smu_send_hbm_bad_channel_flag(struct
> > smu_context *smu, uint32_t size)
> >
> > return ret;
> > }
> > +
> > +static int smu_set_cpu_smt_enable(struct smu_context *smu, bool
> > +enable) {
> > + int ret = -EINVAL;
> > +
> > + if (smu->ppt_funcs && smu->ppt_funcs->set_cpu_smt_enable)
> > + ret = smu->ppt_funcs->set_cpu_smt_enable(smu, enable);
> > +
> > + return ret;
> > +}
> > +
> > +static int smt_notifier_callback(struct notifier_block *nb,
> > +unsigned long action, void *data) {
> > + struct smu_context *smu = current_smu;
> > + int ret = NOTIFY_OK;
> > +
> > + ret = (action == SMT_ENABLED) ?
> > + smu_set_cpu_smt_enable(smu, true) :
> > + smu_set_cpu_smt_enable(smu, false);
> > + if (ret)
> > + ret = NOTIFY_BAD;
> > +
> > + return ret;
> > +}
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > index 09469c750a96..7c6594bba796 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > @@ -1354,6 +1354,11 @@ struct pptable_funcs {
> > * @init_pptable_microcode: Prepare the pptable microcode to
> upload via PSP
> > */
> > int (*init_pptable_microcode)(struct smu_context *smu);
> > +
> > + /**
> > +* @set_cpu_smt_enable: Set the CPU SMT status
> > +*/
> > + int (*set_cpu_smt_enable)(struct smu_context *smu, bool enable);
> > };
> >
> > typedef enum {
RE: [PATCH Review 1/1] drm/amdgpu: print ras drv fw debug info
[AMD Official Use Only - General]
Reviewed-by: Candice Li
Thanks,
Candice
-Original Message-
From: amd-gfx On Behalf Of Stanley.Yang
Sent: Thursday, March 23, 2023 4:35 PM
To: amd-gfx@lists.freedesktop.org
Cc: Yang, Stanley
Subject: [PATCH Review 1/1] drm/amdgpu: print ras drv fw debug info
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 6d2879ac585b..f76b1cb8baf8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -459,6 +459,12 @@ void amdgpu_ucode_print_psp_hdr(const struct
common_firmware_header *hdr)
DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n",
le32_to_cpu(desc->size_bytes));
break;
+ case PSP_FW_TYPE_PSP_RAS_DRV:
+ DRM_DEBUG("psp_ras_drv_version: %u\n",
+ le32_to_cpu(desc->fw_version));
+ DRM_DEBUG("psp_ras_drv_size_bytes: %u\n",
+ le32_to_cpu(desc->size_bytes));
+ break;
default:
DRM_DEBUG("Unsupported PSP fw type: %d\n",
desc->fw_type);
break;
--
2.17.1
[PATCH Review 1/1] drm/amdgpu: print ras drv fw debug info
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 6d2879ac585b..f76b1cb8baf8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -459,6 +459,12 @@ void amdgpu_ucode_print_psp_hdr(const struct
common_firmware_header *hdr)
DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n",
le32_to_cpu(desc->size_bytes));
break;
+ case PSP_FW_TYPE_PSP_RAS_DRV:
+ DRM_DEBUG("psp_ras_drv_version: %u\n",
+ le32_to_cpu(desc->fw_version));
+ DRM_DEBUG("psp_ras_drv_size_bytes: %u\n",
+ le32_to_cpu(desc->size_bytes));
+ break;
default:
DRM_DEBUG("Unsupported PSP fw type: %d\n",
desc->fw_type);
break;
--
2.17.1
[PATCH] drm/amdgpu: Adding MES engine reset in SRIOV
Added AMD_IP_BLOCK_TYPE_MES to the list of engine
under amdgpu_device_ip_reinit_late_sriov, so that MES engine can be
correctly reset in SRIOV environment
Signed-off-by: Bill Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 065f5396d0ce..0d9061151048 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3183,7 +3183,8 @@ static int amdgpu_device_ip_reinit_late_sriov(struct
amdgpu_device *adev)
AMD_IP_BLOCK_TYPE_MES,
AMD_IP_BLOCK_TYPE_UVD,
AMD_IP_BLOCK_TYPE_VCE,
- AMD_IP_BLOCK_TYPE_VCN
+ AMD_IP_BLOCK_TYPE_VCN,
+ AMD_IP_BLOCK_TYPE_MES
};
for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
--
2.34.1
Re: [Resend PATCH v1 2/3] drm/amd/pm: send the SMT-enable message to pmfw
On 3/22/2023 2:46 PM, Wenyou Yang wrote:
When the CPU SMT status change in the fly, sent the SMT-enable
message to pmfw to notify it that the SMT status changed.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 +++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index b5d64749990e..5cd85a9d149d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -22,6 +22,7 @@
#define SWSMU_CODE_LAYER_L1
+#include
#include
#include
@@ -69,6 +70,14 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
+static int smt_notifier_callback(struct notifier_block *nb, unsigned long action, void *data);
+
+extern struct raw_notifier_head smt_notifier_head;
+
+static struct notifier_block smt_notifier = {
+ .notifier_call = smt_notifier_callback,
+};
+
static int smu_sys_get_pp_feature_mask(void *handle,
char *buf)
{
@@ -625,6 +634,8 @@ static int smu_set_funcs(struct amdgpu_device *adev)
return 0;
}
+static struct smu_context *current_smu;
+
static int smu_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -645,6 +656,7 @@ static int smu_early_init(void *handle)
mutex_init(&smu->message_lock);
adev->powerplay.pp_handle = smu;
+ current_smu = smu;
adev->powerplay.pp_funcs = &swsmu_pm_funcs;
r = smu_set_funcs(adev);
@@ -1105,6 +1117,8 @@ static int smu_sw_init(void *handle)
if (!smu->ppt_funcs->get_fan_control_mode)
smu->adev->pm.no_fan = true;
+ raw_notifier_chain_register(&smt_notifier_head, &smt_notifier);
+
It is not required for every dGPU smu to register for and process this
notification regardless of the system they are in. It is only applicable
for vangogh and hence this and below should be moved to some ppt funcs
used in sw_init/sw_fini of amdgpu_smu for vangogh alone.
Thanks,
Lijo
return 0;
}
@@ -1122,6 +1136,8 @@ static int smu_sw_fini(void *handle)
smu_fini_microcode(smu);
+ raw_notifier_chain_unregister(&smt_notifier_head, &smt_notifier);
+
return 0;
}
@@ -3241,3 +3257,28 @@ int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
return ret;
}
+
+static int smu_set_cpu_smt_enable(struct smu_context *smu, bool enable)
+{
+ int ret = -EINVAL;
+
+ if (smu->ppt_funcs && smu->ppt_funcs->set_cpu_smt_enable)
+ ret = smu->ppt_funcs->set_cpu_smt_enable(smu, enable);
+
+ return ret;
+}
+
+static int smt_notifier_callback(struct notifier_block *nb,
+unsigned long action, void *data)
+{
+ struct smu_context *smu = current_smu;
+ int ret = NOTIFY_OK;
+
+ ret = (action == SMT_ENABLED) ?
+ smu_set_cpu_smt_enable(smu, true) :
+ smu_set_cpu_smt_enable(smu, false);
+ if (ret)
+ ret = NOTIFY_BAD;
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 09469c750a96..7c6594bba796 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1354,6 +1354,11 @@ struct pptable_funcs {
* @init_pptable_microcode: Prepare the pptable microcode to upload via
PSP
*/
int (*init_pptable_microcode)(struct smu_context *smu);
+
+ /**
+* @set_cpu_smt_enable: Set the CPU SMT status
+*/
+ int (*set_cpu_smt_enable)(struct smu_context *smu, bool enable);
};
typedef enum {
RE: [Resend PATCH v1 2/3] drm/amd/pm: send the SMT-enable message to pmfw
[AMD Official Use Only - General]
> -Original Message-
> From: Quan, Evan
> Sent: Thursday, March 23, 2023 3:17 PM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Yuan, Perry ; Li, Ying ; amd-
> g...@lists.freedesktop.org; Yang, WenYou ; Liu,
> Kun ; Liang, Richard qi
> Subject: RE: [Resend PATCH v1 2/3] drm/amd/pm: send the SMT-enable
> message to pmfw
>
> [AMD Official Use Only - General]
>
>
>
> > -Original Message-
> > From: amd-gfx On Behalf Of
> > Wenyou Yang
> > Sent: Wednesday, March 22, 2023 5:16 PM
> > To: Deucher, Alexander ; Koenig,
> Christian
> > ; Pan, Xinhui
> > Cc: Yuan, Perry ; Li, Ying ;
> amd-
> > g...@lists.freedesktop.org; Yang, WenYou ; Liu,
> > Kun ; Liang, Richard qi
> > Subject: [Resend PATCH v1 2/3] drm/amd/pm: send the SMT-enable
> message
> > to pmfw
> >
> > When the CPU SMT status change in the fly, sent the SMT-enable message
> > to pmfw to notify it that the SMT status changed.
> >
> > Signed-off-by: Wenyou Yang
> > ---
> > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41
> > +++
> > drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +++
> > 2 files changed, 46 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index b5d64749990e..5cd85a9d149d 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -22,6 +22,7 @@
> >
> > #define SWSMU_CODE_LAYER_L1
> >
> > +#include
> > #include
> > #include
> >
> > @@ -69,6 +70,14 @@ static int smu_set_fan_speed_rpm(void *handle,
> > uint32_t speed); static int smu_set_gfx_cgpg(struct smu_context *smu,
> > bool enabled); static int smu_set_mp1_state(void *handle, enum
> > pp_mp1_state mp1_state);
> >
> > +static int smt_notifier_callback(struct notifier_block *nb, unsigned
> > +long
> > action, void *data);
> > +
> > +extern struct raw_notifier_head smt_notifier_head;
> > +
> > +static struct notifier_block smt_notifier = {
> > + .notifier_call = smt_notifier_callback, };
> By embedding smt_notifier into "struct smu_context" structure, you do not
> need this smt_notifer and current_smu below.
> You can refer to omap_dma_busy_notifier().
Accept. Thanks.
>
> BR
> Evan
> > +
> > static int smu_sys_get_pp_feature_mask(void *handle,
> >char *buf)
> > {
> > @@ -625,6 +634,8 @@ static int smu_set_funcs(struct amdgpu_device
> > *adev)
> > return 0;
> > }
> >
> > +static struct smu_context *current_smu;
> > +
> > static int smu_early_init(void *handle) {
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> @@
> > -645,6 +656,7 @@ static int smu_early_init(void *handle)
> > mutex_init(&smu->message_lock);
> >
> > adev->powerplay.pp_handle = smu;
> > + current_smu = smu;
> > adev->powerplay.pp_funcs = &swsmu_pm_funcs;
> >
> > r = smu_set_funcs(adev);
> > @@ -1105,6 +1117,8 @@ static int smu_sw_init(void *handle)
> > if (!smu->ppt_funcs->get_fan_control_mode)
> > smu->adev->pm.no_fan = true;
> >
> > + raw_notifier_chain_register(&smt_notifier_head, &smt_notifier);
> > +
> > return 0;
> > }
> >
> > @@ -1122,6 +1136,8 @@ static int smu_sw_fini(void *handle)
> >
> > smu_fini_microcode(smu);
> >
> > + raw_notifier_chain_unregister(&smt_notifier_head, &smt_notifier);
> > +
> > return 0;
> > }
> >
> > @@ -3241,3 +3257,28 @@ int smu_send_hbm_bad_channel_flag(struct
> > smu_context *smu, uint32_t size)
> >
> > return ret;
> > }
> > +
> > +static int smu_set_cpu_smt_enable(struct smu_context *smu, bool
> > +enable) {
> > + int ret = -EINVAL;
> > +
> > + if (smu->ppt_funcs && smu->ppt_funcs->set_cpu_smt_enable)
> > + ret = smu->ppt_funcs->set_cpu_smt_enable(smu, enable);
> > +
> > + return ret;
> > +}
> > +
> > +static int smt_notifier_callback(struct notifier_block *nb,
> > +unsigned long action, void *data) {
> > + struct smu_context *smu = current_smu;
> > + int ret = NOTIFY_OK;
> > +
> > + ret = (action == SMT_ENABLED) ?
> > + smu_set_cpu_smt_enable(smu, true) :
> > + smu_set_cpu_smt_enable(smu, false);
> > + if (ret)
> > + ret = NOTIFY_BAD;
> > +
> > + return ret;
> > +}
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > index 09469c750a96..7c6594bba796 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > @@ -1354,6 +1354,11 @@ struct pptable_funcs {
> > * @init_pptable_microcode: Prepare the pptable microcode to
> upload
> > via PSP
> > */
> > int (*init_pptable_microcode)(struct smu_context *smu);
> > +
> > + /**
> > +* @set_cpu_smt_enable: Set the CPU SMT status
> > +*/
> > + int (*set_cpu_smt_enable)(struct smu_context *smu, b
RE: [Resend PATCH v1 3/3] drm/amd/pm: vangogh: support to send SMT enable message
[AMD Official Use Only - General]
Thanks Evan.
> > -Original Message-
> > From: amd-gfx On Behalf Of
> > Wenyou Yang
> > Sent: Wednesday, March 22, 2023 5:16 PM
> > To: Deucher, Alexander ; Koenig,
> Christian
> > ; Pan, Xinhui
> > Cc: Yuan, Perry ; Li, Ying ;
> amd-
> > g...@lists.freedesktop.org; Yang, WenYou ; Liu,
> > Kun ; Liang, Richard qi
> > Subject: [Resend PATCH v1 3/3] drm/amd/pm: vangogh: support to send
> > SMT enable message
> >
> > Add the support to PPSMC_MSG_SetCClkSMTEnable(0x58) message to
> pmfw
> > for vangogh.
> >
> > Signed-off-by: Wenyou Yang
> > ---
> > .../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 3 ++-
> > drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
> > .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 19
> > +++
> > 3 files changed, 23 insertions(+), 2 deletions(-)
> >
> > diff --git
> > a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > index 7471e2df2828..2b182dbc6f9c 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > +++
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> > @@ -111,7 +111,8 @@
> > #define PPSMC_MSG_GetGfxOffStatus 0x50
> > #define PPSMC_MSG_GetGfxOffEntryCount 0x51
> > #define PPSMC_MSG_LogGfxOffResidency 0x52
> > -#define PPSMC_Message_Count0x53
> > +#define PPSMC_MSG_SetCClkSMTEnable0x58
> > +#define PPSMC_Message_Count0x54
> This seems not right. The message count should be bigger than the index of
> any other message.
> That is PPSMC_Message_Count should be 0x59 or bigger.
Accept. Will change in v2.
> >
> > //Argument for PPSMC_MSG_GfxDeviceDriverReset enum { diff --git
> > a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > index 297b70b9388f..820812d910bf 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> > @@ -245,7 +245,8 @@
> > __SMU_DUMMY_MAP(AllowGpo), \
> > __SMU_DUMMY_MAP(Mode2Reset),\
> > __SMU_DUMMY_MAP(RequestI2cTransaction), \
> > - __SMU_DUMMY_MAP(GetMetricsTable),
> > + __SMU_DUMMY_MAP(GetMetricsTable), \
> > + __SMU_DUMMY_MAP(SetCClkSMTEnable),
> >
> > #undef __SMU_DUMMY_MAP
> > #define __SMU_DUMMY_MAP(type) SMU_MSG_##type
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > index 7433dcaa16e0..f0eeb42df96b 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> > @@ -141,6 +141,7 @@ static struct cmn2asic_msg_mapping
> > vangogh_message_map[SMU_MSG_MAX_COUNT] = {
> > MSG_MAP(GetGfxOffStatus,
> > PPSMC_MSG_GetGfxOffStatus,
> > 0),
> > MSG_MAP(GetGfxOffEntryCount,
> > PPSMC_MSG_GetGfxOffEntryCount,
> 0),
> > MSG_MAP(LogGfxOffResidency,
> > PPSMC_MSG_LogGfxOffResidency, 0),
> > + MSG_MAP(SetCClkSMTEnable,
> > PPSMC_MSG_SetCClkSMTEnable,
> > 0),
> > };
> >
> > static struct cmn2asic_mapping
> > vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { @@ -2428,6
> +2429,23 @@
> > static u32 vangogh_get_gfxoff_entrycount(struct
> > smu_context *smu, uint64_t *entr
> > return ret;
> > }
> >
> > +static int vangogh_set_cpu_smt_enable(struct smu_context *smu, bool
> > enable)
> > +{
> > + int ret = 0;
> > +
> > + if (enable) {
> > + ret = smu_cmn_send_smc_msg_with_param(smu,
> > +
> > SMU_MSG_SetCClkSMTEnable,
> > + 1, NULL);
> > + } else {
> > + ret = smu_cmn_send_smc_msg_with_param(smu,
> > +
> > SMU_MSG_SetCClkSMTEnable,
> > + 0, NULL);
> > + }
> > +
> > + return ret;
> It seems the whole bunch of chunks can be simplified as "return
> smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetCClkSMTEnable, enable ? 1 : 0, NULL);"
Yes. Will change it in v2.
>
> BR
> Evan
> > +}
> > +
> > static const struct pptable_funcs vangogh_ppt_funcs = {
> >
> > .check_fw_status = smu_v11_0_check_fw_status, @@ -2474,6
> +2492,7 @@
> > static const struct pptable_funcs vangogh_ppt_funcs = {
> > .get_power_limit = vangogh_get_power_limit,
> > .set_power_limit = vangogh_set_power_limit,
> > .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
> > + .set_cpu_smt_enable = vangogh_set_cpu_smt_enable,
> > };
> >
> > void vangogh_set_ppt_funcs(struct smu_context *smu)
> > --
> > 2.39.2
RE: [Resend PATCH v1 3/3] drm/amd/pm: vangogh: support to send SMT enable message
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of
> Wenyou Yang
> Sent: Wednesday, March 22, 2023 5:16 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Yuan, Perry ; Li, Ying ; amd-
> g...@lists.freedesktop.org; Yang, WenYou ; Liu,
> Kun ; Liang, Richard qi
> Subject: [Resend PATCH v1 3/3] drm/amd/pm: vangogh: support to send
> SMT enable message
>
> Add the support to PPSMC_MSG_SetCClkSMTEnable(0x58) message to
> pmfw
> for vangogh.
>
> Signed-off-by: Wenyou Yang
> ---
> .../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 3 ++-
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 19
> +++
> 3 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> index 7471e2df2828..2b182dbc6f9c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> @@ -111,7 +111,8 @@
> #define PPSMC_MSG_GetGfxOffStatus 0x50
> #define PPSMC_MSG_GetGfxOffEntryCount 0x51
> #define PPSMC_MSG_LogGfxOffResidency0x52
> -#define PPSMC_Message_Count0x53
> +#define PPSMC_MSG_SetCClkSMTEnable 0x58
> +#define PPSMC_Message_Count0x54
This seems not right. The message count should be bigger than the index of any
other message.
That is PPSMC_Message_Count should be 0x59 or bigger.
>
> //Argument for PPSMC_MSG_GfxDeviceDriverReset
> enum {
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> index 297b70b9388f..820812d910bf 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> @@ -245,7 +245,8 @@
> __SMU_DUMMY_MAP(AllowGpo), \
> __SMU_DUMMY_MAP(Mode2Reset),\
> __SMU_DUMMY_MAP(RequestI2cTransaction), \
> - __SMU_DUMMY_MAP(GetMetricsTable),
> + __SMU_DUMMY_MAP(GetMetricsTable), \
> + __SMU_DUMMY_MAP(SetCClkSMTEnable),
>
> #undef __SMU_DUMMY_MAP
> #define __SMU_DUMMY_MAP(type)SMU_MSG_##type
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 7433dcaa16e0..f0eeb42df96b 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -141,6 +141,7 @@ static struct cmn2asic_msg_mapping
> vangogh_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(GetGfxOffStatus,
> PPSMC_MSG_GetGfxOffStatus,
> 0),
> MSG_MAP(GetGfxOffEntryCount,
> PPSMC_MSG_GetGfxOffEntryCount,0),
> MSG_MAP(LogGfxOffResidency,
> PPSMC_MSG_LogGfxOffResidency, 0),
> + MSG_MAP(SetCClkSMTEnable,
> PPSMC_MSG_SetCClkSMTEnable,
> 0),
> };
>
> static struct cmn2asic_mapping
> vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
> @@ -2428,6 +2429,23 @@ static u32 vangogh_get_gfxoff_entrycount(struct
> smu_context *smu, uint64_t *entr
> return ret;
> }
>
> +static int vangogh_set_cpu_smt_enable(struct smu_context *smu, bool
> enable)
> +{
> + int ret = 0;
> +
> + if (enable) {
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> +
> SMU_MSG_SetCClkSMTEnable,
> + 1, NULL);
> + } else {
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> +
> SMU_MSG_SetCClkSMTEnable,
> + 0, NULL);
> + }
> +
> + return ret;
It seems the whole bunch of chunks can be simplified as
"return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetCClkSMTEnable, enable ?
1 : 0, NULL);"
BR
Evan
> +}
> +
> static const struct pptable_funcs vangogh_ppt_funcs = {
>
> .check_fw_status = smu_v11_0_check_fw_status,
> @@ -2474,6 +2492,7 @@ static const struct pptable_funcs
> vangogh_ppt_funcs = {
> .get_power_limit = vangogh_get_power_limit,
> .set_power_limit = vangogh_set_power_limit,
> .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
> + .set_cpu_smt_enable = vangogh_set_cpu_smt_enable,
> };
>
> void vangogh_set_ppt_funcs(struct smu_context *smu)
> --
> 2.39.2
RE: [Resend PATCH v1 2/3] drm/amd/pm: send the SMT-enable message to pmfw
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of
> Wenyou Yang
> Sent: Wednesday, March 22, 2023 5:16 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui
> Cc: Yuan, Perry ; Li, Ying ; amd-
> g...@lists.freedesktop.org; Yang, WenYou ; Liu,
> Kun ; Liang, Richard qi
> Subject: [Resend PATCH v1 2/3] drm/amd/pm: send the SMT-enable
> message to pmfw
>
> When the CPU SMT status change in the fly, sent the SMT-enable
> message to pmfw to notify it that the SMT status changed.
>
> Signed-off-by: Wenyou Yang
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41
> +++
> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +++
> 2 files changed, 46 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index b5d64749990e..5cd85a9d149d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -22,6 +22,7 @@
>
> #define SWSMU_CODE_LAYER_L1
>
> +#include
> #include
> #include
>
> @@ -69,6 +70,14 @@ static int smu_set_fan_speed_rpm(void *handle,
> uint32_t speed);
> static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
> static int smu_set_mp1_state(void *handle, enum pp_mp1_state
> mp1_state);
>
> +static int smt_notifier_callback(struct notifier_block *nb, unsigned long
> action, void *data);
> +
> +extern struct raw_notifier_head smt_notifier_head;
> +
> +static struct notifier_block smt_notifier = {
> + .notifier_call = smt_notifier_callback,
> +};
By embedding smt_notifier into "struct smu_context" structure, you do not need
this smt_notifer and current_smu below.
You can refer to omap_dma_busy_notifier().
BR
Evan
> +
> static int smu_sys_get_pp_feature_mask(void *handle,
> char *buf)
> {
> @@ -625,6 +634,8 @@ static int smu_set_funcs(struct amdgpu_device
> *adev)
> return 0;
> }
>
> +static struct smu_context *current_smu;
> +
> static int smu_early_init(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> @@ -645,6 +656,7 @@ static int smu_early_init(void *handle)
> mutex_init(&smu->message_lock);
>
> adev->powerplay.pp_handle = smu;
> + current_smu = smu;
> adev->powerplay.pp_funcs = &swsmu_pm_funcs;
>
> r = smu_set_funcs(adev);
> @@ -1105,6 +1117,8 @@ static int smu_sw_init(void *handle)
> if (!smu->ppt_funcs->get_fan_control_mode)
> smu->adev->pm.no_fan = true;
>
> + raw_notifier_chain_register(&smt_notifier_head, &smt_notifier);
> +
> return 0;
> }
>
> @@ -1122,6 +1136,8 @@ static int smu_sw_fini(void *handle)
>
> smu_fini_microcode(smu);
>
> + raw_notifier_chain_unregister(&smt_notifier_head, &smt_notifier);
> +
> return 0;
> }
>
> @@ -3241,3 +3257,28 @@ int smu_send_hbm_bad_channel_flag(struct
> smu_context *smu, uint32_t size)
>
> return ret;
> }
> +
> +static int smu_set_cpu_smt_enable(struct smu_context *smu, bool enable)
> +{
> + int ret = -EINVAL;
> +
> + if (smu->ppt_funcs && smu->ppt_funcs->set_cpu_smt_enable)
> + ret = smu->ppt_funcs->set_cpu_smt_enable(smu, enable);
> +
> + return ret;
> +}
> +
> +static int smt_notifier_callback(struct notifier_block *nb,
> + unsigned long action, void *data)
> +{
> + struct smu_context *smu = current_smu;
> + int ret = NOTIFY_OK;
> +
> + ret = (action == SMT_ENABLED) ?
> + smu_set_cpu_smt_enable(smu, true) :
> + smu_set_cpu_smt_enable(smu, false);
> + if (ret)
> + ret = NOTIFY_BAD;
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> index 09469c750a96..7c6594bba796 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> @@ -1354,6 +1354,11 @@ struct pptable_funcs {
>* @init_pptable_microcode: Prepare the pptable microcode to
> upload via PSP
>*/
> int (*init_pptable_microcode)(struct smu_context *smu);
> +
> + /**
> + * @set_cpu_smt_enable: Set the CPU SMT status
> + */
> + int (*set_cpu_smt_enable)(struct smu_context *smu, bool enable);
> };
>
> typedef enum {
> --
> 2.39.2
