[linux-next:master] BUILD SUCCESS WITH WARNING d3f2cd24819158bb70701c3549e586f9df9cee67
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: d3f2cd24819158bb70701c3549e586f9df9cee67 Add linux-next specific files for 20230414 Warning reports: https://lore.kernel.org/oe-kbuild-all/202303161521.jbgbafjj-...@intel.com Warning: (recently discovered and may have been fixed) drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:351:13: warning: variable 'bw_needed' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:352:25: warning: variable 'link' set but not used [-Wunused-but-set-variable] drivers/net/wireless/legacy/ray_cs.c:628:17: warning: 'strncpy' specified bound 32 equals destination size [-Wstringop-truncation] drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: warning: variable 'ret' is uninitialized when used here [-Wuninitialized] Unverified Warning (likely false positive, please contact us if interested): drivers/acpi/property.c:985 acpi_data_prop_read_single() error: potentially dereferencing uninitialized 'obj'. drivers/gpu/host1x/context.c:82 host1x_memory_context_list_init() warn: missing error code 'err' drivers/gpu/host1x/dev.c:417 host1x_iommu_attach() warn: passing zero to 'ERR_PTR' fs/xfs/scrub/refcount.c: xfs_mount.h is included more than once. fs/xfs/scrub/refcount.c: xfs_trans_resv.h is included more than once. Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used | `-- drivers-net-wireless-legacy-ray_cs.c:warning:strncpy-specified-bound-equals-destination-size |-- alpha-randconfig-r013-20230409 | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- arc-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- arc-randconfig-c023-20230412 | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- arc-randconfig-r022-20230409 | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- arm-allmodconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- arm-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- arm-randconfig-m041-20230413 | |-- drivers-gpu-host1x-context.c-host1x_memory_context_list_init()-warn:missing-error-code-err | `-- drivers-gpu-host1x-dev.c-host1x_iommu_attach()-warn:passing-zero-to-ERR_PTR |-- arm64-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- i386-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- i386-randconfig-m021 | `-- drivers-acpi-property.c-acpi_data_prop_read_single()-error:potentially-dereferencing-uninitialized-obj-. |-- ia64-allmodconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used | `-- drivers-net-wireless-legacy-ray_cs.c:warning:strncpy-specified-bound-equals-destination-size |-- loongarch-allmodconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used |-- loongarch-defconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_nee
Re: [PATCH v4 3/3] drm/amdgpu: Add support for querying the max ibs in a submission. (v3)
On Fri, Apr 14, 2023 at 5:24 PM Bas Nieuwenhuizen
wrote:
>
> On Fri, Apr 14, 2023 at 11:18 PM Alex Deucher wrote:
> >
> > On Thu, Apr 13, 2023 at 10:25 AM Bas Nieuwenhuizen
> > wrote:
> > >
> > > This info would be used by radv to figure out when we need to
> > > split a submission into multiple submissions. radv currently has
> > > a limit of 192 which seems to work for most gfx submissions, but
> > > is way too high for e.g. compute or sdma.
> > >
> > > Userspace is available at
> > > https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3
> > >
> > > v3: Completely rewrote based on suggestion of making it a separate query.
> > >
> > > Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498
> > > Signed-off-by: Bas Nieuwenhuizen
> >
> > Maybe a 4th patch to bump the driver version?
>
> In the userspace I just make the query and put in some guessed values
> if it errors out, which doesn't need the driver version enumeration.
Ok. Applied the series. Thanks!
Alex
>
> >
> > Alex
> >
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +
> > > include/uapi/drm/amdgpu_drm.h | 2 ++
> > > 2 files changed, 11 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > index 0efb38539d70..1a2e342af1c0 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > @@ -1140,6 +1140,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void
> > > *data, struct drm_file *filp)
> > > kfree(caps);
> > > return r;
> > > }
> > > + case AMDGPU_INFO_MAX_IBS: {
> > > + uint32_t max_ibs[AMDGPU_HW_IP_NUM];
> > > +
> > > + for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
> > > + max_ibs[i] = amdgpu_ring_max_ibs(i);
> > > +
> > > + return copy_to_user(out, max_ibs,
> > > + min((size_t)size, sizeof(max_ibs))) ?
> > > -EFAULT : 0;
> > > + }
> > > default:
> > > DRM_DEBUG_KMS("Invalid request %d\n", info->query);
> > > return -EINVAL;
> > > diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> > > index b6eb90df5d05..6981e59a9401 100644
> > > --- a/include/uapi/drm/amdgpu_drm.h
> > > +++ b/include/uapi/drm/amdgpu_drm.h
> > > @@ -876,6 +876,8 @@ struct drm_amdgpu_cs_chunk_data {
> > > #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
> > > /* Subquery id: Encode */
> > > #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
> > > +/* Query the max number of IBs per gang per submission */
> > > +#define AMDGPU_INFO_MAX_IBS0x22
> > >
> > > #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
> > > #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
> > > --
> > > 2.40.0
> > >
Re: [PATCH] drm/amd/pm: change pmfw_decoded_link_width, speed variables to globals
Applied. Thanks!
Alex
On Fri, Apr 14, 2023 at 8:04 AM Tom Rix wrote:
>
> gcc with W=1 reports
> In file included from
> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.c:36:
> ./drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0.h:66:18: error:
> ‘pmfw_decoded_link_width’ defined but not used
> [-Werror=unused-const-variable=]
>66 | static const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
> | ^~~
> ./drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0.h:65:18: error:
> ‘pmfw_decoded_link_speed’ defined but not used
> [-Werror=unused-const-variable=]
>65 | static const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
> | ^~~
>
> These variables are defined and used in smu_v13_0_7_ppt.c and
> smu_v13_0_0_ppt.c.
> There should be only one definition. So define the variables as globals
> in smu_v13_0.c
>
> Signed-off-by: Tom Rix
> ---
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 4 ++--
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +++
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
> index 7944ce80e5c3..df3baaab0037 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
> @@ -62,8 +62,8 @@
> #define CTF_OFFSET_HOTSPOT 5
> #define CTF_OFFSET_MEM 5
>
> -static const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
> -static const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
> +extern const int pmfw_decoded_link_speed[5];
> +extern const int pmfw_decoded_link_width[7];
>
> #define DECODE_GEN_SPEED(gen_speed_idx)
> (pmfw_decoded_link_speed[gen_speed_idx])
> #define DECODE_LANE_WIDTH(lane_width_idx)
> (pmfw_decoded_link_width[lane_width_idx])
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> index 73175c993da9..393c6a7b9609 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> @@ -85,6 +85,9 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
> static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
> static const int link_speed[] = {25, 50, 80, 160};
>
> +const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
> +const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
> +
> int smu_v13_0_init_microcode(struct smu_context *smu)
> {
> struct amdgpu_device *adev = smu->adev;
> --
> 2.27.0
>
Re: [PATCH v4 3/3] drm/amdgpu: Add support for querying the max ibs in a submission. (v3)
On Fri, Apr 14, 2023 at 11:18 PM Alex Deucher wrote:
>
> On Thu, Apr 13, 2023 at 10:25 AM Bas Nieuwenhuizen
> wrote:
> >
> > This info would be used by radv to figure out when we need to
> > split a submission into multiple submissions. radv currently has
> > a limit of 192 which seems to work for most gfx submissions, but
> > is way too high for e.g. compute or sdma.
> >
> > Userspace is available at
> > https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3
> >
> > v3: Completely rewrote based on suggestion of making it a separate query.
> >
> > Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498
> > Signed-off-by: Bas Nieuwenhuizen
>
> Maybe a 4th patch to bump the driver version?
In the userspace I just make the query and put in some guessed values
if it errors out, which doesn't need the driver version enumeration.
>
> Alex
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +
> > include/uapi/drm/amdgpu_drm.h | 2 ++
> > 2 files changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index 0efb38539d70..1a2e342af1c0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -1140,6 +1140,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void
> > *data, struct drm_file *filp)
> > kfree(caps);
> > return r;
> > }
> > + case AMDGPU_INFO_MAX_IBS: {
> > + uint32_t max_ibs[AMDGPU_HW_IP_NUM];
> > +
> > + for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
> > + max_ibs[i] = amdgpu_ring_max_ibs(i);
> > +
> > + return copy_to_user(out, max_ibs,
> > + min((size_t)size, sizeof(max_ibs))) ?
> > -EFAULT : 0;
> > + }
> > default:
> > DRM_DEBUG_KMS("Invalid request %d\n", info->query);
> > return -EINVAL;
> > diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> > index b6eb90df5d05..6981e59a9401 100644
> > --- a/include/uapi/drm/amdgpu_drm.h
> > +++ b/include/uapi/drm/amdgpu_drm.h
> > @@ -876,6 +876,8 @@ struct drm_amdgpu_cs_chunk_data {
> > #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
> > /* Subquery id: Encode */
> > #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
> > +/* Query the max number of IBs per gang per submission */
> > +#define AMDGPU_INFO_MAX_IBS0x22
> >
> > #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
> > #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
> > --
> > 2.40.0
> >
Re: [PATCH v4 3/3] drm/amdgpu: Add support for querying the max ibs in a submission. (v3)
On Thu, Apr 13, 2023 at 10:25 AM Bas Nieuwenhuizen
wrote:
>
> This info would be used by radv to figure out when we need to
> split a submission into multiple submissions. radv currently has
> a limit of 192 which seems to work for most gfx submissions, but
> is way too high for e.g. compute or sdma.
>
> Userspace is available at
> https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3
>
> v3: Completely rewrote based on suggestion of making it a separate query.
>
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498
> Signed-off-by: Bas Nieuwenhuizen
Maybe a 4th patch to bump the driver version?
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +
> include/uapi/drm/amdgpu_drm.h | 2 ++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 0efb38539d70..1a2e342af1c0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -1140,6 +1140,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void
> *data, struct drm_file *filp)
> kfree(caps);
> return r;
> }
> + case AMDGPU_INFO_MAX_IBS: {
> + uint32_t max_ibs[AMDGPU_HW_IP_NUM];
> +
> + for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
> + max_ibs[i] = amdgpu_ring_max_ibs(i);
> +
> + return copy_to_user(out, max_ibs,
> + min((size_t)size, sizeof(max_ibs))) ?
> -EFAULT : 0;
> + }
> default:
> DRM_DEBUG_KMS("Invalid request %d\n", info->query);
> return -EINVAL;
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index b6eb90df5d05..6981e59a9401 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -876,6 +876,8 @@ struct drm_amdgpu_cs_chunk_data {
> #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
> /* Subquery id: Encode */
> #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
> +/* Query the max number of IBs per gang per submission */
> +#define AMDGPU_INFO_MAX_IBS0x22
>
> #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
> #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
> --
> 2.40.0
>
Re: [PATCH] drm/amdgpu: add new flag to AMDGPU_CTX_QUERY2
Em 13/04/2023 07:18, Pierre-Eric Pelloux-Prayer escreveu: OpenGL EXT_robustness extension expects the driver to stop reporting GUILTY_CONTEXT_RESET when the reset has completed and the GPU is ready to accept submission again. This commit adds a AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS flag, that let the UMD know that the reset is still not finished. Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290 Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: André Almeida
Re: [PATCH] drm/amdgpu: Fix desktop freezed after gpu-reset
Hi Alan, Em 14/04/2023 13:22, Alan Liu escreveu: [Why] After gpu-reset, sometimes the driver would fail to enable vblank irq, causing flip_done timed out and the desktop freezed. During gpu-reset, we will disable and enable vblank irq in dm_suspend() and dm_resume(). Later on in amdgpu_irq_gpu_reset_resume_helper(), we will check irqs' refcount and decide to enable or disable the irqs again. However, we have 2 sets of API for controling vblank irq, one is dm_vblank_get/put() and another is amdgpu_irq_get/put(). Each API has its own refcount and flag to store the state of vblank irq, and they are not synchronized. In drm we use the first API to control vblank irq but in amdgpu_irq_gpu_reset_resume_helper() we use the second set of API. The failure happens when vblank irq was enabled by dm_vblank_get() before gpu-reset, we have vblank->enabled true. However, during gpu-reset, in amdgpu_irq_gpu_reset_resume_helper(), vblank irq's state checked from amdgpu_irq_update() is DISABLED. So finally it will disable vblank irq again. After gpu-reset, if there is a cursor plane commit, the driver will try to enable vblank irq by calling drm_vblank_enable(), but the vblank->enabled is still true, so it fails to turn on vblank irq and causes flip_done can't be completed in vblank irq handler and desktop become freezed. [How] Combining the 2 vblank control APIs by letting drm's API finally calls amdgpu_irq's API, so the irq's refcount and state of both APIs can be synchronized. Also add a check to prevent refcount from being less then 0 in amdgpu_irq_put(). How have you tested this patch? v2: - Add warning in amdgpu_irq_enable() if the irq is already disabled. - Call dc_interrupt_set() in dm_set_vblank() to avoid refcount change if it is in gpu-reset. If this is a v2, please use [PATCH v2] in the subject. Thanks, André
[pull] amdgpu, amdkfd drm-next-6.4
Hi Dave, Daniel, Last few changes for 6.4. The following changes since commit 55bf14961db9da61220e6f04bc9919c94b1a6585: Merge tag 'mediatek-drm-next-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next (2023-04-11 12:28:10 +0200) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-next-6.4-2023-04-14 for you to fetch changes up to 541372bb62f289f4402cf55be51fb9cec7373627: drm/amdgpu: add some basic elements for multiple XCD case (2023-04-14 13:47:49 -0400) amd-drm-next-6.4-2023-04-14: amdgpu: - S4 fixes for APUs - GFX11 fixes - Misc code cleanups - DCN 3.2 fixes - DCN 3.1.4 fixes - FPO/FAMS work to improve display power savings - DP fixes - UMC 8.10 code cleanup - SDMA v4 fix - GPU clock counter fixes - SMU 13 fixes - Sdma v6 invalidation fix for preemption - RAS fixes - S0ix fix - GC 9.4.3 updates amdkfd: - Fix user pointers with IOMMU - Fix coherency flag handling Aaron Liu (1): drm/amdgpu: skip kfd-iommu suspend/resume for S0ix Alex Deucher (1): drm/amdgpu: simplify amdgpu_ras_eeprom.c Alvin Lee (3): drm/amd/display: Clear FAMS flag if FAMS doesn't reduce vlevel drm/amd/display: Add FPO + VActive support drm/amd/display: On clock init, maintain DISPCLK freq Amber Lin (1): drm/amdkfd: Enable HW_UPDATE_RPTR on GC 9.4.3 Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.161.0 Aric Cyr (1): drm/amd/display: 3.2.230 Arvind Yadav (1): drm/amdgpu: add new parameters in v11_struct Charlene Liu (1): drm/amd/display: add dscclk instance offset check Evan Quan (1): drm/amd/pm: correct the pcie link state check for SMU13 Graham Sider (2): drm/amdgpu: Enable GFX11 SDMA context empty interrupt drm/amdkfd: Add gfx_target_version for GC 9.4.3 Guilherme G. Piccoli (1): drm/amd/pm: Fix incorrect comment about Vangogh power cap support Hamza Mahfooz (1): drm/amd/display: prep work for root clock optimization enablement for DCN314 Hawking Zhang (5): drm/amdgpu: drop temp programming for pagefault handling drm/amdgpu: add gc v9_4_3 rlc_funcs implementation drm/amdgpu: switch to v9_4_3 gfx_funcs callbacks for GC 9.4.3 drm/amdgpu: add common early init support for GC 9.4.3 drm/amdgpu: add common ip block for GC 9.4.3 Horatio Zhang (2): drm/amd/pm: correct SMU13.0.7 pstate profiling clock settings drm/amd/pm: correct SMU13.0.7 max shader clock reporting Igor Artemiev (1): drm/amd/display: Fix potential null dereference Jack Xiao (1): drm/amd/amdgpu: introduce gc_*_mes_2.bin v2 Jane Jian (1): Revert "drm/amdgpu: enable ras for mp0 v13_0_10 on SRIOV" Jesse Zhang (2): drm/amdgpu: switch to golden tsc registers for raven/raven2 drm/amdgpu: change the reference clock for raven/raven2 Le Ma (2): drm/amdgpu: move vmhub out of amdgpu_ring_funcs (v4) drm/amdgpu: add some basic elements for multiple XCD case Li Ma (1): drm/amdgpu: reserve the old gc_11_0_*_mes.bin Lijo Lazar (1): drm/amdgpu: Fix warnings Mario Limonciello (1): drm/amd: Fix an out of bounds error in BIOS parser Michael Strauss (1): drm/amd/display: Improve robustness of FIXED_VS link training at DP1 rates Mukul Joshi (2): drm/amdgpu: Enable IH retry CAM on GFX9 drm/amdgpu: Rework retry fault removal Paul Hsieh (1): drm/amd/display: Correct DML calculation to follow HW SPEC Pierre-Eric Pelloux-Prayer (1): drm/amdgpu: use sdma_v6 single packet invalidation Shane Xiao (3): drm/amdgpu: Add userptr bo support for mGPUs when iommu is on amd/amdgpu: Inherit coherence flags base on original BO flags drm/amdgpu: DROP redundant drm_prime_sg_to_dma_addr_array Shashank Sharma (2): drm/amdgpu: rename num_doorbells drm/amdgpu: include protection for doorbell.h Sreekant Somasekharan (1): drm/amdkfd: Check PCIe atomics support on GFX11 to set CP_HQD_HQ_STATUS0[29] Srinivasan Shanmugam (5): drm/amd/amdgpu: Drop the hang limit parameter drm/amd/display : Log DP link training downspread info drm/amd/display: Add logging for DP link traning Test Pattern Seqeunces drm/amd/display: Add logging when setting DP sink power state fails drm/amd/display: Add logging when DP link training Clock recovery is Successful Stanley.Yang (2): drm/amdgpu: fix unexpected block id drm/amdgpu: correct ras enabled flag Tim Huang (1): drm/amdgpu: allow more APUs to do mode2 reset when go to S4 Tom Rix (6): drm/amd/display: remove unused average_render_time_in_us and i variables drm/amd/display: set variable dcn3_14_soc storage-class-specifier to static drm/amd/display: set variables aperture_default_system and context0
[PATCH] drm/amd/display: fix flickering caused by S/G mode
Currently, we allow the framebuffer for a given plane to move between
memory domains, however when that happens it causes the screen to
flicker, it is even possible for the framebuffer to change memory
domains on every plane update (causing a continuous flicker effect). So,
to fix this, don't perform an immediate flip in the aforementioned case.
Cc: sta...@vger.kernel.org
Fixes: 81d0bcf99009 ("drm/amdgpu: make display pinning more flexible (v2)")
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 ++-
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index da3045fdcb6d..9a4e7408384a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7897,6 +7897,34 @@ static void amdgpu_dm_commit_cursors(struct
drm_atomic_state *state)
amdgpu_dm_plane_handle_cursor_update(plane,
old_plane_state);
}
+static inline uint32_t get_mem_type(struct amdgpu_device *adev,
+ struct drm_gem_object *obj,
+ bool check_domain)
+{
+ struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
+ uint32_t mem_type;
+
+ if (unlikely(amdgpu_bo_reserve(abo, true)))
+ return 0;
+
+ if (unlikely(dma_resv_reserve_fences(abo->tbo.base.resv, 1)))
+ goto err;
+
+ if (check_domain &&
+ amdgpu_display_supported_domains(adev, abo->flags) !=
+ (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT))
+ goto err;
+
+ mem_type = abo->tbo.resource->mem_type;
+ amdgpu_bo_unreserve(abo);
+
+ return mem_type;
+
+err:
+ amdgpu_bo_unreserve(abo);
+ return 0;
+}
+
static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
struct dc_state *dc_state,
struct drm_device *dev,
@@ -7916,6 +7944,7 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
to_dm_crtc_state(drm_atomic_get_old_crtc_state(state,
pcrtc));
int planes_count = 0, vpos, hpos;
unsigned long flags;
+ uint32_t mem_type;
u32 target_vblank, last_flip_vblank;
bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
bool cursor_update = false;
@@ -8035,13 +8064,21 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
}
}
+ mem_type = get_mem_type(dm->adev, old_plane_state->fb->obj[0],
+ true);
+
/*
* Only allow immediate flips for fast updates that don't
-* change FB pitch, DCC state, rotation or mirroing.
+* change memory domain, FB pitch, DCC state, rotation or
+* mirroring.
*/
bundle->flip_addrs[planes_count].flip_immediate =
crtc->state->async_flip &&
- acrtc_state->update_type == UPDATE_TYPE_FAST;
+ acrtc_state->update_type == UPDATE_TYPE_FAST &&
+ (!mem_type || (mem_type && get_mem_type(dm->adev,
+ fb->obj[0],
+ false) ==
+ mem_type));
timestamp_ns = ktime_get_ns();
bundle->flip_addrs[planes_count].flip_timestamp_in_us =
div_u64(timestamp_ns, 1000);
--
2.40.0
[PATCH v3] drm/amd/display: Add logging when DP link training Channel EQ is Successful
Log when Channel Equalization is successful,
and DP link training completed.
Cc: Aurabindo Pillai
Cc: Fangzhi Zuo
Signed-off-by: Srinivasan Shanmugam
---
v2:
- For consistency of the printed messages, either drop or keep %s for both the
lines - it is dropped (Aurabindo)
- For 128b/132b, moved the statements after EQ interlane alignment
is done.
v3:
- retained %s for both the lines, useful for better debugging
.../display/dc/link/protocols/link_dp_training_128b_132b.c | 3 +++
.../amd/display/dc/link/protocols/link_dp_training_8b_10b.c | 6 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
index 23d380f09a21..a1990118cf50 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
@@ -136,6 +136,9 @@ static enum link_training_result
dp_perform_128b_132b_channel_eq_done_sequence(
result = LINK_TRAINING_ABORT;
} else if
(dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) {
/* pass */
+ DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n",
__func__);
+ DC_LOG_HW_LINK_TRAINING("%s: DP 128b/132b Link Training
successful\n",
+ __func__);
break;
} else if (wait_time >= lt_settings->eq_wait_time_limit) {
result = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT;
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
index 3889ebb2256b..104da87f395a 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
@@ -339,8 +339,12 @@ enum link_training_result
perform_8b_10b_channel_equalization_sequence(
/* 6. check CHEQ done*/
if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
dp_is_symbol_locked(lane_count,
dpcd_lane_status) &&
-
dp_is_interlane_aligned(dpcd_lane_status_updated))
+
dp_is_interlane_aligned(dpcd_lane_status_updated)) {
+ DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n",
__func__);
+ DC_LOG_HW_LINK_TRAINING("%s: DP 8b/10b Link Training
successful\n",
+ __func__);
return LINK_TRAINING_SUCCESS;
+ }
/* 7. update VS/PE/PC2 in lt_settings*/
dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
--
2.25.1
[PATCH] drm/amdgpu: Fix desktop freezed after gpu-reset
[Why]
After gpu-reset, sometimes the driver would fail to enable vblank irq,
causing flip_done timed out and the desktop freezed.
During gpu-reset, we will disable and enable vblank irq in dm_suspend()
and dm_resume(). Later on in amdgpu_irq_gpu_reset_resume_helper(), we
will check irqs' refcount and decide to enable or disable the irqs
again.
However, we have 2 sets of API for controling vblank irq, one is
dm_vblank_get/put() and another is amdgpu_irq_get/put(). Each API has
its own refcount and flag to store the state of vblank irq, and they
are not synchronized.
In drm we use the first API to control vblank irq but in
amdgpu_irq_gpu_reset_resume_helper() we use the second set of API.
The failure happens when vblank irq was enabled by dm_vblank_get()
before gpu-reset, we have vblank->enabled true. However, during
gpu-reset, in amdgpu_irq_gpu_reset_resume_helper(), vblank irq's state
checked from amdgpu_irq_update() is DISABLED. So finally it will disable
vblank irq again. After gpu-reset, if there is a cursor plane commit,
the driver will try to enable vblank irq by calling drm_vblank_enable(),
but the vblank->enabled is still true, so it fails to turn on vblank
irq and causes flip_done can't be completed in vblank irq handler and
desktop become freezed.
[How]
Combining the 2 vblank control APIs by letting drm's API finally calls
amdgpu_irq's API, so the irq's refcount and state of both APIs can be
synchronized. Also add a check to prevent refcount from being less then
0 in amdgpu_irq_put().
v2:
- Add warning in amdgpu_irq_enable() if the irq is already disabled.
- Call dc_interrupt_set() in dm_set_vblank() to avoid refcount change
if it is in gpu-reset.
Signed-off-by: Alan Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 +++
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 17 ++---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index a6aef488a822..c8413470e057 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -597,6 +597,9 @@ int amdgpu_irq_put(struct amdgpu_device *adev, struct
amdgpu_irq_src *src,
if (!src->enabled_types || !src->funcs->set)
return -EINVAL;
+ if (WARN_ON(!amdgpu_irq_enabled(adev, src, type)))
+ return -EINVAL;
+
if (atomic_dec_and_test(&src->enabled_types[type]))
return amdgpu_irq_update(adev, src, type);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 1d924dc51a3e..514fefef109d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -169,10 +169,21 @@ static inline int dm_set_vblank(struct drm_crtc *crtc,
bool enable)
if (rc)
return rc;
- irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
+ if (amdgpu_in_reset(adev)) {
+ irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
+ /* During gpu-reset we'll disable and then enable vblank irq,
+* so don't use amdgpu_irq_get/put() to avoid refcount change.
+*/
+ if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
+ rc = -EBUSY;
+ } else {
+ rc = (enable)
+ ? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id)
+ : amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id);
+ }
- if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
- return -EBUSY;
+ if (rc)
+ return rc;
skip:
if (amdgpu_in_reset(adev))
--
2.34.1
[PATCH] drm/amd/display: remove unused variable oldest_index
cpp_check reports
drivers/gpu/drm/amd/display/modules/freesync/freesync.c:1143:17: style: Variable
'oldest_index' is assigned a value that is never used. [unreadVariable]
oldest_index = 0;
^
This variable is not used so remove.
Signed-off-by: Tom Rix
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 5c41a4751db4..5798c0eafa1f 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1137,10 +1137,6 @@ void mod_freesync_handle_preflip(struct mod_freesync
*mod_freesync,
if (in_out_vrr->supported &&
in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
- unsigned int oldest_index = plane->time.index + 1;
-
- if (oldest_index >= DC_PLANE_UPDATE_TIMES_MAX)
- oldest_index = 0;
last_render_time_in_us = curr_time_stamp_in_us -
plane->time.prev_update_time_in_us;
--
2.27.0
[PATCH 66/66] drm/amd/display: 3.2.231
From: Aric Cyr This DC version brings along: - FW Release 0.0.162.0 - Enable FPO+Vactivate - Support for VESA SCR on OLED - Refactor DMUB commands - Fixes in secure display, modeset, memleak and more - Picked up missed patches in history Acked-by: Qingqing Zhuo Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 3b53f36029d0..a1b2f70e2eac 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.230" +#define DC_VER "3.2.231" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.34.1
[PATCH 65/66] drm/amd/display: remove some unused variables
From: Aurabindo Pillai
[Why&How]
Fixes the following warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.c: In function
‘dcn21_set_backlight_level’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.c:229:18: warning:
unused variable ‘otg_inst’ [-Wunused-variable]
229 | uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.c:226:27: warning:
unused variable ‘cmd’ [-Wunused-variable]
226 | union dmub_rb_cmd cmd;
Reviewed-by: Qingqing Zhuo
Reviewed-by: Leo Li
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
index 55a464a39529..43463d08f21b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
@@ -223,10 +223,8 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
uint32_t backlight_pwm_u16_16,
uint32_t frame_ramp)
{
- union dmub_rb_cmd cmd;
struct dc_context *dc = pipe_ctx->stream->ctx;
struct abm *abm = pipe_ctx->stream_res.abm;
- uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;
struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
if (dc->dc->res_pool->dmcu) {
--
2.34.1
[PATCH 60/66] drm/amd/display: update GSP1 generic info packet for PSRSU
From: Po-Ting Chen
Base on PSRSU specification, every seletive update frame need to use two
SDP to indicate the frame active range. So we occupy another GSP1 for
PSRSU execution.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Po-Ting Chen
---
.../display/dc/dcn30/dcn30_dio_stream_encoder.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
index 9d08127d209b..005dbe099a7a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
@@ -436,6 +436,21 @@ void enc3_stream_encoder_update_dp_info_packets(
&info_frame->vsc,
true);
}
+ /* TODO: VSC SDP at packetIndex 1 should be retricted only if PSR-SU on.
+* There should have another Infopacket type (e.g. vsc_psrsu) for
PSR_SU.
+* In addition, currently the driver check the valid bit then update and
+* send the corresponding Infopacket. For PSR-SU, the SDP only be sent
+* while entering PSR-SU mode. So we need another parameter(e.g. send)
+* in dc_info_packet to indicate which infopacket should be enabled by
+* default here.
+*/
+ if (info_frame->vsc.valid) {
+ enc->vpg->funcs->update_generic_info_packet(
+ enc->vpg,
+ 1, /* packetIndex */
+ &info_frame->vsc,
+ true);
+ }
/* TODO: VSC SDP at packetIndex 1 should be restricted only if PSR-SU
on.
* There should have another Infopacket type (e.g. vsc_psrsu) for
PSR_SU.
* In addition, currently the driver check the valid bit then update and
--
2.34.1
[PATCH 62/66] drm/amd/display: Explicitly specify update type per plane info change
From: Nicholas Kazlauskas
[Why]
The bit for flip addr is being set causing the determination for
FAST vs MEDIUM to always return MEDIUM when plane info is provided
as a surface update. This causes extreme stuttering for the typical
atomic update path on Linux.
[How]
Don't use update_flags->raw for determining FAST vs MEDIUM. It's too
fragile to changes like this.
Explicitly specify the update type per update flag instead. It's not
as clever as checking the bits itself but at least it's correct.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 238a13266ad8..e65ba87ee2c5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2482,9 +2482,6 @@ static enum surface_update_type det_surface_update(const
struct dc *dc,
enum surface_update_type overall_type = UPDATE_TYPE_FAST;
union surface_update_flags *update_flags = &u->surface->update_flags;
- if (u->flip_addr)
- update_flags->bits.addr_update = 1;
-
if (!is_surface_in_context(context, u->surface) ||
u->surface->force_full_update) {
update_flags->raw = 0x;
return UPDATE_TYPE_FULL;
--
2.34.1
[PATCH 63/66] drm/amd/display: Add FAMS capability to DCN31
From: Aurabindo Pillai DCN31 supports FAMS, but this was not correctly set to the hardware setup sequence. This commit fixes this issue by setting the MCLK switch capability based on the feature capability retrieved from the DMUB. Reviewed-by: Rodrigo Siqueira Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c index 890268d95495..55494730e500 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c @@ -295,6 +295,7 @@ void dcn31_init_hw(struct dc *dc) // Get DMCUB capabilities dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv); dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; + dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch; } void dcn31_dsc_pg_control( -- 2.34.1
[PATCH 64/66] drm/amd/display: Add FAMS related definitions and documenation for enum fields
From: Aurabindo Pillai
[Why&How]
Add Enum and documenation related to FAMS (Firmware Assisted Memclk
Switching) and CAB (Cache As Buffer)
Reviewed-by: Qingqing Zhuo
Reviewed-by: Leo Li
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 54b7786f5681..b32a5c977d17 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -376,6 +376,7 @@ enum dmub_fw_boot_status_bit {
DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init
done */
DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver
should call restore */
DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS
data is deferred programmed */
+ DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is
enabled*/
DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if
detection need to be triggered by driver*/
DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw
power init is completed */
};
@@ -989,16 +990,25 @@ struct dmub_rb_cmd_mall {
};
/**
- * enum dmub_cmd_cab_type - TODO:
+ * enum dmub_cmd_cab_type - CAB command data.
*/
enum dmub_cmd_cab_type {
+ /**
+* No idle optimizations (i.e. no CAB)
+*/
DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
+ /**
+* No DCN requests for memory
+*/
DMUB_CMD__CAB_NO_DCN_REQ = 1,
+ /**
+* Fit surfaces in CAB (i.e. CAB enable)
+*/
DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
};
/**
- * struct dmub_rb_cmd_cab_for_ss - TODO:
+ * struct dmub_rb_cmd_cab - CAB command data.
*/
struct dmub_rb_cmd_cab_for_ss {
struct dmub_cmd_header header;
@@ -1006,6 +1016,9 @@ struct dmub_rb_cmd_cab_for_ss {
uint8_t debug_bits; /* debug bits */
};
+/**
+ * Enum for indicating which MCLK switch mode per pipe
+ */
enum mclk_switch_mode {
NONE = 0,
FPO = 1,
--
2.34.1
[PATCH 61/66] drm/amd/display: fix dpms_off issue when disabling bios mode
From: Zhongwei
[Why]
disable_vbios_mode_if_required() will set dpms_off to false during boot
when pixel clk dismatches with driver requires. This will cause extra
backlight on and off if OS call 2 times setmode.
[How]
Set dpms_off to true to keep power_off and let OS control backlight by
display's powerState.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Zhongwei
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 9304eb66a1af..238a13266ad8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1268,7 +1268,7 @@ static void disable_vbios_mode_if_required(
if (pix_clk_100hz !=
requested_pix_clk_100hz) {
dc->link_srv->set_dpms_off(pipe);
- pipe->stream->dpms_off = false;
+ pipe->stream->dpms_off = true;
}
}
}
--
2.34.1
[PATCH 59/66] drm/amd/display: Set min_width and min_height capability for DCN30
From: Igor Kravchenko
Add min_width, min_height fields to dc_plane_cap structure. Set values
to 16x16 for discrete ASICs, and 64x64 for others.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Igor Kravchenko
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 965f5ceb33f7..67a34cda3774 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -701,7 +701,9 @@ static const struct dc_plane_cap plane_cap = {
.argb = 167,
.nv12 = 167,
.fp16 = 167
- }
+ },
+ 16,
+ 16
};
static const struct dc_debug_options debug_defaults_drv = {
--
2.34.1
[PATCH 58/66] drm/amd/display: Adjust dmub outbox notification enable
From: Meenakshikumar Somasundaram [Why] Currently driver enables dmub outbox notification before oubox ISR is registered. During boot scenario, sometimes dmub issues hpd outbox message before driver registers ISR and those messages are missed. [How] Enable dmub outbox notification after outbox ISR is registered. Also, restructured outbox enable code to call from dm layer and renamed APIs. Reviewed-by: Rodrigo Siqueira Signed-off-by: Meenakshikumar Somasundaram --- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c index e0c74868d2ee..890268d95495 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c @@ -197,10 +197,6 @@ void dcn31_init_hw(struct dc *dc) } } - /* Enables outbox notifications for usb4 dpia */ - if (dc->res_pool->usb4_dpia_count) - dmub_enable_outbox_notification(dc->ctx->dmub_srv); - /* we want to turn off all dp displays before doing detection */ dc->link_srv->blank_all_dp_displays(dc); -- 2.34.1
[PATCH 54/66] drm/amd/display: Limit nv21 dst_y
From: Dmytro Laktyushkin
Dst_y can become negative in extreme odm 4to1 cases. While not strictly
invalid, this should be limited to 0 for rq/dlg/ttu calculation.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
index cd3cfcb2a2b0..0497a5d74a62 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
@@ -980,7 +980,7 @@ static void dml_rq_dlg_get_dlg_params(struct
display_mode_lib *mode_lib,
unsigned int vstartup_start = 0;
unsigned int dst_x_after_scaler = 0;
- unsigned int dst_y_after_scaler = 0;
+ int dst_y_after_scaler = 0;
double line_wait = 0;
double dst_y_prefetch = 0;
double dst_y_per_vm_vblank = 0;
@@ -1171,6 +1171,8 @@ static void dml_rq_dlg_get_dlg_params(struct
display_mode_lib *mode_lib,
dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param,
num_pipes, pipe_idx);
dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param,
num_pipes, pipe_idx);
+ if (dst_y_after_scaler < 0)
+ dst_y_after_scaler = 0;
// do some adjustment on the dst_after scaler to account for odm
combine mode
dml_print("DML_DLG: %s: input dst_x_after_scaler =
%d\n",
--
2.34.1
[PATCH 56/66] drm/amd/display: Add extra check for 444 16 format
From: Aurabindo Pillai
DCN30 is missing a check for the pixel format 444 when using 16bits
before setting the flag that Viewport exceeds the surface.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index dea2b84e5ebe..9af1a43c042b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -5130,7 +5130,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
ViewportExceedsSurface = true;
if (v->SourcePixelFormat[k] != dm_444_64 &&
v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
- && v->SourcePixelFormat[k] != dm_444_8 &&
v->SourcePixelFormat[k] != dm_rgbe) {
+ && v->SourcePixelFormat[k] != dm_444_16 &&
v->SourcePixelFormat[k] != dm_444_8 && v->SourcePixelFormat[k] != dm_rgbe) {
if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k] ||
v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
ViewportExceedsSurface = true;
}
--
2.34.1
[PATCH 57/66] drm/amd/display: 3-plane MPO enablement for DCN321
From: Krunoslav Kovac Enable 3-planes MPO for DCN321 by reporting max_slave_planes in DC caps for each ASIC. Reviewed-by: Rodrigo Siqueira Signed-off-by: Krunoslav Kovac --- drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index cf21b240fc55..138657c38afe 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -1727,9 +1727,9 @@ static bool dcn321_resource_construct( dc->caps.subvp_pstate_allow_width_us = 20; dc->caps.subvp_vertical_int_margin_us = 30; dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin - dc->caps.max_slave_planes = 1; - dc->caps.max_slave_yuv_planes = 1; - dc->caps.max_slave_rgb_planes = 1; + dc->caps.max_slave_planes = 2; + dc->caps.max_slave_yuv_planes = 2; + dc->caps.max_slave_rgb_planes = 2; dc->caps.post_blend_color_processing = true; dc->caps.force_dp_tps4_for_cp2520 = true; dc->caps.dp_hpo = true; -- 2.34.1
[PATCH 55/66] drm/amd/display: correct DML calc error
From: Sherry Wang
[Why]
DML calculation is different from HW formula.
[How]
Correct the bug to keep it same as HW formula.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Sherry Wang
---
.../gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c| 4 ++--
.../gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c| 4 ++--
.../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 7d0626e42ea6..dea2b84e5ebe 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -4939,8 +4939,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
}
v->TotImmediateFlipBytes = 0.0;
for (k = 0; k <=
v->NumberOfActivePlanes - 1; k++) {
- v->TotImmediateFlipBytes =
v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] *
v->PDEAndMetaPTEBytesPerFrame[i][j][k]
- +
v->MetaRowBytes[i][j][k] + v->DPTEBytesPerRow[i][j][k];
+ v->TotImmediateFlipBytes =
v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] *
(v->PDEAndMetaPTEBytesPerFrame[i][j][k]
+ +
v->MetaRowBytes[i][j][k] + v->DPTEBytesPerRow[i][j][k]);
}
for (k = 0; k <=
v->NumberOfActivePlanes - 1; k++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index bd674dc30df3..330b089d6a86 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -5274,8 +5274,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
v->TotImmediateFlipBytes = 0.0;
for (k = 0; k <
v->NumberOfActivePlanes; k++) {
v->TotImmediateFlipBytes =
v->TotImmediateFlipBytes
- +
v->NoOfDPP[i][j][k] * v->PDEAndMetaPTEBytesPerFrame[i][j][k] +
v->MetaRowBytes[i][j][k]
- +
v->DPTEBytesPerRow[i][j][k];
+ +
v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] +
v->MetaRowBytes[i][j][k]
+ +
v->DPTEBytesPerRow[i][j][k]);
}
for (k = 0; k <
v->NumberOfActivePlanes; k++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index 7eb2173b7691..27b83162ae45 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -5371,8 +5371,8 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_
v->TotImmediateFlipBytes = 0.0;
for (k = 0; k <
v->NumberOfActivePlanes; k++) {
v->TotImmediateFlipBytes =
v->TotImmediateFlipBytes
- +
v->NoOfDPP[i][j][k] * v->PDEAndMetaPTEBytesPerFrame[i][j][k] +
v->MetaRowBytes[i][j][k]
- +
v->DPTEBytesPerRow[i][j][k];
+ +
v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] +
v->MetaRowBytes[i][j][k]
+ +
v->DPTEBytesPerRow[i][j][k]);
}
for (k = 0; k <
v->NumberOfActivePlanes; k++) {
--
2.34.1
[PATCH 53/66] drm/amd/display: Isolate remaining FPU code in DCN32
From: Jasdeep Dhillon
[Why]
DCN32 resource contains code that uses FPU.
[How]
Moved code into DCN32 FPU
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Jasdeep Dhillon
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 6 ++
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 2f7723053042..b8a2518faecc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2881,3 +2881,9 @@ bool dcn32_find_vactive_pipe(struct dc *dc, const struct
dc_state *context, uint
}
return vactive_found;
}
+
+void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb)
+{
+ dc_assert_fp_enabled();
+ dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
index 9a0806a0e2ef..dcf512cd3072 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
@@ -80,4 +80,6 @@ void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const
struct dc_state *co
bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context,
uint32_t vactive_margin_req);
+void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb);
+
#endif
--
2.34.1
[PATCH 52/66] drm/amd/display: Remove DET check from DCN32
From: Aurabindo Pillai Drop duplicate check for DET Swath in DCN32. Reviewed-by: Rodrigo Siqueira Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index e90ddc33c27e..13c7e7394b1c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -1697,7 +1697,6 @@ static void mode_support_configuration(struct vba_vars_st *v, && mode_lib->vba.PTEBufferSizeNotExceeded[i][j] == true && mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] == true && mode_lib->vba.NonsupportedDSCInputBPC == false - && mode_lib->vba.NotEnoughDETSwathFillLatencyHidingPerState[i][j] == false && !mode_lib->vba.ExceededMALLSize && (mode_lib->vba.NotEnoughDETSwathFillLatencyHidingPerState[i][j] == false || i == v->soc.num_states - 1) -- 2.34.1
[PATCH 50/66] drm/amd/display: Set DRAM clock if retraining is required
From: Aurabindo Pillai
Set DRAM clock change state if retraining is required.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index cad2bc3aea67..d39e77d95fc3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -4338,7 +4338,7 @@ void
dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
+ v->WritebackChunkSize * 1024.0 / 32.0 /
SOCCLK;
}
if (v->USRRetrainingRequiredFinal)
- v->Watermark.WritebackUrgentWatermark =
v->Watermark.WritebackUrgentWatermark
+ v->Watermark.WritebackDRAMClockChangeWatermark =
v->Watermark.WritebackDRAMClockChangeWatermark
+ mmSOCParameters.USRRetrainingLatency;
if (TotalActiveWriteback <= 1) {
--
2.34.1
[PATCH 51/66] drm/amd/display: Add check for PState change in DCN32
From: Aurabindo Pillai
For pstate change, allow DML to loop through
all possible prefetch combinations so as to
support more display configurations. Set the max
and min prefetch modes to enable the sequence.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 4
1 file changed, 4 insertions(+)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index d39e77d95fc3..a50e7f4dce42 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -4656,6 +4656,10 @@ void dml32_CalculateMinAndMaxPrefetchMode(
} else if (AllowForPStateChangeOrStutterInVBlankFinal ==
dm_prefetch_support_uclk_fclk_and_stutter) {
*MinPrefetchMode = 0;
*MaxPrefetchMode = 0;
+ } else if (AllowForPStateChangeOrStutterInVBlankFinal ==
+ dm_prefetch_support_uclk_fclk_and_stutter_if_possible) {
+ *MinPrefetchMode = 0;
+ *MaxPrefetchMode = 3;
} else {
*MinPrefetchMode = 0;
*MaxPrefetchMode = 3;
--
2.34.1
[PATCH 48/66] drm/amd/display: Update bounding box values for DCN321
From: Aurabindo Pillai
[Why&how]
Update bounding box values as per hardware spec
Fixes: 1951340bd31a ("drm/amd/display: Create dcn321_fpu file")
Acked-by: Leo Li
Signed-off-by: Aurabindo Pillai
---
.../amd/display/dc/dml/dcn321/dcn321_fpu.c| 24 +--
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
index 57b9bd896678..342a1bcb4927 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
@@ -106,16 +106,16 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
.clock_limits = {
{
.state = 0,
- .dcfclk_mhz = 1564.0,
- .fabricclk_mhz = 400.0,
- .dispclk_mhz = 2150.0,
- .dppclk_mhz = 2150.0,
+ .dcfclk_mhz = 1434.0,
+ .fabricclk_mhz = 2250.0,
+ .dispclk_mhz = 1720.0,
+ .dppclk_mhz = 1720.0,
.phyclk_mhz = 810.0,
.phyclk_d18_mhz = 667.0,
- .phyclk_d32_mhz = 625.0,
+ .phyclk_d32_mhz = 313.0,
.socclk_mhz = 1200.0,
- .dscclk_mhz = 716.667,
- .dram_speed_mts = 1600.0,
+ .dscclk_mhz = 573.333,
+ .dram_speed_mts = 16000.0,
.dtbclk_mhz = 1564.0,
},
},
@@ -125,14 +125,14 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
.sr_exit_z8_time_us = 285.0,
.sr_enter_plus_exit_z8_time_us = 320,
.writeback_latency_us = 12.0,
- .round_trip_ping_latency_dcfclk_cycles = 263,
+ .round_trip_ping_latency_dcfclk_cycles = 207,
.urgent_latency_pixel_data_only_us = 4,
.urgent_latency_pixel_mixed_with_vm_data_us = 4,
.urgent_latency_vm_data_only_us = 4,
- .fclk_change_latency_us = 20,
- .usr_retraining_latency_us = 2,
- .smn_latency_us = 2,
- .mall_allocated_for_dcn_mbytes = 64,
+ .fclk_change_latency_us = 7,
+ .usr_retraining_latency_us = 0,
+ .smn_latency_us = 0,
+ .mall_allocated_for_dcn_mbytes = 32,
.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
--
2.34.1
[PATCH 49/66] drm/amd/display: add support for low bpc
From: Aurabindo Pillai
[WHY&HOW]
Low bpc timings are failing validation, port a patch to allow them to pass.
Signed-off-by: Dillon Varone
Acked-by: Aurabindo Pillai
---
.../dc/dml/dcn32/display_mode_vba_util_32.c| 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 61cc4904ade4..cad2bc3aea67 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -1595,7 +1595,6 @@ double dml32_TruncToValidBPP(
unsigned int NonDSCBPP0;
unsigned int NonDSCBPP1;
unsigned int NonDSCBPP2;
- unsigned int NonDSCBPP3;
if (Format == dm_420) {
NonDSCBPP0 = 12;
@@ -1604,10 +1603,9 @@ double dml32_TruncToValidBPP(
MinDSCBPP = 6;
MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16;
} else if (Format == dm_444) {
- NonDSCBPP0 = 18;
- NonDSCBPP1 = 24;
- NonDSCBPP2 = 30;
- NonDSCBPP3 = 36;
+ NonDSCBPP0 = 24;
+ NonDSCBPP1 = 30;
+ NonDSCBPP2 = 36;
MinDSCBPP = 8;
MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16;
} else {
@@ -1661,9 +1659,7 @@ double dml32_TruncToValidBPP(
else
return dml_floor(16.0 * MaxLinkBPP, 1.0) / 16.0;
} else {
- if (MaxLinkBPP >= NonDSCBPP3)
- return NonDSCBPP3;
- else if (MaxLinkBPP >= NonDSCBPP2)
+ if (MaxLinkBPP >= NonDSCBPP2)
return NonDSCBPP2;
else if (MaxLinkBPP >= NonDSCBPP1)
return NonDSCBPP1;
@@ -1674,7 +1670,7 @@ double dml32_TruncToValidBPP(
}
} else {
if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 ||
DesiredBPP == NonDSCBPP1 ||
- DesiredBPP == NonDSCBPP0 || DesiredBPP ==
NonDSCBPP3)) ||
+ DesiredBPP <= NonDSCBPP0)) ||
(DSCEnable && DesiredBPP >= MinDSCBPP &&
DesiredBPP <= MaxDSCBPP)))
return BPP_INVALID;
else
--
2.34.1
[PATCH 47/66] drm/amd/display: Do not clear GPINT register when releasing DMUB from reset
From: Aurabindo Pillai
[Why & How]
There's no need to clear GPINT register for DMUB
when releasing it from reset. Fix that.
Fixes: ac2e555e0a7f ("drm/amd/display: Add DMCUB source files and changes for
DCN32/321")
Reviewed-by: Leo Li
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
index b45ac31ba555..a7d5607459ed 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -137,7 +137,6 @@ void dmub_dcn32_reset(struct dmub_srv *dmub)
void dmub_dcn32_reset_release(struct dmub_srv *dmub)
{
- REG_WRITE(DMCUB_GPINT_DATAIN1, 0);
REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
--
2.34.1
[PATCH 45/66] drm/amd/display: Clear GPINT1 before taking DMCUB out of reset
From: Samson Tam [Why] Workaround for DMCUB front door load [How] Clear GPINT after reset so its consistent Signed-off-by: Samson Tam Acked-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c index a76da0131add..568a2702d5f7 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c @@ -116,10 +116,6 @@ void dmub_dcn32_reset(struct dmub_srv *dmub) break; } - /* Clear the GPINT command manually so we don't reset again. */ - cmd.all = 0; - dmub->hw_funcs.set_gpint(dmub, cmd); - /* Force reset in case we timed out, DMCUB is likely hung. */ } @@ -131,6 +127,10 @@ void dmub_dcn32_reset(struct dmub_srv *dmub) REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); REG_WRITE(DMCUB_SCRATCH0, 0); + + /* Clear the GPINT command manually so we don't reset again. */ + cmd.all = 0; + dmub->hw_funcs.set_gpint(dmub, cmd); } void dmub_dcn32_reset_release(struct dmub_srv *dmub) -- 2.34.1
[PATCH 44/66] drm/amd/display: Fixes for dcn32_clk_mgr implementation
From: Aurabindo Pillai
[Why&How]
Fix CLK MGR early initialization and add logging.
Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Reviewed-by: Leo Li
Reviewed-by: Qingqing Zhuo
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 2b8a81b6d53b..eea103908b09 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -905,6 +905,8 @@ void dcn32_clk_mgr_construct(
struct pp_smu_funcs *pp_smu,
struct dccg *dccg)
{
+ struct clk_log_info log_info = {0};
+
clk_mgr->base.ctx = ctx;
clk_mgr->base.funcs = &dcn32_funcs;
if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
@@ -938,6 +940,7 @@ void dcn32_clk_mgr_construct(
clk_mgr->base.clks.ref_dtbclk_khz = 268750;
}
+
/* integer part is now VCO frequency in kHz */
clk_mgr->base.dentist_vco_freq_khz =
dcn32_get_vco_frequency_from_reg(clk_mgr);
@@ -945,6 +948,8 @@ void dcn32_clk_mgr_construct(
if (clk_mgr->base.dentist_vco_freq_khz == 0)
clk_mgr->base.dentist_vco_freq_khz = 430; /* Updated as per
HW docs */
+ dcn32_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base,
&log_info);
+
if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
clk_mgr->base.clks.ref_dtbclk_khz !=
clk_mgr->base.boot_snapshot.dtbclk) {
clk_mgr->base.clks.ref_dtbclk_khz =
clk_mgr->base.boot_snapshot.dtbclk;
--
2.34.1
[PATCH 46/66] drm/amd/display: Reset OUTBOX0 r/w pointer on DMUB reset
From: Cruise Hung
[Why & How]
We missed resetting OUTBOX0 mailbox r/w pointer on DMUB reset.
Fix it.
Fixes: 6ecf9773a503 ("drm/amd/display: Fix DMUB outbox trace in S4")
Signed-off-by: Cruise Hung
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
index 568a2702d5f7..b45ac31ba555 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -126,6 +126,8 @@ void dmub_dcn32_reset(struct dmub_srv *dmub)
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
+ REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
+ REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
REG_WRITE(DMCUB_SCRATCH0, 0);
/* Clear the GPINT command manually so we don't reset again. */
--
2.34.1
[PATCH 43/66] drm/amd/display: Update DTBCLK for DCN32
From: Alvin Lee
[Why&How]
- Implement interface to program DTBCLK DTO’s
according to reference DTBCLK returned by PMFW
- This is required because DTO programming
requires exact DTBCLK reference freq or it could
result in underflow
Acked-by: Aurabindo Pillai
Signed-off-by: Alvin Lee
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index ea753f8fa175..2b8a81b6d53b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -233,6 +233,32 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
DC_FP_END();
}
+static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal
*clk_mgr,
+ struct dc_state *context,
+ int ref_dtbclk_khz)
+{
+ struct dccg *dccg = clk_mgr->dccg;
+ uint32_t tg_mask = 0;
+ int i;
+
+ for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+ struct dtbclk_dto_params dto_params = {0};
+
+ /* use mask to program DTO once per tg */
+ if (pipe_ctx->stream_res.tg &&
+ !(tg_mask & (1 <<
pipe_ctx->stream_res.tg->inst))) {
+ tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
+
+ dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
+ dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
+
+ dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
+ //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg,
&dto_params);
+ }
+ }
+}
+
/* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming),
* update DPPCLK to be the exact frequency that will be set after the DPPCLK
* divider is updated. This will prevent rounding issues that could cause DPP
@@ -570,6 +596,7 @@ static void dcn32_update_clocks(struct clk_mgr
*clk_mgr_base,
/* DCCG requires KHz precision for DTBCLK */
clk_mgr_base->clks.ref_dtbclk_khz =
dcn32_smu_set_hard_min_by_freq(clk_mgr,
PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
+ dcn32_update_clocks_update_dtb_dto(clk_mgr, context,
clk_mgr_base->clks.ref_dtbclk_khz);
}
if (dc->config.forced_clocks == false || (force_reset &&
safe_to_lower)) {
--
2.34.1
[PATCH 41/66] drm/amd/display: Disable migration to ensure consistency of per-CPU variable
From: Tianci Yin
[why]
Since the variable fpu_recursion_depth is per-CPU type, it has one copy
on each CPU, thread migration causes data consistency issue, then the
call trace shows up. And preemption disabling can't prevent migration.
[how]
Disable migration to ensure consistency of fpu_recursion_depth.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Tianci Yin
---
drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
index 1743ca0a3641..c42aa947c969 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
@@ -89,6 +89,7 @@ void dc_fpu_begin(const char *function_name, const int line)
if (*pcpu == 1) {
#if defined(CONFIG_X86)
+ migrate_disable();
kernel_fpu_begin();
#elif defined(CONFIG_PPC64)
if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
@@ -129,6 +130,7 @@ void dc_fpu_end(const char *function_name, const int line)
if (*pcpu <= 0) {
#if defined(CONFIG_X86)
kernel_fpu_end();
+ migrate_enable();
#elif defined(CONFIG_PPC64)
if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
disable_kernel_vsx();
--
2.34.1
[PATCH 42/66] drm/amd/display: Add logging for display MALL refresh setting
From: Wesley Chalmers
[WHY]
Add log entry for when display refresh from MALL
settings are sent to SMU.
Fixes: 1664641ea946 ("drm/amd/display: Add logger for SMU msg")
Signed-off-by: Wesley Chalmers
Acked-by: Aurabindo Pillai
---
.../drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
index 1fbf1c105dc1..bdbf18306698 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
@@ -312,6 +312,9 @@ void dcn30_smu_set_display_refresh_from_mall(struct
clk_mgr_internal *clk_mgr, b
/* bits 8:7 for cache timer scale, bits 6:1 for cache timer delay, bit
0 = 1 for enable, = 0 for disable */
uint32_t param = (cache_timer_scale << 7) | (cache_timer_delay << 1) |
(enable ? 1 : 0);
+ smu_print("SMU Set display refresh from mall: enable = %d,
cache_timer_delay = %d, cache_timer_scale = %d\n",
+ enable, cache_timer_delay, cache_timer_scale);
+
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_SetDisplayRefreshFromMall, param, NULL);
}
--
2.34.1
[PATCH 40/66] drm/amd/display: Write TEST_EDID_CHECKSUM_WRITE for EDID tests
From: Mikita Lipski
Extract edid's checksum and send it back for verification if EDID_TEST
is requested.
Signed-off-by: Mikita Lipski
Acked-by: Aurabindo Pillai
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 30 +--
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index c6ce2b7123b7..09e056a64708 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -885,10 +885,34 @@ enum dc_edid_status dm_helpers_read_local_edid(
DRM_ERROR("EDID err: %d, on connector: %s",
edid_status,
aconnector->base.name);
+ if (link->aux_mode) {
+ union test_request test_request = {0};
+ union test_response test_response = {0};
- /* DP Compliance Test 4.2.2.3 */
- if (link->aux_mode)
- drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux,
sink->dc_edid.raw_edid[sink->dc_edid.length-1]);
+ dm_helpers_dp_read_dpcd(ctx,
+ link,
+ DP_TEST_REQUEST,
+ &test_request.raw,
+ sizeof(union test_request));
+
+ if (!test_request.bits.EDID_READ)
+ return edid_status;
+
+ test_response.bits.EDID_CHECKSUM_WRITE = 1;
+
+ dm_helpers_dp_write_dpcd(ctx,
+ link,
+ DP_TEST_EDID_CHECKSUM,
+
&sink->dc_edid.raw_edid[sink->dc_edid.length-1],
+ 1);
+
+ dm_helpers_dp_write_dpcd(ctx,
+ link,
+ DP_TEST_RESPONSE,
+ &test_response.raw,
+ sizeof(test_response));
+
+ }
return edid_status;
}
--
2.34.1
[PATCH 38/66] drm/amd/display: Return error code on DSC atomic check failure
From: hersen wu
[Why&How]
We were not returning -EINVAL on DSC atomic check fail. Add it.
Fixes: 71be4b16d39a ("drm/amd/display: dsc validate fail not pass to atomic
check")
Reviewed-by: Aurabindo Pillai
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 71e3bc9e7f8f..dfcb9815b5a8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -10169,6 +10169,7 @@ static int amdgpu_dm_atomic_check(struct drm_device
*dev,
ret = compute_mst_dsc_configs_for_state(state,
dm_state->context, vars);
if (ret) {
DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state()
failed\n");
+ ret = -EINVAL;
goto fail;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 5dc79b753d5f..810ab682f424 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1410,6 +1410,7 @@ int pre_validate_dsc(struct drm_atomic_state *state,
ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state,
vars);
if (ret != 0) {
DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state()
failed\n");
+ ret = -EINVAL;
goto clean_exit;
}
--
2.34.1
[PATCH 39/66] drm/amd/display: remove incorrect early return
From: Aurabindo Pillai [Why&How] Remove incorrect early return in a device specific fifo reset workaround Reviewed-by: Leo Li Reviewed-by: Qingqing Zhuo Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 330ab036c830..c6ce2b7123b7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -687,7 +687,6 @@ static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) return; data[0] |= (1 << 1); // set bit 1 to 1 - return; if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) return; -- 2.34.1
[PATCH 35/66] drm/amd/display: limit timing for single dimm memory
From: Daniel Miess
[Why]
1. It could hit bandwidth limitdation under single dimm
memory when connecting 8K external monitor.
2. IsSupportedVidPn got validation failed with
2K240Hz eDP + 8K24Hz external monitor.
3. It's better to filter out such combination in
EnumVidPnCofuncModality
4. For short term, filter out in dc bandwidth validation.
[How]
Force 2K@240Hz+8K@24Hz timing validation false in dc.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Daniel Miess
---
.../amd/display/dc/dcn314/dcn314_resource.c | 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 50ed7e09d5ba..24806acc8438 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -1696,6 +1696,23 @@ static void dcn314_get_panel_config_defaults(struct
dc_panel_config *panel_confi
*panel_config = panel_config_defaults;
}
+static bool filter_modes_for_single_channel_workaround(struct dc *dc,
+ struct dc_state *context)
+{
+ // Filter 2K@240Hz+8K@24fps above combination timing if memory only has
single dimm LPDDR
+ if (dc->clk_mgr->bw_params->vram_type == 34 &&
dc->clk_mgr->bw_params->num_channels < 2) {
+ int total_phy_pix_clk = 0;
+
+ for (int i = 0; i < context->stream_count; i++)
+ if (context->res_ctx.pipe_ctx[i].stream)
+ total_phy_pix_clk +=
context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
+
+ if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps
+ return true;
+ }
+ return false;
+}
+
bool dcn314_validate_bandwidth(struct dc *dc,
struct dc_state *context,
bool fast_validate)
@@ -1711,6 +1728,9 @@ bool dcn314_validate_bandwidth(struct dc *dc,
BW_VAL_TRACE_COUNT();
+ if (filter_modes_for_single_channel_workaround(dc, context))
+ goto validate_fail;
+
DC_FP_START();
// do not support self refresh only
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt,
&vlevel, fast_validate, false);
--
2.34.1
[PATCH 37/66] drm/amd/display: add mechanism to skip DCN init
From: Eric Yang
[Why]
If optimized init is done in FW. DCN init can be skipped in driver. This
need to be communicated between driver and fw and maintain backwards
compatibility.
[How]
Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and
use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow
so FW will perform it.
Signed-off-by: Eric Yang
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 --
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 28 +--
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 2 +-
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 ++-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 -
.../gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 6
.../gpu/drm/amd/display/dmub/src/dmub_dcn21.h | 4 ---
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 25 +
8 files changed, 12 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index da6cf3ca372c..9304eb66a1af 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4288,9 +4288,6 @@ void dc_set_power_state(
dc_z10_restore(dc);
- if (dc->ctx->dmub_srv)
- dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
-
dc->hwss.init_hw(dc);
if (dc->hwss.init_sys_ctx != NULL &&
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index eef43577508c..d15ec32243e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -179,31 +179,17 @@ bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv
*dc_dmub_srv, unsigned int coun
return true;
}
-void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
+bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
{
- struct dmub_srv *dmub = dc_dmub_srv->dmub;
- struct dc_context *dc_ctx = dc_dmub_srv->ctx;
- enum dmub_status status;
-
- for (;;) {
- /* Wait up to a second for PHY init. */
- status = dmub_srv_wait_for_phy_init(dmub, 100);
- if (status == DMUB_STATUS_OK)
- /* Initialization OK */
- break;
+ struct dmub_srv *dmub;
+ union dmub_fw_boot_status status;
- DC_ERROR("DMCUB PHY init failed: status=%d\n", status);
- ASSERT(0);
+ if (!dc_dmub_srv || !dc_dmub_srv->dmub)
+ return false;
- if (status != DMUB_STATUS_TIMEOUT)
- /*
-* Server likely initialized or we don't have
-* DMCUB HW support - this won't end.
-*/
- break;
+ dmub = dc_dmub_srv->dmub;
- /* Continue spinning so we don't hang the ASIC. */
- }
+ return status.bits.optimized_init_done;
}
bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 22f7b2704c8e..a5196a9292b3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -54,7 +54,7 @@ struct dc_dmub_srv {
void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv);
-void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv);
+bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv);
bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd
*cmd, enum dm_dmub_wait_type wait_type);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 1c3b6f25a782..a7ad1d7bc43e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1524,7 +1524,9 @@ void dcn10_init_hw(struct dc *dc)
if (!dcb->funcs->is_accelerated_mode(dcb))
hws->funcs.disable_vga(dc->hwseq);
- hws->funcs.bios_golden_init(dc);
+ if (!dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv))
+ hws->funcs.bios_golden_init(dc);
+
if (dc->ctx->dc_bios->fw_info_valid) {
res_pool->ref_clocks.xtalin_clock_inKhz =
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index ba1715e2d25a..719bf9bb168a 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -366,7 +366,6 @@ struct dmub_srv_hw_funcs {
bool (*is_hw_init)(struct dmub_srv *dmub);
- bool (*is_phy_init)(struct dmub_srv *dmub);
void (*enable_dmub_boot_options)(struct dmub_srv *dmub,
const struct dmub_srv_hw_
[PATCH 36/66] drm/amd/display: set dcn315 lb bpp to 48
From: Dmytro Laktyushkin
[Why & How]
Fix a typo for dcn315 line buffer bpp.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index b37d14369a62..59836570603a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -222,7 +222,7 @@ struct _vcs_dpi_ip_params_st dcn3_15_ip = {
.maximum_dsc_bits_per_component = 10,
.dsc422_native_support = false,
.is_line_buffer_bpp_fixed = true,
- .line_buffer_fixed_bpp = 49,
+ .line_buffer_fixed_bpp = 48,
.line_buffer_size_bits = 789504,
.max_line_buffer_lines = 12,
.writeback_interface_buffer_size_kbytes = 90,
--
2.34.1
[PATCH 32/66] drm/amd/display: add extra dc odm debug options
From: Dmytro Laktyushkin
[Why & How]
Add options for dc odm debug.
Reviewed-by: Ariel Bernstein
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dc.h| 2 ++
drivers/gpu/drm/amd/display/dc/dc_stream.h | 5 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 23ee63b98dcd..3595149deceb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -879,6 +879,8 @@ struct dc_debug_options {
uint32_t fpo_vactive_margin_us;
bool disable_fpo_vactive;
bool disable_boot_optimizations;
+ bool override_odm_optimization;
+ bool minimize_dispclk_using_odm;
};
struct gpu_info_soc_bounding_box_v1_0;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 270282fbda4a..0add5ecc895f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -172,6 +172,10 @@ struct mall_temp_config {
bool is_phantom_plane[MAX_PIPES];
};
+struct dc_stream_debug_options {
+ char force_odm_combine_segments;
+};
+
struct dc_stream_state {
// sink is deprecated, new code should not reference
// this pointer
@@ -182,6 +186,7 @@ struct dc_stream_state {
* a stream via the volatile dc_state rather than the static dc_link.
*/
struct link_encoder *link_enc;
+ struct dc_stream_debug_options debug;
struct dc_panel_patch sink_patches;
union display_content_support content_support;
struct dc_crtc_timing timing;
--
2.34.1
[PATCH 31/66] drm/amd/display: fix a divided-by-zero error
From: Alex Hung [Why & How] timing.dsc_cfg.num_slices_v can be zero and it is necessary to check before using it. This fixes the error "divide error: [#1] PREEMPT SMP NOPTI". Reviewed-by: Aurabindo Pillai Acked-by: Qingqing Zhuo Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index 0d3a983cb9ec..51e76bce92ea 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -927,6 +927,10 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link, pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; + + if (stream->timing.dsc_cfg.num_slices_v == 0) + return false; + slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v; config->dsc_slice_height = slice_height; -- 2.34.1
[PATCH 34/66] drm/amd/display: Improvement for handling edp link training fails
From: Jingwen Zhu
[Why]
The eDP retrain will cause the DPCD 300 to be reset to default.
And cause the brightness can't be set correctly.
[How]
delete the call to edp panel power control in both
enable_link_output/disable_link_output entirely and
only call edp panel control in enable_link_dp and
disable_link_dp once.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Jingwen Zhu
---
.../display/dc/dce110/dce110_hw_sequencer.c | 19 +++
.../gpu/drm/amd/display/dc/link/link_dpms.c | 5 +
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 9fe0ce91db00..8d2460d06bce 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -3031,10 +3031,12 @@ void dce110_enable_dp_link_output(
const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
unsigned int i;
-
+ /*
+* Add the logic to extract BOTH power up and power down sequences
+* from enable/disable link output and only call edp panel control
+* in enable_link_dp and disable_link_dp once.
+*/
if (link->connector_signal == SIGNAL_TYPE_EDP) {
- if (!link->dc->config.edp_no_power_sequencing)
- link->dc->hwss.edp_power_control(link, true);
link->dc->hwss.edp_wait_for_hpd_ready(link, true);
}
@@ -3096,11 +3098,12 @@ void dce110_disable_link_output(struct dc_link *link,
link_hwss->disable_link_output(link, link_res, signal);
link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
-
- if (signal == SIGNAL_TYPE_EDP &&
- link->dc->hwss.edp_backlight_control)
- link->dc->hwss.edp_power_control(link, false);
- else if (dmcu != NULL && dmcu->funcs->lock_phy)
+ /*
+* Add the logic to extract BOTH power up and power down sequences
+* from enable/disable link output and only call edp panel control
+* in enable_link_dp and disable_link_dp once.
+*/
+ if (dmcu != NULL && dmcu->funcs->lock_phy)
dmcu->funcs->unlock_phy(dmcu);
dc->link_srv->dp_trace_source_sequence(link,
DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
}
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 027ad1f0144d..2267fb097830 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -1927,6 +1927,11 @@ static void disable_link_dp(struct dc_link *link,
dp_disable_link_phy(link, link_res, signal);
+ if (link->connector_signal == SIGNAL_TYPE_EDP) {
+ if (!link->dc->config.edp_no_power_sequencing)
+ link->dc->hwss.edp_power_control(link, false);
+ }
+
if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
/* set the sink to SST mode after disabling the link */
enable_mst_on_sink(link, false);
--
2.34.1
[PATCH 33/66] drm/amd/display: Apply correct panel mode when reinitializing hardware
From: Michael Mityushkin
[Why]
When link training during engine recovery, ASSR might fail causing panel
mode to be reset to default. This should not happen for eDP as it
will prevent the panel from turning back on.
[How]
Added dp_panel_mode to struct dc_link to remember previously applied
panel mode. Do not reset panel mode to default while performing link
training if previously used panel mode = eDP.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Michael Mityushkin
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../gpu/drm/amd/display/dc/link/protocols/link_dp_training.c | 5 -
.../amd/display/dc/link/protocols/link_edp_panel_control.c | 1 +
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3595149deceb..3b53f36029d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1456,6 +1456,7 @@ struct dc_link {
struct ddc_service *ddc;
+ enum dp_panel_mode panel_mode;
bool aux_mode;
/* Private to DC core */
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
index 70fc0ddf2d7e..d9e8b7ceb0b6 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
@@ -1586,7 +1586,10 @@ bool perform_link_training_with_retries(
* Report and continue with eDP panel mode to
* perform eDP link training with right settings
*/
- cp_psp->funcs.enable_assr(cp_psp->handle, link);
+ bool result;
+ result =
cp_psp->funcs.enable_assr(cp_psp->handle, link);
+ if (!result && link->panel_mode !=
DP_PANEL_MODE_EDP)
+ panel_mode = DP_PANEL_MODE_DEFAULT;
}
}
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 5ab2de12ccf8..2039a345f23a 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -83,6 +83,7 @@ void dp_set_panel_mode(struct dc_link *link, enum
dp_panel_mode panel_mode)
ASSERT(result == DC_OK);
}
}
+ link->panel_mode = panel_mode;
DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
"eDP panel mode enabled: %d \n",
link->link_index,
--
2.34.1
[PATCH 30/66] drm/amd/display: [FW Promotion] Release 0.0.162.0
From: Anthony Koo
- Add DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command
- Remove d3 entry event and instead check for stream mask
- dmu: Enable timeout recovery and detection for p-state
Acked-by: Qingqing Zhuo
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 1c55d3b01f53..54b7786f5681 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -419,7 +419,8 @@ union dmub_fw_boot_options {
uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int
enable supported */
uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW
allocation supported */
uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and
dppclk_ds*/
- uint32_t reserved : 14; /**< reserved */
+ uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery
should be disabled */
+ uint32_t reserved : 13; /**< reserved */
} bits; /**< boot bits */
uint32_t all; /**< 32-bit access to bits */
};
@@ -1125,8 +1126,6 @@ struct dmub_rb_cmd_idle_opt_dcn_restore {
*/
struct dmub_dcn_notify_idle_cntl_data {
uint8_t driver_idle;
- uint8_t d3_entry;
- uint8_t trigger;
uint8_t pad[1];
};
@@ -3550,6 +3549,10 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
*/
struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
+ /**
+* Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
+*/
+ struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;
};
/**
--
2.34.1
[PATCH 29/66] drm/amd/display: Enable FPO + Vactive
From: Alvin Lee
[Description]
- Enable FPO + Vactive
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index a876e6eb6cd8..4f8286ae699b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -726,7 +726,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.override_dispclk_programming = true,
.disable_fpo_optimizations = false,
.fpo_vactive_margin_us = 2000, // 2000us
- .disable_fpo_vactive = true,
+ .disable_fpo_vactive = false,
.disable_boot_optimizations = false,
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index e5ab7f3077c4..cf21b240fc55 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -725,7 +725,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.override_dispclk_programming = true,
.disable_fpo_optimizations = false,
.fpo_vactive_margin_us = 2000, // 2000us
- .disable_fpo_vactive = true,
+ .disable_fpo_vactive = false,
.disable_boot_optimizations = false,
};
--
2.34.1
[PATCH 26/66] drm/amd/display: DSC policy override when ODM combine is forced
From: Nasir Osman
[why]
When we force ODM combine with DSC, we lose several
8 bit and 10 bit modes in validation and thus
not able to use HDR. This is due to the number of
horizontal slices used in DSC not properly being
accounted for currently when 2:1 ODM Combine is forced.
[how]
Enforce at least two horizontal slices are used for DSC when
ODM combine is forced.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Nasir Osman
---
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 1 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 10 +-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index 0e92a322c2ed..9491b76d61f5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -58,6 +58,7 @@ struct dc_dsc_config_options {
uint32_t dsc_min_slice_height_override;
uint32_t max_target_bpp_limit_override_x16;
uint32_t slice_height_granularity;
+ uint32_t dsc_force_odm_hslice_override;
};
bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 2bdc47615543..b9a05bb025db 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -700,7 +700,7 @@ static int inc_num_slices(union dsc_enc_slice_caps
slice_caps, int num_slices)
}
}
- if (new_num_slices == num_slices) // No biger number of slices found
+ if (new_num_slices == num_slices) // No bigger number of slices found
new_num_slices++;
return new_num_slices;
@@ -952,6 +952,13 @@ static bool setup_dsc_config(
else
is_dsc_possible = false;
}
+ // When we force 2:1 ODM, we can't have 1 slice to divide amongst 2
separate DSC instances
+ // need to enforce at minimum 2 horizontal slices
+ if (options->dsc_force_odm_hslice_override) {
+ num_slices_h = fit_num_slices_up(dsc_common_caps.slice_caps, 2);
+ if (num_slices_h == 0)
+ is_dsc_possible = false;
+ }
if (!is_dsc_possible)
goto done;
@@ -1163,6 +1170,7 @@ void dc_dsc_policy_set_disable_dsc_stream_overhead(bool
disable)
void dc_dsc_get_default_config_option(const struct dc *dc, struct
dc_dsc_config_options *options)
{
options->dsc_min_slice_height_override =
dc->debug.dsc_min_slice_height_override;
+ options->dsc_force_odm_hslice_override = dc->debug.force_odm_combine;
options->max_target_bpp_limit_override_x16 = 0;
options->slice_height_granularity = 1;
}
--
2.34.1
[PATCH 28/66] drm/amd/display: Set watermarks set D equal to A
From: Alvin Lee
[Description]
- Since we do not use optimized watermark settings for MALL,
set D = A
- PMFW uses Set D for d0i3.1, so driver should make D = A for the
time being
- If we choose to optimize in the future we can set watermarks D
correctly
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 23a972f2885f..2f7723053042 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2062,6 +2062,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct
dc_state *context,
* sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after
bringup or later, use as decided in Clk Mgr)
*/
+ /*
if (dcn3_2_soc.num_states > 2) {
vlevel_temp = 0;
dcfclk =
dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
@@ -2088,6 +2089,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct
dc_state *context,
context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns =
get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns
= get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns =
get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ */
/* Set C, for Dummy P-State:
* All clocks min.
@@ -2189,6 +2191,9 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct
dc_state *context,
context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns =
get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
}
+ /* Make set D = set A since we do not optimized watermarks for MALL */
+ context->bw_ctx.bw.dcn.watermarks.d =
context->bw_ctx.bw.dcn.watermarks.a;
+
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
--
2.34.1
[PATCH 27/66] drm/amd/display: Correct output color space during HW reinitialize
From: Michael Mityushkin
[Why]
Doing core_link_disable_stream or set_dpms_off when reinitializing
hardware causes issue to repro with external display connected. This is
unnecessary, blanking pixel data should be sufficient.
[How]
Call disable_pixel_data while reinitializing hardware instead of
core_link_disable_stream or set_dpms_off.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Michael Mityushkin
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c | 1 +
3 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 422fbf79da64..5800acf6aae1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -313,6 +313,10 @@ void dcn20_init_blank(
}
opp = dc->res_pool->opps[opp_id_src0];
+ /* don't override the blank pattern if already enabled with the correct
one. */
+ if (opp->funcs->dpg_is_blanked && opp->funcs->dpg_is_blanked(opp))
+ return;
+
if (num_opps == 2) {
otg_active_width = otg_active_width / 2;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
index 3a32810bbe38..8598ea233ef3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
@@ -58,6 +58,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
.enable_audio_stream = dce110_enable_audio_stream,
.disable_audio_stream = dce110_disable_audio_stream,
.disable_plane = dcn20_disable_plane,
+ .disable_pixel_data = dcn20_disable_pixel_data,
.pipe_control_lock = dcn20_pipe_control_lock,
.interdependent_update_lock = dcn10_lock_all_pipes,
.cursor_lock = dcn10_cursor_lock,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
index 5267e901a35c..ce53339b2e10 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
@@ -60,6 +60,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = {
.enable_audio_stream = dce110_enable_audio_stream,
.disable_audio_stream = dce110_disable_audio_stream,
.disable_plane = dcn20_disable_plane,
+ .disable_pixel_data = dcn20_disable_pixel_data,
.pipe_control_lock = dcn20_pipe_control_lock,
.interdependent_update_lock = dcn10_lock_all_pipes,
.cursor_lock = dcn10_cursor_lock,
--
2.34.1
[PATCH 24/66] drm/amd/display: Add FAMS validation before trying to use it
From: Rodrigo Siqueira
To ensure that FAMS can be used, DC must check if there is VRR support.
This commit adds the required configuration to ensure FAMS can be executed in
the target system.
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++
drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 +
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 7 ++-
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +-
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 9b2003a497b4..da6cf3ca372c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2604,6 +2604,12 @@ static enum surface_update_type
check_update_surfaces_for_stream(
if (stream_update->mst_bw_update)
su_flags->bits.mst_bw = 1;
+
+ if (stream_update->stream &&
stream_update->stream->freesync_on_desktop &&
+ (stream_update->vrr_infopacket ||
stream_update->allow_freesync ||
+ stream_update->vrr_active_variable))
+ su_flags->bits.fams_changed = 1;
+
if (stream_update->crtc_timing_adjust &&
dc_extended_blank_supported(dc))
su_flags->bits.crtc_timing_adjust = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 25284006019c..270282fbda4a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -131,6 +131,7 @@ union stream_update_flags {
uint32_t dsc_changed : 1;
uint32_t mst_bw : 1;
uint32_t crtc_timing_adjust : 1;
+ uint32_t fams_changed : 1;
} bits;
uint32_t raw;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index c95f000b63b2..34b08d90dc1d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -301,7 +301,12 @@ static void
optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *o
void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min,
int vtotal_max)
{
- optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);
+ struct dc *dc = optc->ctx->dc;
+
+ if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
+ dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min,
vtotal_max);
+ else
+ optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);
}
void optc3_tg_init(struct timing_generator *optc)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 598fa1de54ce..1c55d3b01f53 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -360,7 +360,7 @@ union dmub_fw_boot_status {
uint32_t optimized_init_done : 1; /**< 1 if optimized init done
*/
uint32_t restore_required : 1; /**< 1 if driver should call
restore */
uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred
programmed */
- uint32_t reserved : 1;
+ uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred
programmed */
uint32_t detection_required: 1; /**< if detection need to be
triggered by driver */
uint32_t hw_power_init_done: 1; /**< 1 if hw power init is
completed */
} bits; /**< status bits */
--
2.34.1
[PATCH 25/66] drm/amd/display: Adding support for VESA SCR
From: Iswara Nagulendran
[HOW&WHY]
Write DPCD 721 bit 7 to high, and
the appropriate luminance level
to DPCD 734-736 if bit 4 from DPCD register
734 is high, indicating that the panel
luminance control is enabled from the panel side.
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
Signed-off-by: Iswara Nagulendran
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 7 +
.../dc/link/protocols/link_dp_capability.c| 9 +-
.../link/protocols/link_edp_panel_control.c | 29 ---
include/drm/display/drm_dp.h | 3 ++
4 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 49aab1924665..4a7f6497dc5a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -566,6 +566,12 @@ struct dpcd_amd_device_id {
uint8_t dal_version_byte2;
};
+struct target_luminance_value {
+ uint8_t byte0;
+ uint8_t byte1;
+ uint8_t byte2;
+};
+
struct dpcd_source_backlight_set {
struct {
uint8_t byte0;
@@ -1225,6 +1231,7 @@ struct dpcd_caps {
union dp_main_line_channel_coding_cap channel_coding_cap;
union dp_sink_video_fallback_formats fallback_formats;
union dp_fec_capability1 fec_cap1;
+ bool panel_luminance_control;
union dp_cable_id cable_id;
uint8_t edp_rev;
union edp_alpm_caps alpm_caps;
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index eeaceed61bc4..50327a559a47 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -1449,7 +1449,8 @@ bool read_is_mst_supported(struct dc_link *link)
*/
static bool dpcd_read_sink_ext_caps(struct dc_link *link)
{
- uint8_t dpcd_data;
+ uint8_t dpcd_data = 0;
+ uint8_t edp_general_cap2 = 0;
if (!link)
return false;
@@ -1458,6 +1459,12 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)
return false;
link->dpcd_sink_ext_caps.raw = dpcd_data;
+
+ if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &edp_general_cap2,
1) != DC_OK)
+ return false;
+
+ link->dpcd_caps.panel_luminance_control = (edp_general_cap2 &
DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) != 0;
+
return true;
}
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index d895046787bc..5ab2de12ccf8 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -164,14 +164,35 @@ bool edp_set_backlight_level_nits(struct dc_link *link,
*(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms =
(uint16_t)transition_time_in_ms;
- if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
+ if (!link->dpcd_caps.panel_luminance_control) {
+ if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
(uint8_t *)(&dpcd_backlight_set),
sizeof(dpcd_backlight_set)) != DC_OK)
- return false;
+ return false;
- if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
+ if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
&backlight_control, 1) != DC_OK)
- return false;
+ return false;
+ } else {
+ const uint8_t backlight_enable =
DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;
+ struct target_luminance_value *target_luminance = NULL;
+
+ //if target luminance value is greater than 24 bits, clip the
value to 24 bits
+ if (backlight_millinits > 0xFF)
+ backlight_millinits = 0xFF;
+
+ target_luminance = (struct target_luminance_value
*)&backlight_millinits;
+
+ if (core_link_write_dpcd(link,
DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+ &backlight_enable,
+ sizeof(backlight_enable)) != DC_OK)
+ return false;
+
+ if (core_link_write_dpcd(link,
DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,
+ (uint8_t *)(target_luminance),
+ sizeof(struct target_luminance_value)) != DC_OK)
+ return false;
+ }
return true;
}
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index ed10e6b6f99d..f1be179c5f1f 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -973,6 +973,7 @@
#define DP_EDP_GENERAL_CAP_2
[PATCH 21/66] drm/amd/display: refactor dmub commands into single function
From: Josip Pavic
[Why & How]
Consolidate dmub access to a single interface. This makes it easier to
add code in the future that needs to run every time a dmub command is
requested (e.g. instrumentation, locking etc).
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Josip Pavic
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +-
.../drm/amd/display/dc/bios/command_table2.c | 25 +--
.../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 4 +-
.../dc/clk_mgr/dcn314/dcn314_clk_mgr.c| 4 +-
.../dc/clk_mgr/dcn315/dcn315_clk_mgr.c| 4 +-
.../dc/clk_mgr/dcn316/dcn316_clk_mgr.c| 4 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 23 +--
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 164 +++---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 13 +-
drivers/gpu/drm/amd/display/dc/dc_helper.c| 28 +--
.../gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c | 28 +--
.../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 4 +-
.../gpu/drm/amd/display/dc/dce/dmub_outbox.c | 4 +-
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 28 +--
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 7 +-
.../drm/amd/display/dc/dcn21/dcn21_hwseq.c| 8 +-
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 16 +-
.../display/dc/dcn31/dcn31_dio_link_encoder.c | 8 +-
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 10 +-
.../amd/display/dc/dcn31/dcn31_panel_cntl.c | 4 +-
.../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 4 +-
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 12 +-
drivers/gpu/drm/amd/display/dc/dm_services.h | 7 +
.../drm/amd/display/dc/dm_services_types.h| 6 +
.../dc/link/protocols/link_dp_capability.c| 2 +-
.../display/dc/link/protocols/link_dp_dpia.c | 2 +-
26 files changed, 148 insertions(+), 283 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fa2acc017437..ffa2743e92e2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -10310,7 +10310,7 @@ static bool dm_edid_parser_send_cea(struct
amdgpu_display_manager *dm,
input->cea_total_length = total_length;
memcpy(input->payload, data, length);
- res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
+ res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd,
DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
if (!res) {
DRM_ERROR("EDID CEA parser failed\n");
return false;
@@ -10760,3 +10760,13 @@ bool check_seamless_boot_capability(struct
amdgpu_device *adev)
return false;
}
+
+bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd,
enum dm_dmub_wait_type wait_type)
+{
+ return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
+}
+
+bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int
count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
+{
+ return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index 1ef9e4053bb7..90a02d7bd3da 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -123,9 +123,7 @@ static void encoder_control_dmcub(
sizeof(cmd.digx_encoder_control.header);
cmd.digx_encoder_control.encoder_control.dig.stream_param = *dig;
- dc_dmub_srv_cmd_queue(dmcub, &cmd);
- dc_dmub_srv_cmd_execute(dmcub);
- dc_dmub_srv_wait_idle(dmcub);
+ dm_execute_dmub_cmd(dmcub->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
}
static enum bp_result encoder_control_digx_v1_5(
@@ -261,9 +259,7 @@ static void transmitter_control_dmcub(
sizeof(cmd.dig1_transmitter_control.header);
cmd.dig1_transmitter_control.transmitter_control.dig = *dig;
- dc_dmub_srv_cmd_queue(dmcub, &cmd);
- dc_dmub_srv_cmd_execute(dmcub);
- dc_dmub_srv_wait_idle(dmcub);
+ dm_execute_dmub_cmd(dmcub->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
}
static enum bp_result transmitter_control_v1_6(
@@ -325,9 +321,7 @@ static void transmitter_control_dmcub_v1_7(
sizeof(cmd.dig1_transmitter_control.header);
cmd.dig1_transmitter_control.transmitter_control.dig_v1_7 = *dig;
- dc_dmub_srv_cmd_queue(dmcub, &cmd);
- dc_dmub_srv_cmd_execute(dmcub);
- dc_dmub_srv_wait_idle(dmcub);
+ dm_execute_dmub_cmd(dmcub->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
}
static enum bp_result transmitter_control_v1_7(
@@ -435,9 +429,7 @@ static void set_pixel_clock_dmcub(
sizeof(cmd.set_pixel_clock.header);
cmd.set_pixel_clock.pixel_clock.clk = *clk;
- dc_dmub_srv_cmd_queue(dmcub, &cmd);
- dc_dmub_srv_cmd_execute(dmcub);
- dc_dmub_srv_wait_idle(dmcub);
+
[PATCH 19/66] drm/amd/display: Only consider DISPCLK when using optimized boot path
From: Alvin Lee
[Description]
- Previous bug fix for audio issue included dtbclk and p-state
on the optimized boot path which is incorarect
- We only care about DISPCLK in the optimized vs. non-optimized
boot path to avoid audio issues
Reviewed-by: Saaem Rizvi
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 1f5ee5cde6e1..26791e3d162f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -721,6 +721,9 @@ static void dcn32_initialize_min_clocks(struct dc *dc)
clocks->socclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;
clocks->dramclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;
clocks->dppclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;
+ clocks->ref_dtbclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
+ clocks->fclk_p_state_change_support = true;
+ clocks->p_state_change_support = true;
if (dc->debug.disable_boot_optimizations) {
clocks->dispclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;
} else {
@@ -730,9 +733,6 @@ static void dcn32_initialize_min_clocks(struct dc *dc)
* freq to ensure that the timing is valid and unchanged.
*/
clocks->dispclk_khz =
dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
- clocks->ref_dtbclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
- clocks->fclk_p_state_change_support = true;
- clocks->p_state_change_support = true;
}
dc->clk_mgr->funcs->update_clocks(
--
2.34.1
[PATCH 23/66] drm/amd/display: fix access hdcp_workqueue assert
From: Hersen Wu
[Why] hdcp are enabled for asics from raven. for old asics
which hdcp are not enabled, hdcp_workqueue are null. some
access to hdcp work queue are not guarded with pointer check.
[How] add hdcp_workqueue pointer check before access workqueue.
Reviewed-by: Bhawanpreet Lakha
Acked-by: Qingqing Zhuo
Signed-off-by: Hersen Wu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c| 6 ++
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 16 ++--
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ffa2743e92e2..71e3bc9e7f8f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8558,6 +8558,9 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
struct amdgpu_crtc *acrtc =
to_amdgpu_crtc(dm_new_con_state->base.crtc);
struct amdgpu_dm_connector *aconnector =
to_amdgpu_dm_connector(connector);
+ if (!adev->dm.hdcp_workqueue)
+ continue;
+
pr_debug("[HDCP_DM] -- i : %x --\n", i);
if (!connector)
@@ -8606,6 +8609,9 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
struct amdgpu_crtc *acrtc =
to_amdgpu_crtc(dm_new_con_state->base.crtc);
struct amdgpu_dm_connector *aconnector =
to_amdgpu_dm_connector(connector);
+ if (!adev->dm.hdcp_workqueue)
+ continue;
+
new_crtc_state = NULL;
old_crtc_state = NULL;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 994ba426ca66..5dc79b753d5f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -379,13 +379,17 @@ static int dm_dp_mst_get_modes(struct drm_connector
*connector)
if (aconnector->dc_sink && connector->state) {
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- struct hdcp_workqueue *hdcp_work =
adev->dm.hdcp_workqueue;
- struct hdcp_workqueue *hdcp_w =
&hdcp_work[aconnector->dc_link->link_index];
- connector->state->hdcp_content_type =
- hdcp_w->hdcp_content_type[connector->index];
- connector->state->content_protection =
- hdcp_w->content_protection[connector->index];
+ if (adev->dm.hdcp_workqueue) {
+ struct hdcp_workqueue *hdcp_work =
adev->dm.hdcp_workqueue;
+ struct hdcp_workqueue *hdcp_w =
+
&hdcp_work[aconnector->dc_link->link_index];
+
+ connector->state->hdcp_content_type =
+ hdcp_w->hdcp_content_type[connector->index];
+ connector->state->content_protection =
+ hdcp_w->content_protection[connector->index];
+ }
}
if (aconnector->dc_sink) {
--
2.34.1
[PATCH 20/66] drm/amd/display: Reduce SubVP + DRR stretch margin
From: Alvin Lee
[Description]
- Having excessively large margin causes failure in the static
schedulability check in some cases for SubVP + DRR
- 100us of DRR margin is sufficient based on a weeks worth of
stress testing on different display configs
Reviewed-by: Michael Strauss
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 181a3408cc61..25284006019c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -144,7 +144,7 @@ struct test_pattern {
unsigned int cust_pattern_size;
};
-#define SUBVP_DRR_MARGIN_US 600 // 600us for DRR margin (SubVP + DRR)
+#define SUBVP_DRR_MARGIN_US 100 // 100us for DRR margin (SubVP + DRR)
enum mall_stream_type {
SUBVP_NONE, // subvp not in use
--
2.34.1
[PATCH 22/66] drm/amd/display: drain dmub inbox if queue is full
From: Josip Pavic
[Why & How]
If dmub command queuing fails due to the inbox being full, flush the
inbox and resubmit the comamnd. This was previously the default behavior
but was lost in a refactor.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 954cbfdbc3b6..eef43577508c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -139,6 +139,15 @@ bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv
*dc_dmub_srv, unsigned int coun
// Queue command
status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
+ if (status == DMUB_STATUS_QUEUE_FULL) {
+ /* Execute and wait for queue to become empty again. */
+ dmub_srv_cmd_execute(dmub);
+ dmub_srv_wait_for_idle(dmub, 10);
+
+ /* Requeue the command. */
+ status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
+ }
+
if (status != DMUB_STATUS_OK) {
DC_ERROR("Error queueing DMUB command: status=%d\n",
status);
dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
--
2.34.1
[PATCH 18/66] drm/amd/display: update max streams per surface
From: Dmytro Laktyushkin
Increse to 6 as that is the max surfaces supported asics can have.
The is no practical use case yet, but this is valuable for pre-si
validation.
Reviewed-by: Ariel Bernstein
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 45ab48fe5d00..34c848311455 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -83,7 +83,7 @@ struct dc_perf_trace {
unsigned long last_entry_write;
};
-#define MAX_SURFACE_NUM 4
+#define MAX_SURFACE_NUM 6
#define NUM_PIXEL_FORMATS 10
enum tiling_mode {
--
2.34.1
[PATCH 14/66] drm/amd/display: allow edp updates for virtual signal
From: Alex Hung
[Why]
When IGT's kms_hdmi_inject forces EDID for HDMI audio, dc rejects the
request because virtual signal is not in dc_is_audio_capable_signal
function.
[How]
Includes SIGNAL_TYPE_VIRTUAL as audio capable.
Reviewed-by: Chao-kai Wang
Acked-by: Qingqing Zhuo
Signed-off-by: Alex Hung
Signed-off-by: Wenchieh Chien
---
drivers/gpu/drm/amd/display/include/signal_types.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h
b/drivers/gpu/drm/amd/display/include/signal_types.h
index beed70179bb5..23a308c3eccb 100644
--- a/drivers/gpu/drm/amd/display/include/signal_types.h
+++ b/drivers/gpu/drm/amd/display/include/signal_types.h
@@ -104,6 +104,7 @@ static inline bool dc_is_audio_capable_signal(enum
signal_type signal)
{
return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
+ signal == SIGNAL_TYPE_VIRTUAL ||
dc_is_hdmi_signal(signal));
}
--
2.34.1
[PATCH 17/66] drm/amd/display: fix memleak in aconnector->timing_requested
From: Hersen Wu
[Why]
when amdgpu_dm_update_connector_after_detect is called
two times successively with valid sink, memory allocated of
aconnector->timing_requested for the first call is not free.
this causes memeleak.
[How]
allocate memory only when aconnector->timing_requested
is null.
Reviewed-by: Qingqing Zhuo
Acked-by: Qingqing Zhuo
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8b4a470a7e60..fa2acc017437 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3127,9 +3127,12 @@ void amdgpu_dm_update_connector_after_detect(
aconnector->edid);
}
- aconnector->timing_requested = kzalloc(sizeof(struct
dc_crtc_timing), GFP_KERNEL);
- if (!aconnector->timing_requested)
- dm_error("%s: failed to create
aconnector->requested_timing\n", __func__);
+ if (!aconnector->timing_requested) {
+ aconnector->timing_requested =
+ kzalloc(sizeof(struct dc_crtc_timing),
GFP_KERNEL);
+ if (!aconnector->timing_requested)
+ dm_error("failed to create
aconnector->requested_timing\n");
+ }
drm_connector_update_edid_property(connector, aconnector->edid);
amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
--
2.34.1
[PATCH 15/66] drm/amd/display: Fix in disabling secure display
From: Alan Liu
[Why]
Currently we don't check if secure display is enabled before we send
command to disable secure display in dmub. It will accidentally cause
some other igt tests to fail, eg, crtc-linear-degamma.
[How]
Refactor the code we reset the secure display state to check secure
display was enabled or not before stopping it in dmub.
Reviewed-by: Wayne Lin
Acked-by: Qingqing Zhuo
Signed-off-by: Alan Liu
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 31 ---
1 file changed, 13 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index 27711743c22c..0802f8e8fac5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -83,12 +83,15 @@ const char *const *amdgpu_dm_crtc_get_crc_sources(struct
drm_crtc *crtc,
}
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
-static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc)
+static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc, struct
dc_stream_state *stream)
{
struct drm_device *drm_dev = crtc->dev;
+ struct amdgpu_display_manager *dm = &drm_to_adev(drm_dev)->dm;
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
+ bool was_activated;
spin_lock_irq(&drm_dev->event_lock);
+ was_activated = acrtc->dm_irq_params.window_param.activated;
acrtc->dm_irq_params.window_param.x_start = 0;
acrtc->dm_irq_params.window_param.y_start = 0;
acrtc->dm_irq_params.window_param.x_end = 0;
@@ -97,6 +100,14 @@ static void amdgpu_dm_set_crc_window_default(struct
drm_crtc *crtc)
acrtc->dm_irq_params.window_param.update_win = false;
acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
spin_unlock_irq(&drm_dev->event_lock);
+
+ /* Disable secure_display if it was enabled */
+ if (was_activated) {
+ /* stop ROI update on this crtc */
+
flush_work(&dm->secure_display_ctxs[crtc->index].notify_ta_work);
+
flush_work(&dm->secure_display_ctxs[crtc->index].forward_roi_work);
+ dc_stream_forward_crc_window(stream, NULL, true);
+ }
}
static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work)
@@ -204,9 +215,6 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc
*crtc,
struct dm_crtc_state *dm_crtc_state,
enum amdgpu_dm_pipe_crc_source source)
{
-#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
- int i;
-#endif
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
struct dc_stream_state *stream_state = dm_crtc_state->stream;
bool enable = amdgpu_dm_is_valid_crc_source(source);
@@ -220,19 +228,6 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc
*crtc,
/* Enable or disable CRTC CRC generation */
if (dm_is_crc_source_crtc(source) || source ==
AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
-#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
- /* Disable secure_display if it was enabled */
- if (!enable) {
- for (i = 0; i < adev->mode_info.num_crtc; i++) {
- if (adev->dm.secure_display_ctxs[i].crtc ==
crtc) {
- /* stop ROI update on this crtc */
-
flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
-
flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
-
dc_stream_forward_crc_window(stream_state, NULL, true);
- }
- }
- }
-#endif
if (!dc_stream_configure_crc(stream_state->ctx->dc,
stream_state, NULL, enable,
enable)) {
ret = -EINVAL;
@@ -363,7 +358,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc,
const char *src_name)
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
/* Reset secure_display when we change crc source from debugfs */
- amdgpu_dm_set_crc_window_default(crtc);
+ amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream);
#endif
if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) {
--
2.34.1
[PATCH 16/66] drm/amd/display: Fix hang when skipping modeset
From: Aurabindo Pillai
[Why&How]
When skipping full modeset since the only state change was a front porch
change, the DC commit sequence requires extra checks to handle non
existant plane states being asked to be removed from context.
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 -
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index da3045fdcb6d..8b4a470a7e60 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7971,6 +7971,8 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
continue;
dc_plane = dm_new_plane_state->dc_state;
+ if (!dc_plane)
+ continue;
bundle->surface_updates[planes_count].surface = dc_plane;
if (new_pcrtc_state->color_mgmt_changed) {
@@ -9619,8 +9621,9 @@ static int dm_update_plane_state(struct dc *dc,
return -EINVAL;
}
+ if (dm_old_plane_state->dc_state)
+ dc_plane_state_release(dm_old_plane_state->dc_state);
- dc_plane_state_release(dm_old_plane_state->dc_state);
dm_new_plane_state->dc_state = NULL;
*lock_and_validation_needed = true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 85d54bfb595c..117d80cb36fb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1707,6 +1707,9 @@ bool dc_remove_plane_from_context(
struct dc_stream_status *stream_status = NULL;
struct resource_pool *pool = dc->res_pool;
+ if (!plane_state)
+ return true;
+
for (i = 0; i < context->stream_count; i++)
if (context->streams[i] == stream) {
stream_status = &context->stream_status[i];
--
2.34.1
[PATCH 12/66] drm/amd/display: Add missing WA and MCLK validation
From: Rodrigo Siqueira
When the commit a983d2631869 (drm/amd/display: Don't set dram clock
change requirement for SubVP) was merged, we missed some parts
associated with the MCLK switch. This commit adds all the missing parts.
Fixes: a983d2631869 (drm/amd/display: Don't set dram clock change requirement
for SubVP)
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 1 +
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 18 +-
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index db0974fe58ab..1f5ee5cde6e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -948,6 +948,7 @@ void dcn32_init_hw(struct dc *dc)
if (dc->ctx->dmub_srv) {
dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
dc->caps.dmub_caps.psr =
dc->ctx->dmub_srv->dmub->feature_caps.psr;
+ dc->caps.dmub_caps.mclk_sw =
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 0beb11d95eb7..a876e6eb6cd8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2023,7 +2023,7 @@ int dcn32_populate_dml_pipes_from_context(
// In general cases we want to keep the dram clock change requirement
// (prefer configs that support MCLK switch). Only override to false
// for SubVP
- if (subvp_in_use)
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use)
context->bw_ctx.dml.soc.dram_clock_change_requirement_final =
false;
else
context->bw_ctx.dml.soc.dram_clock_change_requirement_final =
true;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index 80972ee5e55b..a352c703e258 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -368,7 +368,9 @@ void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct
dc_state *context)
dc_assert_fp_enabled();
if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
- context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
+ if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||
+
context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0)
+ context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
context->bw_ctx.dml.soc.sr_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
}
@@ -563,6 +565,20 @@ void dcn30_fpu_calculate_wm_and_dlg(
pipe_idx++;
}
+ // WA: restrict FPO to use first non-strobe mode (NV24 BW issue)
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching &&
+ dc->dml.soc.num_chans <= 4 &&
+ context->bw_ctx.dml.vba.DRAMSpeed <= 1700 &&
+ context->bw_ctx.dml.vba.DRAMSpeed >= 1500) {
+
+ for (i = 0; i < dc->dml.soc.num_states; i++) {
+ if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) {
+ context->bw_ctx.dml.vba.DRAMSpeed =
dc->dml.soc.clock_limits[i].dram_speed_mts;
+ break;
+ }
+ }
+ }
+
dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
if (!pstate_en)
--
2.34.1
[PATCH 13/66] drm/amd/display: copy dmub caps to dc on dcn31
From: Josip Pavic [Why & How] Add code path to copy dmub caps to dc, which is missing on dcn31 Acked-by: Qingqing Zhuo Signed-off-by: Josip Pavic --- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c index 7ac6e69cff37..62ce36c75c4d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c @@ -295,6 +295,10 @@ void dcn31_init_hw(struct dc *dc) if (dc->res_pool->hubbub->funcs->init_crb) dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); #endif + + // Get DMCUB capabilities + dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); + dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; } void dcn31_dsc_pg_control( -- 2.34.1
[PATCH 09/66] drm/amd/display: Fix ABM pipe/backlight issues when change backlight
From: Leon Huang
[Why]
set ABM pipe/backlight gets some issues when abm callback func pointers
are NULL. For some usecase, driver would like to control PWM level before
ABM resource is ready. However, recent flow refactor of ABM didn't
consider that use case.
[How]
Rollback flow that sending inbox command to dmub directly when ABM
function pointers aren't ready.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Leon Huang
---
.../drm/amd/display/dc/dcn21/dcn21_hwseq.c| 64 ++-
1 file changed, 47 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
index 2a182c2f57d6..1c6477d73c8e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
@@ -159,6 +159,25 @@ static bool dmub_abm_set_pipe(struct abm *abm, uint32_t
otg_inst, uint32_t optio
return true;
}
+static void dmub_abm_set_backlight(struct dc_context *dc, uint32_t
backlight_pwm_u16_16,
+
uint32_t frame_ramp, uint32_t panel_inst)
+{
+ union dmub_rb_cmd cmd;
+
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.abm_set_backlight.header.type = DMUB_CMD__ABM;
+ cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT;
+ cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = frame_ramp;
+ cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level =
backlight_pwm_u16_16;
+ cmd.abm_set_backlight.abm_set_backlight_data.version =
DMUB_CMD_ABM_CONTROL_VERSION_1;
+ cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 <<
panel_inst);
+ cmd.abm_set_backlight.header.payload_bytes = sizeof(struct
dmub_cmd_abm_set_backlight_data);
+
+ dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
+ dc_dmub_srv_cmd_execute(dc->dmub_srv);
+ dc_dmub_srv_wait_idle(dc->dmub_srv);
+}
+
void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
{
struct abm *abm = pipe_ctx->stream_res.abm;
@@ -173,8 +192,12 @@ void dcn21_set_abm_immediate_disable(struct pipe_ctx
*pipe_ctx)
}
if (abm && panel_cntl) {
- dmub_abm_set_pipe(abm, otg_inst,
SET_ABM_PIPE_IMMEDIATELY_DISABLE,
- panel_cntl->inst);
+ if (abm->funcs && abm->funcs->set_pipe_ex) {
+ abm->funcs->set_pipe_ex(abm, otg_inst,
SET_ABM_PIPE_IMMEDIATELY_DISABLE,
+ panel_cntl->inst);
+ } else {
+ dmub_abm_set_pipe(abm, otg_inst,
SET_ABM_PIPE_IMMEDIATELY_DISABLE, panel_cntl->inst);
+ }
panel_cntl->funcs->store_backlight_level(panel_cntl);
}
}
@@ -191,8 +214,13 @@ void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)
return;
}
- if (abm && panel_cntl)
- dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL,
panel_cntl->inst);
+ if (abm && panel_cntl) {
+ if (abm->funcs && abm->funcs->set_pipe_ex) {
+ abm->funcs->set_pipe_ex(abm, otg_inst,
SET_ABM_PIPE_NORMAL, panel_cntl->inst);
+ } else {
+ dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL,
panel_cntl->inst);
+ }
+ }
}
bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
@@ -210,21 +238,23 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
return true;
}
- if (abm && panel_cntl)
- dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL,
panel_cntl->inst);
+ if (abm != NULL) {
+ uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;
- memset(&cmd, 0, sizeof(cmd));
- cmd.abm_set_backlight.header.type = DMUB_CMD__ABM;
- cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT;
- cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = frame_ramp;
- cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level =
backlight_pwm_u16_16;
- cmd.abm_set_backlight.abm_set_backlight_data.version =
DMUB_CMD_ABM_CONTROL_VERSION_1;
- cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 <<
panel_cntl->inst);
- cmd.abm_set_backlight.header.payload_bytes = sizeof(struct
dmub_cmd_abm_set_backlight_data);
+ if (abm && panel_cntl) {
+ if (abm->funcs && abm->funcs->set_pipe_ex) {
+ abm->funcs->set_pipe_ex(abm, otg_inst,
SET_ABM_PIPE_NORMAL, panel_cntl->inst);
+ } else {
+ dmub_abm_set_pipe(abm, otg_inst,
SET_ABM_PIPE_NORMAL, panel_cntl->inst);
+ }
+ }
+ }
- dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
- dc_dmub_srv_cmd_execute(dc->dmub_srv);
- dc_dmub_srv_wait_idle(dc->dmub_srv);
+
[PATCH 11/66] drm/amd/display: Block optimize on consecutive FAMS enables
From: Wesley Chalmers
[WHY]
It is possible to commit state multiple times in rapid succession with
FAMS enabled; if each of these commits were to set optimized_required,
then the user may see latency.
[HOW]
fw_based_mclk_switching is currently not used in dc->clk_mgr; use it
to track whether the current state has FAMS enabled;
if it has, then do not disable FAMS in prepare_bandwidth, and do not set
optimized_required.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Wesley Chalmers
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 3 +++
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 22 ---
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 6ce10fd4bb1a..422fbf79da64 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2117,6 +2117,9 @@ void dcn20_optimize_bandwidth(
dc_dmub_srv_p_state_delegate(dc,
true, context);
context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
+ dc->clk_mgr->clks.fw_based_mclk_switching = true;
+ } else {
+ dc->clk_mgr->clks.fw_based_mclk_switching = false;
}
dc->clk_mgr->funcs->update_clocks(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 0411867654dd..8263a07f265f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -983,9 +983,13 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
}
void dcn30_prepare_bandwidth(struct dc *dc,
- struct dc_state *context)
+ struct dc_state *context)
{
- if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
+ bool p_state_change_support =
context->bw_ctx.bw.dcn.clk.p_state_change_support;
+ /* Any transition into an FPO config should disable MCLK switching
first to avoid
+* driver and FW P-State synchronization issues.
+*/
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||
dc->clk_mgr->clks.fw_based_mclk_switching) {
dc->optimized_required = true;
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
}
@@ -996,7 +1000,19 @@ void dcn30_prepare_bandwidth(struct dc *dc,
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr,
dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries
- 1].memclk_mhz);
dcn20_prepare_bandwidth(dc, context);
+ /*
+* enabled -> enabled: do not disable
+* enabled -> disabled: disable
+* disabled -> enabled: don't care
+* disabled -> disabled: don't care
+*/
+ if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
+ dc_dmub_srv_p_state_delegate(dc, false, context);
- dc_dmub_srv_p_state_delegate(dc, false, context);
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||
dc->clk_mgr->clks.fw_based_mclk_switching) {
+ /* After disabling P-State, restore the original value to
ensure we get the correct P-State
+* on the next optimize. */
+ context->bw_ctx.bw.dcn.clk.p_state_change_support =
p_state_change_support;
+ }
}
--
2.34.1
[PATCH 08/66] drm/amd/display: Refactor ABM feature
From: Leon Huang
[Why]
Refactor ABM feature and implement inbox command for DMUB.
[How]
Implement the ioctl to send inbox command to DMUB.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Leon Huang
---
drivers/gpu/drm/amd/display/dc/dce/Makefile | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 264 +++-
.../gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c | 286 ++
.../gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h | 46 +++
drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 6 +
5 files changed, 442 insertions(+), 162 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h
diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile
b/drivers/gpu/drm/amd/display/dc/dce/Makefile
index 0d7db132a20f..01490c9ba958 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile
@@ -29,7 +29,7 @@
DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \
dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \
-dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o dmub_psr.o dmub_abm.o dce_panel_cntl.o \
+dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o dmub_psr.o dmub_abm.o dmub_abm_lcd.o
dce_panel_cntl.o \
dmub_hw_lock_mgr.o dmub_outbox.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 9fc48208c2e4..a66f83a61402 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -24,212 +24,151 @@
*/
#include "dmub_abm.h"
-#include "dce_abm.h"
+#include "dmub_abm_lcd.h"
#include "dc.h"
-#include "dc_dmub_srv.h"
-#include "dmub/dmub_srv.h"
#include "core_types.h"
-#include "dm_services.h"
-#include "reg_helper.h"
-#include "fixed31_32.h"
-
-#include "atom.h"
#define TO_DMUB_ABM(abm)\
container_of(abm, struct dce_abm, base)
-#define REG(reg) \
- (dce_abm->regs->reg)
+#define ABM_FEATURE_NO_SUPPORT 0
+#define ABM_LCD_SUPPORT1
-#undef FN
-#define FN(reg_name, field_name) \
- dce_abm->abm_shift->field_name, dce_abm->abm_mask->field_name
+static unsigned int abm_feature_support(struct abm *abm, unsigned int
panel_inst)
+{
+ struct dc_context *dc = abm->ctx;
+ struct dc_link *edp_links[MAX_NUM_EDP];
+ int i;
+ int edp_num;
+ unsigned int ret = ABM_FEATURE_NO_SUPPORT;
-#define CTX \
- dce_abm->base.ctx
+ dc_get_edp_links(dc->dc, edp_links, &edp_num);
-#define DISABLE_ABM_IMMEDIATELY 255
+ for (i = 0; i < edp_num; i++) {
+ if (panel_inst == i)
+ break;
+ }
+ if (i < edp_num) {
+ ret = ABM_LCD_SUPPORT;
+ }
+ return ret;
+}
-static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)
+static void dmub_abm_init_ex(struct abm *abm, uint32_t backlight)
{
- union dmub_rb_cmd cmd;
- uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm ==
false) ? 1 : 0;
- uint32_t edp_id_count = dc->dc_edp_id_count;
- int i;
- uint8_t panel_mask = 0;
-
- for (i = 0; i < edp_id_count; i++)
- panel_mask |= 0x01 << i;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.abm_set_pwm_frac.header.type = DMUB_CMD__ABM;
- cmd.abm_set_pwm_frac.header.sub_type = DMUB_CMD__ABM_SET_PWM_FRAC;
- cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.fractional_pwm =
fractional_pwm;
- cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.version =
DMUB_CMD_ABM_CONTROL_VERSION_1;
- cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.panel_mask = panel_mask;
- cmd.abm_set_pwm_frac.header.payload_bytes = sizeof(struct
dmub_cmd_abm_set_pwm_frac_data);
-
- dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
- dc_dmub_srv_cmd_execute(dc->dmub_srv);
- dc_dmub_srv_wait_idle(dc->dmub_srv);
+ dmub_abm_init(abm, backlight);
}
-static void dmub_abm_init(struct abm *abm, uint32_t backlight)
+static unsigned int dmub_abm_get_current_backlight_ex(struct abm *abm)
{
- struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
-
- REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x3);
- REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x1);
- REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x3);
- REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x1);
- REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x1);
-
- REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,
- ABM1_HG_NUM_OF_BINS_SEL, 0,
- ABM1_HG_VMAX_SEL, 1,
- ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0);
-
- REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,
- ABM1_IPCSC_COEFF_SEL_R, 2,
- ABM1_IPCSC_COEFF_SEL_G, 4,
- ABM1_IPCSC_COEFF_SEL_B, 2);
+ return dmub_abm_get_current_backlight(abm);
+}
[PATCH 10/66] drm/amd/display: Do not set drr on pipe commit
From: Wesley Chalmers
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
[HOW]
Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets
optimized_required.
This change expects that Freesync requests are blocked when
optimized_required is true.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Wesley Chalmers
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ++
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 +++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 5403e9399a46..6ce10fd4bb1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2113,6 +2113,12 @@ void dcn20_optimize_bandwidth(
if (hubbub->funcs->program_compbuf_size)
hubbub->funcs->program_compbuf_size(hubbub,
context->bw_ctx.bw.dcn.compbuf_size_kb, true);
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
+ dc_dmub_srv_p_state_delegate(dc,
+ true, context);
+ context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
+ }
+
dc->clk_mgr->funcs->update_clocks(
dc->clk_mgr,
context,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 0e071fbc9154..0411867654dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -985,11 +985,18 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
void dcn30_prepare_bandwidth(struct dc *dc,
struct dc_state *context)
{
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
+ dc->optimized_required = true;
+ context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
+ }
+
if (dc->clk_mgr->dc_mode_softmax_enabled)
if (dc->clk_mgr->clks.dramclk_khz <=
dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
context->bw_ctx.bw.dcn.clk.dramclk_khz >
dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr,
dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries
- 1].memclk_mhz);
dcn20_prepare_bandwidth(dc, context);
+
+ dc_dmub_srv_p_state_delegate(dc, false, context);
}
--
2.34.1
[PATCH 03/66] drm/amd/display: Adjust code identation and other minor details
From: Rodrigo Siqueira
This commit replaces spaces with tabs in multiple functions and adjusts
the indentation in some other parts of the code to improve readability.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 44 ++---
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 170 +-
2 files changed, 109 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index e30d1f60695d..0beb11d95eb7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -324,7 +324,6 @@ static const struct dcn10_link_enc_shift le_shift = {
static const struct dcn10_link_enc_mask le_mask = {
LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
-
//DPCS_DCN31_MASK_SH_LIST(_MASK)
};
@@ -2093,27 +2092,28 @@ static bool dcn32_resource_construct(
uint32_t pipe_fuses = 0;
uint32_t num_pipes = 4;
- #undef REG_STRUCT
- #define REG_STRUCT bios_regs
- bios_regs_init();
-
- #undef REG_STRUCT
- #define REG_STRUCT clk_src_regs
- clk_src_regs_init(0, A),
- clk_src_regs_init(1, B),
- clk_src_regs_init(2, C),
- clk_src_regs_init(3, D),
- clk_src_regs_init(4, E);
- #undef REG_STRUCT
- #define REG_STRUCT abm_regs
- abm_regs_init(0),
- abm_regs_init(1),
- abm_regs_init(2),
- abm_regs_init(3);
-
- #undef REG_STRUCT
- #define REG_STRUCT dccg_regs
- dccg_regs_init();
+#undef REG_STRUCT
+#define REG_STRUCT bios_regs
+ bios_regs_init();
+
+#undef REG_STRUCT
+#define REG_STRUCT clk_src_regs
+ clk_src_regs_init(0, A),
+ clk_src_regs_init(1, B),
+ clk_src_regs_init(2, C),
+ clk_src_regs_init(3, D),
+ clk_src_regs_init(4, E);
+
+#undef REG_STRUCT
+#define REG_STRUCT abm_regs
+ abm_regs_init(0),
+ abm_regs_init(1),
+ abm_regs_init(2),
+ abm_regs_init(3);
+
+#undef REG_STRUCT
+#define REG_STRUCT dccg_regs
+ dccg_regs_init();
DC_FP_START();
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 38d1f2be8cf3..6e32dc68f7bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -917,19 +917,19 @@ void dcn20_populate_dml_writeback_from_context(struct dc
*dc,
}
void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params,
-struct dc_state *context,
-display_e2e_pipe_params_st *pipes,
-int pipe_cnt, int i)
+struct dc_state *context,
+display_e2e_pipe_params_st *pipes,
+int pipe_cnt, int i)
{
- int k;
+ int k;
- dc_assert_fp_enabled();
+ dc_assert_fp_enabled();
- for (k = 0; k <
sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]);
k++) {
- wb_arb_params->cli_watermark[k] =
get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
- wb_arb_params->pstate_watermark[k] =
get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) *
1000;
- }
- wb_arb_params->time_per_pixel = 16.0 * 1000 /
(context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction,
ms */
+ for (k = 0; k <
sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]);
k++) {
+ wb_arb_params->cli_watermark[k] =
get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ wb_arb_params->pstate_watermark[k] =
get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) *
1000;
+ }
+ wb_arb_params->time_per_pixel = 16.0 * 1000 /
(context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction,
ms */
}
static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
@@ -1037,11 +1037,11 @@ static void dcn20_adjust_freesync_v_startup(
*vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup :
*vstartup_start);
}
-void dcn20_calculate_dlg_params(
- struct dc *dc, struct dc_state *context,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt,
- int vlevel)
+void dcn20_calculate_dlg_params(struct dc *dc,
+ struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt,
+ int vlevel)
{
int i, pipe_idx;
@@ -1083,6 +1083,7 @@ void dc
[PATCH 07/66] drm/amd/display: Use pointer in the memcpy
From: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 03718cc148e0..f1c1a4b5fcac 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -2333,7 +2333,7 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct
clk_bw_params *bw_params
k++;
}
- memcpy(dcn2_1_soc.clock_limits, s, sizeof(dcn2_1_soc.clock_limits));
+ memcpy(&dcn2_1_soc.clock_limits, s, sizeof(dcn2_1_soc.clock_limits));
if (clk_table->num_entries) {
dcn2_1_soc.num_states = clk_table->num_entries + 1;
--
2.34.1
[PATCH 05/66] drm/amd/display: Set dp_rate to dm_dp_rate_na by default
From: Rodrigo Siqueira Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index b79014f04cef..9fadac1b4c64 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -1300,8 +1300,7 @@ int dcn20_populate_dml_pipes_from_context(struct dc *dc, pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; pipes[pipe_cnt].dout.dp_lanes = 4; - if (res_ctx->pipe_ctx[i].stream->link) - pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na; + pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na; pipes[pipe_cnt].dout.is_virtual = 0; pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; -- 2.34.1
[PATCH 06/66] drm/amd/display: Remove wrong assignment of DP link rate
From: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 9fadac1b4c64..03718cc148e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1360,7 +1360,6 @@ int dcn20_populate_dml_pipes_from_context(struct dc *dc,
pipes[pipe_cnt].dout.is_virtual = 1;
pipes[pipe_cnt].dout.output_type = dm_dp;
pipes[pipe_cnt].dout.dp_lanes = 4;
- pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2;
}
switch
(res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
--
2.34.1
[PATCH 04/66] drm/amd/display: Set maximum VStartup if is DCN201
From: Rodrigo Siqueira Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 6e32dc68f7bc..b79014f04cef 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -1259,6 +1259,8 @@ int dcn20_populate_dml_pipes_from_context(struct dc *dc, pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; + pipes[pipe_cnt].pipe.dest.use_maximum_vstartup = dc->ctx->dce_version == DCN_VERSION_2_01; + pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; /* todo: rotation?*/ pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; -- 2.34.1
[PATCH 02/66] drm/amd/display: Add missing mclk update
From: Rodrigo Siqueira When using FPO, there is some misconfiguration that happens for the lack of configuration of the MCLK switch in some circumstances. This commit adds the required field update when using the MCLK switch. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index f0037cb43dca..23a972f2885f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -1331,6 +1331,11 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != dm_dram_clock_change_unsupported; + /* Pstate change might not be supported by hardware, but it might be +* possible with firmware driven vertical blank stretching. +*/ + context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; + context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; -- 2.34.1
[PATCH 01/66] drm/amd/display: Update bouding box values for DCN32
From: Rodrigo Siqueira
All clock values came from firmware, but bounding box values can be
helpful in some debug situations. This commit updates some of the values
associated with clock speed and memory channels.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 4548320217fc..f0037cb43dca 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -109,7 +109,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
{
.state = 0,
.dcfclk_mhz = 1564.0,
- .fabricclk_mhz = 400.0,
+ .fabricclk_mhz = 2500.0,
.dispclk_mhz = 2150.0,
.dppclk_mhz = 2150.0,
.phyclk_mhz = 810.0,
@@ -117,7 +117,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
.phyclk_d32_mhz = 625.0,
.socclk_mhz = 1200.0,
.dscclk_mhz = 716.667,
- .dram_speed_mts = 16000.0,
+ .dram_speed_mts = 18000.0,
.dtbclk_mhz = 1564.0,
},
},
@@ -148,7 +148,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
.max_avg_fabric_bw_use_normal_percent = 60.0,
.max_avg_dram_bw_use_normal_strobe_percent = 50.0,
.max_avg_dram_bw_use_normal_percent = 15.0,
- .num_chans = 8,
+ .num_chans = 24,
.dram_channel_width_bytes = 2,
.fabric_datapath_to_dcn_data_return_bytes = 64,
.return_bus_width_bytes = 64,
--
2.34.1
[PATCH 00/66] DC Patches Apr 17th, 2023
This DC patchset brings improvements in multiple areas. In summary, we highlight: - FW Release 0.0.162.0 - Enable FPO+Vactivate - Support for VESA SCR on OLED - Refactor DMUB commands - Fixes in secure display, modeset, memleak and more - Picked up missed patches in history Cc: Daniel Wheeler Alan Liu (1): drm/amd/display: Fix in disabling secure display Alex Hung (2): drm/amd/display: allow edp updates for virtual signal drm/amd/display: fix a divided-by-zero error Alvin Lee (5): drm/amd/display: Only consider DISPCLK when using optimized boot path drm/amd/display: Reduce SubVP + DRR stretch margin drm/amd/display: Set watermarks set D equal to A drm/amd/display: Enable FPO + Vactive drm/amd/display: Update DTBCLK for DCN32 Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.162.0 Aric Cyr (1): drm/amd/display: 3.2.231 Aurabindo Pillai (13): drm/amd/display: Fix hang when skipping modeset drm/amd/display: remove incorrect early return drm/amd/display: Fixes for dcn32_clk_mgr implementation drm/amd/display: Do not clear GPINT register when releasing DMUB from reset drm/amd/display: Update bounding box values for DCN321 drm/amd/display: add support for low bpc drm/amd/display: Set DRAM clock if retraining is required drm/amd/display: Add check for PState change in DCN32 drm/amd/display: Remove DET check from DCN32 drm/amd/display: Add extra check for 444 16 format drm/amd/display: Add FAMS capability to DCN31 drm/amd/display: Add FAMS related definitions and documenation for enum fields drm/amd/display: remove some unused variables Cruise Hung (1): drm/amd/display: Reset OUTBOX0 r/w pointer on DMUB reset Daniel Miess (1): drm/amd/display: limit timing for single dimm memory Dmytro Laktyushkin (4): drm/amd/display: update max streams per surface drm/amd/display: add extra dc odm debug options drm/amd/display: set dcn315 lb bpp to 48 drm/amd/display: Limit nv21 dst_y Eric Yang (1): drm/amd/display: add mechanism to skip DCN init Hersen Wu (2): drm/amd/display: fix memleak in aconnector->timing_requested drm/amd/display: fix access hdcp_workqueue assert Igor Kravchenko (1): drm/amd/display: Set min_width and min_height capability for DCN30 Iswara Nagulendran (1): drm/amd/display: Adding support for VESA SCR Jasdeep Dhillon (1): drm/amd/display: Isolate remaining FPU code in DCN32 Jingwen Zhu (1): drm/amd/display: Improvement for handling edp link training fails Josip Pavic (3): drm/amd/display: copy dmub caps to dc on dcn31 drm/amd/display: refactor dmub commands into single function drm/amd/display: drain dmub inbox if queue is full Krunoslav Kovac (1): drm/amd/display: 3-plane MPO enablement for DCN321 Leon Huang (2): drm/amd/display: Refactor ABM feature drm/amd/display: Fix ABM pipe/backlight issues when change backlight Meenakshikumar Somasundaram (1): drm/amd/display: Adjust dmub outbox notification enable Michael Mityushkin (2): drm/amd/display: Correct output color space during HW reinitialize drm/amd/display: Apply correct panel mode when reinitializing hardware Mikita Lipski (1): drm/amd/display: Write TEST_EDID_CHECKSUM_WRITE for EDID tests Nasir Osman (1): drm/amd/display: DSC policy override when ODM combine is forced Nicholas Kazlauskas (1): drm/amd/display: Explicitly specify update type per plane info change Po-Ting Chen (1): drm/amd/display: update GSP1 generic info packet for PSRSU Rodrigo Siqueira (9): drm/amd/display: Update bouding box values for DCN32 drm/amd/display: Add missing mclk update drm/amd/display: Adjust code identation and other minor details drm/amd/display: Set maximum VStartup if is DCN201 drm/amd/display: Set dp_rate to dm_dp_rate_na by default drm/amd/display: Remove wrong assignment of DP link rate drm/amd/display: Use pointer in the memcpy drm/amd/display: Add missing WA and MCLK validation drm/amd/display: Add FAMS validation before trying to use it Samson Tam (1): drm/amd/display: Clear GPINT1 before taking DMCUB out of reset Sherry Wang (1): drm/amd/display: correct DML calc error Tianci Yin (1): drm/amd/display: Disable migration to ensure consistency of per-CPU variable Wesley Chalmers (3): drm/amd/display: Do not set drr on pipe commit drm/amd/display: Block optimize on consecutive FAMS enables drm/amd/display: Add logging for display MALL refresh setting Zhongwei (1): drm/amd/display: fix dpms_off issue when disabling bios mode hersen wu (1): drm/amd/display: Return error code on DSC atomic check failure .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 ++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 31 +- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 31 +- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 17 +- .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c| 2 + .../drm/amd/display/dc/bios/command_table2.c | 25 +- .../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
Re: BUG: KASAN: null-ptr-deref in drm_sched_job_cleanup+0x96/0x290 [gpu_sched]
On Tue, Apr 11, 2023 at 10:40 PM Mikhail Gavrilov wrote: > > Hi, > KASAN continues to find problems in the drm_sched_job_cleanup code at 6.3rc6. > I not got any feedback in the thread > https://lore.kernel.org/lkml/cabxgcsmvub2ra4d+k5cna0_2521tox++d4nmoukki4x2-q_...@mail.gmail.com/ > Therefore, I decided to start a separate thread. Since the problems > are different, the symptoms are also different. > > Reproduction scenario. > After launching one of the listed games: > - Cyberpunk 2077 > - Forza Horizon 4 > - Forza Horizon 5 > - Sackboy: A Big Adventure > > Firstly after some time (may be after several attempts) appears bug > message from KASAN: > == > BUG: KASAN: null-ptr-deref in drm_sched_job_cleanup+0x96/0x290 [gpu_sched] > Read of size 4 at addr 0078 by task ForzaHorizon4.e/31587 > > CPU: 15 PID: 31587 Comm: ForzaHorizon4.e Tainted: GWL > --- --- 6.3.0-0.rc6.49.fc39.x86_64+debug #1 > Hardware name: System manufacturer System Product Name/ROG STRIX > X570-I GAMING, BIOS 4601 02/02/2023 > Call Trace: > > dump_stack_lvl+0x72/0xc0 > kasan_report+0xa4/0xe0 > ? drm_sched_job_cleanup+0x96/0x290 [gpu_sched] > kasan_check_range+0x104/0x1b0 > drm_sched_job_cleanup+0x96/0x290 [gpu_sched] > ? __pfx_drm_sched_job_cleanup+0x10/0x10 [gpu_sched] > ? slab_free_freelist_hook+0x11e/0x1d0 > ? amdgpu_cs_parser_fini+0x363/0x5a0 [amdgpu] > amdgpu_job_free+0x40/0x1b0 [amdgpu] > amdgpu_cs_parser_fini+0x3c9/0x5a0 [amdgpu] > ? __pfx_amdgpu_cs_parser_fini+0x10/0x10 [amdgpu] > amdgpu_cs_ioctl+0x3d9/0x5630 [amdgpu] > ? __pfx_amdgpu_cs_ioctl+0x10/0x10 [amdgpu] > ? __kmem_cache_free+0xbc/0x2e0 > ? mark_lock+0x101/0x16e0 > ? __lock_acquire+0xe54/0x59f0 > ? kasan_save_stack+0x3f/0x50 > ? __pfx_lock_release+0x10/0x10 > ? __pfx_amdgpu_cs_ioctl+0x10/0x10 [amdgpu] > drm_ioctl_kernel+0x1f8/0x3d0 > ? __pfx_drm_ioctl_kernel+0x10/0x10 > drm_ioctl+0x4c1/0xaa0 > ? __pfx_amdgpu_cs_ioctl+0x10/0x10 [amdgpu] > ? __pfx_drm_ioctl+0x10/0x10 > ? _raw_spin_unlock_irqrestore+0x62/0x80 > ? lockdep_hardirqs_on+0x7d/0x100 > ? _raw_spin_unlock_irqrestore+0x4b/0x80 > amdgpu_drm_ioctl+0xce/0x1b0 [amdgpu] > __x64_sys_ioctl+0x12d/0x1a0 > do_syscall_64+0x5c/0x90 > ? do_syscall_64+0x68/0x90 > ? lockdep_hardirqs_on+0x7d/0x100 > ? do_syscall_64+0x68/0x90 > ? do_syscall_64+0x68/0x90 > ? lockdep_hardirqs_on+0x7d/0x100 > ? do_syscall_64+0x68/0x90 > ? asm_exc_page_fault+0x22/0x30 > ? lockdep_hardirqs_on+0x7d/0x100 > entry_SYSCALL_64_after_hwframe+0x72/0xdc > RIP: 0033:0x7fb8a270881d > Code: 04 25 28 00 00 00 48 89 45 c8 31 c0 48 8d 45 10 c7 45 b0 10 00 > 00 00 48 89 45 b8 48 8d 45 d0 48 89 45 c0 b8 10 00 00 00 0f 05 <89> c2 > 3d 00 f0 ff ff 77 1a 48 8b 45 c8 64 48 2b 04 25 28 00 00 00 > RSP: 002b:467ad060 EFLAGS: 0246 ORIG_RAX: 0010 > RAX: ffda RBX: 467ad358 RCX: 7fb8a270881d > RDX: 467ad140 RSI: c0186444 RDI: 005a > RBP: 467ad0b0 R08: 7fb7f00d3eb0 R09: 467ad100 > R10: 7fb88c68fb20 R11: 0246 R12: 467ad140 > R13: c0186444 R14: 005a R15: 7fb7f00d3e50 > > == > > Finally it ends up with the games listed above stopping working they > stuck after a kernel warning: > general protection fault, probably for non-canonical address > 0xdc0f: [#1] PREEMPT SMP KASAN NOPTI > KASAN: null-ptr-deref in range [0x0078-0x007f] > CPU: 15 PID: 31587 Comm: ForzaHorizon4.e Tainted: GB WL > --- --- 6.3.0-0.rc6.49.fc39.x86_64+debug #1 > Hardware name: System manufacturer System Product Name/ROG STRIX > X570-I GAMING, BIOS 4601 02/02/2023 > RIP: 0010:drm_sched_job_cleanup+0xa7/0x290 [gpu_sched] > Code: d6 01 00 00 4c 8b 75 20 be 04 00 00 00 4d 8d 66 78 4c 89 e7 e8 > ba 4d 4e c9 4c 89 e2 48 b8 00 00 00 00 00 fc ff df 48 c1 ea 03 <0f> b6 > 14 02 4c 89 e0 83 e0 07 83 c0 03 38 d0 7c 08 84 d2 0f 85 8a > RSP: 0018:c9003676f5a8 EFLAGS: 00010216 > RAX: dc00 RBX: 88816f81f020 RCX: 0001 > RDX: 000f RSI: 0008 RDI: 9053e5e0 > RBP: 88816f81f000 R08: 0001 R09: 9053e5e7 > R10: fbfff20a7cbc R11: 6e696c6261736944 R12: 0078 > R13: 192006cedeb5 R14: R15: c9003676f870 > FS: 4680f6c0() GS:888fa5c0() knlGS:2991 > CS: 0010 DS: ES: CR0: 80050033 > CR2: 7fb854d6f010 CR3: 00017b2d6000 CR4: 00350ee0 > Call Trace: > > ? __pfx_drm_sched_job_cleanup+0x10/0x10 [gpu_sched] > ? slab_free_freelist_hook+0x11e/0x1d0 > ? amdgpu_cs_parser_fini+0x363/0x5a0 [amdgpu] > amdgpu_job_free+0x40/0x1b0 [amdgpu] > amdgpu_cs_parser_fini+0x3c9/0x5a0 [amdgpu] > ? __pfx_amdgpu_cs_parser_fini+0x10/0x10 [amdgpu] > amdgpu_cs_ioctl+0x3d9/0x5630 [amdgp
Re: [PATCH 1/9] drm: execution context for GEM buffers v3
Hi Christian, hi Thomas, On Fri, Mar 10, 2023 at 11:42:56AM +0100, Thomas Hellström (Intel) wrote: > Nice. This seems to have all we need for now for Xe as well, although not > for i915 ATM. A series to use drm_exec in Xe has been sent for review: https://patchwork.freedesktop.org/series/116477/ Thanks, Francois
[PATCH] drm/amd/pm: change pmfw_decoded_link_width, speed variables to globals
gcc with W=1 reports
In file included from
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.c:36:
./drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0.h:66:18: error:
‘pmfw_decoded_link_width’ defined but not used
[-Werror=unused-const-variable=]
66 | static const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
| ^~~
./drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0.h:65:18: error:
‘pmfw_decoded_link_speed’ defined but not used
[-Werror=unused-const-variable=]
65 | static const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
| ^~~
These variables are defined and used in smu_v13_0_7_ppt.c and smu_v13_0_0_ppt.c.
There should be only one definition. So define the variables as globals
in smu_v13_0.c
Signed-off-by: Tom Rix
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 4 ++--
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 7944ce80e5c3..df3baaab0037 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -62,8 +62,8 @@
#define CTF_OFFSET_HOTSPOT 5
#define CTF_OFFSET_MEM 5
-static const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
-static const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
+extern const int pmfw_decoded_link_speed[5];
+extern const int pmfw_decoded_link_width[7];
#define DECODE_GEN_SPEED(gen_speed_idx)
(pmfw_decoded_link_speed[gen_speed_idx])
#define DECODE_LANE_WIDTH(lane_width_idx)
(pmfw_decoded_link_width[lane_width_idx])
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 73175c993da9..393c6a7b9609 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -85,6 +85,9 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static const int link_speed[] = {25, 50, 80, 160};
+const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
+const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
+
int smu_v13_0_init_microcode(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
--
2.27.0
Re: [PATCH v4 3/3] drm/amdgpu: Add support for querying the max ibs in a submission. (v3)
Am 13.04.23 um 16:22 schrieb Bas Nieuwenhuizen:
This info would be used by radv to figure out when we need to
split a submission into multiple submissions. radv currently has
a limit of 192 which seems to work for most gfx submissions, but
is way too high for e.g. compute or sdma.
Userspace is available at
https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3
v3: Completely rewrote based on suggestion of making it a separate query.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +
include/uapi/drm/amdgpu_drm.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 0efb38539d70..1a2e342af1c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1140,6 +1140,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file *filp)
kfree(caps);
return r;
}
+ case AMDGPU_INFO_MAX_IBS: {
+ uint32_t max_ibs[AMDGPU_HW_IP_NUM];
+
+ for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
+ max_ibs[i] = amdgpu_ring_max_ibs(i);
+
+ return copy_to_user(out, max_ibs,
+ min((size_t)size, sizeof(max_ibs))) ?
-EFAULT : 0;
+ }
default:
DRM_DEBUG_KMS("Invalid request %d\n", info->query);
return -EINVAL;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index b6eb90df5d05..6981e59a9401 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -876,6 +876,8 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
/* Subquery id: Encode */
#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
+/* Query the max number of IBs per gang per submission */
+#define AMDGPU_INFO_MAX_IBS0x22
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
Re: [PATCH v4 2/3] drm/amdgpu: Add a max ibs per submission limit.
Am 13.04.23 um 16:22 schrieb Bas Nieuwenhuizen:
And ensure each ring supports that many submissions. This makes
sure that we don't get surprises after the submission has been
scheduled where the ring allocation actually gets rejected.
My calculations on the existing limits:
COMPUTE v10: 128
COMPUTE v11: 128
COMPUTE v6: 157
COMPUTE v7: 133
COMPUTE v8: 130
COMPUTE v9: 125
GFX v10: 208
GFX v11: 213
GFX v6: 154 (doubling this in the previous patch)
GFX v7: 226
GFX v8: 213
GFX v9: 208
GFX v9 (SW): 208
SDMA CIK: 87
SDMA SI: 97
SDMA v2.4: 74
SDMA v3.0: 74
SDMA v4.0: 72
SDMA v5.0: 51
SDMA v6.0: 52
UVD ENC v6.0: 98
UVD ENC v7.0: 92
UVD v3.1: 124
UVD v4.2: 124
UVD v5.0: 83
UVD v6.0 (VM): 55
UVD v7.0: 51
VCE v2.0: 126
VCE v3.0 (VM): 98
VCE v4.0: 93
VCN DEC v1.0: 49
VCN DEC v2.0: 51
VCN DEC v3.0: 51
VCN ENC v1.0: 58
VCN ENC v2.0: 93
VCN ENC v3.0: 93
VCN ENC v4.0: 93
VCN JPEG v1.0: 17
VCN JPEG v2.0: 16
VCN JPEG v2.5: 17
VCN JPEG v3.0: 17
VCN JPEG v4.0: 17
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 29
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 7af3041ccd0e..8362738974c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -110,6 +110,9 @@ static int amdgpu_cs_p1_ib(struct amdgpu_cs_parser *p,
if (r < 0)
return r;
+ if (num_ibs[r] >= amdgpu_ring_max_ibs(chunk_ib->ip_type))
+ return -EINVAL;
+
++(num_ibs[r]);
p->gang_leader_idx = r;
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index dc474b809604..f676c236b657 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -49,6 +49,26 @@
* them until the pointers are equal again.
*/
+/**
+ * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission.
+ *
+ * @type: ring type for which to return the limit.
+ */
+unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
+{
+ switch (type) {
+ case AMDGPU_RING_TYPE_GFX:
+ /* Need to keep at least 192 on GFX7+ for old radv. */
+ return 192;
+ case AMDGPU_RING_TYPE_COMPUTE:
+ return 125;
+ case AMDGPU_RING_TYPE_VCN_JPEG:
+ return 16;
+ default:
+ return 49;
+ }
+}
+
/**
* amdgpu_ring_alloc - allocate space on the ring buffer
*
@@ -182,6 +202,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct
amdgpu_ring *ring,
int sched_hw_submission = amdgpu_sched_hw_submission;
u32 *num_sched;
u32 hw_ip;
+ unsigned int max_ibs_dw;
/* Set the hw submission limit higher for KIQ because
* it's used for a number of gfx/compute tasks by both
@@ -290,6 +311,14 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct
amdgpu_ring *ring,
return r;
}
+ max_ibs_dw = ring->funcs->emit_frame_size +
+amdgpu_ring_max_ibs(ring->funcs->type) *
ring->funcs->emit_ib_size;
+ max_ibs_dw = (max_ibs_dw + ring->funcs->align_mask) &
~ring->funcs->align_mask;
+
+ if (WARN_ON(max_ibs_dw > max_dw)) {
+ max_dw = max_ibs_dw;
+ }
+
ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
ring->buf_mask = (ring->ring_size / 4) - 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 3989e755a5b4..e6e672727529 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -317,6 +317,7 @@ struct amdgpu_ring {
#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
+unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type);
int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
void amdgpu_ring_ib_end(struct amdgpu_ring *ring);
Re: [PATCH v4 1/3] drm/amdgpu: Increase GFX6 graphics ring size.
Am 13.04.23 um 16:22 schrieb Bas Nieuwenhuizen: To ensure it supports 192 IBs per submission, so we can keep a simplified IB limit in the follow up patch without having to look at IP or GPU version. Signed-off-by: Bas Nieuwenhuizen I've took the time and double checked the docs and the maximum size of the ring buffer on GFX6 is indeed only 1MiB. So even with this change sched_hw_submission can still go as high as 512 without problems (the default is 2 or 4 IIRC). Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index c41219e23151..d9ce4d1c50e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3073,7 +3073,7 @@ static int gfx_v6_0_sw_init(void *handle) ring = &adev->gfx.gfx_ring[i]; ring->ring_obj = NULL; sprintf(ring->name, "gfx"); - r = amdgpu_ring_init(adev, ring, 1024, + r = amdgpu_ring_init(adev, ring, 2048, &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, AMDGPU_RING_PRIO_DEFAULT, NULL);
[PATCH] drm/amdgpu: release gpu full access after "amdgpu_device_ip_late_init"
[WHY]
Function "amdgpu_irq_update()" called by "amdgpu_device_ip_late_init()" is an
atomic context.
We shouldn't access registers through KIQ since "msleep()" may be called in
"amdgpu_kiq_rreg()".
[HOW]
Move function "amdgpu_virt_release_full_gpu()" after function
"amdgpu_device_ip_late_init()",
to ensure that registers be accessed through RLCG instead of KIQ.
Call Trace:
show_stack+0x52/0x69
dump_stack_lvl+0x49/0x6d
dump_stack+0x10/0x18
__schedule_bug.cold+0x4f/0x6b
__schedule+0x473/0x5d0
? __wake_up_klogd.part.0+0x40/0x70
? vprintk_emit+0xbe/0x1f0
schedule+0x68/0x110
schedule_timeout+0x87/0x160
? timer_migration_handler+0xa0/0xa0
msleep+0x2d/0x50
amdgpu_kiq_rreg+0x18d/0x1f0 [amdgpu]
amdgpu_device_rreg.part.0+0x59/0xd0 [amdgpu]
amdgpu_device_rreg+0x3a/0x50 [amdgpu]
amdgpu_sriov_rreg+0x3c/0xb0 [amdgpu]
gfx_v10_0_set_gfx_eop_interrupt_state.constprop.0+0x16c/0x190 [amdgpu]
gfx_v10_0_set_eop_interrupt_state+0xa5/0xb0 [amdgpu]
amdgpu_irq_update+0x53/0x80 [amdgpu]
amdgpu_irq_get+0x7c/0xb0 [amdgpu]
amdgpu_fence_driver_hw_init+0x58/0x90 [amdgpu]
amdgpu_device_init.cold+0x16b7/0x2022 [amdgpu]
Signed-off-by: Chong Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 32 --
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 051b9e231cf4..ee21a99ab4d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2538,8 +2538,6 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
amdgpu_fru_get_product_info(adev);
init_failed:
- if (amdgpu_sriov_vf(adev))
- amdgpu_virt_release_full_gpu(adev, true);
return r;
}
@@ -3856,18 +3854,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_device_ip_init(adev);
if (r) {
- /* failed in exclusive mode due to timeout */
- if (amdgpu_sriov_vf(adev) &&
- !amdgpu_sriov_runtime(adev) &&
- amdgpu_virt_mmio_blocked(adev) &&
- !amdgpu_virt_wait_reset(adev)) {
- dev_err(adev->dev, "VF exclusive mode timeout\n");
- /* Don't send request since VF is inactive. */
- adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
- adev->virt.ops = NULL;
- r = -EAGAIN;
- goto release_ras_con;
- }
dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0,
0);
goto release_ras_con;
@@ -3936,8 +3922,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
msecs_to_jiffies(AMDGPU_RESUME_MS));
}
- if (amdgpu_sriov_vf(adev))
+ if (amdgpu_sriov_vf(adev)) {
+ amdgpu_virt_release_full_gpu(adev, true);
flush_delayed_work(&adev->delayed_init_work);
+ }
r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
if (r)
@@ -3977,6 +3965,20 @@ int amdgpu_device_init(struct amdgpu_device *adev,
return 0;
release_ras_con:
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_release_full_gpu(adev, true);
+
+ /* failed in exclusive mode due to timeout */
+ if (amdgpu_sriov_vf(adev) &&
+ !amdgpu_sriov_runtime(adev) &&
+ amdgpu_virt_mmio_blocked(adev) &&
+ !amdgpu_virt_wait_reset(adev)) {
+ dev_err(adev->dev, "VF exclusive mode timeout\n");
+ /* Don't send request since VF is inactive. */
+ adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
+ adev->virt.ops = NULL;
+ r = -EAGAIN;
+ }
amdgpu_release_ras_context(adev);
failed:
--
2.34.1
[linux-next:master] BUILD REGRESSION e3342532ecd39bbd9c2ab5b9001cec1589bc37e9
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: e3342532ecd39bbd9c2ab5b9001cec1589bc37e9 Add linux-next specific files for 20230413 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202303161521.jbgbafjj-...@intel.com https://lore.kernel.org/oe-kbuild-all/202304061839.hi01vpl1-...@intel.com https://lore.kernel.org/oe-kbuild-all/202304102354.q4voxgte-...@intel.com https://lore.kernel.org/oe-kbuild-all/202304140706.aobnhuj2-...@intel.com https://lore.kernel.org/oe-kbuild-all/202304140707.coh337ux-...@intel.com https://lore.kernel.org/oe-kbuild-all/202304140732.nzcq7rdc-...@intel.com Error/Warning: (recently discovered and may have been fixed) drivers/bluetooth/hci_qca.c:1894:37: warning: unused variable 'qca_soc_data_wcn6855' [-Wunused-const-variable] drivers/clk/clk-sp7021.c:316:8: warning: result of comparison of constant 18446744073709551615 with expression of type 'typeof (_Generic((_m), char: (unsigned char)0, unsigned char: (unsigned char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned long long: (unsigned long long)0, long long: (unsigned long long)0, default: (_m)))' (aka 'unsigned int') is always false [-Wtautological-constant-out-of-range-compare] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:351:13: warning: variable 'bw_needed' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:352:25: warning: variable 'link' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h:62: warning: wrong kernel-doc identifier on line: drivers/gpu/drm/i915/i915_pmu.h:41: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/gpu/drm/i915/i915_request.h:176: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/gpu/drm/i915/i915_vma.h:145: warning: expecting prototype for i915_vma_offset(). Prototype was for i915_vma_size() instead drivers/net/wireless/legacy/ray_cs.c:628:17: warning: 'strncpy' specified bound 32 equals destination size [-Wstringop-truncation] drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240: undefined reference to `__floatundidf' drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: warning: variable 'ret' is uninitialized when used here [-Wuninitialized] kismet: WARNING: unmet direct dependencies detected for RESET_STARFIVE_JH7110 when selected by CLK_STARFIVE_JH7110_SYS loongarch64-linux-ld: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240: undefined reference to `__ltdf2' loongarch64-linux-ld: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:242: undefined reference to `__gedf2' phy-mtk-hdmi-mt8195.c:(.text+0x228): undefined reference to `__floatundidf' phy-mtk-hdmi-mt8195.c:(.text+0x23c): undefined reference to `__ltdf2' phy-mtk-hdmi-mt8195.c:(.text+0x264): undefined reference to `__gedf2' Unverified Error/Warning (likely false positive, please contact us if interested): drivers/acpi/property.c:985 acpi_data_prop_read_single() error: potentially dereferencing uninitialized 'obj'. drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240 mtk_hdmi_pll_calc() warn: impossible condition '(tmds_clk < 1.483500e+02 * 100) => (0.00e+00-1.844674e+19 < -1.786711e-113)' drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:242 mtk_hdmi_pll_calc() warn: always true condition '(tmds_clk >= 1.483500e+02 * 100) => (0-u64max >= -1.786711e-113)' drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:242 mtk_hdmi_pll_calc() warn: impossible condition '(tmds_clk < 2.967000e+02 * 100) => (0.00e+00-1.844674e+19 < -4.419080e+60)' drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:244 mtk_hdmi_pll_calc() warn: always true condition '(tmds_clk >= 2.967000e+02 * 100) => (0-u64max >= -4.419080e+60)' drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:331 mtk_hdmi_pll_drv_setting() warn: always true condition '(pixel_clk >= 7.417500e+01 * 100) => (0-u32max >= -7.223985e-287)' drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:336 mtk_hdmi_pll_drv_setting() warn: impossible condition '(pixel_clk < 7.417500e+01 * 100) => (0.00e+00-4.294967e+09 < -7.223985e-287)' Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-link-set-but-not-used | `-- drivers-net-wir
