Re: [PATCH] kernel/resource: optimize find_next_iomem_res
On Mon, Jun 3, 2024 at 12:24 AM Ilpo Järvinen wrote: > > On Sun, 2 Jun 2024, Andy Shevchenko wrote: > > > On Fri, May 31, 2024 at 02:31:45PM -0700, Chia-I Wu wrote: > > > On Fri, May 31, 2024 at 1:57 AM Andy Shevchenko < > > > andriy.shevche...@linux.intel.com> wrote: > > > > On Thu, May 30, 2024 at 10:36:57PM -0700, Chia-I Wu wrote: > > > > ... > > > > > > P.S> I'm not so sure about this change. It needs a thoroughly testing, > > > > esp. > > > > in PCI case. Cc'ing to Ilpo. > > > > > What's special about PCI? > > > > PCI, due to its nature, may rebuild resources either by shrinking or > > expanding > > of the entire subtree after the PCI bridge in question. And this may happen > > at > > run-time due to hotplug support. But I'm not a deep expert in this area, > > Ilpo > > knows much more than me. > > There is code which clearly tries to do expanding resource but that > usually fails to work as intended because of a parent resource whose size > is fixed because it's already assigned. > > Some other code might block shrinking too under certain conditions. > > This area would need to be reworked in PCI core but it's massive and > scary looking change. Given the nature of this change (skip checking against children when the parent does not match), unless a child resource can exceed its parent resource, I don't think this change affects correctness. The walk does not hold the resource lock outside of find_next_iomem_res(). Updating the tree while the walk is in progress has always been a bit ill-defined. The patch does not change that (but it might change the timing a bit). I can export __walk_iomem_res_desc() and write some unit tests against it. Would that be enough to justify this change? > > -- > i.
RE: [PATCH 05/12] drm/amd/pm: remove dead code in navi10_emit_clk_levels and navi10_print_clk_levels
[AMD Official Use Only - AMD Internal Distribution Only]
Thank you for your clarification.
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: Zhang, Jesse(Jie)
Sent: Tuesday, June 4, 2024 11:52 AM
To: Wang, Yang(Kevin) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Kuehling, Felix ; Huang,
Tim
Subject: RE: [PATCH 05/12] drm/amd/pm: remove dead code in
navi10_emit_clk_levels and navi10_print_clk_levels
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Kevin
I guess you didn't apply the patch correctly.
This patch doesn't remove default branch for clk_type.
In the case of SMU_OD_VDDC_CURVE in function navi10_emit_clk_levels , The
variable i ranges from 0 -3, so the default branch in case SMU_OD_VDDC_CURVE
cannot be executed.
static int navi10_emit_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
char *buf,
int *offset) {
switch (clk_type) {
...
case SMU_OD_VDDC_CURVE:
if (!smu->od_enabled || !od_table || !od_settings)
return -EOPNOTSUPP;
if (!navi10_od_feature_is_supported(od_settings,
SMU_11_0_ODCAP_GFXCLK_CURVE))
break;
*offset += sysfs_emit_at(buf, *offset, "OD_VDDC_CURVE:\n");
for (i = 0; i < 3; i++) {
switch (i) {
case 0:
curve_settings = _table->GfxclkFreq1;
break;
case 1:
curve_settings = _table->GfxclkFreq2;
break;
case 2:
curve_settings = _table->GfxclkFreq3;
break;
default: //don't need the default case.
break;
}
}
Thanks
Jesse
-Original Message-
From: Wang, Yang(Kevin)
Sent: Tuesday, June 4, 2024 10:39 AM
To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Kuehling, Felix ; Huang,
Tim
Subject: RE: [PATCH 05/12] drm/amd/pm: remove dead code in
navi10_emit_clk_levels and navi10_print_clk_levels
[AMD Official Use Only - AMD Internal Distribution Only]
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.o
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:
In function 'navi10_emit_clk_levels':
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_VCLK1' not handled in switch [-Wswitch]
1275 | switch (clk_type) {
| ^~
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_DCLK1' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_ECLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_DISPCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_PIXCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_PHYCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_LCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_CCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_VDDGFX_OFFSET' not handled in switch
[-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_FAN_CURVE' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_ACOUSTIC_LIMIT' not handled in switch
[-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_ACOUSTIC_TARGET' not handled in switch
[-Wswitch]
RE: [PATCH 05/12] drm/amd/pm: remove dead code in navi10_emit_clk_levels and navi10_print_clk_levels
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Kevin
I guess you didn't apply the patch correctly.
This patch doesn't remove default branch for clk_type.
In the case of SMU_OD_VDDC_CURVE in function navi10_emit_clk_levels ,
The variable i ranges from 0 -3, so the default branch in case
SMU_OD_VDDC_CURVE cannot be executed.
static int navi10_emit_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
char *buf,
int *offset)
{
switch (clk_type) {
...
case SMU_OD_VDDC_CURVE:
if (!smu->od_enabled || !od_table || !od_settings)
return -EOPNOTSUPP;
if (!navi10_od_feature_is_supported(od_settings,
SMU_11_0_ODCAP_GFXCLK_CURVE))
break;
*offset += sysfs_emit_at(buf, *offset, "OD_VDDC_CURVE:\n");
for (i = 0; i < 3; i++) {
switch (i) {
case 0:
curve_settings = _table->GfxclkFreq1;
break;
case 1:
curve_settings = _table->GfxclkFreq2;
break;
case 2:
curve_settings = _table->GfxclkFreq3;
break;
default: //don't need the default case.
break;
}
}
Thanks
Jesse
-Original Message-
From: Wang, Yang(Kevin)
Sent: Tuesday, June 4, 2024 10:39 AM
To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Kuehling, Felix ; Huang,
Tim
Subject: RE: [PATCH 05/12] drm/amd/pm: remove dead code in
navi10_emit_clk_levels and navi10_print_clk_levels
[AMD Official Use Only - AMD Internal Distribution Only]
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.o
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:
In function 'navi10_emit_clk_levels':
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_VCLK1' not handled in switch [-Wswitch]
1275 | switch (clk_type) {
| ^~
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_DCLK1' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_ECLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_DISPCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_PIXCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_PHYCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_LCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_CCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_VDDGFX_OFFSET' not handled in switch
[-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_FAN_CURVE' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_ACOUSTIC_LIMIT' not handled in switch
[-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_ACOUSTIC_TARGET' not handled in switch
[-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_FAN_TARGET_TEMPERATURE' not handled in
switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_FAN_MINIMUM_PWM' not handled in switch
[-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value
RE: [PATCH] drm/amdgpu: Set PTE_IS_PTE bit for gfx12
[AMD Official Use Only - AMD Internal Distribution Only] Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: Min, Frank Sent: Monday, June 3, 2024 23:04 To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Koenig, Christian ; Zhang, Hawking ; Gao, Likun ; Olsak, Marek Subject: RE: [PATCH] drm/amdgpu: Set PTE_IS_PTE bit for gfx12 [AMD Official Use Only - AMD Internal Distribution Only] From: Frank Min Set PTE_IS_PTE bit while PRT is enabled on gfx12. Signed-off-by: Frank Min --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 7d99fcc58baf..e09be1a6c7d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -512,6 +512,7 @@ static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, *flags |= AMDGPU_PTE_PRT_GFX12; *flags |= AMDGPU_PTE_SNOOPED; *flags |= AMDGPU_PTE_SYSTEM; + *flags |= AMDGPU_PTE_IS_PTE; *flags &= ~AMDGPU_PTE_VALID; } -- 2.34.1
RE: [PATCH 05/12] drm/amd/pm: remove dead code in navi10_emit_clk_levels and navi10_print_clk_levels
[AMD Official Use Only - AMD Internal Distribution Only]
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.o
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:
In function 'navi10_emit_clk_levels':
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_VCLK1' not handled in switch [-Wswitch]
1275 | switch (clk_type) {
| ^~
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_DCLK1' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_ECLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_DISPCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_PIXCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_PHYCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_LCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_CCLK' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_VDDGFX_OFFSET' not handled in switch
[-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_FAN_CURVE' not handled in switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_ACOUSTIC_LIMIT' not handled in switch
[-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_ACOUSTIC_TARGET' not handled in switch
[-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_FAN_TARGET_TEMPERATURE' not handled in
switch [-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_OD_FAN_MINIMUM_PWM' not handled in switch
[-Wswitch]
/home/kevin/Work/disk/linux/linux-next/drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.c:1275:9:
warning: enumeration value 'SMU_CLK_COUNT' not handled in switch [-Wswitch]
LD [M] drivers/gpu/drm/amd/amdgpu/amdgpu.o
After applied your patch , the kernel will show above compile warnings with
'W=1' flag.
# grep -nR -A 1 "default:" drivers | grep -i 'break' -B 1
And the above command will show all similar cases in kernel driver folder.
So, your patch is not necessary as my understanding.
Best Regards,
Kevin
-Original Message-
From: Zhang, Jesse(Jie)
Sent: Tuesday, June 4, 2024 9:23 AM
To: Wang, Yang(Kevin) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Kuehling, Felix ; Huang,
Tim
Subject: RE: [PATCH 05/12] drm/amd/pm: remove dead code in
navi10_emit_clk_levels and navi10_print_clk_levels
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Kevin,
-Original Message-
From: Wang, Yang(Kevin)
Sent: Monday, June 3, 2024 5:09 PM
To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Kuehling, Felix ; Huang,
Tim ; Zhang, Jesse(Jie) ; Zhang,
Jesse(Jie)
Subject: RE: [PATCH 05/12] drm/amd/pm: remove dead code in
navi10_emit_clk_levels and navi10_print_clk_levels
[AMD Official Use Only - AMD Internal Distribution Only]
Could you share the problems you encountered?
Some compilers may prompt you to forget to handle default cases.
[Zhang, Jesse(Jie)] These warning scan by Coverity. These are useless redundant
codes.
Thanks
Jesse
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Jesse Zhang
Sent: Monday, June 3, 2024 4:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Kuehling, Felix ; Huang,
Tim ; Zhang, Jesse(Jie) ; Zhang,
Jesse(Jie)
Subject: [PATCH 05/12] drm/amd/pm: remove dead code in navi10_emit_clk_levels
and navi10_print_clk_levels
Since the range of the varibable i is 0 - 3.
So execution cannot reach this statement: default.
Signed-off-by: Jesse Zhang
---
[PATCH] drm/amdgpu: Update soc24_enum.h and soc21_enum.h
[AMD Official Use Only - AMD Internal Distribution Only]
From: Frank Min mailto:frank@amd.com>>
Update to latest changes.
Signed-off-by: Frank Min mailto:frank@amd.com>>
---
drivers/gpu/drm/amd/include/soc21_enum.h | 2 +-
drivers/gpu/drm/amd/include/soc24_enum.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/soc21_enum.h
b/drivers/gpu/drm/amd/include/soc21_enum.h
index 951ec2900c61..07d98bff7f73 100644
--- a/drivers/gpu/drm/amd/include/soc21_enum.h
+++ b/drivers/gpu/drm/amd/include/soc21_enum.h
@@ -92,7 +92,7 @@ DSM_SINGLE_WRITE_EN = 0x0001,
*/
typedef enum ENUM_NUM_SIMD_PER_CU {
-NUM_SIMD_PER_CU = 0x0004,
+NUM_SIMD_PER_CU = 0x0002,
} ENUM_NUM_SIMD_PER_CU;
/*
diff --git a/drivers/gpu/drm/amd/include/soc24_enum.h
b/drivers/gpu/drm/amd/include/soc24_enum.h
index c47b8cc2f203..3eb7662bbbda 100644
--- a/drivers/gpu/drm/amd/include/soc24_enum.h
+++ b/drivers/gpu/drm/amd/include/soc24_enum.h
@@ -73,7 +73,7 @@ CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x0005,
*/
typedef enum ENUM_NUM_SIMD_PER_CU {
-NUM_SIMD_PER_CU = 0x0004,
+NUM_SIMD_PER_CU = 0x0002,
} ENUM_NUM_SIMD_PER_CU;
/*
--
2.34.1
Re: [PATCH v2] drm/client: Detect when ACPI lid is closed during initialization
Hi Mario,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on drm/drm-next drm-exynos/exynos-drm-next
drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip
linus/master v6.10-rc2 next-20240603]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Mario-Limonciello/drm-client-Detect-when-ACPI-lid-is-closed-during-initialization/20240529-050440
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
https://lore.kernel.org/r/20240528210319.1242-1-mario.limonciello%40amd.com
patch subject: [PATCH v2] drm/client: Detect when ACPI lid is closed during
initialization
config: i386-randconfig-053-20240604
(https://download.01.org/0day-ci/archive/20240604/202406040928.eu1griwv-...@intel.com/config)
compiler: gcc-9 (Ubuntu 9.5.0-4ubuntu2) 9.5.0
reproduce (this is a W=1 build):
(https://download.01.org/0day-ci/archive/20240604/202406040928.eu1griwv-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202406040928.eu1griwv-...@intel.com/
All errors (new ones prefixed by >>):
ld: drivers/gpu/drm/drm_client_modeset.o: in function
`drm_client_match_edp_lid':
>> drivers/gpu/drm/drm_client_modeset.c:281:(.text+0x221b): undefined reference
>> to `acpi_lid_open'
vim +281 drivers/gpu/drm/drm_client_modeset.c
260
261 static void drm_client_match_edp_lid(struct drm_device *dev,
262 struct drm_connector **connectors,
263 unsigned int connector_count,
264 bool *enabled)
265 {
266 int i;
267
268 for (i = 0; i < connector_count; i++) {
269 struct drm_connector *connector = connectors[i];
270
271 switch (connector->connector_type) {
272 case DRM_MODE_CONNECTOR_LVDS:
273 case DRM_MODE_CONNECTOR_eDP:
274 if (!enabled[i])
275 continue;
276 break;
277 default:
278 continue;
279 }
280
> 281 if (!acpi_lid_open()) {
282 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] lid is
closed, disabling\n",
283 connector->base.id,
connector->name);
284 enabled[i] = false;
285 }
286 }
287 }
288
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
RE: [PATCH 05/12] drm/amd/pm: remove dead code in navi10_emit_clk_levels and navi10_print_clk_levels
[AMD Official Use Only - AMD Internal Distribution Only] Hi Kevin, -Original Message- From: Wang, Yang(Kevin) Sent: Monday, June 3, 2024 5:09 PM To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Koenig, Christian ; Kuehling, Felix ; Huang, Tim ; Zhang, Jesse(Jie) ; Zhang, Jesse(Jie) Subject: RE: [PATCH 05/12] drm/amd/pm: remove dead code in navi10_emit_clk_levels and navi10_print_clk_levels [AMD Official Use Only - AMD Internal Distribution Only] Could you share the problems you encountered? Some compilers may prompt you to forget to handle default cases. [Zhang, Jesse(Jie)] These warning scan by Coverity. These are useless redundant codes. Thanks Jesse Best Regards, Kevin -Original Message- From: amd-gfx On Behalf Of Jesse Zhang Sent: Monday, June 3, 2024 4:48 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Koenig, Christian ; Kuehling, Felix ; Huang, Tim ; Zhang, Jesse(Jie) ; Zhang, Jesse(Jie) Subject: [PATCH 05/12] drm/amd/pm: remove dead code in navi10_emit_clk_levels and navi10_print_clk_levels Since the range of the varibable i is 0 - 3. So execution cannot reach this statement: default. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index cf556f1b5ed1..076620fa3ef5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -1389,8 +1389,6 @@ static int navi10_emit_clk_levels(struct smu_context *smu, case 2: curve_settings = _table->GfxclkFreq3; break; - default: - break; } *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n", i, curve_settings[0], @@ -1594,8 +1592,6 @@ static int navi10_print_clk_levels(struct smu_context *smu, case 2: curve_settings = _table->GfxclkFreq3; break; - default: - break; } size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n", i, curve_settings[0], -- 2.25.1
Re: [PATCH] drm/amd/display: Increase frame-larger-than warning limit
Hi Palmer,
On Thu, May 30, 2024 at 07:57:42AM -0700, Palmer Dabbelt wrote:
> From: Palmer Dabbelt
>
> I get a handful of build errors along the lines of
>
>
> linux/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:58:13:
> error: stack frame size (2352) exceeds limit (2048) in
> 'DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation'
> [-Werror,-Wframe-larger-than]
> static void
> DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
> ^
>
> linux/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1724:6:
> error: stack frame size (2096) exceeds limit (2048) in
> 'dml32_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than]
> void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib
> *mode_lib)
> ^
Judging from the message, this is clang/LLVM? What version? I assume
this showed up in 6.10-rc1 because of commit 77acc6b55ae4 ("riscv: add
support for kernel-mode FPU"), which allows this driver to be built for
RISC-V. Is this allmodconfig or some other configuration?
> as of 6.10-rc1.
>
> Signed-off-by: Palmer Dabbelt
> ---
> drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile
> b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> index c4a5efd2dda5..b2bd72e63734 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> @@ -62,9 +62,9 @@ endif
>
> ifneq ($(CONFIG_FRAME_WARN),0)
> ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
> -frame_warn_flag := -Wframe-larger-than=3072
> +frame_warn_flag := -Wframe-larger-than=4096
> else
> -frame_warn_flag := -Wframe-larger-than=2048
> +frame_warn_flag := -Wframe-larger-than=3072
> endif
> endif
>
> --
> 2.45.1
>
[PATCH 3/3] drm/amdgpu: remove amdgpu_mes_fence_wait_polling()
No longer used so remove it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 12
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 4
2 files changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 62edf6328566..e0c36e0d7beb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -32,18 +32,6 @@
#define AMDGPU_MES_MAX_NUM_OF_QUEUES_PER_PROCESS 1024
#define AMDGPU_ONE_DOORBELL_SIZE 8
-signed long amdgpu_mes_fence_wait_polling(u64 *fence,
- u64 wait_seq,
- signed long timeout)
-{
-
- while ((s64)(wait_seq - *fence) > 0 && timeout > 0) {
- udelay(2);
- timeout -= 2;
- }
- return timeout > 0 ? timeout : 0;
-}
-
int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev)
{
return roundup(AMDGPU_ONE_DOORBELL_SIZE *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index df9f0404d842..e11051271f71 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -352,10 +352,6 @@ struct amdgpu_mes_funcs {
#define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
#define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev))
-signed long amdgpu_mes_fence_wait_polling(u64 *fence,
- u64 wait_seq,
- signed long timeout);
-
int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);
int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
--
2.45.1
[PATCH 1/3] drm/amdgpu: cleanup MES11 command submission
From: Christian König
The approach of having a separate WB slot for each submission doesn't
really work well and for example breaks GPU reset.
Use a status query packet for the fence update instead since those
should always succeed we can use the fence of the original packet to
signal the state of the operation.
While at it cleanup the coding style.
Fixes: eef016ba8986 ("drm/amdgpu/mes11: Use a separate fence per transaction")
Signed-off-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 76 --
1 file changed, 48 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 8263b97c4466..3b1f6ad99100 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -154,18 +154,18 @@ static int
mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
void *pkt, int size,
int api_status_off)
{
- int ndw = size / 4;
- signed long r;
- union MESAPI__MISC *x_pkt = pkt;
- struct MES_API_STATUS *api_status;
+ union MESAPI__QUERY_MES_STATUS mes_status_pkt;
+ signed long timeout = 300; /* 3000 ms */
struct amdgpu_device *adev = mes->adev;
struct amdgpu_ring *ring = >ring;
- unsigned long flags;
- signed long timeout = 300; /* 3000 ms */
+ struct MES_API_STATUS *api_status;
+ union MESAPI__MISC *x_pkt = pkt;
const char *op_str, *misc_op_str;
- u32 fence_offset;
- u64 fence_gpu_addr;
- u64 *fence_ptr;
+ unsigned long flags;
+ u64 status_gpu_addr;
+ u32 status_offset;
+ u64 *status_ptr;
+ signed long r;
int ret;
if (x_pkt->header.opcode >= MES_SCH_API_MAX)
@@ -177,28 +177,38 @@ static int
mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
/* Worst case in sriov where all other 15 VF timeout, each VF
needs about 600ms */
timeout = 15 * 600 * 1000;
}
- BUG_ON(size % 4 != 0);
- ret = amdgpu_device_wb_get(adev, _offset);
+ ret = amdgpu_device_wb_get(adev, _offset);
if (ret)
return ret;
- fence_gpu_addr =
- adev->wb.gpu_addr + (fence_offset * 4);
- fence_ptr = (u64 *)>wb.wb[fence_offset];
- *fence_ptr = 0;
+
+ status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);
+ status_ptr = (u64 *)>wb.wb[status_offset];
+ *status_ptr = 0;
spin_lock_irqsave(>ring_lock, flags);
- if (amdgpu_ring_alloc(ring, ndw)) {
- spin_unlock_irqrestore(>ring_lock, flags);
- amdgpu_device_wb_free(adev, fence_offset);
- return -ENOMEM;
- }
+ r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
+ if (r)
+ goto error_unlock_free;
api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
- api_status->api_completion_fence_addr = fence_gpu_addr;
+ api_status->api_completion_fence_addr = status_gpu_addr;
api_status->api_completion_fence_value = 1;
- amdgpu_ring_write_multiple(ring, pkt, ndw);
+ amdgpu_ring_write_multiple(ring, pkt, size / 4);
+
+ memset(_status_pkt, 0, sizeof(mes_status_pkt));
+ mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
+ mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
+ mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+ mes_status_pkt.api_status.api_completion_fence_addr =
+ ring->fence_drv.gpu_addr;
+ mes_status_pkt.api_status.api_completion_fence_value =
+ ++ring->fence_drv.sync_seq;
+
+ amdgpu_ring_write_multiple(ring, _status_pkt,
+ sizeof(mes_status_pkt) / 4);
+
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
@@ -206,15 +216,16 @@ static int
mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
misc_op_str = mes_v11_0_get_misc_op_string(x_pkt);
if (misc_op_str)
- dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str,
misc_op_str);
+ dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str,
+ misc_op_str);
else if (op_str)
dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str);
else
- dev_dbg(adev->dev, "MES msg=%d was emitted\n",
x_pkt->header.opcode);
+ dev_dbg(adev->dev, "MES msg=%d was emitted\n",
+ x_pkt->header.opcode);
- r = amdgpu_mes_fence_wait_polling(fence_ptr, (u64)1, timeout);
- amdgpu_device_wb_free(adev, fence_offset);
- if (r < 1) {
+ r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
[PATCH 2/3] drm/amdgpu: cleanup MES12 command submission
The approach of having a separate WB slot for each submission doesn't
really work well and for example breaks GPU reset.
Use a status query packet for the fence update instead since those
should always succeed we can use the fence of the original packet to
signal the state of the operation.
While at it cleanup the coding style.
Fixes: ade887c63394 ("drm/amdgpu/mes12: Use a separate fence per transaction")
Suggested-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 76 --
1 file changed, 48 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index f18fdda023c9..106eef1ff5cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -144,18 +144,18 @@ static int
mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
void *pkt, int size,
int api_status_off)
{
- int ndw = size / 4;
- signed long r;
- union MESAPI__MISC *x_pkt = pkt;
- struct MES_API_STATUS *api_status;
+ union MESAPI__QUERY_MES_STATUS mes_status_pkt;
+ signed long timeout = 300; /* 3000 ms */
struct amdgpu_device *adev = mes->adev;
struct amdgpu_ring *ring = >ring;
- unsigned long flags;
+ struct MES_API_STATUS *api_status;
+ union MESAPI__MISC *x_pkt = pkt;
const char *op_str, *misc_op_str;
- signed long timeout = 300; /* 3000 ms */
- u32 fence_offset;
- u64 fence_gpu_addr;
- u64 *fence_ptr;
+ unsigned long flags;
+ u64 status_gpu_addr;
+ u32 status_offset;
+ u64 *status_ptr;
+ signed long r;
int ret;
if (x_pkt->header.opcode >= MES_SCH_API_MAX)
@@ -167,28 +167,38 @@ static int
mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
/* Worst case in sriov where all other 15 VF timeout, each VF
needs about 600ms */
timeout = 15 * 600 * 1000;
}
- BUG_ON(size % 4 != 0);
- ret = amdgpu_device_wb_get(adev, _offset);
+ ret = amdgpu_device_wb_get(adev, _offset);
if (ret)
return ret;
- fence_gpu_addr =
- adev->wb.gpu_addr + (fence_offset * 4);
- fence_ptr = (u64 *)>wb.wb[fence_offset];
- *fence_ptr = 0;
+
+ status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);
+ status_ptr = (u64 *)>wb.wb[status_offset];
+ *status_ptr = 0;
spin_lock_irqsave(>ring_lock, flags);
- if (amdgpu_ring_alloc(ring, ndw)) {
- spin_unlock_irqrestore(>ring_lock, flags);
- amdgpu_device_wb_free(adev, fence_offset);
- return -ENOMEM;
- }
+ r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
+ if (r)
+ goto error_unlock_free;
api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
- api_status->api_completion_fence_addr = fence_gpu_addr;
+ api_status->api_completion_fence_addr = status_gpu_addr;
api_status->api_completion_fence_value = 1;
- amdgpu_ring_write_multiple(ring, pkt, ndw);
+ amdgpu_ring_write_multiple(ring, pkt, size / 4);
+
+ memset(_status_pkt, 0, sizeof(mes_status_pkt));
+ mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
+ mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
+ mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+ mes_status_pkt.api_status.api_completion_fence_addr =
+ ring->fence_drv.gpu_addr;
+ mes_status_pkt.api_status.api_completion_fence_value =
+ ++ring->fence_drv.sync_seq;
+
+ amdgpu_ring_write_multiple(ring, _status_pkt,
+ sizeof(mes_status_pkt) / 4);
+
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
@@ -196,16 +206,17 @@ static int
mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
misc_op_str = mes_v12_0_get_misc_op_string(x_pkt);
if (misc_op_str)
- dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str,
misc_op_str);
+ dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str,
+ misc_op_str);
else if (op_str)
dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str);
else
- dev_dbg(adev->dev, "MES msg=%d was emitted\n",
x_pkt->header.opcode);
+ dev_dbg(adev->dev, "MES msg=%d was emitted\n",
+ x_pkt->header.opcode);
- r = amdgpu_mes_fence_wait_polling(fence_ptr, (u64)1, timeout);
- amdgpu_device_wb_free(adev, fence_offset);
+ r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, timeout);
+ if (r < 1 || !*status_ptr) {
[PATCH] Revert "drm/amd/display: dynamically allocate dml2_configuration_options structures"
This reverts commit 416b5c5eec9e708b31c68f00cb79130f2cfaf7ed.
This patch caused a regression on DCN 3.2 on the IGT test assr-links-suspend,
with
the dmesg warning:
BUG: sleeping function called from invalid context at
include/linux/sched/mm.h:306
in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 449, name: kworker/u64:8
preempt_count: 2, expected: 0
RCU nest depth: 0, expected: 0
Preemption disabled at:
c0ce1580>] dc_fpu_begin+0x30/0xd0 [amdgpu]
CPU: 5 PID: 449 Comm: kworker/u64:8 Tainted: GW 6.8.0+ #35
Hardware name: System manufacturer System Product Name/ROG STRIX X570-E GAMING
WIFI II, BIOS 4204 02/24/2022
Workqueue: events_unbound async_run_entry_fn
Reverting this patch will re-introduce stack size warnings.
Cc: Alex Deucher
Signed-off-by: George Zhang
---
.../display/dc/resource/dcn32/dcn32_resource.c | 16 +---
.../display/dc/resource/dcn321/dcn321_resource.c | 16 +---
2 files changed, 10 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 0f11d7c8791c..022d320be1d5 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -2007,27 +2007,21 @@ void dcn32_calculate_wm_and_dlg(struct dc *dc, struct
dc_state *context,
static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params
*bw_params)
{
- struct dml2_configuration_options *dml2_opt;
-
- dml2_opt = kmemdup(>dml2_options, sizeof(dc->dml2_options),
GFP_KERNEL);
- if (!dml2_opt)
- return;
+ struct dml2_configuration_options dml2_opt = dc->dml2_options;
DC_FP_START();
dcn32_update_bw_bounding_box_fpu(dc, bw_params);
- dml2_opt->use_clock_dc_limits = false;
+ dml2_opt.use_clock_dc_limits = false;
if (dc->debug.using_dml2 && dc->current_state &&
dc->current_state->bw_ctx.dml2)
- dml2_reinit(dc, dml2_opt, >current_state->bw_ctx.dml2);
+ dml2_reinit(dc, _opt, >current_state->bw_ctx.dml2);
- dml2_opt->use_clock_dc_limits = true;
+ dml2_opt.use_clock_dc_limits = true;
if (dc->debug.using_dml2 && dc->current_state &&
dc->current_state->bw_ctx.dml2_dc_power_source)
- dml2_reinit(dc, dml2_opt,
>current_state->bw_ctx.dml2_dc_power_source);
+ dml2_reinit(dc, _opt,
>current_state->bw_ctx.dml2_dc_power_source);
DC_FP_END();
-
- kfree(dml2_opt);
}
static struct resource_funcs dcn32_res_pool_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index 07ca6f58447d..e4b360d89b3b 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -1581,27 +1581,21 @@ static struct dc_cap_funcs cap_funcs = {
static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params
*bw_params)
{
- struct dml2_configuration_options *dml2_opt;
-
- dml2_opt = kmemdup(>dml2_options, sizeof(dc->dml2_options),
GFP_KERNEL);
- if (!dml2_opt)
- return;
+ struct dml2_configuration_options dml2_opt = dc->dml2_options;
DC_FP_START();
dcn321_update_bw_bounding_box_fpu(dc, bw_params);
- dml2_opt->use_clock_dc_limits = false;
+ dml2_opt.use_clock_dc_limits = false;
if (dc->debug.using_dml2 && dc->current_state &&
dc->current_state->bw_ctx.dml2)
- dml2_reinit(dc, dml2_opt, >current_state->bw_ctx.dml2);
+ dml2_reinit(dc, _opt, >current_state->bw_ctx.dml2);
- dml2_opt->use_clock_dc_limits = true;
+ dml2_opt.use_clock_dc_limits = true;
if (dc->debug.using_dml2 && dc->current_state &&
dc->current_state->bw_ctx.dml2_dc_power_source)
- dml2_reinit(dc, dml2_opt,
>current_state->bw_ctx.dml2_dc_power_source);
+ dml2_reinit(dc, _opt,
>current_state->bw_ctx.dml2_dc_power_source);
DC_FP_END();
-
- kfree(dml2_opt);
}
static struct resource_funcs dcn321_res_pool_funcs = {
--
2.34.1
RE: [PATCH] drm/amd/display: prevent register access while in IPS
[Public]
Reviewed-by: Roman Li
> -Original Message-
> From: Mahfooz, Hamza
> Sent: Monday, June 3, 2024 10:35 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wentland, Harry ; Li, Sun peng (Leo)
> ; Siqueira, Rodrigo ;
> Deucher, Alexander ; Hung, Alex
> ; Li, Roman ; Mahfooz, Hamza
> ; sta...@vger.kernel.org
> Subject: [PATCH] drm/amd/display: prevent register access while in IPS
>
> We can't read/write to DCN registers while in IPS. Since, that can cause the
> system to hang. So, before proceeding with the access in that scenario, force
> the system out of IPS.
>
> Cc: sta...@vger.kernel.org # 6.6+
> Signed-off-by: Hamza Mahfooz
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10
> ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 059f78c8cd04..c8bc4098ed18 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -11796,6 +11796,12 @@ void amdgpu_dm_trigger_timing_sync(struct
> drm_device *dev)
> mutex_unlock(>dm.dc_lock);
> }
>
> +static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) {
> + if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)
> + dc_exit_ips_for_hw_access(dc);
> +}
> +
> void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
> u32 value, const char *func_name) { @@ -11806,6
> +11812,8 @@ void dm_write_reg_func(const struct dc_context *ctx, uint32_t
> address,
> return;
> }
> #endif
> +
> + amdgpu_dm_exit_ips_for_hw_access(ctx->dc);
> cgs_write_register(ctx->cgs_device, address, value);
> trace_amdgpu_dc_wreg(>perf_trace->write_count, address,
> value); } @@ -11829,6 +11837,8 @@ uint32_t dm_read_reg_func(const
> struct dc_context *ctx, uint32_t address,
> return 0;
> }
>
> + amdgpu_dm_exit_ips_for_hw_access(ctx->dc);
> +
> value = cgs_read_register(ctx->cgs_device, address);
>
> trace_amdgpu_dc_rreg(>perf_trace->read_count, address,
> value);
> --
> 2.45.0
RE: [PATCH v2 03/10] drm/amdgpu: abort fence poll if reset is started
[AMD Official Use Only - AMD Internal Distribution Only] Thanks Christian for the detail explanation. I checked your patch , you try to use query_scheduler_status package to check the command completion . It may not work as expected since this API query the status is for MES itself , so mes can update the fence address with the expected seq value, but the command itself (ex .remove_queue for mes and then mes send the unmap_queue to kiq internally) still fails. For mes , driver always poll for the command completion , do you think it's an acceptable solution that MES set a specific failure value(ex , -1) in the fence address to indicate the failure of the operation ? But that should be similar to let driver poll the completion till timeout . MES internally also need to wait for a timeout on some command that it sent to CP (ex. 2 seconds for unmap_queue command). I'm actually a little bit confused here , has driver use the lock to ensure there is only one submission into MES at any time ? MES can also trigger the interrupt on the failure if driver side require us to do so , the payload will have the seq number to indicate which submission cause the failure , that might requires more code change from driver side .Please let me what's preferred from driver side. Regards Shaoyun.liu -Original Message- From: Koenig, Christian Sent: Monday, June 3, 2024 6:59 AM To: Liu, Shaoyun ; Christian König ; Li, Yunxiang (Teddy) ; amd-gfx@lists.freedesktop.org; Deucher, Alexander ; Xiao, Hua Subject: Re: [PATCH v2 03/10] drm/amdgpu: abort fence poll if reset is started Hi Shaoyun, yes my thinking goes into the same direction. The basic problem here is that we are trying to stuff two different information into the same variable. The first information is if the commands haven been read by the MES from the ring buffer. This information is necessary for the normal ring buffer and reset handling, e.g. prevents ring buffer overflow, ordering of command, lockups during reset etc... The second information is if a certain operation was successfully or not. For example this is necessary to get signaled back if y queue map/unmap operation has been successfully or if the CP not responding or any other error has happened etc... Another issue is that while it is in general a good idea to have the firmware work in a way where errors are reported instead of completely stopping all processing, here we run into trouble because the driver usually assumes that work can be scheduled on the ring buffer and a subsequent work is processed only when everything previously submitted has completed successfully. So as initial fix for the issue we see I've send Alex a patch on Friday to partially revert his change to use an individual writeback for each submission. Instead we will submit an addition QUERY_STATUS command after the real command and let that one write fence value. This way the fence value is always written, independent of the result of the operation. Additional to that we need to insert something like a dependency between submissions, e.g. when you have commands A, B and C on the ring and C can only execute when A was successfully then we need to somehow tell that the MES. Only other alternative is to not scheduler commands behind each other on the ring and that in turn is a bad idea from the performance point of view. Regards, Christian. Am 31.05.24 um 16:44 schrieb Liu, Shaoyun: > [AMD Official Use Only - AMD Internal Distribution Only] > > Hi, Christian > > I think we have a discussion about this before . Alex also have a change that > allow driver to use different write back address for the fence for each > submission for the original issue . > From MES point of view , MES will update the fence when the API can be > complete successfully, so if the API (ex . remove_queue) fails due to > other component issue (ex , CP hang), the MES will not update the fence In > this situation , but MES itself still works and can respond to other > commands (ex ,,read_reg) . Alex's change allow driver to check the fence > for each API without mess around them . If you expect MES to stop > responding to further commands after one API fails , that will introduce > combability issue since this design already exist on products for customer > and MES also need to works for windows . Also MES always need to respond to > some commands like RESET etc that might make things worse if we need to > change the logic . > > One possible solution is MES can trigger an Interrupt to indicate which > submission has failed with the seq number . In this case driver can get the > failure of the submission to MES in time and make its own decision for what > to do next , What do you think about this ? > > Regards > Shaoyun.liu > > -Original Message- > From: amd-gfx On Behalf Of > Christian König > Sent: Wednesday, May 29, 2024 11:19 AM > To: Li,
[PATCH 2/2] drm/amdkfd: add reset cause in gpu pre-reset smi event
reset cause is requested by customer as additional
info for gpu reset smi event.
v2: integerate reset sources suggested by Lijo Lazar
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 10 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 7 ---
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 16 ++--
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h | 5 -
6 files changed, 33 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index e3738d417245..eb601b41d9d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -133,6 +133,9 @@ static void amdgpu_amdkfd_reset_work(struct work_struct
*work)
reset_context.method = AMD_RESET_METHOD_NONE;
reset_context.reset_req_dev = adev;
+ reset_context.src = adev->enable_mes ?
+ AMDGPU_RESET_SRC_MES :
+ AMDGPU_RESET_SRC_HWS;
clear_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
amdgpu_device_gpu_recover(adev, NULL, _context);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 1de021ebdd46..7e945a4790bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -47,6 +47,7 @@ enum TLB_FLUSH_TYPE {
};
struct amdgpu_device;
+struct amdgpu_reset_context;
enum kfd_mem_attachment_type {
KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
@@ -170,7 +171,8 @@ bool amdgpu_amdkfd_have_atomics_support(struct
amdgpu_device *adev);
bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
-int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
+int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev,
+ struct amdgpu_reset_context *reset_context);
int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
@@ -416,7 +418,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
void kgd2kfd_device_exit(struct kfd_dev *kfd);
void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
-int kgd2kfd_pre_reset(struct kfd_dev *kfd);
+int kgd2kfd_pre_reset(struct kfd_dev *kfd,
+ struct amdgpu_reset_context *reset_context);
int kgd2kfd_post_reset(struct kfd_dev *kfd);
void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
@@ -459,7 +462,8 @@ static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool
run_pm)
return 0;
}
-static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)
+static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd,
+ struct amdgpu_reset_context *reset_context)
{
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6711836054f9..4096cb3e937e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5775,7 +5775,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
cancel_delayed_work_sync(_adev->delayed_init_work);
- amdgpu_amdkfd_pre_reset(tmp_adev);
+ amdgpu_amdkfd_pre_reset(tmp_adev, reset_context);
/*
* Mark these ASICs to be reseted as untracked first
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index fba9b9a258a5..52be4e340fb1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -924,7 +924,8 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd)
kfree(kfd);
}
-int kgd2kfd_pre_reset(struct kfd_dev *kfd)
+int kgd2kfd_pre_reset(struct kfd_dev *kfd,
+ struct amdgpu_reset_context *reset_context)
{
struct kfd_node *node;
int i;
@@ -934,7 +935,7 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd)
for (i = 0; i < kfd->num_nodes; i++) {
node = kfd->nodes[i];
- kfd_smi_event_update_gpu_reset(node, false);
+ kfd_smi_event_update_gpu_reset(node, false, reset_context);
node->dqm->ops.pre_reset(node->dqm);
}
@@ -974,7 +975,7 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
for (i = 0; i < kfd->num_nodes; i++) {
node = kfd->nodes[i];
atomic_set(>sram_ecc_flag, 0);
- kfd_smi_event_update_gpu_reset(node, true);
+ kfd_smi_event_update_gpu_reset(node, true, NULL);
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
index 06ac835190f9..ea6a8e43bd5b 100644
---
[PATCH 1/2] drm/amdgpu: add reset sources in gpu reset context
reset source or reset cause is very useful info
for reset context, it will be used by events API.
Suggested-by: Lijo Lazar
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 34 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 13 +
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index bfdde772b7ee..f07f0fb9f827 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -160,3 +160,37 @@ void amdgpu_device_unlock_reset_domain(struct
amdgpu_reset_domain *reset_domain)
atomic_set(_domain->in_gpu_reset, 0);
up_write(_domain->sem);
}
+
+void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf,
+size_t len)
+{
+ struct amdgpu_ring *ring;
+
+ if (!buf || !len)
+ return;
+
+ switch (rst_ctxt->src) {
+ case AMDGPU_RESET_SRC_JOB:
+ if (rst_ctxt->job) {
+ ring = amdgpu_job_ring(rst_ctxt->job);
+ snprintf(buf, len, "job hang on ring:%s", ring->name);
+ } else {
+ strscpy(buf, "job hang", len);
+ }
+ break;
+ case AMDGPU_RESET_SRC_RAS:
+ strscpy(buf, "RAS error", len);
+ break;
+ case AMDGPU_RESET_SRC_MES:
+ strscpy(buf, "MES hang", len);
+ break;
+ case AMDGPU_RESET_SRC_HWS:
+ strscpy(buf, "HWS hang", len);
+ break;
+ case AMDGPU_RESET_SRC_USER:
+ strscpy(buf, "user trigger", len);
+ break;
+ default:
+ strscpy(buf, "unknown", len);
+ }
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
index 5a9cc043b858..9de8e4157a4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
@@ -36,6 +36,15 @@ enum AMDGPU_RESET_FLAGS {
AMDGPU_HOST_FLR = 3,
};
+enum AMDGPU_RESET_SRCS {
+ AMDGPU_RESET_SRC_UNKNOWN,
+ AMDGPU_RESET_SRC_JOB,
+ AMDGPU_RESET_SRC_RAS,
+ AMDGPU_RESET_SRC_MES,
+ AMDGPU_RESET_SRC_HWS,
+ AMDGPU_RESET_SRC_USER,
+};
+
struct amdgpu_reset_context {
enum amd_reset_method method;
struct amdgpu_device *reset_req_dev;
@@ -43,6 +52,7 @@ struct amdgpu_reset_context {
struct amdgpu_hive_info *hive;
struct list_head *reset_device_list;
unsigned long flags;
+ enum AMDGPU_RESET_SRCS src;
};
struct amdgpu_reset_handler {
@@ -130,6 +140,9 @@ void amdgpu_device_lock_reset_domain(struct
amdgpu_reset_domain *reset_domain);
void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain
*reset_domain);
+void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf,
+size_t len);
+
#define for_each_handler(i, handler, reset_ctl) \
for (i = 0; (i < AMDGPU_RESET_MAX_HANDLERS) && \
(handler = (*reset_ctl->reset_handlers)[i]); \
--
2.34.1
Re: [PATCH] drm/amdgpu: use local xcc write to flush tlb
Am 03.06.24 um 13:46 schrieb Yiqing Yao:
When flushing gpu tlb using kiq from gfxhub, kiq ring is always
local as xcc instance is selected for it. Thus using lower 18 bits
to access mmregs inside local xcc instead of full address used
when accessing regs outside of local xcc.
Remove redundent code.
Signed-off-by: Yiqing Yao
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 350f6b6676f1..864fea31c354 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -853,8 +853,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
*/
if (adev->gfx.kiq[inst].ring.sched.ready &&
(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
- uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
- uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
+
+ /* Select lower 18 bits to write in local xcc */
+ if (vmhub < AMDGPU_MMHUB0(0))
+ req = req & 0x3;
A bit more explanation would be good here, e.g. what you have in the
commit message.
Apart from that why do we need that in the first place? Isn't the KIQ
able to access the register anyway?
Regards,
Christian.
amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
1 << vmid, inst);
[linux-next:master] BUILD REGRESSION 861a3cb5a2a8480d361fa6708da24747d6fa72fe
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 861a3cb5a2a8480d361fa6708da24747d6fa72fe Add linux-next specific files for 20240603 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202406031357.4t4jtalq-...@intel.com https://lore.kernel.org/oe-kbuild-all/202406031506.hgei9sbs-...@intel.com Error/Warning: (recently discovered and may have been fixed) Warning: MAINTAINERS references a file that doesn't exist: Documentation/hwmon/chros_ec_hwmon.rst Unverified Error/Warning (likely false positive, please contact us if interested): drivers/gpu/drm/xe/xe_vram.c:335 xe_vram_probe() error: '%pa' expects argument of type 'phys_addr_t*', argument 3 has type 'ullong*' Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- i386-randconfig-141-20240603 | |-- drivers-gpu-drm-i915-display-intel_dpt.c-intel_dpt_pin_to_ggtt()-error:uninitialized-symbol-vma-. | |-- drivers-gpu-drm-i915-display-intel_fb_pin.c-intel_fb_pin_to_dpt()-error:uninitialized-symbol-vma-. | |-- drivers-gpu-drm-i915-display-intel_fb_pin.c-intel_fb_pin_to_dpt()-error:vma-dereferencing-possible-ERR_PTR() | |-- drivers-gpu-drm-xe-xe_drm_client.c-show_run_ticks()-error:uninitialized-symbol-gpu_timestamp-. | |-- drivers-gpu-drm-xe-xe_drm_client.c-show_run_ticks()-error:uninitialized-symbol-hwe-. | |-- drivers-gpu-drm-xe-xe_sched_job.c-xe_sched_job_arm()-error:uninitialized-symbol-fence-. | `-- drivers-gpu-drm-xe-xe_vram.c-xe_vram_probe()-error:pa-expects-argument-of-type-phys_addr_t-argument-has-type-ullong |-- loongarch-defconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-hubbub-dcn401-dcn401_hubbub.o:warning:objtool:unexpected-relocation-symbol-type-in-.rela.discard.reachable | `-- drivers-thermal-thermal_trip.o:warning:objtool:unexpected-relocation-symbol-type-in-.rela.discard.reachable |-- loongarch-loongson3_defconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-hubbub-dcn401-dcn401_hubbub.o:warning:objtool:unexpected-relocation-symbol-type-in-.rela.discard.reachable | `-- drivers-thermal-thermal_trip.o:warning:objtool:unexpected-relocation-symbol-type-in-.rela.discard.reachable |-- nios2-randconfig-002-20240603 | |-- drivers-gpu-drm-arm-display-komeda-komeda_dev.c:error:implicit-declaration-of-function-seq_puts | |-- drivers-gpu-drm-arm-display-komeda-komeda_dev.c:error:invalid-use-of-undefined-type-struct-seq_file | `-- drivers-gpu-drm-arm-display-komeda-komeda_dev.c:error:type-defaults-to-int-in-declaration-of-DEFINE_SHOW_ATTRIBUTE |-- sparc64-randconfig-r051-20240603 | |-- drivers-gpu-drm-arm-display-komeda-komeda_dev.c:error:implicit-declaration-of-function-seq_puts | |-- drivers-gpu-drm-arm-display-komeda-komeda_dev.c:error:invalid-use-of-undefined-type-struct-seq_file | `-- drivers-gpu-drm-arm-display-komeda-komeda_dev.c:error:type-defaults-to-int-in-declaration-of-DEFINE_SHOW_ATTRIBUTE |-- um-allyesconfig | `-- kernel-bpf-verifier.c:error:pcpu_hot-undeclared-(first-use-in-this-function) |-- um-randconfig-r131-20240603 | `-- kernel-bpf-verifier.c:error:pcpu_hot-undeclared-(first-use-in-this-function) `-- um-randconfig-r132-20240603 |-- drivers-mtd-nand-raw-mxc_nand.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-void-buf-got-void-noderef-__iomem `-- drivers-mtd-nand-raw-mxc_nand.c:sparse:sparse:incorrect-type-in-initializer-(different-address-spaces)-expected-unsigned-short-noderef-usertype-__iomem-t-got-void-buf clang_recent_errors |-- arm64-allmodconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:error:arithmetic-between-different-enumeration-types-(-enum-dc_irq_source-and-enum-irq_type-)-Werror-Wenum-enum-conversion | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-irq-dce110-irq_service_dce110.c:error:arithmetic-between-different-enumeration-types-(-enum-dc_irq_source-and-enum-irq_type-)-Werror-Wenum-enum-conversion | |-- drivers-gpu-drm-i915-display-intel_cursor.c:error:arithmetic-between-different-enumeration-types-(-enum-pipe-and-enum-intel_display_power_domain-)-Werror-Wenum-enum-conversion | |-- drivers-gpu-drm-i915-display-intel_ddi.c:error:arithmetic-between-different-enumeration-types-(-enum-hpd_pin-and-enum-port-)-Werror-Wenum-enum-conversion | |-- drivers-gpu-drm-i915-display-intel_ddi.c:error:arithmetic-between-different-enumeration-types-(-enum-transcoder-and-enum-intel_display_power_domain-)-Werror-Wenum-enum-conversion | |-- drivers-gpu-drm-i915-display-intel_display.c:error:arithmetic-between-different-enumeration-types-(-enum-phy-and-enum-port-)-Werror-Wenum-enum-conversion | |-- drivers-gpu-drm-i915-display-intel_display.c:error:arithmetic-between-different-enumeration-types-(-enum-pipe-and-enum-intel_display_power_domain-)-Werror-Wenum-enum-conversion | |-- drivers-gpu-drm-i915-display-intel_display.c:error:arithmetic-between-different-enumeration-types-(-enum-tc_port-and-enum-port-)-Werror
Re: [PATCH] drm/amdkfd: add reset cause in gpu pre-reset smi event
Thanks Lijo, I will send another patch with your suggestion.
Regards,
Eric
On 2024-06-03 04:03, Lazar, Lijo wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Eric,
To consider other reset cases also, you may have something like attached.
Thanks,
Lijo
-Original Message-
From: amd-gfx On Behalf Of Eric Huang
Sent: Friday, May 31, 2024 8:38 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kasiviswanathan, Harish ; Huang, JinHuiEric
Subject: [PATCH] drm/amdkfd: add reset cause in gpu pre-reset smi event
reset cause is requested by customer as additional info for gpu reset smi event.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 34 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 17 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 9 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 7 +-
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 71 +++
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 13 +++-
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h | 5 +-
9 files changed, 133 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index e3738d417245..3588c912214a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -125,17 +125,26 @@ static void amdgpu_doorbell_get_kfd_info(struct
amdgpu_device *adev, static void amdgpu_amdkfd_reset_work(struct work_struct
*work) {
struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
- kfd.reset_work);
-
- struct amdgpu_reset_context reset_context;
+ kfd.reset_work.work);
+
+ if (adev->kfd.reset_work.reset_context) {
+ amdgpu_device_gpu_recover(
+ adev, NULL,
+ (struct amdgpu_reset_context *)
+ adev->kfd.reset_work.reset_context);
+ kfree(adev->kfd.reset_work.reset_context);
+ adev->kfd.reset_work.reset_context = NULL;
+ } else {
+ struct amdgpu_reset_context reset_context;
- memset(_context, 0, sizeof(reset_context));
+ memset(_context, 0, sizeof(reset_context));
- reset_context.method = AMD_RESET_METHOD_NONE;
- reset_context.reset_req_dev = adev;
- clear_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
+ reset_context.method = AMD_RESET_METHOD_NONE;
+ reset_context.reset_req_dev = adev;
+ clear_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
- amdgpu_device_gpu_recover(adev, NULL, _context);
+ amdgpu_device_gpu_recover(adev, NULL, _context);
+ }
}
static const struct drm_client_funcs kfd_client_funcs = { @@ -225,7 +234,7 @@
void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
- INIT_WORK(>kfd.reset_work, amdgpu_amdkfd_reset_work);
+ INIT_WORK(>kfd.reset_work.work, amdgpu_amdkfd_reset_work);
}
}
@@ -261,12 +270,13 @@ int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool
run_pm)
return r;
}
-int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
+int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev,
+ struct amdgpu_reset_context *reset_context)
{
int r = 0;
if (adev->kfd.dev)
- r = kgd2kfd_pre_reset(adev->kfd.dev);
+ r = kgd2kfd_pre_reset(adev->kfd.dev, reset_context);
return r;
}
@@ -285,7 +295,7 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) {
if (amdgpu_device_should_recover_gpu(adev))
amdgpu_reset_domain_schedule(adev->reset_domain,
->kfd.reset_work);
+>kfd.reset_work.work);
}
int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, diff
--git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 1de021ebdd46..1fc9ed33a1c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -47,6 +47,7 @@ enum TLB_FLUSH_TYPE {
};
struct amdgpu_device;
+struct amdgpu_reset_context;
enum kfd_mem_attachment_type {
KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
@@ -98,12 +99,17 @@ struct amdgpu_amdkfd_fence {
struct svm_range_bo *svm_bo;
};
+struct kfd_reset_work {
+ struct work_struct work;
+ void *reset_context;
+};
+
struct amdgpu_kfd_dev {
struct kfd_dev *dev;
int64_t vram_used[MAX_XCP];
RE: [PATCH] drm/amdgpu: Set PTE_IS_PTE bit for gfx12
[AMD Official Use Only - AMD Internal Distribution Only] From: Frank Min Set PTE_IS_PTE bit while PRT is enabled on gfx12. Signed-off-by: Frank Min --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 7d99fcc58baf..e09be1a6c7d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -512,6 +512,7 @@ static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, *flags |= AMDGPU_PTE_PRT_GFX12; *flags |= AMDGPU_PTE_SNOOPED; *flags |= AMDGPU_PTE_SYSTEM; + *flags |= AMDGPU_PTE_IS_PTE; *flags &= ~AMDGPU_PTE_VALID; } -- 2.34.1
[PATCH] drm/amd/display: prevent register access while in IPS
We can't read/write to DCN registers while in IPS. Since, that can cause
the system to hang. So, before proceeding with the access in that
scenario, force the system out of IPS.
Cc: sta...@vger.kernel.org # 6.6+
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 059f78c8cd04..c8bc4098ed18 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -11796,6 +11796,12 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device
*dev)
mutex_unlock(>dm.dc_lock);
}
+static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc)
+{
+ if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)
+ dc_exit_ips_for_hw_access(dc);
+}
+
void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
u32 value, const char *func_name)
{
@@ -11806,6 +11812,8 @@ void dm_write_reg_func(const struct dc_context *ctx,
uint32_t address,
return;
}
#endif
+
+ amdgpu_dm_exit_ips_for_hw_access(ctx->dc);
cgs_write_register(ctx->cgs_device, address, value);
trace_amdgpu_dc_wreg(>perf_trace->write_count, address, value);
}
@@ -11829,6 +11837,8 @@ uint32_t dm_read_reg_func(const struct dc_context *ctx,
uint32_t address,
return 0;
}
+ amdgpu_dm_exit_ips_for_hw_access(ctx->dc);
+
value = cgs_read_register(ctx->cgs_device, address);
trace_amdgpu_dc_rreg(>perf_trace->read_count, address, value);
--
2.45.0
Re: [PATCH 1/2] amdgpu: add the amdgpu_vm ptr in the vm_bo_map/unmap events
Am 03.06.24 um 13:52 schrieb Pierre-Eric Pelloux-Prayer:
Hi Christia,
Le 03/06/2024 à 11:58, Christian König a écrit :
Am 03.06.24 um 10:46 schrieb Pierre-Eric Pelloux-Prayer:
These 2 traces events are tied to a specific VM so in order for them
to be useful for a tool we need to trace the amdgpu_vm as well.
The bo_va already contains the VM pointer the map/unmap operation
belongs to.
Indeed, I've missed that. I'll fix that in v2.
Signed-off-by: Pierre-Eric Pelloux-Prayer
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index f539b1d00234..c84050d318d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -243,10 +243,11 @@ TRACE_EVENT(amdgpu_vm_grab_id,
);
TRACE_EVENT(amdgpu_vm_bo_map,
- TP_PROTO(struct amdgpu_bo_va *bo_va,
+ TP_PROTO(struct amdgpu_vm *vm, struct amdgpu_bo_va *bo_va,
struct amdgpu_bo_va_mapping *mapping),
- TP_ARGS(bo_va, mapping),
+ TP_ARGS(vm, bo_va, mapping),
TP_STRUCT__entry(
+ __field(struct amdgpu_vm *, vm)
__field(struct amdgpu_bo *, bo)
__field(long, start)
__field(long, last)
@@ -255,22 +256,24 @@ TRACE_EVENT(amdgpu_vm_bo_map,
),
TP_fast_assign(
+ __entry->vm = vm;
__entry->bo = bo_va ? bo_va->base.bo : NULL;
__entry->start = mapping->start;
__entry->last = mapping->last;
__entry->offset = mapping->offset;
__entry->flags = mapping->flags;
),
- TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%llx",
- __entry->bo, __entry->start, __entry->last,
+ TP_printk("vm=%p bo=%p, start=%lx, last=%lx,
offset=%010llx, flags=%llx",
+ __entry->vm, __entry->bo, __entry->start, __entry->last,
__entry->offset, __entry->flags)
);
TRACE_EVENT(amdgpu_vm_bo_unmap,
- TP_PROTO(struct amdgpu_bo_va *bo_va,
+ TP_PROTO(struct amdgpu_vm *vm, struct amdgpu_bo_va *bo_va,
struct amdgpu_bo_va_mapping *mapping),
- TP_ARGS(bo_va, mapping),
+ TP_ARGS(vm, bo_va, mapping),
TP_STRUCT__entry(
+ __field(struct amdgpu_vm *, vm)
__field(struct amdgpu_bo *, bo)
__field(long, start)
__field(long, last)
@@ -279,14 +282,15 @@ TRACE_EVENT(amdgpu_vm_bo_unmap,
),
TP_fast_assign(
+ __entry->vm = vm;
__entry->bo = bo_va ? bo_va->base.bo : NULL;
__entry->start = mapping->start;
__entry->last = mapping->last;
__entry->offset = mapping->offset;
__entry->flags = mapping->flags;
),
- TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%llx",
- __entry->bo, __entry->start, __entry->last,
+ TP_printk("vm=%p bo=%p, start=%lx, last=%lx,
offset=%010llx, flags=%llx",
+ __entry->vm, __entry->bo, __entry->start, __entry->last,
__entry->offset, __entry->flags)
);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 3abfa66d72a2..e04928d2e26a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1642,7 +1642,7 @@ static void amdgpu_vm_bo_insert_map(struct
amdgpu_device *adev,
if (amdgpu_vm_is_bo_always_valid(vm, bo) && !bo_va->base.moved)
amdgpu_vm_bo_moved(_va->base);
- trace_amdgpu_vm_bo_map(bo_va, mapping);
+ trace_amdgpu_vm_bo_map(vm, bo_va, mapping);
}
/* Validate operation parameters to prevent potential abuse */
@@ -1834,7 +1834,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev,
list_del(>list);
amdgpu_vm_it_remove(mapping, >va);
mapping->bo_va = NULL;
- trace_amdgpu_vm_bo_unmap(bo_va, mapping);
+ trace_amdgpu_vm_bo_unmap(vm, bo_va, mapping);
if (valid)
list_add(>list, >freed);
@@ -1929,7 +1929,7 @@ int amdgpu_vm_bo_clear_mappings(struct
amdgpu_device *adev,
tmp->bo_va = NULL;
list_add(>list, >freed);
- trace_amdgpu_vm_bo_unmap(NULL, tmp);
+ trace_amdgpu_vm_bo_unmap(vm, NULL, tmp);
That bo_va is NULL here is probably a bug and should be fixed.
Would something like this work?
trace_amdgpu_vm_bo_unmap(tmp->bo_va, tmp);
tmp->bo_va = NULL;
list_add(>list, >freed);
It's not 100% accurate because only parts of the mapping is unmapped,
but yes I think that should work.
Regards,
Christian.
Thanks,
Pierre-Eric
Regards,
Christian.
RE: [PATCH 00/32] DC Patches May 20, 2024
[Public] Hi all, This week this patchset was tested on the following systems: • Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U • MSI Gaming X Trio RX 6800 • Gigabyte Gaming OC RX 7900 XTX These systems were tested on the following display/connection types: • eDP, (1080p 60hz [5650U]) (1920x1200 60hz [6600U]) (2560x1600 120hz[6600U]) • VGA and DVI (1680x1050 60hz [DP to VGA/DVI, USB-C to VGA/DVI]) • DP/HDMI/USB-C (1440p 170hz, 4k 60hz, 4k 144hz, 4k 240hz [Includes USB-C to DP/HDMI adapters]) • Thunderbolt (LG Ultrafine 5k) • MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60Hz displays) • DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60 displays, and HP Hook G2 with 1 4k60 display) • USB 4 (Kensington SD5700T and 1x 4k 60Hz display) • PCON (Club3D CAC-1085 and 1x 4k 144Hz display [at 4k 120HZ, as that is the max the adapter supports]) The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to): • Changing display configurations and settings • Benchmark testing • Feature testing (Freesync, etc.) Automated testing includes (but is not limited to): • Script testing (scripts to automate some of the manual checks) • IGT testing The patchset consists of the amd-staging-drm-next branch (Head commit - 16e25cc8375f59ff2a16a762d102e398ecba3d0d -> drm/amdgpu: Add lock around VF RLCG interface) with new patches added on top of it. Tested on Ubuntu 22.04.3, on Wayland and X11, using KDE Plasma and Gnome. Tested-by: Daniel Wheeler Thank you, Dan Wheeler Sr. Technologist | AMD SW Display -- 1 Commerce Valley Dr E, Thornhill, ON L3T 7X6 amd.com -Original Message- From: Mohamed, Zaeem Sent: Friday, May 31, 2024 12:51 PM To: amd-gfx@lists.freedesktop.org Cc: Wentland, Harry ; Li, Sun peng (Leo) ; Siqueira, Rodrigo ; Pillai, Aurabindo ; Li, Roman ; Lin, Wayne ; Gutierrez, Agustin ; Chung, ChiaHsuan (Tom) ; Zuo, Jerry ; Mohamed, Zaeem ; Wheeler, Daniel Subject: [PATCH 00/32] DC Patches May 20, 2024 This DC patchset brings improvements in multiple areas. In summary, we have: * DML2 fixes * FAMS2 Improvements * Fix YUV video color corruption, oled eDP not lighting up DCN401 * add UCLK p-state support message for DCN401 * Extends PSRSU residency mode * Introducing deferred replay coasting vtotal update * Fix DSC slice and delay calculations Cc: Daniel Wheeler Alex Hung (1): drm/amd/display: Increase MAX_LINKS by 2 Alvin Lee (4): drm/amd/display: Only program P-State force if pipe config changed drm/amd/display: Move fpo_in_use to stream_status drm/amd/display: Use current_state when checking old_pipe subvp type drm/amd/display: Program DIG FE source select for DVI before PHY en Aric Cyr (1): SWDEV-1 - dc: 3.2.287 Chiawen Huang (1): drm/amd/display: add set ips disable Chris Park (1): drm/amd/display: Support new VA page table block size Chun-LiangChang (1): drm/amd/display: Add params of set_abm_event for VB Scaling ChunTao Tso (1): drm/amd/display: Introduce deferred Replay coasting vtotal update Daniel Sa (1): drm/amd/display: Fetch Mall caps from DC Dillon Varone (5): drm/amd/display: Wait for hardmins to complete on dcn401 drm/amd/display: Add UCLK p-state support message to dcn401 drm/amd/display: Force max clocks unconditionally when p-state is unsupported drm/amd/display: Add recovery timeout to FAMS2 drm/amd/display: Various DML2 fixes for FAMS2 Fangzhi Zuo (1): drm/amd/display: Prevent IPX From Link Detect and Set Mode Jack Chang (1): drm/amd/display: Extend PSRSU residency mode Joan Lee (1): drm/amd/display: Add retires when read DPCD Joshua Aberback (2): drm/amd/display: Fix swapped dimension calculations drm/amd/display: workaround for oled eDP not lighting up on DCN401 Lewis Huang (1): drm/amd/display: Add monitor patch skip disable crtc during psr and ips1 Nicholas Kazlauskas (2): drm/amd/display: Add outbox notification support for HPD redetect drm/amd/display: Guard reading 3DLUT registers for dcn32/dcn35 Nicholas Susanto (1): drm/amd/display: Fix DML2 logic to set clk state to min Relja Vojvodic (1): drm/amd/display: Updated optc401_set_drr to use dcn401 functions Samson Tam (1): drm/amd/display: fix YUV video color corruption in DCN401 Sung Joon Kim (1): drm/amd/display: Fix DSC slice and delay calculations Wayne Lin (1): drm/amd/display: Change the order of setting DP_IS_USB_C flag Wenjing Liu (1): drm/amd/display: turn on symclk for dio virtual stream in dpms sequence Yihan Zhu (1): drm/amd/display: bypass ODM before CRTC off yi-lchen (1): drm/amd/display: Keep VBios pixel rate div setting until next mode set .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++
Re: [PATCH] kernel/resource: optimize find_next_iomem_res
On Fri, 31 May 2024, Chia-I Wu wrote: > On Fri, May 31, 2024 at 1:57 AM Andy Shevchenko > > wrote: > On Thu, May 30, 2024 at 10:36:57PM -0700, Chia-I Wu wrote: > > We can skip children resources when the parent resource does not cover > > the range. > > > > This should help vmf_insert_* users on x86, such as several DRM > drivers. > > On my AMD Ryzen 5 7520C, when streaming data from cpu memory into > amdgpu > > bo, the throughput goes from 5.1GB/s to 6.6GB/s. perf report says > > > > 34.69%--__do_fault > > 34.60%--amdgpu_gem_fault > > 34.00%--ttm_bo_vm_fault_reserved > > 32.95%--vmf_insert_pfn_prot > > 25.89%--track_pfn_insert > > 24.35%--lookup_memtype > > 21.77%--pat_pagerange_is_ram > > 20.80%--walk_system_ram_range > > 17.42%--find_next_iomem_res > > > > before this change, and > > > > 26.67%--__do_fault > > 26.57%--amdgpu_gem_fault > > 25.83%--ttm_bo_vm_fault_reserved > > 24.40%--vmf_insert_pfn_prot > > 14.30%--track_pfn_insert > > 12.20%--lookup_memtype > > 9.34%--pat_pagerange_is_ram > > 8.22%--walk_system_ram_range > > 5.09%--find_next_iomem_res > > > > after. > > Is there any documentation that explicitly says that the children > resources > must not overlap parent's one? Do we have some test cases? (Either way > they > needs to be added / expanded). > > I think it's the opposite. The assumption here is that a child is always a > subset of > its parent. Thus, if the range to be checked is not covered by a parent, we > can skip > the children. > > That's guaranteed by __request_resource. I am less sure about > __insert_resource but > it appears to be the case too. FWIW, resource_is_exclusive has the same > assumption > already. Yes, the children resources are contained within the parent resource (at least in PCI but given the code, I'd expect that to be general state of affairs). > It looks like I need to do some refactoring to add tests. > > > P.S> I'm not so sure about this change. It needs a thoroughly testing, > esp. > in PCI case. Cc'ing to Ilpo. > > What's special about PCI? -- i.
Re: [PATCH] drm/amd/display: Convert some legacy DRM debug macros into appropriate categories
On 30/05/2024 20:57, Hamza Mahfooz wrote:
On 5/28/24 08:57, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Currently when one enables driver debugging dmesg gets spammed, at I
suspect vblank rate, with messages like:
[drm:amdgpu_dm_atomic_check [amdgpu]] MPO enablement requested on
crtc:[f073c3bb]
Fix if by converting some logging from deprecated and incorrect
DRM_DEBUG_DRIVER to drm_dbg_atomic. Plus some localized drive-by changes
to drm_dbg_kms.
By no means an exhaustive conversion but at least it allows turning on
driver debug selectively.
Signed-off-by: Tvrtko Ursulin
Applied, thanks!
Oh so fast for this one, thank you!
Regards,
Tvrtko
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 73 ++-
1 file changed, 39 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 975feb1c69b8..bf9db488eee6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2363,13 +2363,13 @@ static int
detect_mst_link_for_all_connectors(struct drm_device *dev)
aconnector = to_amdgpu_dm_connector(connector);
if (aconnector->dc_link->type == dc_connection_mst_branch &&
aconnector->mst_mgr.aux) {
- DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p
[id: %d]\n",
+ drm_dbg_kms(dev, "DM_MST: starting TM on aconnector: %p
[id: %d]\n",
aconnector,
aconnector->base.base.id);
ret =
drm_dp_mst_topology_mgr_set_mst(>mst_mgr, true);
if (ret < 0) {
- DRM_ERROR("DM_MST: Failed to start MST\n");
+ drm_err(dev, "DM_MST: Failed to start MST\n");
aconnector->dc_link->type =
dc_connection_single;
ret =
dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
@@ -3298,15 +3298,15 @@ void amdgpu_dm_update_connector_after_detect(
* We got a DP short pulse (Link Loss, DP CTS, etc...).
* Do nothing!!
*/
- DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't
change.\n",
- aconnector->connector_id);
+ drm_dbg_kms(dev, "DCHPD: connector_id=%d: dc_sink didn't
change.\n",
+ aconnector->connector_id);
if (sink)
dc_sink_release(sink);
return;
}
- DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New
sink=%p\n",
- aconnector->connector_id, aconnector->dc_sink, sink);
+ drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New
sink=%p\n",
+ aconnector->connector_id, aconnector->dc_sink, sink);
mutex_lock(>mode_config.mutex);
@@ -9191,7 +9191,9 @@ static void amdgpu_dm_commit_streams(struct
drm_atomic_state *state,
if (amdgpu_dm_crtc_modeset_required(new_crtc_state,
dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
- DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n",
acrtc->crtc_id, acrtc);
+ drm_dbg_atomic(dev,
+ "Atomic commit: SET crtc id %d: [%p]\n",
+ acrtc->crtc_id, acrtc);
if (!dm_new_crtc_state->stream) {
/*
@@ -9209,8 +9211,9 @@ static void amdgpu_dm_commit_streams(struct
drm_atomic_state *state,
* have a sink to keep the pipe running so that
* hw state is consistent with the sw state
*/
- DRM_DEBUG_DRIVER("%s: Failed to create new stream for
crtc %d\n",
- __func__, acrtc->base.base.id);
+ drm_dbg_atomic(dev,
+ "Failed to create new stream for crtc %d\n",
+ acrtc->base.base.id);
continue;
}
@@ -9224,7 +9227,9 @@ static void amdgpu_dm_commit_streams(struct
drm_atomic_state *state,
crtc->hwmode = new_crtc_state->mode;
mode_set_reset_required = true;
} else if (modereset_required(new_crtc_state)) {
- DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id
%d:[%p]\n", acrtc->crtc_id, acrtc);
+ drm_dbg_atomic(dev,
+ "Atomic commit: RESET. crtc id %d:[%p]\n",
+ acrtc->crtc_id, acrtc);
/* i.e. reset mode */
if (dm_old_crtc_state->stream)
remove_stream(adev, acrtc, dm_old_crtc_state->stream);
@@ -9679,7 +9684,7 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
#endif
if (amdgpu_dm_crtc_configure_crc_source(
crtc, dm_new_crtc_state, cur_crc_src))
- DRM_DEBUG_DRIVER("Failed to configure crc source");
+ drm_dbg_atomic(dev, "Failed to configure crc
source");
}
}
#endif
Re: [PATCH] kernel/resource: optimize find_next_iomem_res
On Fri, May 31, 2024 at 02:31:45PM -0700, Chia-I Wu wrote: > On Fri, May 31, 2024 at 1:57 AM Andy Shevchenko < > andriy.shevche...@linux.intel.com> wrote: > > On Thu, May 30, 2024 at 10:36:57PM -0700, Chia-I Wu wrote: ... > > P.S> I'm not so sure about this change. It needs a thoroughly testing, esp. > > in PCI case. Cc'ing to Ilpo. > What's special about PCI? PCI, due to its nature, may rebuild resources either by shrinking or expanding of the entire subtree after the PCI bridge in question. And this may happen at run-time due to hotplug support. But I'm not a deep expert in this area, Ilpo knows much more than me. -- With Best Regards, Andy Shevchenko
[PATCH v2] drm/amdgpu/pptable: Fix UBSAN array-index-out-of-bounds
Flexible arrays used [1] instead of []. Replace the former with the latter
to resolve multiple UBSAN warnings observed on boot with a BONAIRE card.
In addition, use the __counted_by attribute where possible to hint the
length of the arrays to the compiler and any sanitizers.
Signed-off-by: Tasos Sahanidis
---
V1 -> V2: Added the __counted_by attribute where possible and reworded
the commit message.
drivers/gpu/drm/amd/include/pptable.h | 91 ++-
1 file changed, 49 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/pptable.h
b/drivers/gpu/drm/amd/include/pptable.h
index 2e8e6c9875f6..f83ace2d7ec3 100644
--- a/drivers/gpu/drm/amd/include/pptable.h
+++ b/drivers/gpu/drm/amd/include/pptable.h
@@ -477,31 +477,30 @@ typedef struct _ATOM_PPLIB_STATE_V2
} ATOM_PPLIB_STATE_V2;
typedef struct _StateArray{
-//how many states we have
-UCHAR ucNumEntries;
-
-ATOM_PPLIB_STATE_V2 states[1];
+ //how many states we have
+ UCHAR ucNumEntries;
+
+ ATOM_PPLIB_STATE_V2 states[] /* __counted_by(ucNumEntries) */;
}StateArray;
typedef struct _ClockInfoArray{
-//how many clock levels we have
-UCHAR ucNumEntries;
-
-//sizeof(ATOM_PPLIB_CLOCK_INFO)
-UCHAR ucEntrySize;
-
-UCHAR clockInfo[];
+ //how many clock levels we have
+ UCHAR ucNumEntries;
+
+ //sizeof(ATOM_PPLIB_CLOCK_INFO)
+ UCHAR ucEntrySize;
+
+ UCHAR clockInfo[];
}ClockInfoArray;
typedef struct _NonClockInfoArray{
+ //how many non-clock levels we have. normally should be same as number
of states
+ UCHAR ucNumEntries;
+ //sizeof(ATOM_PPLIB_NONCLOCK_INFO)
+ UCHAR ucEntrySize;
-//how many non-clock levels we have. normally should be same as number of
states
-UCHAR ucNumEntries;
-//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
-UCHAR ucEntrySize;
-
-ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[];
+ ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[] __counted_by(ucNumEntries);
}NonClockInfoArray;
typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
@@ -513,8 +512,10 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
{
-UCHAR ucNumEntries;//
Number of entries.
-ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; //
Dynamically allocate entries.
+ // Number of entries.
+ UCHAR ucNumEntries;
+ // Dynamically allocate entries.
+ ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[]
__counted_by(ucNumEntries);
}ATOM_PPLIB_Clock_Voltage_Dependency_Table;
typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
@@ -529,8 +530,10 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
{
-UCHAR ucNumEntries;//
Number of entries.
-ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; //
Dynamically allocate entries.
+ // Number of entries.
+ UCHAR ucNumEntries;
+ // Dynamically allocate entries.
+ ATOM_PPLIB_Clock_Voltage_Limit_Record entries[]
__counted_by(ucNumEntries);
}ATOM_PPLIB_Clock_Voltage_Limit_Table;
union _ATOM_PPLIB_CAC_Leakage_Record
@@ -553,8 +556,10 @@ typedef union _ATOM_PPLIB_CAC_Leakage_Record
ATOM_PPLIB_CAC_Leakage_Record;
typedef struct _ATOM_PPLIB_CAC_Leakage_Table
{
-UCHAR ucNumEntries; //
Number of entries.
-ATOM_PPLIB_CAC_Leakage_Record entries[1]; //
Dynamically allocate entries.
+ // Number of entries.
+ UCHAR ucNumEntries;
+ // Dynamically allocate entries.
+ ATOM_PPLIB_CAC_Leakage_Record entries[] __counted_by(ucNumEntries);
}ATOM_PPLIB_CAC_Leakage_Table;
typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
@@ -568,8 +573,10 @@ typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table
{
-UCHAR ucNumEntries; //
Number of entries.
-ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; //
Dynamically allocate entries.
+ // Number of entries.
+ UCHAR ucNumEntries;
+ // Dynamically allocate entries.
+ ATOM_PPLIB_PhaseSheddingLimits_Record entries[]
__counted_by(ucNumEntries);
}ATOM_PPLIB_PhaseSheddingLimits_Table;
typedef struct _VCEClockInfo{
@@ -580,8 +587,8 @@ typedef struct _VCEClockInfo{
}VCEClockInfo;
typedef struct _VCEClockInfoArray{
-UCHAR ucNumEntries;
-VCEClockInfo entries[1];
+ UCHAR ucNumEntries;
+ VCEClockInfo entries[] __counted_by(ucNumEntries);
}VCEClockInfoArray;
typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
@@ -592,8 +599,8 @@ typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
typedef struct
Re: [PATCH v1 1/1] drm/amd/display: Fix too big frame size
On Sun, Jun 02, 2024 at 05:21:03PM +0300, Andy Shevchenko wrote:
> Compilation fails on arm with:
>
> link_factory.c:743:1: error: the frame size of 1032 bytes is larger than
> 1024 bytes [-Werror=frame-larger-than=]
>
> Fix the frame size by allocation one of the big structures.
Fixed even in better way in 0b6dc64b4e22 ("drm/amd/display: Refactor
construct_phy function in dc/link/link_factory.c").
--
With Best Regards,
Andy Shevchenko
Re: [PATCH] kernel/resource: optimize find_next_iomem_res
On Thu, May 30, 2024 at 10:36:57PM -0700, Chia-I Wu wrote: > We can skip children resources when the parent resource does not cover > the range. > This should help vmf_insert_* users on x86, such as several DRM drivers. vmf_insert_*() > On my AMD Ryzen 5 7520C, when streaming data from cpu memory into amdgpu > bo, the throughput goes from 5.1GB/s to 6.6GB/s. perf report says Also in the $Subj (and pay attention to the prefix) "resource: ... find_next_iomem_res()" -- With Best Regards, Andy Shevchenko
WARNING: CPU: 29 PID: 673 at drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:1382 amdgpu_bo_release_notify+0x1f5/0x210 [amdgpu]
Hello, with 6.10.0-rc1, I noticed the following in dmesg: [ 10.967791] amdgpu :0b:00.0: amdgpu: RAS: optional ras ta ucode is not available [ 10.973672] amdgpu :0b:00.0: amdgpu: RAP: optional rap ta ucode is not available [ 10.973674] amdgpu :0b:00.0: amdgpu: SECUREDISPLAY: securedisplay ta ucode is not available [ 10.974841] amdgpu :0b:00.0: amdgpu: SMU is initialized successfully! [ 10.974843] [drm] Seamless boot condition check passed [ 10.975510] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 10.975602] [ cut here ] [ 10.975603] WARNING: CPU: 29 PID: 673 at drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:1382 amdgpu_bo_release_notify+0x1f5/0x210 [amdgpu] [ 10.975678] Modules linked in: fmpm(-) amd_atl intel_rapl_msr intel_rapl_common edac_mce_amd kvm_amd amdgpu(+) kvm ghash_clmulni_intel sha512_ssse3 snd_hda_codec_realtek sha256_ssse3 snd_hda_codec_generic sha1_ssse3 snd_hda_scodec_component snd_hda_codec_hdmi snd_hda_intel snd_intel_dspcfg snd_intel_sdw_acpi drm_exec snd_hda_codec amdxcp eeepc_wmi drm_buddy asus_wmi gpu_sched aesni_intel battery snd_hda_core drm_suballoc_helper sparse_keymap crypto_simd snd_hwdep drm_display_helper joydev platform_profile cryptd drm_ttm_helper snd_pcm rfkill rapl ttm snd_timer sp5100_tco wmi_bmof drm_kms_helper ccp snd k10temp watchdog pcspkr soundcore i2c_algo_bit rng_core button evdev nfsd auth_rpcgss nfs_acl parport_pc lockd ppdev grace lp parport drm loop fuse dm_mod efi_pstore configfs sunrpc ip_tables x_tables autofs4 ext4 crc16 mbcache jbd2 btrfs blake2b_generic efivarfs raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx raid1 raid0 md_mod hid_lenovo hid_generic usbhid hid nvme ahci nvme_core xhci_pci [ 10.975702] libahci mpt3sas t10_pi xhci_hcd libata r8169 raid_class scsi_transport_sas realtek crc64_rocksoft crc32_pclmul mdio_devres crc_t10dif usbcore scsi_mod crc32c_intel crct10dif_generic video libphy i2c_piix4 crct10dif_pclmul usb_common scsi_common crct10dif_common wmi gpio_amdpt gpio_generic [ 10.975717] CPU: 29 PID: 673 Comm: (udev-worker) Not tainted 6.10.0-rc1 #6 [ 10.975719] Hardware name: ASUS System Product Name/TUF GAMING B650M-PLUS, BIOS 2412 01/26/2024 [ 10.975720] RIP: 0010:amdgpu_bo_release_notify+0x1f5/0x210 [amdgpu] [ 10.975785] Code: 0b e9 b3 fe ff ff 48 ba ff ff ff ff ff ff ff 7f 31 f6 4c 89 e7 e8 bb 50 92 c4 eb 98 e8 44 4a 92 c4 eb b2 0f 0b e9 60 fe ff ff <0f> 0b eb a7 be 03 00 00 00 e8 dd 4f 6a c4 eb 9b e8 46 40 c1 c4 66 [ 10.975787] RSP: 0018:a5f2c26d3560 EFLAGS: 00010282 [ 10.975788] RAX: ffea RBX: 8be251cb6c48 RCX: [ 10.975790] RDX: RSI: 86828d16 RDI: [ 10.975791] RBP: 8be24ff8ef58 R08: R09: 0003 [ 10.975791] R10: a5f2c26d32e0 R11: 8bf19de35fe8 R12: 8be251cb6c00 [ 10.975793] R13: 8be251cb6d48 R14: 8be24ff8ef58 R15: 0258 [ 10.975793] FS: 7f0b752898c0() GS:8bf15e48() knlGS: [ 10.975795] CS: 0010 DS: ES: CR0: 80050033 [ 10.975796] CR2: 7f0b74cf7a2d CR3: 000108b0f000 CR4: 00750ef0 [ 10.975797] PKRU: 5554 [ 10.975797] Call Trace: [ 10.975799] [ 10.975800] ? __warn+0x7c/0x120 [ 10.975804] ? amdgpu_bo_release_notify+0x1f5/0x210 [amdgpu] [ 10.975867] ? report_bug+0x189/0x1c0 [ 10.975869] ? handle_bug+0x41/0x70 [ 10.975872] ? exc_invalid_op+0x13/0x60 [ 10.975873] ? asm_exc_invalid_op+0x16/0x20 [ 10.975876] ? amdgpu_bo_release_notify+0x1f5/0x210 [amdgpu] [ 10.975938] ttm_bo_release+0xfb/0x2e0 [ttm] [ 10.975941] ? amdgpu_ttm_debugfs_init+0xf0/0xf0 [amdgpu] [ 10.976005] ? ttm_resource_move_to_lru_tail+0x138/0x1d0 [ttm] [ 10.976008] amdgpu_bo_free_kernel+0xc7/0x120 [amdgpu] [ 10.976071] dm_helpers_free_gpu_mem+0x3d/0x80 [amdgpu] [ 10.976171] dcn315_clk_mgr_construct+0x190/0x7e0 [amdgpu] [ 10.976265] dc_clk_mgr_create+0x31c/0x500 [amdgpu] [ 10.976351] dc_create+0x286/0x630 [amdgpu] [ 10.976454] amdgpu_dm_init.isra.0+0x2e9/0x1f10 [amdgpu] [ 10.976537] ? console_unlock+0x74/0x110 [ 10.976540] ? irq_work_queue+0xa/0x50 [ 10.976543] ? vprintk_emit+0x17f/0x2b0 [ 10.976544] ? dev_printk_emit+0xa1/0xd0 [ 10.976548] dm_hw_init+0xe/0x20 [amdgpu] [ 10.976614] amdgpu_device_init+0x1ede/0x26c0 [amdgpu] [ 10.976686] ? _raw_spin_unlock_irqrestore+0x23/0x40 [ 10.976688] amdgpu_driver_load_kms+0x15/0xa0 [amdgpu] [ 10.976754] amdgpu_pci_probe+0x183/0x4f0 [amdgpu] [ 10.976820] local_pci_probe+0x3c/0x80 [ 10.976823] pci_device_probe+0xc3/0x240 [ 10.976824] really_probe+0xcd/0x370 [ 10.976826] ? __device_attach_driver+0xf0/0xf0 [ 10.976827] __driver_probe_device+0x78/0x150 [ 10.976828] driver_probe_device+0x1f/0x90 [ 10.976829] __driver_attach+0xbf/0x1b0 [ 10.976830]
Re: [PATCH][next] drm/amd/display: Fix a handful of spelling mistakes
On 5/31/24 2:32 AM, Colin Ian King wrote:
> There are a few spelling mistakes in dml2_printf messages. Fix them.
>
> Signed-off-by: Colin Ian King
Reviewed-by: Randy Dunlap
Thanks.
> ---
> .../dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 6 +++---
> .../display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git
> a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
>
> b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
> index 8062144a5a6d..e7e6751f4477 100644
> ---
> a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
> +++
> b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
> @@ -5731,7 +5731,7 @@ static bool CalculatePrefetchSchedule(struct
> dml2_core_internal_scratch *scratch
> dml2_printf("DML: Tvm: %fus - time to fetch vm\n",
> s->TimeForFetchingVM);
> dml2_printf("DML: Tr0: %fus - time to fetch first row of data
> pagetables\n", s->TimeForFetchingRowInVBlank);
> dml2_printf("DML: Tsw: %fus = time to fetch enough pixel data
> and cursor data to feed the scalers init position and detile\n",
> (double)s->LinesToRequestPrefetchPixelData * s->LineTime);
> - dml2_printf("DML: To: %fus - time for propogation from scaler
> to optc\n", (*p->DSTYAfterScaler + ((double)(*p->DSTXAfterScaler) /
> (double)p->myPipe->HTotal)) * s->LineTime);
> + dml2_printf("DML: To: %fus - time for propagation from scaler
> to optc\n", (*p->DSTYAfterScaler + ((double)(*p->DSTXAfterScaler) /
> (double)p->myPipe->HTotal)) * s->LineTime);
> dml2_printf("DML: Tvstartup - TSetup - Tcalc - TWait - Tpre -
> To > 0\n");
> dml2_printf("DML: Tslack(pre): %fus - time left over in
> schedule\n", p->VStartup * s->LineTime - s->TimeForFetchingVM - 2 *
> s->TimeForFetchingRowInVBlank - (*p->DSTYAfterScaler +
> ((double)(*p->DSTXAfterScaler) / (double)p->myPipe->HTotal)) * s->LineTime -
> p->TWait - p->TCalc - *p->TSetup);
> dml2_printf("DML: row_bytes = dpte_row_bytes (per_pipe) =
> PixelPTEBytesPerRow = : %u\n", p->PixelPTEBytesPerRow);
> @@ -8268,7 +8268,7 @@ static bool dml_core_mode_support(struct
> dml2_core_calcs_mode_support_ex *in_out
> dml2_printf("DML::%s: mode_lib->ms.DCFCLK = %f\n", __func__,
> mode_lib->ms.DCFCLK);
> dml2_printf("DML::%s: mode_lib->ms.FabricClock = %f\n", __func__,
> mode_lib->ms.FabricClock);
> dml2_printf("DML::%s: mode_lib->ms.uclk_freq_mhz = %f\n", __func__,
> mode_lib->ms.uclk_freq_mhz);
> - dml2_printf("DML::%s: urgent latency tolarance = %f\n", __func__,
> ((mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes)
> * 1024 / (mode_lib->ms.DCFCLK * mode_lib->soc.return_bus_width_bytes)));
> + dml2_printf("DML::%s: urgent latency tolerance = %f\n", __func__,
> ((mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes)
> * 1024 / (mode_lib->ms.DCFCLK * mode_lib->soc.return_bus_width_bytes)));
> #endif
>
> mode_lib->ms.support.OutstandingRequestsSupport = true;
> @@ -11089,7 +11089,7 @@ static bool dml_core_mode_programming(struct
> dml2_core_calcs_mode_programming_ex
> if
> (display_cfg->plane_descriptors[k].immediate_flip &&
> mode_lib->mp.ImmediateFlipSupportedForPipe[k] == false) {
> mode_lib->mp.ImmediateFlipSupported =
> false;
> #ifdef __DML_VBA_DEBUG__
> - dml2_printf("DML::%s: Pipe %0d not
> supporing iflip!\n", __func__, k);
> + dml2_printf("DML::%s: Pipe %0d not
> supporting iflip!\n", __func__, k);
> #endif
> }
> }
> diff --git
> a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c
> b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c
> index f2e2250d28d3..6eb3fec87ec1 100644
> ---
> a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c
> +++
> b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c
> @@ -1988,7 +1988,7 @@ bool dml2_core_shared_mode_support(struct
> dml2_core_calcs_mode_support_ex *in_ou
> dml2_printf("DML::%s: mode_lib->ms.FabricClock = %f\n", __func__,
> mode_lib->ms.FabricClock);
> dml2_printf("DML::%s: mode_lib->ms.uclk_freq_mhz = %f\n", __func__,
> mode_lib->ms.uclk_freq_mhz);
> dml2_printf("DML::%s: max_urgent_latency_us = %f\n", __func__,
> mode_lib->ms.support.max_urgent_latency_us);
> - dml2_printf("DML::%s: urgent latency tolarance = %f\n", __func__,
> ((mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes)
> * 1024 / (mode_lib->ms.DCFCLK * mode_lib->soc.return_bus_width_bytes)));
> + dml2_printf("DML::%s:
[PATCH v1 1/1] drm/amd/display: Fix too big frame size
Compilation fails on arm with:
link_factory.c:743:1: error: the frame size of 1032 bytes is larger than 1024
bytes [-Werror=frame-larger-than=]
Fix the frame size by allocation one of the big structures.
Signed-off-by: Andy Shevchenko
---
.../gpu/drm/amd/display/dc/link/link_factory.c| 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index cf22b8f28ba6..78f1b2102839 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -456,10 +456,10 @@ static bool construct_phy(struct dc_link *link,
struct dc_context *dc_ctx = init_params->ctx;
struct encoder_init_data enc_init_data = { 0 };
struct panel_cntl_init_data panel_cntl_init_data = { 0 };
- struct integrated_info info = { 0 };
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
+ struct integrated_info *info;
DC_LOGGER_INIT(dc_ctx->logger);
@@ -672,12 +672,16 @@ static bool construct_phy(struct dc_link *link,
}
if (bios->integrated_info)
- info = *bios->integrated_info;
+ info = kmemdup(bios->integrated_info, sizeof(*info),
GFP_KERNEL);
+ else
+ info = kzalloc(sizeof(*info), GFP_KERNEL);
+ if (!info)
+ goto device_tag_fail;
/* Look for channel mapping corresponding to connector and device tag */
for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
struct external_display_path *path =
- _disp_conn_info.path[i];
+ >ext_disp_conn_info.path[i];
if (path->device_connector_id.enum_id == link->link_id.enum_id
&&
path->device_connector_id.id == link->link_id.id &&
@@ -698,14 +702,15 @@ static bool construct_phy(struct dc_link *link,
if (link->chip_caps &
EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
link->bios_forced_drive_settings.VOLTAGE_SWING =
-
(info.ext_disp_conn_info.fixdpvoltageswing & 0x3);
+
info->ext_disp_conn_info.fixdpvoltageswing & 0x3;
link->bios_forced_drive_settings.PRE_EMPHASIS =
-
((info.ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
+
(info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3;
}
break;
}
}
+ kfree(info);
if (bios->funcs->get_atom_dc_golden_table)
bios->funcs->get_atom_dc_golden_table(bios);
--
2.43.0.rc1.1336.g36b5255a03ac
Re: [PATCH] kernel/resource: optimize find_next_iomem_res
On Sun, 2 Jun 2024, Andy Shevchenko wrote: > On Fri, May 31, 2024 at 02:31:45PM -0700, Chia-I Wu wrote: > > On Fri, May 31, 2024 at 1:57 AM Andy Shevchenko < > > andriy.shevche...@linux.intel.com> wrote: > > > On Thu, May 30, 2024 at 10:36:57PM -0700, Chia-I Wu wrote: > > ... > > > > P.S> I'm not so sure about this change. It needs a thoroughly testing, > > > esp. > > > in PCI case. Cc'ing to Ilpo. > > > What's special about PCI? > > PCI, due to its nature, may rebuild resources either by shrinking or expanding > of the entire subtree after the PCI bridge in question. And this may happen at > run-time due to hotplug support. But I'm not a deep expert in this area, Ilpo > knows much more than me. There is code which clearly tries to do expanding resource but that usually fails to work as intended because of a parent resource whose size is fixed because it's already assigned. Some other code might block shrinking too under certain conditions. This area would need to be reworked in PCI core but it's massive and scary looking change. -- i.
Re: [PATCH 1/2] amdgpu: add the amdgpu_vm ptr in the vm_bo_map/unmap events
Hi Christia,
Le 03/06/2024 à 11:58, Christian König a écrit :
Am 03.06.24 um 10:46 schrieb Pierre-Eric Pelloux-Prayer:
These 2 traces events are tied to a specific VM so in order for them
to be useful for a tool we need to trace the amdgpu_vm as well.
The bo_va already contains the VM pointer the map/unmap operation
belongs to.
Indeed, I've missed that. I'll fix that in v2.
Signed-off-by: Pierre-Eric Pelloux-Prayer
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index f539b1d00234..c84050d318d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -243,10 +243,11 @@ TRACE_EVENT(amdgpu_vm_grab_id,
);
TRACE_EVENT(amdgpu_vm_bo_map,
- TP_PROTO(struct amdgpu_bo_va *bo_va,
+ TP_PROTO(struct amdgpu_vm *vm, struct amdgpu_bo_va *bo_va,
struct amdgpu_bo_va_mapping *mapping),
- TP_ARGS(bo_va, mapping),
+ TP_ARGS(vm, bo_va, mapping),
TP_STRUCT__entry(
+ __field(struct amdgpu_vm *, vm)
__field(struct amdgpu_bo *, bo)
__field(long, start)
__field(long, last)
@@ -255,22 +256,24 @@ TRACE_EVENT(amdgpu_vm_bo_map,
),
TP_fast_assign(
+ __entry->vm = vm;
__entry->bo = bo_va ? bo_va->base.bo : NULL;
__entry->start = mapping->start;
__entry->last = mapping->last;
__entry->offset = mapping->offset;
__entry->flags = mapping->flags;
),
- TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%llx",
- __entry->bo, __entry->start, __entry->last,
+ TP_printk("vm=%p bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%llx",
+ __entry->vm, __entry->bo, __entry->start, __entry->last,
__entry->offset, __entry->flags)
);
TRACE_EVENT(amdgpu_vm_bo_unmap,
- TP_PROTO(struct amdgpu_bo_va *bo_va,
+ TP_PROTO(struct amdgpu_vm *vm, struct amdgpu_bo_va *bo_va,
struct amdgpu_bo_va_mapping *mapping),
- TP_ARGS(bo_va, mapping),
+ TP_ARGS(vm, bo_va, mapping),
TP_STRUCT__entry(
+ __field(struct amdgpu_vm *, vm)
__field(struct amdgpu_bo *, bo)
__field(long, start)
__field(long, last)
@@ -279,14 +282,15 @@ TRACE_EVENT(amdgpu_vm_bo_unmap,
),
TP_fast_assign(
+ __entry->vm = vm;
__entry->bo = bo_va ? bo_va->base.bo : NULL;
__entry->start = mapping->start;
__entry->last = mapping->last;
__entry->offset = mapping->offset;
__entry->flags = mapping->flags;
),
- TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%llx",
- __entry->bo, __entry->start, __entry->last,
+ TP_printk("vm=%p bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%llx",
+ __entry->vm, __entry->bo, __entry->start, __entry->last,
__entry->offset, __entry->flags)
);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 3abfa66d72a2..e04928d2e26a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1642,7 +1642,7 @@ static void amdgpu_vm_bo_insert_map(struct
amdgpu_device *adev,
if (amdgpu_vm_is_bo_always_valid(vm, bo) && !bo_va->base.moved)
amdgpu_vm_bo_moved(_va->base);
- trace_amdgpu_vm_bo_map(bo_va, mapping);
+ trace_amdgpu_vm_bo_map(vm, bo_va, mapping);
}
/* Validate operation parameters to prevent potential abuse */
@@ -1834,7 +1834,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
list_del(>list);
amdgpu_vm_it_remove(mapping, >va);
mapping->bo_va = NULL;
- trace_amdgpu_vm_bo_unmap(bo_va, mapping);
+ trace_amdgpu_vm_bo_unmap(vm, bo_va, mapping);
if (valid)
list_add(>list, >freed);
@@ -1929,7 +1929,7 @@ int amdgpu_vm_bo_clear_mappings(struct
amdgpu_device *adev,
tmp->bo_va = NULL;
list_add(>list, >freed);
- trace_amdgpu_vm_bo_unmap(NULL, tmp);
+ trace_amdgpu_vm_bo_unmap(vm, NULL, tmp);
That bo_va is NULL here is probably a bug and should be fixed.
Would something like this work?
trace_amdgpu_vm_bo_unmap(tmp->bo_va, tmp);
tmp->bo_va = NULL;
list_add(>list, >freed);
Thanks,
Pierre-Eric
Regards,
Christian.
}
/* Insert partial mapping before the range */
@@ -2056,7 +2056,7 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev,
list_del(>list);
[PATCH] drm/amdgpu: use local xcc write to flush tlb
When flushing gpu tlb using kiq from gfxhub, kiq ring is always
local as xcc instance is selected for it. Thus using lower 18 bits
to access mmregs inside local xcc instead of full address used
when accessing regs outside of local xcc.
Remove redundent code.
Signed-off-by: Yiqing Yao
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 350f6b6676f1..864fea31c354 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -853,8 +853,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
*/
if (adev->gfx.kiq[inst].ring.sched.ready &&
(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
- uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
- uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
+
+ /* Select lower 18 bits to write in local xcc */
+ if (vmhub < AMDGPU_MMHUB0(0))
+ req = req & 0x3;
amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
1 << vmid, inst);
--
2.34.1
Re: [PATCH] drm/amdgpu: replace int with unsigned int for imu_v12_0.c
Am 03.06.24 um 10:53 schrieb Zhou, Bob:
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Christian,
It fixes a potential Overflowed constant (INTEGER_OVERFLOW) warning reported by
Coverity.
You need to mention that in the commit message.
And I haven't checked the hardware docs, but it can be that this isn't
the right solution for the warning. Instead you should probably use the
RREG32_SOC15() macro with a mask which only leaves the valid bits around.
Only when the register is really 32bit wide you need an unsigned
datatype and if that is the case I suggest to use either uint32_t or u32
instead.
Regards,
Christian.
Regards,
Bob
-Original Message-
From: Koenig, Christian
Sent: 2024年6月3日 15:56
To: Zhou, Bob ; amd-gfx@lists.freedesktop.org; Huang, Tim
; Zhang, Jesse(Jie)
Cc: Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu: replace int with unsigned int for imu_v12_0.c
Am 03.06.24 um 07:59 schrieb Bob Zhou:
The return value of RREG32_SOC15 is unsigned int, so modify variable to
unsigned.
And why is that an improvement?
Regards,
Christian.
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
index 0c8ef908d112..2d6f7549c2af 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
@@ -119,7 +119,7 @@ static int imu_v12_0_load_microcode(struct
amdgpu_device *adev)
static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev)
{
- int i, imu_reg_val = 0;
+ unsigned int i, imu_reg_val = 0;
for (i = 0; i < adev->usec_timeout; i++) {
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); @@
-138,7 +138,7 @@ static int imu_v12_0_wait_for_reset_status(struct
amdgpu_device *adev)
static void imu_v12_0_setup(struct amdgpu_device *adev)
{
- int imu_reg_val;
+ unsigned int imu_reg_val;
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xff);
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0x); @@
-157,7 +157,7 @@ static void imu_v12_0_setup(struct amdgpu_device
*adev)
static int imu_v12_0_start(struct amdgpu_device *adev)
{
- int imu_reg_val;
+ unsigned int imu_reg_val;
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);
imu_reg_val &= 0xfffe;
Re: [PATCH 01/18] drm/amdgpu: enhance amdgpu_ucode_request() function flexibility
Am 31.05.24 um 08:52 schrieb Yang Wang:
Adding formatting string feature to improve function flexibility.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 30 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 ++-
2 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index a9de78bb96e2..a452d9b6afdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -28,6 +28,8 @@
#include "amdgpu.h"
#include "amdgpu_ucode.h"
+#define AMDGPU_MAX_FW_NAME_LEN (128)
Please drop that define and use NAME_MAX instead.
+
static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header
*hdr)
{
DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
@@ -1432,28 +1434,40 @@ void amdgpu_ucode_ip_version_decode(struct
amdgpu_device *adev, int block_type,
*
* @adev: amdgpu device
* @fw: pointer to load firmware to
- * @fw_name: firmware to load
+ * @fmt: firmware name format string
+ * @...: variable arguments
*
* This is a helper that will use request_firmware and amdgpu_ucode_validate
* to load and run basic validation on firmware. If the load fails, remap
* the error code to -ENODEV, so that early_init functions will fail to load.
*/
int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware
**fw,
-const char *fw_name)
+const char *fmt, ...)
{
- int err = request_firmware(fw, fw_name, adev->dev);
+ char fname[AMDGPU_MAX_FW_NAME_LEN];
+ va_list ap;
+ int r;
+
+ va_start(ap, fmt);
+ r = vsnprintf(fname, sizeof(fname), fmt, ap);
+ va_end(ap);
+ if (r == sizeof(fname)) {
+ dev_warn(adev->dev, "amdgpu firmware name buffer overflow\n");
+ return -EOVERFLOW;
+ }
- if (err)
+ r = request_firmware(fw, fname, adev->dev);
+ if (r)
return -ENODEV;
- err = amdgpu_ucode_validate(*fw);
- if (err) {
- dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name);
+ r = amdgpu_ucode_validate(*fw);
+ if (r) {
+ dev_dbg(adev->dev, "\"%s\" failed to validate\n", fname);
release_firmware(*fw);
*fw = NULL;
}
- return err;
+ return r;
}
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index db745ab7b0c8..5bc37acd3981 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -594,8 +594,9 @@ void amdgpu_ucode_print_rlc_hdr(const struct
common_firmware_header *hdr);
void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header
*hdr);
+__printf(3, 4)
int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware
**fw,
-const char *fw_name);
+const char *fmt, ...);
That should probably have __printf() annotation so that the compiler can
check the format and arguments.
See here
https://elixir.free-electrons.com/linux/v6.10-rc2/source/include/linux/compiler_attributes.h#L171
Regards,
Christian.
void amdgpu_ucode_release(const struct firmware **fw);
bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
uint16_t hdr_major, uint16_t hdr_minor);
Re: [PATCH v2 03/10] drm/amdgpu: abort fence poll if reset is started
Hi Shaoyun, yes my thinking goes into the same direction. The basic problem here is that we are trying to stuff two different information into the same variable. The first information is if the commands haven been read by the MES from the ring buffer. This information is necessary for the normal ring buffer and reset handling, e.g. prevents ring buffer overflow, ordering of command, lockups during reset etc... The second information is if a certain operation was successfully or not. For example this is necessary to get signaled back if y queue map/unmap operation has been successfully or if the CP not responding or any other error has happened etc... Another issue is that while it is in general a good idea to have the firmware work in a way where errors are reported instead of completely stopping all processing, here we run into trouble because the driver usually assumes that work can be scheduled on the ring buffer and a subsequent work is processed only when everything previously submitted has completed successfully. So as initial fix for the issue we see I've send Alex a patch on Friday to partially revert his change to use an individual writeback for each submission. Instead we will submit an addition QUERY_STATUS command after the real command and let that one write fence value. This way the fence value is always written, independent of the result of the operation. Additional to that we need to insert something like a dependency between submissions, e.g. when you have commands A, B and C on the ring and C can only execute when A was successfully then we need to somehow tell that the MES. Only other alternative is to not scheduler commands behind each other on the ring and that in turn is a bad idea from the performance point of view. Regards, Christian. Am 31.05.24 um 16:44 schrieb Liu, Shaoyun: [AMD Official Use Only - AMD Internal Distribution Only] Hi, Christian I think we have a discussion about this before . Alex also have a change that allow driver to use different write back address for the fence for each submission for the original issue . From MES point of view , MES will update the fence when the API can be complete successfully, so if the API (ex . remove_queue) fails due to other component issue (ex , CP hang), the MES will not update the fence In this situation , but MES itself still works and can respond to other commands (ex ,,read_reg) . Alex's change allow driver to check the fence for each API without mess around them . If you expect MES to stop responding to further commands after one API fails , that will introduce combability issue since this design already exist on products for customer and MES also need to works for windows . Also MES always need to respond to some commands like RESET etc that might make things worse if we need to change the logic . One possible solution is MES can trigger an Interrupt to indicate which submission has failed with the seq number . In this case driver can get the failure of the submission to MES in time and make its own decision for what to do next , What do you think about this ? Regards Shaoyun.liu -Original Message- From: amd-gfx On Behalf Of Christian König Sent: Wednesday, May 29, 2024 11:19 AM To: Li, Yunxiang (Teddy) ; Koenig, Christian ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH v2 03/10] drm/amdgpu: abort fence poll if reset is started Am 29.05.24 um 16:48 schrieb Li, Yunxiang (Teddy): [AMD Official Use Only - AMD Internal Distribution Only] Yeah, I know. That's one of the reason I've pointed out on the patch adding that that this behavior is actually completely broken. If you run into issues with the MES because of this then please suggest a revert of that patch. I think it just need to be improved to allow this force-signal behavior. The current behavior is slow/inconvenient, but the old behavior is wrong. Since MES will continue process submissions even when one submission failed. So with just one fence location there's no way to tell if a command failed or not. No the MES behavior is broken. When a submission failed it should stop processing or signal that the operation didn't completed through some other mechanism. Just not writing the fence and continuing results in tons of problems, from the TLB fence all the way to the ring buffer and reset handling. This is a hard requirement and really can't be changed. Regards, Christian.
Re: [PATCH 1/2] amdgpu: add the amdgpu_vm ptr in the vm_bo_map/unmap events
Am 03.06.24 um 10:46 schrieb Pierre-Eric Pelloux-Prayer:
These 2 traces events are tied to a specific VM so in order for them
to be useful for a tool we need to trace the amdgpu_vm as well.
The bo_va already contains the VM pointer the map/unmap operation
belongs to.
Signed-off-by: Pierre-Eric Pelloux-Prayer
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 8
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index f539b1d00234..c84050d318d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -243,10 +243,11 @@ TRACE_EVENT(amdgpu_vm_grab_id,
);
TRACE_EVENT(amdgpu_vm_bo_map,
- TP_PROTO(struct amdgpu_bo_va *bo_va,
+ TP_PROTO(struct amdgpu_vm *vm, struct amdgpu_bo_va *bo_va,
struct amdgpu_bo_va_mapping *mapping),
- TP_ARGS(bo_va, mapping),
+ TP_ARGS(vm, bo_va, mapping),
TP_STRUCT__entry(
+__field(struct amdgpu_vm *, vm)
__field(struct amdgpu_bo *, bo)
__field(long, start)
__field(long, last)
@@ -255,22 +256,24 @@ TRACE_EVENT(amdgpu_vm_bo_map,
),
TP_fast_assign(
+ __entry->vm = vm;
__entry->bo = bo_va ? bo_va->base.bo : NULL;
__entry->start = mapping->start;
__entry->last = mapping->last;
__entry->offset = mapping->offset;
__entry->flags = mapping->flags;
),
- TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx",
- __entry->bo, __entry->start, __entry->last,
+ TP_printk("vm=%p bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%llx",
+ __entry->vm, __entry->bo, __entry->start, __entry->last,
__entry->offset, __entry->flags)
);
TRACE_EVENT(amdgpu_vm_bo_unmap,
- TP_PROTO(struct amdgpu_bo_va *bo_va,
+ TP_PROTO(struct amdgpu_vm *vm, struct amdgpu_bo_va *bo_va,
struct amdgpu_bo_va_mapping *mapping),
- TP_ARGS(bo_va, mapping),
+ TP_ARGS(vm, bo_va, mapping),
TP_STRUCT__entry(
+__field(struct amdgpu_vm *, vm)
__field(struct amdgpu_bo *, bo)
__field(long, start)
__field(long, last)
@@ -279,14 +282,15 @@ TRACE_EVENT(amdgpu_vm_bo_unmap,
),
TP_fast_assign(
+ __entry->vm = vm;
__entry->bo = bo_va ? bo_va->base.bo : NULL;
__entry->start = mapping->start;
__entry->last = mapping->last;
__entry->offset = mapping->offset;
__entry->flags = mapping->flags;
),
- TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx",
- __entry->bo, __entry->start, __entry->last,
+ TP_printk("vm=%p bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%llx",
+ __entry->vm, __entry->bo, __entry->start, __entry->last,
__entry->offset, __entry->flags)
);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 3abfa66d72a2..e04928d2e26a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1642,7 +1642,7 @@ static void amdgpu_vm_bo_insert_map(struct amdgpu_device
*adev,
if (amdgpu_vm_is_bo_always_valid(vm, bo) && !bo_va->base.moved)
amdgpu_vm_bo_moved(_va->base);
- trace_amdgpu_vm_bo_map(bo_va, mapping);
+ trace_amdgpu_vm_bo_map(vm, bo_va, mapping);
}
/* Validate operation parameters to prevent potential abuse */
@@ -1834,7 +1834,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
list_del(>list);
amdgpu_vm_it_remove(mapping, >va);
mapping->bo_va = NULL;
- trace_amdgpu_vm_bo_unmap(bo_va, mapping);
+ trace_amdgpu_vm_bo_unmap(vm, bo_va, mapping);
if (valid)
list_add(>list, >freed);
@@ -1929,7 +1929,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device
*adev,
tmp->bo_va = NULL;
list_add(>list, >freed);
- trace_amdgpu_vm_bo_unmap(NULL, tmp);
+ trace_amdgpu_vm_bo_unmap(vm, NULL, tmp);
That bo_va is NULL here is probably a bug and should be fixed.
Regards,
Christian.
}
/* Insert partial mapping before the range */
@@ -2056,7
RE: [PATCH 05/12] drm/amd/pm: remove dead code in navi10_emit_clk_levels and navi10_print_clk_levels
[AMD Official Use Only - AMD Internal Distribution Only] Could you share the problems you encountered? Some compilers may prompt you to forget to handle default cases. Best Regards, Kevin -Original Message- From: amd-gfx On Behalf Of Jesse Zhang Sent: Monday, June 3, 2024 4:48 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Koenig, Christian ; Kuehling, Felix ; Huang, Tim ; Zhang, Jesse(Jie) ; Zhang, Jesse(Jie) Subject: [PATCH 05/12] drm/amd/pm: remove dead code in navi10_emit_clk_levels and navi10_print_clk_levels Since the range of the varibable i is 0 - 3. So execution cannot reach this statement: default. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index cf556f1b5ed1..076620fa3ef5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -1389,8 +1389,6 @@ static int navi10_emit_clk_levels(struct smu_context *smu, case 2: curve_settings = _table->GfxclkFreq3; break; - default: - break; } *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n", i, curve_settings[0], @@ -1594,8 +1592,6 @@ static int navi10_print_clk_levels(struct smu_context *smu, case 2: curve_settings = _table->GfxclkFreq3; break; - default: - break; } size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n", i, curve_settings[0], -- 2.25.1
RE: [PATCH] drm/amdgpu: replace int with unsigned int for imu_v12_0.c
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Christian,
It fixes a potential Overflowed constant (INTEGER_OVERFLOW) warning reported by
Coverity.
Regards,
Bob
-Original Message-
From: Koenig, Christian
Sent: 2024年6月3日 15:56
To: Zhou, Bob ; amd-gfx@lists.freedesktop.org; Huang, Tim
; Zhang, Jesse(Jie)
Cc: Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu: replace int with unsigned int for imu_v12_0.c
Am 03.06.24 um 07:59 schrieb Bob Zhou:
> The return value of RREG32_SOC15 is unsigned int, so modify variable to
> unsigned.
And why is that an improvement?
Regards,
Christian.
>
> Signed-off-by: Bob Zhou
> ---
> drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
> b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
> index 0c8ef908d112..2d6f7549c2af 100644
> --- a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
> @@ -119,7 +119,7 @@ static int imu_v12_0_load_microcode(struct
> amdgpu_device *adev)
>
> static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev)
> {
> - int i, imu_reg_val = 0;
> + unsigned int i, imu_reg_val = 0;
>
> for (i = 0; i < adev->usec_timeout; i++) {
> imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); @@
> -138,7 +138,7 @@ static int imu_v12_0_wait_for_reset_status(struct
> amdgpu_device *adev)
>
> static void imu_v12_0_setup(struct amdgpu_device *adev)
> {
> - int imu_reg_val;
> + unsigned int imu_reg_val;
>
> WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xff);
> WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0x); @@
> -157,7 +157,7 @@ static void imu_v12_0_setup(struct amdgpu_device
> *adev)
>
> static int imu_v12_0_start(struct amdgpu_device *adev)
> {
> - int imu_reg_val;
> + unsigned int imu_reg_val;
>
> imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);
> imu_reg_val &= 0xfffe;
[PATCH 12/12] drm/amdgpu: remove dead code in si_program_aspm
The variable disable_l1 is false and execution cannot reach the else branch.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/si.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 85235470e872..d80eec275090 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -2598,9 +2598,6 @@ static void si_program_aspm(struct amdgpu_device *adev)
WREG32(SPLL_CNTL_MODE, data);
}
}
- } else {
- if (orig != data)
- WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
}
orig = data = RREG32_PCIE(PCIE_CNTL2);
--
2.25.1
[PATCH 11/12] drm/amdkfd: remove logically dead code
idr_for_each_entry can ensure that mem is not empty during the loop.
So don't need check mem again.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index fdf171ad4a3c..32e5db509560 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1913,11 +1913,6 @@ static int criu_checkpoint_bos(struct kfd_process *p,
struct kfd_criu_bo_priv_data *bo_priv;
int i, dev_idx = 0;
- if (!mem) {
- ret = -ENOMEM;
- goto exit;
- }
-
kgd_mem = (struct kgd_mem *)mem;
dumper_bo = kgd_mem->bo;
--
2.25.1
[PATCH 10/12] drm/amdkfd: remove dead code in kq_initialize
The queue type can only be KFD_QUEUE_TYPE_DIQ or KFD_QUEUE_TYPE_HIQ,
and the default cannot be reached.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 32c926986dbb..3142b2593e2b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -67,9 +67,6 @@ static bool kq_initialize(struct kernel_queue *kq, struct
kfd_node *dev,
case KFD_QUEUE_TYPE_HIQ:
kq->mqd_mgr = dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ];
break;
- default:
- pr_err("Invalid queue type %d\n", type);
- return false;
}
if (!kq->mqd_mgr)
--
2.25.1
[PATCH 09/12] [PATCH 28/28] drm/amdgpu: remove dead code in cik_program_aspm
Since disable_l1 is false, the else branch cannot be reached.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/cik.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 5428fd4071b8..0ad736e775db 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1819,9 +1819,6 @@ static void cik_program_aspm(struct amdgpu_device *adev)
WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data);
}
}
- } else {
- if (orig != data)
- WREG32_PCIE(ixPCIE_LC_CNTL, data);
}
orig = data = RREG32_PCIE(ixPCIE_CNTL2);
--
2.25.1
[PATCH 08/12] drm/amdgpu/pm: remove dead code in aldebaran_emit_clk_levels and arcturus_emit_clk_levels
The value of type check at the start. The switch governing value type cannot reach the default case. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 -- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index c0f6b59369b7..f31cf8ad025f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -937,8 +937,6 @@ static int arcturus_emit_clk_levels(struct smu_context *smu, smu->smu_table.boot_values.lclk / 100); break; - default: - return -EINVAL; } return 0; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index 825786fc849e..35eadd7906ca 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -919,8 +919,6 @@ static int aldebaran_emit_clk_levels(struct smu_context *smu, (freq_match) ? "*" : ""); } break; - default: - return -EINVAL; } return 0; -- 2.25.1
[PATCH 07/12] drm/amdgpu: remove dead code in amdgpu_vpe_configure_dpm
When switching on idx, the value of idx must be between 0 and 3. The switch governing value idx cannot reach the default case. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index 49881073ff58..fb1902ba0c80 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -183,8 +183,6 @@ int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe) case 3: pratio_vmax_freq = min_freq; break; - default: - break; } } -- 2.25.1
[PATCH 06/12] drm/amd/pm: remove dead code in smu_get_power_limit
At the start it checks limit_level. When switching on limit_level, the value of limit_level must be between -1 and 2. The switch governing value limit_level cannot reach the default case. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 6f742d88867d..0b4193639e65 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2754,8 +2754,6 @@ int smu_get_power_limit(void *handle, case SMU_PPT_LIMIT_MIN: *limit = smu->min_power_limit; break; - default: - return -EINVAL; } } -- 2.25.1
[PATCH 2/2] amdgpu: don't dereference a NULL resource in sysfs code
dma_resv_trylock being successful doesn't guarantee that bo->tbo.base.resv
is not NULL, so check its validity before using it.
Signed-off-by: Pierre-Eric Pelloux-Prayer
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 63 +++---
1 file changed, 33 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1eadcad1856d..6faeb9e4a572 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1594,36 +1594,39 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo,
struct seq_file *m)
u64 size;
if (dma_resv_trylock(bo->tbo.base.resv)) {
-
- switch (bo->tbo.resource->mem_type) {
- case TTM_PL_VRAM:
- if (amdgpu_res_cpu_visible(adev, bo->tbo.resource))
- placement = "VRAM VISIBLE";
- else
- placement = "VRAM";
- break;
- case TTM_PL_TT:
- placement = "GTT";
- break;
- case AMDGPU_PL_GDS:
- placement = "GDS";
- break;
- case AMDGPU_PL_GWS:
- placement = "GWS";
- break;
- case AMDGPU_PL_OA:
- placement = "OA";
- break;
- case AMDGPU_PL_PREEMPT:
- placement = "PREEMPTIBLE";
- break;
- case AMDGPU_PL_DOORBELL:
- placement = "DOORBELL";
- break;
- case TTM_PL_SYSTEM:
- default:
- placement = "CPU";
- break;
+ if (!bo->tbo.resource) {
+ placement = "NONE";
+ } else {
+ switch (bo->tbo.resource->mem_type) {
+ case TTM_PL_VRAM:
+ if (amdgpu_res_cpu_visible(adev,
bo->tbo.resource))
+ placement = "VRAM VISIBLE";
+ else
+ placement = "VRAM";
+ break;
+ case TTM_PL_TT:
+ placement = "GTT";
+ break;
+ case AMDGPU_PL_GDS:
+ placement = "GDS";
+ break;
+ case AMDGPU_PL_GWS:
+ placement = "GWS";
+ break;
+ case AMDGPU_PL_OA:
+ placement = "OA";
+ break;
+ case AMDGPU_PL_PREEMPT:
+ placement = "PREEMPTIBLE";
+ break;
+ case AMDGPU_PL_DOORBELL:
+ placement = "DOORBELL";
+ break;
+ case TTM_PL_SYSTEM:
+ default:
+ placement = "CPU";
+ break;
+ }
}
dma_resv_unlock(bo->tbo.base.resv);
} else {
--
2.40.1
[PATCH 1/2] amdgpu: add the amdgpu_vm ptr in the vm_bo_map/unmap events
These 2 traces events are tied to a specific VM so in order for them
to be useful for a tool we need to trace the amdgpu_vm as well.
Signed-off-by: Pierre-Eric Pelloux-Prayer
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 8
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index f539b1d00234..c84050d318d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -243,10 +243,11 @@ TRACE_EVENT(amdgpu_vm_grab_id,
);
TRACE_EVENT(amdgpu_vm_bo_map,
- TP_PROTO(struct amdgpu_bo_va *bo_va,
+ TP_PROTO(struct amdgpu_vm *vm, struct amdgpu_bo_va *bo_va,
struct amdgpu_bo_va_mapping *mapping),
- TP_ARGS(bo_va, mapping),
+ TP_ARGS(vm, bo_va, mapping),
TP_STRUCT__entry(
+__field(struct amdgpu_vm *, vm)
__field(struct amdgpu_bo *, bo)
__field(long, start)
__field(long, last)
@@ -255,22 +256,24 @@ TRACE_EVENT(amdgpu_vm_bo_map,
),
TP_fast_assign(
+ __entry->vm = vm;
__entry->bo = bo_va ? bo_va->base.bo : NULL;
__entry->start = mapping->start;
__entry->last = mapping->last;
__entry->offset = mapping->offset;
__entry->flags = mapping->flags;
),
- TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx",
- __entry->bo, __entry->start, __entry->last,
+ TP_printk("vm=%p bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%llx",
+ __entry->vm, __entry->bo, __entry->start, __entry->last,
__entry->offset, __entry->flags)
);
TRACE_EVENT(amdgpu_vm_bo_unmap,
- TP_PROTO(struct amdgpu_bo_va *bo_va,
+ TP_PROTO(struct amdgpu_vm *vm, struct amdgpu_bo_va *bo_va,
struct amdgpu_bo_va_mapping *mapping),
- TP_ARGS(bo_va, mapping),
+ TP_ARGS(vm, bo_va, mapping),
TP_STRUCT__entry(
+__field(struct amdgpu_vm *, vm)
__field(struct amdgpu_bo *, bo)
__field(long, start)
__field(long, last)
@@ -279,14 +282,15 @@ TRACE_EVENT(amdgpu_vm_bo_unmap,
),
TP_fast_assign(
+ __entry->vm = vm;
__entry->bo = bo_va ? bo_va->base.bo : NULL;
__entry->start = mapping->start;
__entry->last = mapping->last;
__entry->offset = mapping->offset;
__entry->flags = mapping->flags;
),
- TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx",
- __entry->bo, __entry->start, __entry->last,
+ TP_printk("vm=%p bo=%p, start=%lx, last=%lx, offset=%010llx,
flags=%llx",
+ __entry->vm, __entry->bo, __entry->start, __entry->last,
__entry->offset, __entry->flags)
);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 3abfa66d72a2..e04928d2e26a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1642,7 +1642,7 @@ static void amdgpu_vm_bo_insert_map(struct amdgpu_device
*adev,
if (amdgpu_vm_is_bo_always_valid(vm, bo) && !bo_va->base.moved)
amdgpu_vm_bo_moved(_va->base);
- trace_amdgpu_vm_bo_map(bo_va, mapping);
+ trace_amdgpu_vm_bo_map(vm, bo_va, mapping);
}
/* Validate operation parameters to prevent potential abuse */
@@ -1834,7 +1834,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
list_del(>list);
amdgpu_vm_it_remove(mapping, >va);
mapping->bo_va = NULL;
- trace_amdgpu_vm_bo_unmap(bo_va, mapping);
+ trace_amdgpu_vm_bo_unmap(vm, bo_va, mapping);
if (valid)
list_add(>list, >freed);
@@ -1929,7 +1929,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device
*adev,
tmp->bo_va = NULL;
list_add(>list, >freed);
- trace_amdgpu_vm_bo_unmap(NULL, tmp);
+ trace_amdgpu_vm_bo_unmap(vm, NULL, tmp);
}
/* Insert partial mapping before the range */
@@ -2056,7 +2056,7 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev,
list_del(>list);
amdgpu_vm_it_remove(mapping, >va);
mapping->bo_va = NULL;
-
[PATCH 05/12] drm/amd/pm: remove dead code in navi10_emit_clk_levels and navi10_print_clk_levels
Since the range of the varibable i is 0 - 3. So execution cannot reach this statement: default. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index cf556f1b5ed1..076620fa3ef5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -1389,8 +1389,6 @@ static int navi10_emit_clk_levels(struct smu_context *smu, case 2: curve_settings = _table->GfxclkFreq3; break; - default: - break; } *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n", i, curve_settings[0], @@ -1594,8 +1592,6 @@ static int navi10_print_clk_levels(struct smu_context *smu, case 2: curve_settings = _table->GfxclkFreq3; break; - default: - break; } size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n", i, curve_settings[0], -- 2.25.1
[PATCH 04/12] drm/amdgpu: remove dead code in atom_get_src_int
Since the range of align is 0~7, the expression is: align = (attr >> 3) & 7.
In the case of ATOM_ARG_IMM, the code cannot reach the default case.
So there is no need for "break".
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/atom.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c
b/drivers/gpu/drm/amd/amdgpu/atom.c
index d552e013354c..c660e4a663ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -320,7 +320,6 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx,
uint8_t attr,
DEBUG("IMM 0x%02X\n", val);
return val;
}
- break;
case ATOM_ARG_PLL:
idx = U8(*ptr);
(*ptr)++;
--
2.25.1
[PATCH 03/12] drm/amdgpu: remove dead code in sdma_v6_0_load_microcode
Remove legacy method to load firmware mode, since that code cannot be reach.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 39 --
1 file changed, 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index c833b6b8373b..b54b9cc2bf75 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -631,45 +631,6 @@ static int sdma_v6_0_load_microcode(struct amdgpu_device
*adev)
msleep(1);
WREG32(sdma_v6_0_get_reg_offset(adev, 0,
regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
}
- } else {
- dev_info(adev->dev, "Use legacy method to load SDMA
firmware\n");
- for (i = 0; i < adev->sdma.num_instances; i++) {
- /* load Control Thread microcode */
- hdr = (const struct sdma_firmware_header_v2_0
*)adev->sdma.instance[0].fw->data;
- amdgpu_ucode_print_sdma_hdr(>header);
- fw_size = le32_to_cpu(hdr->ctx_jt_offset +
hdr->ctx_jt_size) / 4;
-
- fw_data = (const __le32 *)
- (adev->sdma.instance[0].fw->data +
-
le32_to_cpu(hdr->header.ucode_array_offset_bytes));
-
- WREG32(sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_UCODE_ADDR), 0);
-
- for (j = 0; j < fw_size; j++) {
- if (amdgpu_emu_mode == 1 && j % 500 == 0)
- msleep(1);
- WREG32(sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
- }
-
- WREG32(sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
-
- /* load Context Switch microcode */
- fw_size = le32_to_cpu(hdr->ctl_jt_offset +
hdr->ctl_jt_size) / 4;
-
- fw_data = (const __le32 *)
- (adev->sdma.instance[0].fw->data +
- le32_to_cpu(hdr->ctl_ucode_offset));
-
- WREG32(sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_UCODE_ADDR), 0x8000);
-
- for (j = 0; j < fw_size; j++) {
- if (amdgpu_emu_mode == 1 && j % 500 == 0)
- msleep(1);
- WREG32(sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
- }
-
- WREG32(sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
- }
}
return 0;
--
2.25.1
[PATCH 02/12] drm/amdgpu: remove dead code in cik_program_aspm
Since disable_clkreq is false, execution cannot reach this statement:
clk_req_support = false.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/cik.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index cf1d5d462b67..5428fd4071b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1777,8 +1777,6 @@ static void cik_program_aspm(struct amdgpu_device *adev)
pcie_capability_read_dword(root,
PCI_EXP_LNKCAP, );
if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
clk_req_support = true;
- } else {
- clk_req_support = false;
}
if (clk_req_support) {
--
2.25.1
[PATCH 01/12] drm/amd/pm: remove dead code in si_convert_power_level_to_smc
Since gmc_pg is false, setting mcFlags with SISLANDS_SMC_MC_PG_EN cannot be
reach.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index 68ac01a8bc3a..a18f75a6d480 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -5487,9 +5487,6 @@ static int si_convert_power_level_to_smc(struct
amdgpu_device *adev,
(RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
(adev->pm.dpm.new_active_crtc_count <= 2)) {
level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
-
- if (gmc_pg)
- level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
}
if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
--
2.25.1
[PATCH 00/12] *** Remove dead code ***
Jesse Zhang (12): drm/amd/pm: remove dead code in si_convert_power_level_to_smc drm/amdgpu: remove dead code in cik_program_aspm drm/amdgpu: remove dead code in sdma_v6_0_load_microcode drm/amdgpu: remove dead code in atom_get_src_int drm/amd/pm: remove dead code in navi10_emit_clk_levels and navi10_print_clk_levels drm/amd/pm: remove dead code in smu_get_power_limit drm/amdgpu: remove dead code in amdgpu_vpe_configure_dpm drm/amdgpu/pm: remove dead code in aldebaran_emit_clk_levels and arcturus_emit_clk_levels drm/amdgpu: remove dead code in cik_program_aspm drm/amdkfd: remove dead code in kq_initialize drm/amdkfd: remove logically dead code drm/amdgpu: remove dead code in si_program_aspm drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 2 - drivers/gpu/drm/amd/amdgpu/atom.c | 1 - drivers/gpu/drm/amd/amdgpu/cik.c | 5 --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c| 39 --- drivers/gpu/drm/amd/amdgpu/si.c | 3 -- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 --- drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 3 -- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c| 3 -- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 - .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 - .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 -- .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 2 - 12 files changed, 71 deletions(-) -- 2.25.1
Re: [PATCH] Revert "drm/amdgpu/gfx11: enable gfx pipe1 hardware support"
Thanks Alex, the patch is: Acked-by: Pierre-Eric Pelloux-Prayer Le 31/05/2024 à 19:42, Alex Deucher a écrit : This reverts commit 269226a8fdf2cac0e03920f9ba0d670a056af3d6. Pierre-Eric reported problems with this on his navi33. Revert for now until we understand what is going wrong. Signed-off-by: Alex Deucher Cc: pierre-eric.pelloux-pra...@amd.com --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 72676bfbac8c..bf05ff77feb8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -50,7 +50,7 @@ #include "nbio_v4_3.h" #include "mes_v11_0.h" -#define GFX11_NUM_GFX_RINGS 2 +#define GFX11_NUM_GFX_RINGS1 #define GFX11_MEC_HPD_SIZE2048 #define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L @@ -1526,7 +1526,7 @@ static int gfx_v11_0_sw_init(void *handle) case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 3): adev->gfx.me.num_me = 1; - adev->gfx.me.num_pipe_per_me = 2; + adev->gfx.me.num_pipe_per_me = 1; adev->gfx.me.num_queue_per_pipe = 1; adev->gfx.mec.num_mec = 2; adev->gfx.mec.num_pipe_per_mec = 4; @@ -1537,7 +1537,7 @@ static int gfx_v11_0_sw_init(void *handle) case IP_VERSION(11, 5, 0): case IP_VERSION(11, 5, 1): adev->gfx.me.num_me = 1; - adev->gfx.me.num_pipe_per_me = 2; + adev->gfx.me.num_pipe_per_me = 1; adev->gfx.me.num_queue_per_pipe = 1; adev->gfx.mec.num_mec = 1; adev->gfx.mec.num_pipe_per_mec = 4;
RE: [PATCH] drm/amdkfd: add reset cause in gpu pre-reset smi event
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Eric,
To consider other reset cases also, you may have something like attached.
Thanks,
Lijo
-Original Message-
From: amd-gfx On Behalf Of Eric Huang
Sent: Friday, May 31, 2024 8:38 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kasiviswanathan, Harish ; Huang, JinHuiEric
Subject: [PATCH] drm/amdkfd: add reset cause in gpu pre-reset smi event
reset cause is requested by customer as additional info for gpu reset smi event.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 34 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 17 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 9 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 7 +-
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 71 +++
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 13 +++-
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h | 5 +-
9 files changed, 133 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index e3738d417245..3588c912214a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -125,17 +125,26 @@ static void amdgpu_doorbell_get_kfd_info(struct
amdgpu_device *adev, static void amdgpu_amdkfd_reset_work(struct work_struct
*work) {
struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
- kfd.reset_work);
-
- struct amdgpu_reset_context reset_context;
+ kfd.reset_work.work);
+
+ if (adev->kfd.reset_work.reset_context) {
+ amdgpu_device_gpu_recover(
+ adev, NULL,
+ (struct amdgpu_reset_context *)
+ adev->kfd.reset_work.reset_context);
+ kfree(adev->kfd.reset_work.reset_context);
+ adev->kfd.reset_work.reset_context = NULL;
+ } else {
+ struct amdgpu_reset_context reset_context;
- memset(_context, 0, sizeof(reset_context));
+ memset(_context, 0, sizeof(reset_context));
- reset_context.method = AMD_RESET_METHOD_NONE;
- reset_context.reset_req_dev = adev;
- clear_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
+ reset_context.method = AMD_RESET_METHOD_NONE;
+ reset_context.reset_req_dev = adev;
+ clear_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
- amdgpu_device_gpu_recover(adev, NULL, _context);
+ amdgpu_device_gpu_recover(adev, NULL, _context);
+ }
}
static const struct drm_client_funcs kfd_client_funcs = { @@ -225,7 +234,7 @@
void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
- INIT_WORK(>kfd.reset_work, amdgpu_amdkfd_reset_work);
+ INIT_WORK(>kfd.reset_work.work, amdgpu_amdkfd_reset_work);
}
}
@@ -261,12 +270,13 @@ int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool
run_pm)
return r;
}
-int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
+int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev,
+ struct amdgpu_reset_context *reset_context)
{
int r = 0;
if (adev->kfd.dev)
- r = kgd2kfd_pre_reset(adev->kfd.dev);
+ r = kgd2kfd_pre_reset(adev->kfd.dev, reset_context);
return r;
}
@@ -285,7 +295,7 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) {
if (amdgpu_device_should_recover_gpu(adev))
amdgpu_reset_domain_schedule(adev->reset_domain,
->kfd.reset_work);
+>kfd.reset_work.work);
}
int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, diff
--git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 1de021ebdd46..1fc9ed33a1c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -47,6 +47,7 @@ enum TLB_FLUSH_TYPE {
};
struct amdgpu_device;
+struct amdgpu_reset_context;
enum kfd_mem_attachment_type {
KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
@@ -98,12 +99,17 @@ struct amdgpu_amdkfd_fence {
struct svm_range_bo *svm_bo;
};
+struct kfd_reset_work {
+ struct work_struct work;
+ void *reset_context;
+};
+
struct amdgpu_kfd_dev {
struct kfd_dev *dev;
int64_t vram_used[MAX_XCP];
uint64_t vram_used_aligned[MAX_XCP];
bool init_complete;
- struct work_struct reset_work;
+ struct kfd_reset_work reset_work;
/* HMM
Re: [PATCH] drm/amdgpu: replace int with unsigned int for imu_v12_0.c
Am 03.06.24 um 07:59 schrieb Bob Zhou:
The return value of RREG32_SOC15 is unsigned int, so modify variable to
unsigned.
And why is that an improvement?
Regards,
Christian.
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
index 0c8ef908d112..2d6f7549c2af 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
@@ -119,7 +119,7 @@ static int imu_v12_0_load_microcode(struct amdgpu_device
*adev)
static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev)
{
- int i, imu_reg_val = 0;
+ unsigned int i, imu_reg_val = 0;
for (i = 0; i < adev->usec_timeout; i++) {
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
@@ -138,7 +138,7 @@ static int imu_v12_0_wait_for_reset_status(struct
amdgpu_device *adev)
static void imu_v12_0_setup(struct amdgpu_device *adev)
{
- int imu_reg_val;
+ unsigned int imu_reg_val;
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xff);
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0x);
@@ -157,7 +157,7 @@ static void imu_v12_0_setup(struct amdgpu_device *adev)
static int imu_v12_0_start(struct amdgpu_device *adev)
{
- int imu_reg_val;
+ unsigned int imu_reg_val;
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);
imu_reg_val &= 0xfffe;
RE: [PATCH] drm/amdgpu: Don't show false warning for reg list
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Monday, June 3, 2024 2:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Li, Candice
Subject: [PATCH] drm/amdgpu: Don't show false warning for reg list
If reg list is already loaded on PSP 13.0.2 SOCs, psp will give TEE_ERR_CANCEL
response on second time load. Avoid printing warn message for it.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 25 +
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 5 +++--
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 6d1911773043..079feb139b16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -643,6 +643,20 @@ static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id
cmd_id)
}
}
+static bool psp_err_warn(struct psp_context *psp) {
+ struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem;
+
+ /* This response indicates reg list is already loaded */
+ if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) &&
+ cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW &&
+ cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST &&
+ cmd->resp.status == TEE_ERROR_CANCEL)
+ return false;
+
+ return true;
+}
+
static int
psp_cmd_submit_buf(struct psp_context *psp,
struct amdgpu_firmware_info *ucode, @@ -702,10 +716,13 @@
psp_cmd_submit_buf(struct psp_context *psp,
dev_warn(psp->adev->dev,
"failed to load ucode %s(0x%X) ",
amdgpu_ucode_name(ucode->ucode_id),
ucode->ucode_id);
- dev_warn(psp->adev->dev,
-"psp gfx command %s(0x%X) failed and response status
is (0x%X)\n",
-psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id),
psp->cmd_buf_mem->cmd_id,
-psp->cmd_buf_mem->resp.status);
+ if (psp_err_warn(psp))
+ dev_warn(
+ psp->adev->dev,
+ "psp gfx command %s(0x%X) failed and response
status is (0x%X)\n",
+ psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id),
+ psp->cmd_buf_mem->cmd_id,
+ psp->cmd_buf_mem->resp.status);
/* If any firmware (including CAP) load fails under SRIOV, it
should
* return failure to stop the VF from initializing.
* Also return failure in case of timeout diff --git
a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index 7566973ed8f5..37b5ddd6f13b 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -464,8 +464,9 @@ struct psp_gfx_rb_frame #define PSP_ERR_UNKNOWN_COMMAND
0x0100
enum tee_error_code {
-TEE_SUCCESS = 0x,
-TEE_ERROR_NOT_SUPPORTED = 0x000A,
+ TEE_SUCCESS = 0x,
+ TEE_ERROR_CANCEL= 0x0002,
+ TEE_ERROR_NOT_SUPPORTED = 0x000A,
};
#endif /* _PSP_TEE_GFX_IF_H_ */
--
2.25.1
Re: [PATCH] drm/amdgpu: Skip coredump during resets for debug
Am 31.05.24 um 14:34 schrieb Lijo Lazar: Skip scheduling coredump when gpu reset is intentionally triggered through debugfs. Signed-off-by: Lijo Lazar Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 10832b470448..1a9fda1d20fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -981,6 +981,7 @@ static void amdgpu_debugfs_reset_work(struct work_struct *work) reset_context.method = AMD_RESET_METHOD_NONE; reset_context.reset_req_dev = adev; set_bit(AMDGPU_NEED_FULL_RESET, _context.flags); + set_bit(AMDGPU_SKIP_COREDUMP, _context.flags); amdgpu_device_gpu_recover(adev, NULL, _context); }
[PATCH] drm/amdgpu: Don't show false warning for reg list
If reg list is already loaded on PSP 13.0.2 SOCs, psp will give
TEE_ERR_CANCEL response on second time load. Avoid printing warn
message for it.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 25 +
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 5 +++--
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 6d1911773043..079feb139b16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -643,6 +643,20 @@ static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id
cmd_id)
}
}
+static bool psp_err_warn(struct psp_context *psp)
+{
+ struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem;
+
+ /* This response indicates reg list is already loaded */
+ if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) &&
+ cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW &&
+ cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST &&
+ cmd->resp.status == TEE_ERROR_CANCEL)
+ return false;
+
+ return true;
+}
+
static int
psp_cmd_submit_buf(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
@@ -702,10 +716,13 @@ psp_cmd_submit_buf(struct psp_context *psp,
dev_warn(psp->adev->dev,
"failed to load ucode %s(0x%X) ",
amdgpu_ucode_name(ucode->ucode_id),
ucode->ucode_id);
- dev_warn(psp->adev->dev,
-"psp gfx command %s(0x%X) failed and response status
is (0x%X)\n",
-psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id),
psp->cmd_buf_mem->cmd_id,
-psp->cmd_buf_mem->resp.status);
+ if (psp_err_warn(psp))
+ dev_warn(
+ psp->adev->dev,
+ "psp gfx command %s(0x%X) failed and response
status is (0x%X)\n",
+ psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id),
+ psp->cmd_buf_mem->cmd_id,
+ psp->cmd_buf_mem->resp.status);
/* If any firmware (including CAP) load fails under SRIOV, it
should
* return failure to stop the VF from initializing.
* Also return failure in case of timeout
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index 7566973ed8f5..37b5ddd6f13b 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -464,8 +464,9 @@ struct psp_gfx_rb_frame
#define PSP_ERR_UNKNOWN_COMMAND 0x0100
enum tee_error_code {
-TEE_SUCCESS = 0x,
-TEE_ERROR_NOT_SUPPORTED = 0x000A,
+ TEE_SUCCESS = 0x,
+ TEE_ERROR_CANCEL= 0x0002,
+ TEE_ERROR_NOT_SUPPORTED = 0x000A,
};
#endif /* _PSP_TEE_GFX_IF_H_ */
--
2.25.1
