Re: [PATCH] drm/amdgpu/vcn: port mmsch ctx table size fix from jpeg v4

[JingWen Chen]

feel free to add

Reviewed-by: Jingwen Chen 

On 2024/6/12 11:41, Jane Jian wrote:
> add jpeg table size to ctx table size rather than override it
>
> v2:
> save jpeg header info otherwise it will lose debug info
> Signed-off-by: Jane Jian 
> ---
>  drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c 
> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> index 04d8966423de..ba052b104668 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> @@ -200,9 +200,12 @@ static int jpeg_v4_0_3_start_sriov(struct amdgpu_device 
> *adev)
>   for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
>   jpeg_inst = GET_INST(JPEG, i);
>  
> - memset(, 0, sizeof(struct mmsch_v4_0_3_init_header));
> + size = sizeof(struct mmsch_v4_0_3_init_header);
> + table_loc = (uint32_t *)table->cpu_addr;
> + memcpy(, (void *)table_loc, size);
> +
>   header.version = MMSCH_VERSION;
> - header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 
> 2;
> + header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE);
>  
>   table_loc = (uint32_t *)table->cpu_addr;
>   table_loc += header.total_size;

-- 
Best Regards,
JingWen Chen

[linux-next:master] BUILD REGRESSION a957267fa7e9159d3d2ee1421359ebf228570c68

[kernel test robot]

tree/branch: 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: a957267fa7e9159d3d2ee1421359ebf228570c68  Add linux-next specific 
files for 20240611

Error/Warning reports:

https://lore.kernel.org/oe-kbuild-all/202406111949.9wfztbkm-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202406121201.ynea7woo-...@intel.com

Error/Warning: (recently discovered and may have been fixed)

drivers/pinctrl/pinctrl-keembay.c:1630:35: error: 'struct function_desc' has no 
member named 'name'
or1k-linux-ld: sound/soc/tegra/tegra210_i2s.c:932:(.text+0x668): undefined 
reference to `simple_util_get_sample_fmt'
powerpc-linux-ld: tegra210_i2s.c:(.text+0x56c): undefined reference to 
`simple_util_get_sample_fmt'
sound/soc/tegra/tegra210_i2s.c:922:(.text+0x62c): relocation truncated to fit: 
R_OR1K_INSN_REL_26 against undefined symbol `simple_util_parse_convert'
sound/soc/tegra/tegra210_i2s.c:922:(.text+0x62c): undefined reference to 
`simple_util_parse_convert'
sound/soc/tegra/tegra210_i2s.c:932:(.text+0x668): relocation truncated to fit: 
R_OR1K_INSN_REL_26 against undefined symbol `simple_util_get_sample_fmt'
tegra210_i2s.c:(.text+0x538): undefined reference to `simple_util_parse_convert'

Error/Warning ids grouped by kconfigs:

gcc_recent_errors
|-- arc-randconfig-r131-20240611
|   |-- 
drivers-mtd-nand-raw-mxc_nand.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-void-buf-got-void-noderef-__iomem
|   `-- 
drivers-mtd-nand-raw-mxc_nand.c:sparse:sparse:incorrect-type-in-initializer-(different-address-spaces)-expected-unsigned-short-noderef-usertype-__iomem-t-got-void-buf
|-- arm-randconfig-051-20240611
|   |-- 
arch-arm-boot-dts-rockchip-rk3128-evb.dtb:dsi:failed-to-match-any-schema-with-compatible:rockchip-rk3128-mipi-dsi-snps-dw-mipi-dsi
|   `-- 
arch-arm-boot-dts-rockchip-rk3128-xpi-.dtb:dsi:failed-to-match-any-schema-with-compatible:rockchip-rk3128-mipi-dsi-snps-dw-mipi-dsi
|-- arm64-randconfig-001-20240612
|   `-- 
drivers-pinctrl-pinctrl-keembay.c:error:struct-function_desc-has-no-member-named-name
|-- i386-randconfig-061-20240611
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-B-got-struct-ftrace_hash-noderef-__rcu-filter_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-B-got-struct-ftrace_hash-noderef-__rcu-notrace_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-new_hash-got-struct-ftrace_hash-noderef-__rcu-filter_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-new_hash1-got-struct-ftrace_hash-noderef-__rcu-filter_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-new_hash2-got-struct-ftrace_hash-noderef-__rcu-filter_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-new_hash2-got-struct-ftrace_hash-noderef-__rcu-notrace_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-orig_hash-got-struct-ftrace_hash-noderef-__rcu
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-src-got-struct-ftrace_hash-noderef-__rcu-filter_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-ftrace_hash-src-got-struct-ftrace_hash-noderef-__rcu-notrace_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-expected-struct-ftrace_hash-noderef-__rcu-filter_hash-got-struct-ftrace_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-expected-struct-ftrace_hash-noderef-__rcu-filter_hash-got-struct-ftrace_hash-assigned-filter_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-expected-struct-ftrace_hash-noderef-__rcu-filter_hash-got-struct-ftrace_hash-save_filter_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-expected-struct-ftrace_hash-noderef-__rcu-notrace_hash-got-struct-ftrace_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-expected-struct-ftrace_hash-noderef-__rcu-notrace_hash-got-struct-ftrace_hash-assigned-notrace_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-expected-struct-ftrace_hash-noderef-__rcu-notrace_hash-got-struct-ftrace_hash-save_notrace_hash
|   |-- 
kernel-trace-ftrace.c:sparse:sparse:incorrect-type-in-assignment-(different

[PATCH] drm/amdgpu/vcn: port mmsch ctx table size fix from jpeg v4

[Jane Jian]

add jpeg table size to ctx table size rather than override it

v2:
save jpeg header info otherwise it will lose debug info
Signed-off-by: Jane Jian 
---
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c 
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 04d8966423de..ba052b104668 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -200,9 +200,12 @@ static int jpeg_v4_0_3_start_sriov(struct amdgpu_device 
*adev)
for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
jpeg_inst = GET_INST(JPEG, i);
 
-   memset(, 0, sizeof(struct mmsch_v4_0_3_init_header));
+   size = sizeof(struct mmsch_v4_0_3_init_header);
+   table_loc = (uint32_t *)table->cpu_addr;
+   memcpy(, (void *)table_loc, size);
+
header.version = MMSCH_VERSION;
-   header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 
2;
+   header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE);
 
table_loc = (uint32_t *)table->cpu_addr;
table_loc += header.total_size;
-- 
2.34.1

[PATCH] drm/amd/display: Enable idle optimizations on DCN401

[Aurabindo Pillai]

Idle optimizations were disabled due to some bugs which are now fixed in
DMCUB and PM firwmare. Enable these the optimizations back.

Signed-off-by: Aurabindo Pillai 
---
 .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c| 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c 
b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index ea803df8645e..d78dc63f82fd 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -731,9 +731,7 @@ static const struct dc_debug_options debug_defaults_drv = {
}
},
.force_cositing = CHROMA_COSITING_TOPLEFT + 1,
-   .disable_idle_power_optimizations = true,
.edp_oled_no_backlight_enable = true,
-   .disable_boot_optimizations = true,
 };
 
 static struct dce_aux *dcn401_aux_engine_create(
-- 
2.45.2

Re: [RFC PATCH v4 00/42] Color Pipeline API w/ VKMS

[Harry Wentland]

On 2024-06-05 06:04, Melissa Wen wrote:
> On 02/26, Harry Wentland wrote:
>> This is an RFC set for a color pipeline API, along with a sample
>> implementation in VKMS. All the key API bits are here. VKMS now
>> supports two named transfer function colorops and two matrix
>> colorops. We have IGT tests that check all four of these colorops
>> with a pixel-by-pixel comparison that checks that these colorops
>> do what we expect them to do with a +/- 1 8 bpc code point margin.
>>
>> The big new change with v4 is the addition of an amdgpu color
>> pipeline, for all AMD GPUs with DCN 3 and newer. Amdgpu now support
>> the following:
>>
>> 1. 1D Curve EOTF
>> 2. 3x4 CTM
>> 3. Multiplier
>> 4. 1D Curve Inverse EOTF
>> 5. 1D LUT
>> 6. 1D Curve EOTF
>> 7. 1D LUT
>>
>> The supported curves for the 1D Curve type are:
>> - sRGB EOTF and its inverse
>> - PQ EOTF, scaled to [0.0, 125.0] and its inverse
>> - BT.2020/BT.709 OETF and its inverse
> 
> So, as we talked in the 2024 Linux Display Next Hackfest, I hacked
> `drm_info` to show the KMS color pipeline properties. You can find the
> experimental-and-ugly code here:
> - https://gitlab.freedesktop.org/mwen/drm_info/-/merge_requests/1
> It depends on updating libdrm [1] and you will only see something if you
> use a custom kernel with this series applied.
> 

Thanks. That's very useful.

> After checking the output, I missed a kind of Default or "Identity"
> curve for the `CURVE_1D_TYPE` enum. I understand that if the color
> operation is set bypass, we can ignore all property values, but I didn't
> find a similar approach on plane properties, so it looks weird to me:
> 
> └───"CURVE_1D_TYPE" (atomic): enum {sRGB Inverse EOTF, BT.2020 OETF, PQ 125 
> Inverse EOTF} = invalid (0)
> 

Good catch. That's where drm_info is useful. We shouldn't be reporting
"invalid (0)" but default to any other value. I'll fix that.

While your suggestion would work for AMD I'm a bit reluctant to add an
Identity element. It doesn't add value over "BYPASS". But more importantly
we discussed that there might be some HW that doesn't support HW on
colorops. It would be better if we avoid assumptions about the availability
of identity or bypass.

> Another thing that caught my attention was the size property for 1D
> Curve Custom LUT, that I expected a similar setup to CRTC 1D LUTs:
> 
> └───"GAMMA_LUT_SIZE" (immutable): range [0, UINT32_MAX] = 4096
> 
> But I got:
> 
> ├───"SIZE" (atomic): range [4096, 4096] = 4096
> 
> Any thoughts?

We should stick with same behavior as GAMMA_LUT_SIZE. I'll change
that.

> 
> Anyway, see below an example of `drm_info` output on AMD DCN301 for a
> given Overlay/Primary plane without userspace usage of the properties:
> 
> │   └───"COLOR_PIPELINE" (atomic): enum {Bypass, Color Pipeline 265} 
> = Bypass
> │   ├───Bypass
> │   └───Color Pipeline 265
> │   ├───Color Operation 265
> │   │   ├───"TYPE" (immutable): enum {1D Curve, 1D Curve 
> Custom LUT, 3x4 Matrix, Multiplier} = 1D Curve
> │   │   ├───"BYPASS" (atomic): range [0, 1] = 1
> │   │   └───"CURVE_1D_TYPE" (atomic): enum {sRGB EOTF, 
> BT.2020 Inverse OETF, PQ 125 EOTF} = sRGB EOTF
> │   ├───Color Operation 270
> │   │   ├───"TYPE" (immutable): enum {1D Curve, 1D Curve 
> Custom LUT, 3x4 Matrix, Multiplier} = 3x4 Matrix
> │   │   ├───"BYPASS" (atomic): range [0, 1] = 1
> │   │   └───"DATA" (atomic): blob = 0
> │   ├───Color Operation 275
> │   │   ├───"TYPE" (immutable): enum {1D Curve, 1D Curve 
> Custom LUT, 3x4 Matrix, Multiplier} = Multiplier
> │   │   ├───"BYPASS" (atomic): range [0, 1] = 1
> │   │   └───"MULTIPLIER" (atomic): range [0, UINT64_MAX] = 0
> │   ├───Color Operation 280
> │   │   ├───"TYPE" (immutable): enum {1D Curve, 1D Curve 
> Custom LUT, 3x4 Matrix, Multiplier} = 1D Curve
> │   │   ├───"BYPASS" (atomic): range [0, 1] = 1
> │   │   └───"CURVE_1D_TYPE" (atomic): enum {sRGB Inverse 
> EOTF, BT.2020 OETF, PQ 125 Inverse EOTF} = invalid (0)
> │   ├───Color Operation 285
> │   │   ├───"TYPE" (immutable): enum {1D Curve, 1D Curve 
> Custom LUT, 3x4 Matrix, Multiplier} = 1D Curve Custom LUT
> │   │   ├───"BYPASS" (atomic): range [0, 1] = 1
> │   │   ├───"SIZE" (atomic): range [4096, 4096] = 4096
> │   │   └───"DATA" (atomic): blob = 0
> │   ├───Color Operation 291
> │   │   ├───"TYPE" (immutable): enum {1D Curve, 1D Curve 
> Custom LUT, 3x4 Matrix, Multiplier} = 1D Curve
> │   │   ├───"BYPASS" (atomic): range [0, 1] = 1
> │   │   └───"CURVE_1D_TYPE" (atomic): enum {sRGB EOTF, 
> BT.2020 Inverse OETF, PQ 125 EOTF} = sRGB EOTF
> │   └───Color 

[PATCH 35/36] drm/amd/display: [FW Promotion] Release 0.0.222.0

[Hamza Mahfooz]

From: Anthony Koo 

 - Add new condition for PSR exit due to ESD recovery
 - Add new VB scaling feature for ABM by interpolating between
   existing VB parameters, allowing driver to have fine grain
   scaled VB levels between 0 - 250

Acked-by: Hamza Mahfooz 
Signed-off-by: Anthony Koo 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b75653faf40e..78e8698fe378 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -208,6 +208,11 @@ union abm_flags {
 * @abm_new_frame: Indicates if a new frame update needed for 
ABM to ramp up into steady
 */
unsigned int abm_new_frame : 1;
+
+   /**
+* @vb_scaling_enabled: Indicates variBright Scaling Enable
+*/
+   unsigned int vb_scaling_enabled : 1;
} bitfields;
 
unsigned int u32All;
@@ -2796,9 +2801,9 @@ struct dmub_cmd_psr_copy_settings_data {
 */
uint8_t relock_delay_frame_cnt;
/**
-* Explicit padding to 4 byte boundary.
+* esd recovery indicate.
 */
-   uint8_t pad3;
+   uint8_t esd_recovery;
/**
 * DSC Slice height.
 */
-- 
2.45.1

[PATCH 25/36] drm/amd/display: Fix warning caused by an attempt to configure a non-otg master

[Hamza Mahfooz]

From: Rodrigo Siqueira 

When booting the system with DCN401, the driver adds the following dmesg
warning:

WARNING: CPU: 8 PID: 175 at
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:1923
resource_get_opp_heads_for_otg_master+0x13/0x70 [amdgpu]

Modules linked in: amdgpu(+) hid_generic amdxcp i2c_algo_bit
drm_ttm_helper ttm drm_exec gpu_sched drm_suballoc_helper drm_buddy
drm_display_helper drm_kms_helper usbhid hid drm i2c_piix4 ahci igc
libahci video wmi

CPU: 8 PID: 175 Comm: systemd-udevd Not tainted 6.8.0-EXTRA-PROMO-MAY-29+ #66
Hardware name: ASUS System Product Name/TUF GAMING X570-PRO (WI-FI),
BIOS 4021 08/10/2021

RIP: 0010:resource_get_opp_heads_for_otg_master+0x13/0x70 [amdgpu]
Code: 8b 66 0f 1f 44 00 00 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90
90 0f 1f 44 00 00 55 48 83 bf f8 07 00 00 00 48 89 e5 74 0c <0f> 0b 31
f6 89 f0 5d e9 0c 65 01 e5 48 83 bf e0 07 00 00 00 75 ea

RSP: 0018:a5f000816ed8 EFLAGS: 00010246
[...]
PKRU: 5554
Call Trace:
 
 ? show_regs+0x65/0x70
 ? __warn+0x85/0x160
 ? resource_get_opp_heads_for_otg_master+0x13/0x70 [amdgpu]
 ? report_bug+0x192/0x1c0
 ? handle_bug+0x44/0x90
 ? exc_invalid_op+0x18/0x70
[...]

This warning is triggered by a check in the function
resource_get_opp_heads_for_otg_master that validates if the request
operation is in a master OTG pipe; if not, the warning above is
displayed. In other words, another part of the code might be calling
this function in a non-OTG master pipe context, resulting in the log
message.

The reason the ASSERT was triggered is that the current state wasn't
updated after applying the context to the hardware. This means that the
update_dsc_for_odm_change might be called from a non-OTG-MASTER. To
prevent this, it's crucial to check if the current reference is pointing
to an OTG master before operate in the old OTG master reference. If it's
not, the function must set the old OTG reference to NULL and avoid
calling resource_get_opp_heads_for_otg_master before the context is
updated.

Reviewed-by: Wenjing Liu 
Acked-by: Hamza Mahfooz 
Co-developed-by: Wenjing Liu 
Signed-off-by: Wenjing Liu 
Signed-off-by: Rodrigo Siqueira 
---
 .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 24 ++-
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 0fafbec442b1..cb8e417fb032 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1561,16 +1561,28 @@ static void update_dsc_for_odm_change(struct dc *dc, 
struct dc_state *context,
struct pipe_ctx *new_pipe;
struct pipe_ctx *old_opp_heads[MAX_PIPES];
struct dccg *dccg = dc->res_pool->dccg;
-   struct pipe_ctx *old_otg_master =
-   
>current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];
-   int old_opp_head_count = resource_get_opp_heads_for_otg_master(
-   old_otg_master, >current_state->res_ctx,
-   old_opp_heads);
+   struct pipe_ctx *old_otg_master;
+   int old_opp_head_count = 0;
+
+   old_otg_master = 
>current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];
+
+   if (resource_is_pipe_type(old_otg_master, OTG_MASTER)) {
+   old_opp_head_count = 
resource_get_opp_heads_for_otg_master(old_otg_master,
+  
>current_state->res_ctx,
+  
old_opp_heads);
+   } else {
+   // DC cannot assume that the current state and the new state
+   // share the same OTG pipe since this is not true when called
+   // in the context of a commit stream not checked. Hence, set
+   // old_otg_master to NULL to skip the DSC configuration.
+   old_otg_master = NULL;
+   }
+
 
if (otg_master->stream_res.dsc)
dcn32_update_dsc_on_stream(otg_master,
otg_master->stream->timing.flags.DSC);
-   if (old_otg_master->stream_res.dsc) {
+   if (old_otg_master && old_otg_master->stream_res.dsc) {
for (i = 0; i < old_opp_head_count; i++) {
old_pipe = old_opp_heads[i];
new_pipe = 
>res_ctx.pipe_ctx[old_pipe->pipe_idx];
-- 
2.45.1

[PATCH 29/36] drm/amd/display: Remove unused value set from 'min_hratio_fact' in dml

[Hamza Mahfooz]

From: Ivan Lipski 

These portions of code are flagged as 'UNUSED_VALUE' by the
Coverity analysis since the assigned values of these vars
are never used in the code.

Reviewed-by: Alex Hung 
Reviewed-by: Aurabindo Pillai 
Acked-by: Hamza Mahfooz 
Signed-off-by: Ivan Lipski 
---
 .../drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c| 5 -
 .../drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c  | 5 -
 .../drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c| 5 -
 .../drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c| 5 -
 .../drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c| 5 -
 .../drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c  | 5 -
 .../gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c| 5 -
 7 files changed, 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
index 548cdef8a8ad..07146569e335 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
@@ -1156,11 +1156,6 @@ static void dml20_rq_dlg_get_dlg_params(struct 
display_mode_lib *mode_lib,
swath_width_pixels_ub_c = swath_width_ub_c * 1;
}
 
-   hscale_pixel_rate_l = 0.;
-   hscale_pixel_rate_c = 0.;
-   min_hratio_fact_l = 1.0;
-   min_hratio_fact_c = 1.0;
-
if (htaps_l <= 1)
min_hratio_fact_l = 2.0;
else if (htaps_l <= 6) {
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
index 0fc9f3e3ffae..f4bba1f2aeb6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
@@ -1157,11 +1157,6 @@ static void dml20v2_rq_dlg_get_dlg_params(struct 
display_mode_lib *mode_lib,
swath_width_pixels_ub_c = swath_width_ub_c * 1;
}
 
-   hscale_pixel_rate_l = 0.;
-   hscale_pixel_rate_c = 0.;
-   min_hratio_fact_l = 1.0;
-   min_hratio_fact_c = 1.0;
-
if (htaps_l <= 1)
min_hratio_fact_l = 2.0;
else if (htaps_l <= 6) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
index 708e1632170d..c229a9edf82a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
@@ -1205,11 +1205,6 @@ static void dml_rq_dlg_get_dlg_params(
swath_width_pixels_ub_c = swath_width_ub_c * 1;
}
 
-   hscale_pixel_rate_l = 0.;
-   hscale_pixel_rate_c = 0.;
-   min_hratio_fact_l = 1.0;
-   min_hratio_fact_c = 1.0;
-
if (hratio_l <= 1)
min_hratio_fact_l = 2.0;
else if (htaps_l <= 6) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
index 0497a5d74a62..f3ee7baac786 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
@@ -1309,11 +1309,6 @@ static void dml_rq_dlg_get_dlg_params(struct 
display_mode_lib *mode_lib,
swath_width_pixels_ub_c = swath_width_ub_c * 1;
}
 
-   hscale_pixel_rate_l = 0.;
-   hscale_pixel_rate_c = 0.;
-   min_hratio_fact_l = 1.0;
-   min_hratio_fact_c = 1.0;
-
if (hratio_l <= 1)
min_hratio_fact_l = 2.0;
else if (htaps_l <= 6) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
index 4113ce79c4af..b6d954d9aa00 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
@@ -1150,11 +1150,6 @@ static void dml_rq_dlg_get_dlg_params(
swath_width_pixels_ub_c = swath_width_ub_c * 1;
}
 
-   hscale_pixel_rate_l = 0.;
-   hscale_pixel_rate_c = 0.;
-   min_hratio_fact_l = 1.0;
-   min_hratio_fact_c = 1.0;
-
if (hratio_l <= 1)
min_hratio_fact_l = 2.0;
else if (htaps_l <= 6) {
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
index b3e8dc08030c..94975b0fa398 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
@@ -1238,11 +1238,6 @@ static void dml_rq_dlg_get_dlg_params(
swath_width_pixels_ub_c = swath_width_ub_c * 1;
}
 
-   hscale_pixel_rate_l = 0.;
-   

[PATCH 33/36] drm/amd/display: Check UnboundedRequestEnabled's value

[Hamza Mahfooz]

From: Alex Hung 

CalculateSwathAndDETConfiguration_params_st's UnboundedRequestEnabled
is a pointer (i.e. dml_bool_t *UnboundedRequestEnabled), and thus
if (p->UnboundedRequestEnabled) checks its address, not bool value.

This fixes 1 REVERSE_INULL issue reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c 
b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
index 791f1725b62b..547dfcc80fde 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
@@ -4283,7 +4283,7 @@ static void CalculateSwathAndDETConfiguration(struct 
display_mode_lib_scratch_st
}
 
*p->compbuf_reserved_space_64b = 2 * p->PixelChunkSizeInKByte * 1024 / 
64;
-   if (p->UnboundedRequestEnabled) {
+   if (*p->UnboundedRequestEnabled) {
*p->compbuf_reserved_space_64b = 
dml_max(*p->compbuf_reserved_space_64b,
(dml_float_t)(p->ROBBufferSizeInKByte * 1024/64)
- 
(dml_float_t)(RoundedUpSwathSizeBytesY[SurfaceDoingUnboundedRequest] * 
TTUFIFODEPTH / MAXIMUMCOMPRESSION/64));
-- 
2.45.1

[PATCH 27/36] drm/amd/display: Remove redundant checks for res_pool->dccg

[Hamza Mahfooz]

From: Alex Hung 

The null checks for res_pool->dccg are redundant as it was already
dereferenced previously, as reported by Coverity; therefore the
null checks are removed.

This fixes 6 REVERSE_INULL issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 2 +-
 drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
index 86d871cc74c7..f96adc689055 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
@@ -240,7 +240,7 @@ void dcn201_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-   if (res_pool->dccg && res_pool->hubbub) {
+   if (res_pool->hubbub) {

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

_pool->ref_clocks.dccg_ref_clock_inKhz);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 9ef38a3759b1..567300c3acaa 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -656,7 +656,7 @@ void dcn30_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-   if (res_pool->dccg && res_pool->hubbub) {
+   if (res_pool->hubbub) {
 

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 1c8abb417b6e..746c522adf84 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -132,7 +132,7 @@ void dcn31_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-   if (res_pool->dccg && res_pool->hubbub) {
+   if (res_pool->hubbub) {
 

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 33b8df995869..a597b2342472 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -806,7 +806,7 @@ void dcn32_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-   if (res_pool->dccg && res_pool->hubbub) {
+   if (res_pool->hubbub) {

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

_pool->ref_clocks.dccg_ref_clock_inKhz);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index d894c52bfdaf..a1e1f76bfde7 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -188,7 +188,7 @@ void dcn35_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-   if (res_pool->dccg && res_pool->hubbub) {
+   if (res_pool->hubbub) {
 

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index cb8e417fb032..6ba2e1cd20c7 100644
--- 

[PATCH 34/36] drm/amd/display: Remove redundant null checks

[Hamza Mahfooz]

From: Alex Hung 

The null checks for aconnector and aconnector->dc_link and
stream redundant as they were already dereferenced previously
as reported by Coverity; therefore the null checks are removed.

This fixes 4 REVERSE_INULL issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 ---
 3 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 48a9243ada7d..1fd851b93d40 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3180,7 +3180,7 @@ static int dm_resume(void *handle)
 * this is the case when traversing through already created end 
sink
 * MST connectors, should be skipped
 */
-   if (aconnector && aconnector->mst_root)
+   if (aconnector->mst_root)
continue;
 
mutex_lock(>hpd_lock);
@@ -6422,13 +6422,13 @@ static void apply_dsc_policy_for_stream(struct 
amdgpu_dm_connector *aconnector,
dc_dsc_policy_set_enable_dsc_when_not_needed(
aconnector->dsc_settings.dsc_force_enable == 
DSC_CLK_FORCE_ENABLE);
 
-   if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
+   if (sink->sink_signal == SIGNAL_TYPE_EDP &&
!aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
dc->caps.edp_dsc_support && 
aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
 
apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, 
max_dsc_target_bpp_limit_override);
 
-   } else if (aconnector->dc_link && sink->sink_signal == 
SIGNAL_TYPE_DISPLAY_PORT) {
+   } else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
if 
(dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
dsc_caps,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 7cfa240a3cea..717d97191dda 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1420,7 +1420,7 @@ static ssize_t trigger_hotplug(struct file *f, const char 
__user *buf,
uint8_t param_nums = 0;
bool ret = false;
 
-   if (!aconnector || !aconnector->dc_link)
+   if (!aconnector->dc_link)
return -EINVAL;
 
if (size == 0)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 8eb2f10f2c38..659dd67be1ba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -807,9 +807,6 @@ bool dm_helpers_dp_write_dsc_enable(
uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
uint8_t ret = 0;
 
-   if (!stream)
-   return false;
-
if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
if (!aconnector->dsc_aux)
return false;
-- 
2.45.1

[PATCH 36/36] drm/amd/display: 3.2.289

[Hamza Mahfooz]

From: Aric Cyr 

This version brings along the following:

- DCN401 fixes
- DPIA fixes
- DML21 fixes
- Misc Coverity fixes

Acked-by: Hamza Mahfooz 
Signed-off-by: Aric Cyr 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index fa4e6b09409e..d0d1af451b64 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -55,7 +55,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.288"
+#define DC_VER "3.2.289"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.45.1

[PATCH 30/36] drm/amd/display: Remove redundant null checks

[Hamza Mahfooz]

From: Alex Hung 

The null checks are redundant as they were already dereferenced
previously, as reported by Coverity; therefore the null checks
are removed.

This fixes 7 REVERSE_INULL issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  4 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  2 +-
 .../dc/dml2/dml21/dml21_translation_helper.c  |  4 +-
 .../amd/display/dc/hwss/dce110/dce110_hwseq.c |  8 +-
 .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c   | 81 +--
 6 files changed, 47 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index ee4b02c8c807..06f0c41ad6f1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -553,7 +553,7 @@ static void dcn32_auto_dpm_test_log(
//
//  AutoDPMTest: clk1:%d - clk2:%d - 
clk3:%d - clk4:%d\n"


-   if (new_clocks && active_pipe_count > 0 &&
+   if (active_pipe_count > 0 &&
new_clocks->dramclk_khz > 0 &&
new_clocks->fclk_khz > 0 &&
new_clocks->dcfclk_khz > 0 &&
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index fce1c3e03094..a4ba6f99cd34 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2640,7 +2640,7 @@ static enum surface_update_type det_surface_update(const 
struct dc *dc,
 
if (u->plane_info)
format = u->plane_info->format;
-   else if (u->surface)
+   else
format = u->surface->format;
 
if (dce_use_lut(format))
@@ -2741,7 +2741,7 @@ static enum surface_update_type 
check_update_surfaces_for_stream(
if (stream_update->mst_bw_update)
su_flags->bits.mst_bw = 1;
 
-   if (stream_update->stream && 
stream_update->stream->freesync_on_desktop &&
+   if (stream_update->stream->freesync_on_desktop &&
(stream_update->vrr_infopacket || 
stream_update->allow_freesync ||
stream_update->vrr_active_variable || 
stream_update->vrr_active_fixed))
su_flags->bits.fams_changed = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 1cba8f58f1e6..eb053e1791c0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2099,7 +2099,7 @@ int resource_get_odm_slice_dst_width(struct pipe_ctx 
*otg_master,
timing->h_border_right;
width = h_active / count;
 
-   if (otg_master->stream_res.tg && otg_master->stream)
+   if (otg_master->stream_res.tg)
two_pixel_alignment_required =

otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) ||
/*
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
index a7d02da16bb5..d5ead0205053 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
@@ -102,9 +102,7 @@ void dml21_apply_soc_bb_overrides(struct 
dml2_initialize_instance_in_out *dml_in
struct dml2_soc_state_table *dml_clk_table = _soc_bb->clk_table;
 
/* override clocks if smu is present */
-   if (in_dc->clk_mgr &&
-   in_dc->clk_mgr->funcs->is_smu_present &&
-   in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr)) {
+   if (in_dc->clk_mgr->funcs->is_smu_present && 
in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr)) {
/* dcfclk */
if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
dml_clk_table->dcfclk.num_clk_values = 
dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 871f1e1ca2e0..307af11b4bb6 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -742,12 +742,10 @@ void dce110_edp_wait_for_hpd_ready(
return;
}
 
-   if (link != NULL) {
-   if (link->panel_config.pps.extra_t3_ms > 0) {
-   int extra_t3_in_ms 

[PATCH 32/36] drm/amd/display: Remove redundant checks for context

[Hamza Mahfooz]

From: Alex Hung 

The null checks for context are redundant as it was already
dereferenced previously, as reported by Coverity; therefore
the null checks are removed.

This fixes 2 REVERSE_INULL issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c| 5 +
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 33318a112282..5037474bf95c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -505,7 +505,7 @@ void set_p_state_switch_method(
struct vba_vars_st *vba = >bw_ctx.dml.vba;
bool enable_subvp;
 
-   if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba || !context)
+   if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)
return;
 
if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] !=
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index 17ea15682d3a..19b61290ef9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -573,10 +573,7 @@ static bool dml2_validate_and_build_resource(const struct 
dc *in_dc, struct dc_s
bool need_recalculation = false;
uint32_t cstate_enter_plus_exit_z8_ns;
 
-   if (!context)
-   return true;
-
-   else if (context->stream_count == 0) {
+   if (context->stream_count == 0) {
unsigned int lowest_state_idx = 0;
 
out_clks.p_state_supported = true;
-- 
2.45.1

[PATCH 21/36] drm/amd/display: Make sure to reprogram ODM when resync fifo

[Hamza Mahfooz]

From: Alvin Lee 

Need to reconfigure ODM when resyncing FIFO because on OTG disable we
clear all ODM programming

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alvin Lee 
---
 .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 19 ++-
 .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c   | 19 ++-
 2 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index 8e68e05e3b72..388404cdeeaa 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -379,8 +379,25 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, 
struct dc *dc, struct dc
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = >current_state->res_ctx.pipe_ctx[i];
 
-   if (otg_disabled[i])
+   if (otg_disabled[i]) {
+   int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst 
};
+   int opp_cnt = 1;
+   int last_odm_slice_width = 
resource_get_odm_slice_dst_width(pipe, true);
+   int odm_slice_width = 
resource_get_odm_slice_dst_width(pipe, false);
+   struct pipe_ctx *odm_pipe;
+
+   for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe 
= odm_pipe->next_odm_pipe) {
+   opp_inst[opp_cnt] = 
odm_pipe->stream_res.opp->inst;
+   opp_cnt++;
+   }
+   if (opp_cnt > 1)
+   pipe->stream_res.tg->funcs->set_odm_combine(
+   pipe->stream_res.tg,
+   opp_inst, opp_cnt,
+   odm_slice_width,
+   last_odm_slice_width);

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
+   }
}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 732da5e5c1ba..33b8df995869 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1237,8 +1237,25 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, 
struct dc *dc, struct dc_
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = >current_state->res_ctx.pipe_ctx[i];
 
-   if (otg_disabled[i])
+   if (otg_disabled[i]) {
+   int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst 
};
+   int opp_cnt = 1;
+   int last_odm_slice_width = 
resource_get_odm_slice_dst_width(pipe, true);
+   int odm_slice_width = 
resource_get_odm_slice_dst_width(pipe, false);
+   struct pipe_ctx *odm_pipe;
+
+   for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe 
= odm_pipe->next_odm_pipe) {
+   opp_inst[opp_cnt] = 
odm_pipe->stream_res.opp->inst;
+   opp_cnt++;
+   }
+   if (opp_cnt > 1)
+   pipe->stream_res.tg->funcs->set_odm_combine(
+   pipe->stream_res.tg,
+   opp_inst, opp_cnt,
+   odm_slice_width,
+   last_odm_slice_width);

pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
+   }
}
 }
 
-- 
2.45.1

[PATCH 22/36] drm/amd/display: Check dc_stream_state before it is used

[Hamza Mahfooz]

From: Alex Hung 

dc_state_get_stream_status dc_state_get_paired_subvp_stream and other
functions can return null, and therefore null must be checked before
status can be used.

This fixes 21 NULL_RETURNS issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 17 +
 .../gpu/drm/amd/display/dc/core/dc_state.c| 24 ---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  | 20 ++--
 .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c  |  8 +++
 .../amd/display/dc/dml2/dml21/dml21_utils.c   | 12 +-
 .../display/dc/dml2/dml2_dc_resource_mgmt.c   |  6 +++--
 .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c   |  9 ---
 .../dc/resource/dcn32/dcn32_resource.c|  2 ++
 8 files changed, 74 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 25a498f65c1c..fce1c3e03094 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1233,11 +1233,14 @@ static void disable_dangling_plane(struct dc *dc, 
struct dc_state *context)
 */
if (is_phantom) {
if (tg->funcs->enable_crtc) {
-   int main_pipe_width, main_pipe_height;
+   int main_pipe_width = 0, 
main_pipe_height = 0;
struct dc_stream_state 
*old_paired_stream = dc_state_get_paired_subvp_stream(dc->current_state, 
old_stream);
 
-   main_pipe_width = 
old_paired_stream->dst.width;
-   main_pipe_height = 
old_paired_stream->dst.height;
+   if (old_paired_stream) {
+   main_pipe_width = 
old_paired_stream->dst.width;
+   main_pipe_height = 
old_paired_stream->dst.height;
+   }
+
if (dc->hwss.blank_phantom)
dc->hwss.blank_phantom(dc, tg, 
main_pipe_width, main_pipe_height);
tg->funcs->enable_crtc(tg);
@@ -1628,6 +1631,9 @@ static void program_timing_sync(
for (k = 0; k < group_size; k++) {
struct dc_stream_status *status = 
dc_state_get_stream_status(ctx, pipe_set[k]->stream);
 
+   if (!status)
+   continue;
+
status->timing_sync_info.group_id = num_group;
status->timing_sync_info.group_size = group_size;
if (k == 0)
@@ -2225,6 +2231,9 @@ enum dc_status dc_commit_streams(struct dc *dc, struct 
dc_commit_streams_params
if (dc_is_embedded_signal(params->streams[i]->signal)) {
struct dc_stream_status *status = 
dc_state_get_stream_status(context, params->streams[i]);
 
+   if (!status)
+   continue;
+
if (dc->hwss.is_abm_supported)
status->is_abm_supported = 
dc->hwss.is_abm_supported(dc, context, params->streams[i]);
else
@@ -4023,7 +4032,7 @@ static void commit_planes_for_stream(struct dc *dc,
stream_status =
stream_get_status(context, pipe_ctx->stream);
 
-   if (dc->hwss.apply_ctx_for_surface)
+   if (dc->hwss.apply_ctx_for_surface && stream_status)
dc->hwss.apply_ctx_for_surface(
dc, pipe_ctx->stream, 
stream_status->plane_count, context);
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index c75dcdc20428..e990346e51f6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -794,11 +794,16 @@ enum dc_status dc_state_add_phantom_stream(const struct 
dc *dc,
 
/* setup subvp meta */
main_stream_status = dc_state_get_stream_status(state, main_stream);
+   if (main_stream_status) {
+   main_stream_status->mall_stream_config.type = SUBVP_MAIN;
+   main_stream_status->mall_stream_config.paired_stream = 
phantom_stream;
+   }
+
phantom_stream_status = dc_state_get_stream_status(state, 
phantom_stream);
-   phantom_stream_status->mall_stream_config.type = SUBVP_PHANTOM;
-   phantom_stream_status->mall_stream_config.paired_stream = main_stream;
-   main_stream_status->mall_stream_config.type = SUBVP_MAIN;
-   

[PATCH 31/36] drm/amd/display: Remove redundant checks for opp

[Hamza Mahfooz]

From: Alex Hung 

The null checks for opp are redundant as they were already
dereferenced previously, as reported by Coverity; therefore
the null checks are removed.

This fixes 2 REVERSE_INULL issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 85f014cae6be..841b6423952c 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1260,7 +1260,7 @@ void dcn10_plane_atomic_disconnect(struct dc *dc,
mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
// Phantom pipes have OTG disabled by default, so MPCC_STATUS will 
never assert idle,
// so don't wait for MPCC_IDLE in the programming sequence
-   if (opp != NULL && dc_state_get_pipe_subvp_type(state, pipe_ctx) != 
SUBVP_PHANTOM)
+   if (dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM)
opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = 
true;
 
dc->optimized_required = true;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
index f96adc689055..1635e5a552ad 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
@@ -408,8 +408,7 @@ void dcn201_plane_atomic_disconnect(struct dc *dc,
if (mpcc_removed == false)
return;
 
-   if (opp != NULL)
-   opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = 
true;
+   opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 
dc->optimized_required = true;
 
-- 
2.45.1

[PATCH 20/36] drm/amd/display: Remove duplicate HWSS interfaces

[Hamza Mahfooz]

From: Joshua Aberback 

[Why]
Some interface functions are defined in both the public and private HWSS
interfaces, which can lead to confusion and runtime issues, therefore
the duplicates should be eliminated.

[How]
 - power_down should only be private, because it's only used within HWSS
 - update_plane_addr should only be public, as it's used outside HWSS

Reviewed-by: Aric Cyr 
Acked-by: Hamza Mahfooz 
Signed-off-by: Joshua Aberback 
---
 .../gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c  |  1 -
 .../gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c| 10 +-
 drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c |  2 --
 .../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c|  2 +-
 drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c |  1 -
 .../gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c   |  1 -
 drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c |  2 --
 .../gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c|  8 
 drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c |  1 -
 .../gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c   |  1 -
 drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c |  2 --
 .../gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c   |  2 --
 .../gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c|  8 
 drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c |  1 -
 .../gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c|  8 
 drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c |  2 --
 .../gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c   |  2 --
 .../gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c  |  8 
 .../gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c   |  2 --
 drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h |  1 -
 .../gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h |  2 --
 21 files changed, 22 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index f489371a3bc6..871f1e1ca2e0 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -3262,7 +3262,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 
 static const struct hwseq_private_funcs dce110_private_funcs = {
.init_pipes = init_pipes,
-   .update_plane_addr = update_plane_addr,
.set_input_transfer_func = dce110_set_input_transfer_func,
.set_output_transfer_func = dce110_set_output_transfer_func,
.power_down = dce110_power_down,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 0bfab66b8038..85f014cae6be 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1712,10 +1712,10 @@ void dcn10_power_down_on_boot(struct dc *dc)
if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&

edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
dc->hwseq->funcs.edp_backlight_control &&
-   dc->hwss.power_down &&
+   dc->hwseq->funcs.power_down &&
dc->hwss.edp_power_control) {
dc->hwseq->funcs.edp_backlight_control(edp_link, false);
-   dc->hwss.power_down(dc);
+   dc->hwseq->funcs.power_down(dc);
dc->hwss.edp_power_control(edp_link, false);
} else {
for (i = 0; i < dc->link_count; i++) {
@@ -1723,8 +1723,8 @@ void dcn10_power_down_on_boot(struct dc *dc)
 
if (link->link_enc && 
link->link_enc->funcs->is_dig_enabled &&

link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
-   dc->hwss.power_down) {
-   dc->hwss.power_down(dc);
+   dc->hwseq->funcs.power_down) {
+   dc->hwseq->funcs.power_down(dc);
break;
}
 
@@ -2929,7 +2929,7 @@ static void dcn10_update_dchubp_dpp(
 
hubp->power_gated = false;
 
-   hws->funcs.update_plane_addr(dc, pipe_ctx);
+   dc->hwss.update_plane_addr(dc, pipe_ctx);
 
if (is_pipe_tree_visible(pipe_ctx))
hubp->funcs->set_blank(hubp, false);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
index a5bdac79a744..5e51e1761707 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
@@ -78,7 +78,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.get_clock = dcn10_get_clock,
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
.calc_vupdate_position = 

[PATCH 05/36] drm/amd/display: Remove redundant condition with DEADCODE

[Hamza Mahfooz]

From: Ivan Lipski 

[WHY]
Coverity analysis flagged this condition as DEADCODE since the
variable 'req128_c' is always false, thus the condition is never
true.

[HOW]
Remove the condition.

Reviewed-by: Aurabindo Pillai 
Acked-by: Hamza Mahfooz 
Signed-off-by: Ivan Lipski 
---
 .../gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c  | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
index 618f4b682ab1..708e1632170d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
@@ -297,9 +297,6 @@ static void handle_det_buf_split(
 
if (swath_height_c > 0)
log2_swath_height_c = dml_log2(swath_height_c);
-
-   if (req128_c && log2_swath_height_c > 0)
-   log2_swath_height_c -= 1;
}
 
rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
-- 
2.45.1

[PATCH 17/36] drm/amd/display: Add null checker before access structs

[Hamza Mahfooz]

From: Alex Hung 

Checks null pointer before accessing various structs.

This fixes 5 NULL_RETURNS issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c  | 2 ++
 .../display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 5 +
 .../gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c   | 2 +-
 .../gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c | 4 +++-
 4 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
index 4166332b5b89..b97d9abfdbc6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
@@ -360,6 +360,8 @@ static struct dc_plane_state 
*dml21_add_phantom_plane(struct dml2_context *dml_c
struct dc_plane_state *phantom_plane;
 
phantom_plane = 
dml_ctx->config.svp_pstate.callbacks.create_phantom_plane(dc, context, 
main_plane);
+   if (!phantom_plane)
+   return NULL;
 
phantom_plane->format = main_plane->format;
phantom_plane->rotation = main_plane->rotation;
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
index 7272a04b9d1d..00fedc00a735 100644
--- 
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+++ 
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
@@ -1082,12 +1082,17 @@ static bool is_timing_group_schedulable(
 
/* init allow start and end lines for timing group */
stream_method_fams2_meta = get_per_method_common_meta(pmo, 
per_stream_pstate_strategy[base_stream_idx], base_stream_idx);
+   if (!stream_method_fams2_meta)
+   return false;
+
group_fams2_meta->allow_start_otg_vline = 
stream_method_fams2_meta->allow_start_otg_vline;
group_fams2_meta->allow_end_otg_vline = 
stream_method_fams2_meta->allow_end_otg_vline;
group_fams2_meta->period_us = stream_method_fams2_meta->period_us;
for (i = base_stream_idx + 1; i < 
display_cfg->display_config.num_streams; i++) {
if 
(is_bit_set_in_bitfield(pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx],
 i)) {
stream_method_fams2_meta = 
get_per_method_common_meta(pmo, per_stream_pstate_strategy[i], i);
+   if (!stream_method_fams2_meta)
+   continue;
 
if (group_fams2_meta->allow_start_otg_vline < 
stream_method_fams2_meta->allow_start_otg_vline) {
/* set group allow start to larger otg vline */
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index f93853d434d2..e783afbbb397 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -2628,7 +2628,7 @@ static bool dcn20_resource_construct(
ranges.writer_wm_sets[0].max_drain_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 
/* Notify PP Lib/SMU which Watermarks to use for which clock 
ranges */
-   if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
+   if (pool->base.pp_smu && 
pool->base.pp_smu->nv_funcs.set_wm_ranges)

pool->base.pp_smu->nv_funcs.set_wm_ranges(>base.pp_smu->nv_funcs.pp_smu, 
);
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c 
b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
index 070a4efb308b..131d98025bd4 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
@@ -795,11 +795,13 @@ static struct link_encoder *dcn201_link_encoder_create(
 {
struct dcn20_link_encoder *enc20 =
kzalloc(sizeof(struct dcn20_link_encoder), GFP_ATOMIC);
-   struct dcn10_link_encoder *enc10 = >enc10;
+   struct dcn10_link_encoder *enc10;
 
if (!enc20)
return NULL;
 
+   enc10 = >enc10;
+
dcn201_link_encoder_construct(enc20,
enc_init_data,
_enc_feature,
-- 
2.45.1

[PATCH 24/36] drm/amd/display: Covert integers to double before divisions

[Hamza Mahfooz]

From: Alex Hung 

Integer divisions result in loss of fractional and accuracy is lost
when assigned or compared with double. It is necessary to perform
double/integer instead or explicitly cast them to double.

This fixes 54 UNINTENDED_INTEGER_DIVISION issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 .../drm/amd/display/dc/dml/calcs/dcn_calcs.c  |  2 +-
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 20 ++---
 .../dc/dml/dcn20/display_mode_vba_20.c| 16 +--
 .../dc/dml/dcn20/display_mode_vba_20v2.c  |  4 +--
 .../dc/dml/dcn21/display_mode_vba_21.c|  2 +-
 .../dc/dml/dcn30/display_mode_vba_30.c|  2 +-
 .../dc/dml/dcn31/display_mode_vba_31.c|  4 +--
 .../dc/dml/dcn314/display_mode_vba_314.c  |  2 +-
 .../dc/dml/dcn32/display_mode_vba_util_32.c   |  8 +++---
 .../amd/display/dc/dml2/display_mode_core.c   | 10 +++
 .../src/dml2_core/dml2_core_dcn4_calcs.c  | 28 +--
 .../dml21/src/dml2_core/dml2_core_shared.c| 24 
 12 files changed, 61 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
index f1cde1e4265f..39525721c976 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
@@ -690,7 +690,7 @@ static void hack_disable_optional_pipe_split(struct 
dcn_bw_internal_vars *v)
 static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
unsigned int pixel_rate_100hz)
 {
-   float pixel_rate_mhz = pixel_rate_100hz / 1;
+   float pixel_rate_mhz = pixel_rate_100hz / 1.0;
 
/*
 * force enabling pipe split by lower dpp clock for DPM0 to just
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 74da9ebda016..54dd7e164635 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1882,10 +1882,10 @@ void dcn20_update_bounding_box(struct dc *dc,
bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk 
< min_dcfclk) ?
min_dcfclk : min_fclk_required_by_uclk;
 
-   bb->clock_limits[i].socclk_mhz = 
(bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
+   bb->clock_limits[i].socclk_mhz = 
(bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000.0) ?
max_clocks->socClockInKhz / 1000 : 
bb->clock_limits[i].fabricclk_mhz;
 
-   bb->clock_limits[i].dcfclk_mhz = 
(bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
+   bb->clock_limits[i].dcfclk_mhz = 
(bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000.0) ?
max_clocks->dcfClockInKhz / 1000 : 
bb->clock_limits[i].fabricclk_mhz;
 
bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz 
/ 1000;
@@ -1917,35 +1917,35 @@ void dcn20_cap_soc_clocks(struct 
_vcs_dpi_soc_bounding_box_st *bb,
 
// First pass - cap all clocks higher than the reported max
for (i = 0; i < bb->num_states; i++) {
-   if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz 
/ 1000))
+   if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz 
/ 1000.0))
&& max_clocks.dcfClockInKhz != 0)
bb->clock_limits[i].dcfclk_mhz = 
(max_clocks.dcfClockInKhz / 1000);
 
-   if ((bb->clock_limits[i].dram_speed_mts > 
(max_clocks.uClockInKhz / 1000) * 16)
+   if ((bb->clock_limits[i].dram_speed_mts > 
(max_clocks.uClockInKhz / 1000.0) * 16)
&& max_clocks.uClockInKhz != 0)
bb->clock_limits[i].dram_speed_mts = 
(max_clocks.uClockInKhz / 1000) * 16;
 
-   if ((bb->clock_limits[i].fabricclk_mhz > 
(max_clocks.fabricClockInKhz / 1000))
+   if ((bb->clock_limits[i].fabricclk_mhz > 
(max_clocks.fabricClockInKhz / 1000.0))
&& max_clocks.fabricClockInKhz 
!= 0)
bb->clock_limits[i].fabricclk_mhz = 
(max_clocks.fabricClockInKhz / 1000);
 
-   if ((bb->clock_limits[i].dispclk_mhz > 
(max_clocks.displayClockInKhz / 1000))
+   if ((bb->clock_limits[i].dispclk_mhz > 
(max_clocks.displayClockInKhz / 1000.0))
&& max_clocks.displayClockInKhz 
!= 0)
bb->clock_limits[i].dispclk_mhz = 
(max_clocks.displayClockInKhz / 1000);
 
-   if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz 
/ 1000))
+   if ((bb->clock_limits[i].dppclk_mhz > 

[PATCH 28/36] drm/amd/display: Remove redundant checks for ctx->dc_bios

[Hamza Mahfooz]

From: Alex Hung 

The null checks for ctx->dc_bios are redundant as it was already
dereferenced previously, as reported by Coverity; therefore the
null checks are removed.

This fixes 7 REVERSE_INULL issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c  | 2 +-
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 2 +-
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 2 +-
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 2 +-
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c   | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index a650a9877097..e18097f82091 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -772,7 +772,7 @@ void rn_clk_mgr_construct(
status = 
pp_smu->rn_funcs.get_dpm_clock_table(_smu->rn_funcs.pp_smu, _table);
 
if (status == PP_SMU_RESULT_OK &&
-   ctx->dc_bios && ctx->dc_bios->integrated_info) {
+   ctx->dc_bios->integrated_info) {
rn_clk_mgr_helper_populate_bw_params 
(clk_mgr->base.bw_params, _table, ctx->dc_bios->integrated_info);
/* treat memory config as single channel if memory is 
asymmetrics. */
if (ctx->dc->config.is_asymmetric_memory)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
index 148a0e4cdea2..9e2ef0e724fc 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -731,7 +731,7 @@ void vg_clk_mgr_construct(
clk_mgr->base.base.bw_params = _bw_params;
 
vg_get_dpm_table_from_smu(_mgr->base, _dpm_clks);
-   if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
+   if (ctx->dc_bios->integrated_info) {
vg_clk_mgr_helper_populate_bw_params(
_mgr->base,
ctx->dc_bios->integrated_info,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 12a7752758b8..e93df3d6222e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -785,7 +785,7 @@ void dcn31_clk_mgr_construct(
   i, 
smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
   i, 
smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
}
-   if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
+   if (ctx->dc_bios->integrated_info) {
dcn31_clk_mgr_helper_populate_bw_params(
_mgr->base,
ctx->dc_bios->integrated_info,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
index a84f1e376dee..29eff386505a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -896,7 +896,7 @@ void dcn314_clk_mgr_construct(
   i, 
smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
}
 
-   if (ctx->dc_bios && ctx->dc_bios->integrated_info && 
ctx->dc->config.use_default_clock_table == false) {
+   if (ctx->dc_bios->integrated_info && 
ctx->dc->config.use_default_clock_table == false) {
dcn314_clk_mgr_helper_populate_bw_params(
_mgr->base,
ctx->dc_bios->integrated_info,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index 5506cf9b3672..a0fb4481d2f1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -712,7 +712,7 @@ void dcn315_clk_mgr_construct(
   i, 
smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
}
 
-   if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
+   if (ctx->dc_bios->integrated_info) {
dcn315_clk_mgr_helper_populate_bw_params(

[PATCH 23/36] drm/amd/display: Check pipe_ctx before it is used

[Hamza Mahfooz]

From: Alex Hung 

resource_get_odm_slice_count and resource_get_otg_master_for_stream can
return null, and their returns must be checked before used.

This fixes 4 NULL_RETURNS issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 7 ++-
 drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c   | 3 +++
 drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c| 3 ++-
 .../gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c| 3 +++
 4 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 76b849bdd914..87e84b0a3d48 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -3127,9 +3127,14 @@ bool resource_update_pipes_for_stream_with_slice_count(
int i;
struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(
_ctx->res_ctx, stream);
-   int cur_slice_count = resource_get_odm_slice_count(otg_master);
+   int cur_slice_count;
bool result = true;
 
+   if (!otg_master)
+   return false;
+
+   cur_slice_count = resource_get_odm_slice_count(otg_master);
+
if (new_slice_count == cur_slice_count)
return result;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index a63b5dcba3f5..7abf8b88ca91 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1177,6 +1177,9 @@ static void init_pipe_slice_table_from_context(
stream = context->streams[i];
otg_master = resource_get_otg_master_for_stream(
>res_ctx, stream);
+   if (!otg_master)
+   continue;
+
count = resource_get_odm_slice_count(otg_master);
update_slice_table_for_stream(table, stream, count);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
index 87c7b13391bc..d276458e50fd 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
@@ -120,7 +120,8 @@ int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,
} else {
/* stream was configured with dummy plane, so get pipes from 
opp head */
struct pipe_ctx *otg_master_pipe = 
dml_ctx->config.callbacks.get_otg_master_for_stream(>res_ctx, 
dc_main_stream);
-   num_pipes = 
dml_ctx->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe, 
>res_ctx, dc_main_pipes);
+   if (otg_master_pipe != NULL)
+   num_pipes = 
dml_ctx->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe, 
>res_ctx, dc_main_pipes);
}
 
/* if phantom exists, find associated pipes */
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
index 486b222083e0..6eccf0241d85 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
@@ -905,6 +905,9 @@ static unsigned int get_source_odm_factor(const struct 
dml2_context *ctx,
 {
struct pipe_ctx *otg_master = 
ctx->config.callbacks.get_otg_master_for_stream(>res_ctx, stream);
 
+   if (!otg_master)
+   return 0;
+
return ctx->config.callbacks.get_odm_slice_count(otg_master);
 }
 
-- 
2.45.1

[PATCH 26/36] drm/amd/display: Improve warning log for get OPP for OTG master

[Hamza Mahfooz]

From: Rodrigo Siqueira 

If some part of the driver tries to call
resource_get_opp_heads_for_otg_master in a non-OTG master context, DC
will trigger a dmesg warning since this situation indicates that some
configuration associated with ODM slices might be wrong. This commit
adds an extra log to describe why the warning was triggered to make the
debugging more straightforward.

Reviewed-by: Wenjing Liu 
Acked-by: Hamza Mahfooz 
Signed-off-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 87e84b0a3d48..1cba8f58f1e6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1917,9 +1917,15 @@ int resource_get_opp_heads_for_otg_master(const struct 
pipe_ctx *otg_master,
struct pipe_ctx *opp_heads[MAX_PIPES])
 {
struct pipe_ctx *opp_head = _ctx->pipe_ctx[otg_master->pipe_idx];
+   struct dc *dc = otg_master->stream->ctx->dc;
int i = 0;
 
+   DC_LOGGER_INIT(dc->ctx->logger);
+
if (!resource_is_pipe_type(otg_master, OTG_MASTER)) {
+   DC_LOG_WARNING("%s called from a non OTG master, something "
+  "is wrong in the pipe configuration",
+  __func__);
ASSERT(0);
return 0;
}
-- 
2.45.1

[PATCH 18/36] drm/amd/display: mirror case cleanup for cursors

[Hamza Mahfooz]

From: Sridevi Arvindekar 

Mirror case unsupported for cursors. So, remove code for mirror case
with cursors.

Reviewed-by: Nevenko Stupar 
Acked-by: Hamza Mahfooz 
Signed-off-by: Sridevi Arvindekar 
---
 .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 30 +--
 1 file changed, 1 insertion(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index e7d6d987e3d3..ef0a42f2933d 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1209,34 +1209,7 @@ void dcn401_set_cursor_position(struct pipe_ctx 
*pipe_ctx)
if (pos_cpy.enable && dcn401_can_pipe_disable_cursor(pipe_ctx))
pos_cpy.enable = false;
 
-   if (param.rotation == ROTATION_ANGLE_0) {
-   int recout_width =
-   pipe_ctx->plane_res.scl_data.recout.width;
-   int recout_x =
-   pipe_ctx->plane_res.scl_data.recout.x;
-
-   if (param.mirror) {
-   if (pipe_split_on || odm_combine_on) {
-   if (pos_cpy.x >= recout_width + recout_x) {
-   pos_cpy.x = 2 * recout_width
-   - pos_cpy.x + 2 * recout_x;
-   } else {
-   uint32_t temp_x = pos_cpy.x;
-
-   pos_cpy.x = 2 * recout_x - pos_cpy.x;
-   if (temp_x >= recout_x +
-   (int)hubp->curs_attr.width || 
pos_cpy.x
-   <= (int)hubp->curs_attr.width +
-   
pipe_ctx->plane_state->src_rect.x) {
-   pos_cpy.x = 2 * recout_width - 
temp_x;
-   }
-   }
-   } else {
-   pos_cpy.x = recout_width - pos_cpy.x + 2 * 
recout_x;
-   }
-   }
-   } else if (param.rotation == ROTATION_ANGLE_90) {
-   } else if (param.rotation == ROTATION_ANGLE_270) {
+   if (param.rotation == ROTATION_ANGLE_270) {
// Swap axis and mirror vertically
uint32_t temp_x = pos_cpy.x;
 
@@ -1285,7 +1258,6 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
pos_cpy.x = 
pipe_ctx->plane_res.scl_data.recout.width + next_odm_width + next_odm_offset - 
pos_cpy.y;
pos_cpy.y = temp_x;
}
-   } else {
}
} else if (param.rotation == ROTATION_ANGLE_180) {
// Mirror horizontally and vertically
-- 
2.45.1

[PATCH 16/36] drm/amd/display: Skip wbscl_set_scaler_filter if filter is null

[Hamza Mahfooz]

From: Alex Hung 

Callers can pass null in filter (i.e. from returned from the function
wbscl_get_filter_coeffs_16p) and a null check is added to ensure that is
not the case.

This fixes 4 NULL_RETURNS issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
index 994fb732a7cb..a0d437f0ce2b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
@@ -690,6 +690,9 @@ static void wbscl_set_scaler_filter(
int pair;
uint16_t odd_coef, even_coef;
 
+   if (!filter)
+   return;
+
for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
for (pair = 0; pair < tap_pairs; pair++) {
even_coef = filter[phase * taps + 2 * pair];
-- 
2.45.1

[PATCH 19/36] drm/amd/display: Fix NULL pointer dereference for DTN log in DCN401

[Hamza Mahfooz]

From: Rodrigo Siqueira 

When users run the command:

cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log

The following NULL pointer dereference happens:

[  +0.03] BUG: kernel NULL pointer dereference, address: NULL
[  +0.05] #PF: supervisor instruction fetch in kernel mode
[  +0.02] #PF: error_code(0x0010) - not-present page
[  +0.02] PGD 0 P4D 0
[  +0.04] Oops: 0010 [#1] PREEMPT SMP NOPTI
[  +0.03] RIP: 0010:0x0
[  +0.08] Code: Unable to access opcode bytes at 0xffd6.
[...]
[  +0.02] PKRU: 5554
[  +0.02] Call Trace:
[  +0.02]  
[  +0.03]  ? show_regs+0x65/0x70
[  +0.06]  ? __die+0x24/0x70
[  +0.04]  ? page_fault_oops+0x160/0x470
[  +0.06]  ? do_user_addr_fault+0x2b5/0x690
[  +0.03]  ? prb_read_valid+0x1c/0x30
[  +0.05]  ? exc_page_fault+0x8c/0x1a0
[  +0.05]  ? asm_exc_page_fault+0x27/0x30
[  +0.12]  dcn10_log_color_state+0xf9/0x510 [amdgpu]
[  +0.000306]  ? srso_alias_return_thunk+0x5/0xfbef5
[  +0.03]  ? vsnprintf+0x2fb/0x600
[  +0.09]  dcn10_log_hw_state+0xfd0/0xfe0 [amdgpu]
[  +0.000218]  ? __mod_memcg_lruvec_state+0xe8/0x170
[  +0.08]  ? srso_alias_return_thunk+0x5/0xfbef5
[  +0.02]  ? debug_smp_processor_id+0x17/0x20
[  +0.03]  ? srso_alias_return_thunk+0x5/0xfbef5
[  +0.02]  ? srso_alias_return_thunk+0x5/0xfbef5
[  +0.02]  ? set_ptes.isra.0+0x2b/0x90
[  +0.04]  ? srso_alias_return_thunk+0x5/0xfbef5
[  +0.02]  ? _raw_spin_unlock+0x19/0x40
[  +0.04]  ? srso_alias_return_thunk+0x5/0xfbef5
[  +0.02]  ? do_anonymous_page+0x337/0x700
[  +0.04]  dtn_log_read+0x82/0x120 [amdgpu]
[  +0.000207]  full_proxy_read+0x66/0x90
[  +0.07]  vfs_read+0xb0/0x340
[  +0.05]  ? __count_memcg_events+0x79/0xe0
[  +0.02]  ? srso_alias_return_thunk+0x5/0xfbef5
[  +0.03]  ? count_memcg_events.constprop.0+0x1e/0x40
[  +0.03]  ? handle_mm_fault+0xb2/0x370
[  +0.03]  ksys_read+0x6b/0xf0
[  +0.04]  __x64_sys_read+0x19/0x20
[  +0.03]  do_syscall_64+0x60/0x130
[  +0.04]  entry_SYSCALL_64_after_hwframe+0x6e/0x76
[  +0.03] RIP: 0033:0x7fdf32f147e2
[...]

This error happens when the color log tries to read the gamut remap
information from DCN401 which is not initialized in the dcn401_dpp_funcs
which leads to a null pointer dereference. This commit addresses this
issue by adding a proper guard to access the gamut_remap callback in
case the specific ASIC did not implement this function.

Reviewed-by: Aurabindo Pillai 
Acked-by: Hamza Mahfooz 
Signed-off-by: Rodrigo Siqueira 
---
 .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c   | 49 ++-
 1 file changed, 27 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index de6ee6bf0a88..0bfab66b8038 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -289,6 +289,7 @@ static void dcn10_log_color_state(struct dc *dc,
 {
struct dc_context *dc_ctx = dc->ctx;
struct resource_pool *pool = dc->res_pool;
+   bool is_gamut_remap_available = false;
int i;
 
DTN_INFO("DPP:IGAM formatIGAM modeDGAM modeRGAM mode"
@@ -301,16 +302,15 @@ static void dcn10_log_color_state(struct dc *dc,
struct dcn_dpp_state s = {0};
 
dpp->funcs->dpp_read_state(dpp, );
-   dpp->funcs->dpp_get_gamut_remap(dpp, _remap);
+   if (dpp->funcs->dpp_get_gamut_remap) {
+   dpp->funcs->dpp_get_gamut_remap(dpp, _remap);
+   is_gamut_remap_available = true;
+   }
 
if (!s.is_enabled)
continue;
 
-   DTN_INFO("[%2d]:  %11xh  %11s%9s%9s"
-"  %12s  "
-"%010lld %010lld %010lld %010lld "
-"%010lld %010lld %010lld %010lld "
-"%010lld %010lld %010lld %010lld",
+   DTN_INFO("[%2d]:  %11xh  %11s%9s%9s",
dpp->inst,
s.igam_input_format,
(s.igam_lut_mode == 0) ? "BypassFixed" :
@@ -329,22 +329,27 @@ static void dcn10_log_color_state(struct dc *dc,
((s.rgam_lut_mode == 2) ? "Ycc" :
((s.rgam_lut_mode == 3) ? "RAM" :
((s.rgam_lut_mode == 4) ? "RAM" :
-"Unknown",
-   (s.gamut_remap.gamut_adjust_type == 0) ? 
"Bypass" :
-   ((s.gamut_remap.gamut_adjust_type == 1) 
? "HW" :
-   
  "SW"),
-   

[PATCH 15/36] drm/amd/display: Check BIOS images before it is used

[Hamza Mahfooz]

From: Alex Hung 

BIOS images may fail to load and null checks are added before they are
used.

This fixes 6 NULL_RETURNS issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 25fe1a124029..3bacf470f7c5 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -665,6 +665,9 @@ static enum bp_result get_ss_info_v3_1(
ss_table_header_include = ((ATOM_ASIC_INTERNAL_SS_INFO_V3 *) 
bios_get_image(>base,
DATA_TABLES(ASIC_InternalSS_Info),
struct_size(ss_table_header_include, 
asSpreadSpectrum, 1)));
+   if (!ss_table_header_include)
+   return BP_RESULT_UNSUPPORTED;
+
table_size =
(le16_to_cpu(ss_table_header_include->sHeader.usStructureSize)
- sizeof(ATOM_COMMON_TABLE_HEADER))
@@ -1034,6 +1037,8 @@ static enum bp_result 
get_ss_info_from_internal_ss_info_tbl_V2_1(
>base,
DATA_TABLES(ASIC_InternalSS_Info),
struct_size(header, asSpreadSpectrum, 1)));
+   if (!header)
+   return result;
 
memset(info, 0, sizeof(struct spread_spectrum_info));
 
@@ -1107,6 +1112,8 @@ static enum bp_result get_ss_info_from_ss_info_table(
get_atom_data_table_revision(header, );
 
tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO, DATA_TABLES(SS_Info));
+   if (!tbl)
+   return result;
 
if (1 != revision.major || 2 > revision.minor)
return result;
@@ -1634,6 +1641,8 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
 
tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO,
DATA_TABLES(SS_Info));
+   if (!tbl)
+   return number;
 
if (1 != revision.major || 2 > revision.minor)
return number;
@@ -1716,6 +1725,8 @@ static uint32_t 
get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
>base,
DATA_TABLES(ASIC_InternalSS_Info),
struct_size(header_include, asSpreadSpectrum, 
1)));
+   if (!header_include)
+   return 0;
 
size = (le16_to_cpu(header_include->sHeader.usStructureSize)
- sizeof(ATOM_COMMON_TABLE_HEADER))
@@ -1755,6 +1766,9 @@ static uint32_t 
get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
header_include = ((ATOM_ASIC_INTERNAL_SS_INFO_V3 *) 
bios_get_image(>base,
DATA_TABLES(ASIC_InternalSS_Info),
struct_size(header_include, asSpreadSpectrum, 
1)));
+   if (!header_include)
+   return number;
+
size = (le16_to_cpu(header_include->sHeader.usStructureSize) -
sizeof(ATOM_COMMON_TABLE_HEADER)) /
sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
-- 
2.45.1

[PATCH 12/36] drm/amd/display: Send message to notify the DPIA host router bandwidth

[Hamza Mahfooz]

From: Sung Joon Kim 

[why]
Tell the system about the current host router bandwidth to be used to
measure and calculate the right voltage to be used.

[how]
Send SMU message of each DPIA host router bandwidth.

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Hamza Mahfooz 
Signed-off-by: Sung Joon Kim 
---
 .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c  | 55 +++
 .../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c  | 21 ++-
 .../amd/display/dc/clk_mgr/dcn35/dcn35_smu.h  |  2 +
 drivers/gpu/drm/amd/display/dc/dc.h   |  3 +
 .../dc/resource/dcn351/dcn351_resource.c  |  1 +
 5 files changed, 81 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 6c9b4e6491a5..9a414f49f15a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -218,6 +218,57 @@ static void dcn35_update_clocks_update_dpp_dto(struct 
clk_mgr_internal *clk_mgr,
}
 }
 
+static uint8_t get_lowest_dpia_index(const struct dc_link *link)
+{
+   const struct dc *dc_struct = link->dc;
+   uint8_t idx = 0xFF;
+   int i;
+
+   for (i = 0; i < MAX_PIPES * 2; ++i) {
+   if (!dc_struct->links[i] || dc_struct->links[i]->ep_type != 
DISPLAY_ENDPOINT_USB4_DPIA)
+   continue;
+
+   if (idx > dc_struct->links[i]->link_index)
+   idx = dc_struct->links[i]->link_index;
+   }
+
+   return idx;
+}
+
+static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct 
dc_state *context,
+   bool safe_to_lower)
+{
+   struct dc_clocks *new_clocks = >bw_ctx.bw.dcn.clk;
+   struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+   uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };
+   int i;
+
+   for (i = 0; i < context->stream_count; ++i) {
+   const struct dc_stream_state *stream = context->streams[i];
+   const struct dc_link *link = stream->link;
+   uint8_t lowest_dpia_index = 0, hr_index = 0;
+
+   if (!link)
+   continue;
+
+   lowest_dpia_index = get_lowest_dpia_index(link);
+   if (link->link_index < lowest_dpia_index)
+   continue;
+
+   hr_index = (link->link_index - lowest_dpia_index) / 2;
+   host_router_bw_kbps[hr_index] += 
dc_bandwidth_in_kbps_from_timing(
+   >timing, 
dc_link_get_highest_encoding_format(link));
+   }
+
+   for (i = 0; i < MAX_HOST_ROUTERS_NUM; ++i) {
+   new_clocks->host_router_bw_kbps[i] = host_router_bw_kbps[i];
+   if (should_set_clock(safe_to_lower, 
new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_router_bw_kbps[i])) 
{
+   clk_mgr_base->clks.host_router_bw_kbps[i] = 
new_clocks->host_router_bw_kbps[i];
+   dcn35_smu_notify_host_router_bw(clk_mgr, i, 
new_clocks->host_router_bw_kbps[i]);
+   }
+   }
+}
+
 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
bool safe_to_lower)
@@ -342,6 +393,10 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
dcn35_update_clocks_update_dpp_dto(clk_mgr, context, 
safe_to_lower);
}
 
+   // notify PMFW of bandwidth per DPIA tunnel
+   if (dc->debug.notify_dpia_hr_bw)
+   dcn35_notify_host_router_bw(clk_mgr_base, context, 
safe_to_lower);
+
// notify DMCUB of latest clocks
memset(, 0, sizeof(cmd));
cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index 1399b41dfd1c..f6f0e6a33001 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -89,7 +89,8 @@
 #define VBIOSSMC_MSG_DisableLSdma 0x1A ///< Disable LSDMA; 
only sent by VBIOS
 #define VBIOSSMC_MSG_DpControllerPhyStatus0x1B ///< Inform PMFW about 
the pre conditions for turning SLDO2 on/off . bit[0]==1 precondition is met, 
bit[1-2] are for DPPHY number
 #define VBIOSSMC_MSG_QueryIPS2Support 0x1C ///< Return 1: support; 
else not supported
-#define VBIOSSMC_Message_Count0x1D
+#define VBIOSSMC_MSG_NotifyHostRouterBW   0x1D
+#define VBIOSSMC_Message_Count0x1E
 
 #define VBIOSSMC_Status_BUSY  0x0
 #define VBIOSSMC_Result_OK0x1
@@ -98,6 +99,14 @@
 #define VBIOSSMC_Result_CmdRejectedPrereq 0xFD
 #define VBIOSSMC_Result_CmdRejectedBusy   0xFC
 
+union dcn35_dpia_host_router_bw {
+   

[PATCH 11/36] drm/amd/display: Add null check to dml21_find_dc_pipes_for_plane

[Hamza Mahfooz]

From: Dillon Varone 

When a phantom stream is in the process of being deconstructed, there
could be pipes with no associated planes.  In that case, ignore the
phantom stream entirely when searching for associated pipes.

Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee 
Acked-by: Hamza Mahfooz 
Signed-off-by: Dillon Varone 
---
 .../gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c   | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
index 4e12810308a4..4166332b5b89 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
@@ -126,10 +126,15 @@ int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,
if (dc_phantom_stream && num_pipes > 0) {
dc_phantom_stream_status = 
dml_ctx->config.callbacks.get_stream_status(context, dc_phantom_stream);
 
-   /* phantom plane will have same index as main */
-   dc_phantom_plane = 
dc_phantom_stream_status->plane_states[dc_plane_index];
+   if (dc_phantom_stream_status) {
+   /* phantom plane will have same index as main */
+   dc_phantom_plane = 
dc_phantom_stream_status->plane_states[dc_plane_index];
 
-   
dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_phantom_plane, 
>res_ctx, dc_phantom_pipes);
+   if (dc_phantom_plane) {
+   /* only care about phantom pipes if they 
contain the phantom plane */
+   
dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_phantom_plane, 
>res_ctx, dc_phantom_pipes);
+   }
+   }
}
 
return num_pipes;
-- 
2.45.1

[PATCH 14/36] drm/amd/display: Add null checker before passing variables

[Hamza Mahfooz]

From: Alex Hung 

Checks null pointer before passing variables to functions.

This fixes 3 NULL_RETURNS issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4de50b297035..48a9243ada7d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2875,7 +2875,8 @@ static int dm_suspend(void *handle)
 
dm->cached_dc_state = 
dc_state_create_copy(dm->dc->current_state);
 
-   dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
+   if (dm->cached_dc_state)
+   dm_gpureset_toggle_interrupts(adev, 
dm->cached_dc_state, false);
 
amdgpu_dm_commit_zero_streams(dm->dc);
 
@@ -7102,7 +7103,8 @@ static void create_eml_sink(struct amdgpu_dm_connector 
*aconnector)
aconnector->dc_sink = aconnector->dc_link->local_sink ?
aconnector->dc_link->local_sink :
aconnector->dc_em_sink;
-   dc_sink_retain(aconnector->dc_sink);
+   if (aconnector->dc_sink)
+   dc_sink_retain(aconnector->dc_sink);
}
 }
 
@@ -7929,7 +7931,8 @@ static int amdgpu_dm_connector_get_modes(struct 
drm_connector *connector)
drm_add_modes_noedid(connector, 1920, 1080);
} else {
amdgpu_dm_connector_ddc_get_modes(connector, edid);
-   amdgpu_dm_connector_add_common_modes(encoder, connector);
+   if (encoder)
+   amdgpu_dm_connector_add_common_modes(encoder, 
connector);
amdgpu_dm_connector_add_freesync_modes(connector, edid);
}
amdgpu_dm_fbc_init(connector);
-- 
2.45.1

[PATCH 07/36] drm/amd/display: fix minor coding errors where dml21 phase 5 uses wrong variables

[Hamza Mahfooz]

From: Wenjing Liu 

There is a coding error which causes incorrect variables to be assigned
in DML21 phase 5.

Reviewed-by: Dillon Varone 
Acked-by: Hamza Mahfooz 
Signed-off-by: Wenjing Liu 
---
 .../gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c  | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c
index 1142fdade334..6f334fdc6eb8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c
@@ -259,7 +259,7 @@ bool dml2_build_mode_programming(struct 
dml2_build_mode_programming_in_out *in_o
/*
* Phase 5: Optimize for Stutter
*/
-   memset(>vmin_phase, 0, sizeof(struct optimization_phase_params));
+   memset(>stutter_phase, 0, sizeof(struct optimization_phase_params));
l->stutter_phase.dml = dml;
l->stutter_phase.display_config = >base_display_config_with_meta;
l->stutter_phase.init_function = 
dml2_top_optimization_init_function_stutter;
@@ -272,7 +272,7 @@ bool dml2_build_mode_programming(struct 
dml2_build_mode_programming_in_out *in_o
 
if (stutter_success) {
memcpy(>base_display_config_with_meta, 
>optimized_display_config_with_meta, sizeof(struct 
display_configuation_with_meta));
-   l->base_display_config_with_meta.stage4.success = true;
+   l->base_display_config_with_meta.stage5.success = true;
}
 
/*
-- 
2.45.1

[PATCH 13/36] drm/amd/display: Explicitly extend unsigned 16 bit to 64 bit

[Hamza Mahfooz]

From: Alex Hung 

Coverity reports sign extention defects as below:

Suspicious implicit sign extension: mode->htotal with type u16 ... to
int (32 bits, signed), then sign-extended to type unsigned long
(64 bits, unsigned). If mode->htotal * mode->vtotal is greater than
0x7FFF, the upper bits of the result will all be 1.

Cast it to unsigned long to avoid possible overflow.

This fixes 4 SIGN_EXTENSION issues reported by Coverity.

Reviewed-by: Harry Wentland 
Acked-by: Hamza Mahfooz 
Signed-off-by: Alex Hung 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0940c2facb30..4de50b297035 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -977,8 +977,8 @@ static void amdgpu_dm_fbc_init(struct drm_connector 
*connector)
 
 
list_for_each_entry(mode, >modes, head) {
-   if (max_size < mode->htotal * mode->vtotal)
-   max_size = mode->htotal * mode->vtotal;
+   if (max_size < (unsigned long) mode->htotal * mode->vtotal)
+   max_size = (unsigned long) mode->htotal * mode->vtotal;
}
 
if (max_size) {
-- 
2.45.1

[PATCH 10/36] drm/amd/display: Attempt to avoid empty TUs when endpoint is DPIA

[Hamza Mahfooz]

From: Michael Strauss 

[WHY]
Empty SST TUs are illegal to transmit over a USB4 DP tunnel.
Current policy is to configure stream encoder to pack 2 pixels per pclk
even when ODM combine is not in use, allowing seamless dynamic ODM
reconfiguration. However, in extreme edge cases where average pixel
count per TU is less than 2, this can lead to unexpected empty TU
generation during compliance testing. For example, VIC 1 with a 1xHBR3
link configuration will average 1.98 pix/TU.

[HOW]
Calculate average pixel count per TU, and block 2 pixels per clock if
endpoint is a DPIA tunnel and pixel clock is low enough that we will
never require 2:1 ODM combine.

Cc: sta...@vger.kernel.org # 6.6+
Reviewed-by: Wenjing Liu 
Acked-by: Hamza Mahfooz 
Signed-off-by: Michael Strauss 
---
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   | 72 +++
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.h   |  2 +
 .../amd/display/dc/hwss/dcn35/dcn35_init.c|  2 +-
 3 files changed, 75 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 4f87316e1318..0602921399cd 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -1529,3 +1529,75 @@ void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,
}
}
 }
+
+static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx)
+{
+   /* Calculate average pixel count per TU, return false if under ~2.00 to
+* avoid empty TUs. This is only required for DPIA tunneling as empty 
TUs
+* are legal to generate for native DP links. Assume TU size 64 as there
+* is currently no scenario where it's reprogrammed from HW default.
+* MTPs have no such limitation, so this does not affect MST use cases.
+*/
+   unsigned int pix_clk_mhz;
+   unsigned int symclk_mhz;
+   unsigned int avg_pix_per_tu_x1000;
+   unsigned int tu_size_bytes = 64;
+   struct dc_crtc_timing *timing = _ctx->stream->timing;
+   struct dc_link_settings *link_settings = 
_ctx->link_config.dp_link_settings;
+   const struct dc *dc = pipe_ctx->stream->link->dc;
+
+   if (pipe_ctx->stream->link->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
+   return false;
+
+   // Not necessary for MST configurations
+   if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+   return false;
+
+   pix_clk_mhz = timing->pix_clk_100hz / 1;
+
+   // If this is true, can't block due to dynamic ODM
+   if (pix_clk_mhz > 
dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz)
+   return false;
+
+   switch (link_settings->link_rate) {
+   case LINK_RATE_LOW:
+   symclk_mhz = 162;
+   break;
+   case LINK_RATE_HIGH:
+   symclk_mhz = 270;
+   break;
+   case LINK_RATE_HIGH2:
+   symclk_mhz = 540;
+   break;
+   case LINK_RATE_HIGH3:
+   symclk_mhz = 810;
+   break;
+   default:
+   // We shouldn't be tunneling any other rates, something is wrong
+   ASSERT(0);
+   return false;
+   }
+
+   avg_pix_per_tu_x1000 = (1000 * pix_clk_mhz * tu_size_bytes)
+   / (symclk_mhz * link_settings->lane_count);
+
+   // Add small empirically-decided margin to account for potential jitter
+   return (avg_pix_per_tu_x1000 < 2020);
+}
+
+bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
+{
+   struct dc *dc = pipe_ctx->stream->ctx->dc;
+
+   if (!is_h_timing_divisible_by_2(pipe_ctx->stream))
+   return false;
+
+   if (should_avoid_empty_tu(pipe_ctx))
+   return false;
+
+   if (dc_is_dp_signal(pipe_ctx->stream->signal) && 
!dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&
+   dc->debug.enable_dp_dig_pixel_rate_div_policy)
+   return true;
+
+   return false;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
index bc05beba5f2c..e27b3609020f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
@@ -97,4 +97,6 @@ void dcn35_set_static_screen_control(struct pipe_ctx 
**pipe_ctx,
 void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,
int num_pipes, uint32_t v_total_min, uint32_t v_total_max);
 
+bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
+
 #endif /* __DC_HWSS_DCN35_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index 30e6a6398839..428912f37129 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -161,7 

[PATCH 04/36] Revert "drm/amd/display: workaround for oled eDP not lighting up on DCN401"

[Hamza Mahfooz]

From: Joshua Aberback 

This reverts commit e296c84e7d0561ed626591e1cf9b71a7ba0133f4.

A proper fix for this issue has been implemented in DMUB FW. So, no need
to keep the workaround.

Reviewed-by: Wenjing Liu 
Acked-by: Hamza Mahfooz 
Signed-off-by: Joshua Aberback 
---
 drivers/gpu/drm/amd/display/dc/dc.h| 1 -
 .../drm/amd/display/dc/link/protocols/link_edp_panel_control.c | 3 ---
 .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c   | 1 -
 3 files changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 35ca38ea2efa..b9c67bac7beb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1045,7 +1045,6 @@ struct dc_debug_options {
unsigned int force_easf;
unsigned int force_sharpness;
unsigned int force_lls;
-   bool edp_oled_no_backlight_enable;
 };
 
 
diff --git 
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c 
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index b0e17064a960..455b85adec28 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -248,9 +248,6 @@ bool edp_backlight_enable_aux(struct dc_link *link, bool 
enable)
link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
return false;
 
-   if (link->dc->debug.edp_oled_no_backlight_enable && 
link->dpcd_sink_ext_caps.bits.oled)
-   return true;
-
if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
_enable, 1) != DC_OK)
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c 
b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index d78dc63f82fd..74fb21b88f12 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -731,7 +731,6 @@ static const struct dc_debug_options debug_defaults_drv = {
}
},
.force_cositing = CHROMA_COSITING_TOPLEFT + 1,
-   .edp_oled_no_backlight_enable = true,
 };
 
 static struct dce_aux *dcn401_aux_engine_create(
-- 
2.45.1

[PATCH 09/36] drm/amd/display: Refactor DCN3X into component folder

[Hamza Mahfooz]

From: Mounika Adhuri 

[why]
Move DCN3X files to unique component folder.

[how]
Create respective component folder in dc, move the DCN3X files into
corresponding new folders and made appropriate changes for compilation
in Makefiles.

Reviewed-by: Martin Leung 
Acked-by: Hamza Mahfooz 
Signed-off-by: Mounika Adhuri 
---
 drivers/gpu/drm/amd/display/Makefile  |  7 +++
 drivers/gpu/drm/amd/display/dc/Makefile   |  6 +-
 drivers/gpu/drm/amd/display/dc/dcn32/Makefile | 19 --
 .../gpu/drm/amd/display/dc/dcn321/Makefile| 17 -
 drivers/gpu/drm/amd/display/dc/dcn35/Makefile | 19 --
 drivers/gpu/drm/amd/display/dc/dio/Makefile   | 63 +++
 .../{ => dio}/dcn32/dcn32_dio_link_encoder.c  |  0
 .../{ => dio}/dcn32/dcn32_dio_link_encoder.h  |  0
 .../dcn32/dcn32_dio_stream_encoder.c  |  0
 .../dcn32/dcn32_dio_stream_encoder.h  |  0
 .../dcn321/dcn321_dio_link_encoder.c  |  0
 .../dcn321/dcn321_dio_link_encoder.h  |  0
 .../{ => dio}/dcn35/dcn35_dio_link_encoder.c  |  0
 .../{ => dio}/dcn35/dcn35_dio_link_encoder.h  |  0
 .../dcn35/dcn35_dio_stream_encoder.c  |  0
 .../dcn35/dcn35_dio_stream_encoder.h  |  0
 .../dcn401/dcn401_dio_link_encoder.c  |  0
 .../dcn401/dcn401_dio_link_encoder.h  |  0
 .../dcn401/dcn401_dio_stream_encoder.c|  0
 .../dcn401/dcn401_dio_stream_encoder.h|  0
 drivers/gpu/drm/amd/display/dc/dwb/Makefile   | 37 +++
 .../display/dc/{ => dwb}/dcn35/dcn35_dwb.c|  0
 .../display/dc/{ => dwb}/dcn35/dcn35_dwb.h|  0
 drivers/gpu/drm/amd/display/dc/hpo/Makefile   | 35 +++
 .../dcn32/dcn32_hpo_dp_link_encoder.c |  0
 .../dcn32/dcn32_hpo_dp_link_encoder.h |  0
 .../gpu/drm/amd/display/dc/mmhubbub/Makefile  | 45 +
 .../dc/{ => mmhubbub}/dcn32/dcn32_mmhubbub.c  |  0
 .../dc/{ => mmhubbub}/dcn32/dcn32_mmhubbub.h  |  0
 .../dc/{ => mmhubbub}/dcn35/dcn35_mmhubbub.c  |  0
 .../dc/{ => mmhubbub}/dcn35/dcn35_mmhubbub.h  |  0
 drivers/gpu/drm/amd/display/dc/mpc/Makefile   | 45 +
 .../display/dc/{ => mpc}/dcn32/dcn32_mpc.c|  0
 .../display/dc/{ => mpc}/dcn32/dcn32_mpc.h|  0
 .../display/dc/{ => mpc}/dcn401/dcn401_mpc.c  |  0
 .../display/dc/{ => mpc}/dcn401/dcn401_mpc.h  |  0
 drivers/gpu/drm/amd/display/dc/opp/Makefile   | 35 +++
 .../display/dc/{ => opp}/dcn35/dcn35_opp.c|  0
 .../display/dc/{ => opp}/dcn35/dcn35_opp.h|  0
 drivers/gpu/drm/amd/display/dc/pg/Makefile| 35 +++
 .../display/dc/{ => pg}/dcn35/dcn35_pg_cntl.c |  0
 .../display/dc/{ => pg}/dcn35/dcn35_pg_cntl.h |  0
 .../gpu/drm/amd/display/dc/resource/Makefile  |  2 +-
 .../dcn32/dcn32_resource_helpers.c|  0
 44 files changed, 304 insertions(+), 61 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/Makefile
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/Makefile
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn35/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/dc/dio/Makefile
 rename drivers/gpu/drm/amd/display/dc/{ => dio}/dcn32/dcn32_dio_link_encoder.c 
(100%)
 rename drivers/gpu/drm/amd/display/dc/{ => dio}/dcn32/dcn32_dio_link_encoder.h 
(100%)
 rename drivers/gpu/drm/amd/display/dc/{ => 
dio}/dcn32/dcn32_dio_stream_encoder.c (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => 
dio}/dcn32/dcn32_dio_stream_encoder.h (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => 
dio}/dcn321/dcn321_dio_link_encoder.c (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => 
dio}/dcn321/dcn321_dio_link_encoder.h (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => dio}/dcn35/dcn35_dio_link_encoder.c 
(100%)
 rename drivers/gpu/drm/amd/display/dc/{ => dio}/dcn35/dcn35_dio_link_encoder.h 
(100%)
 rename drivers/gpu/drm/amd/display/dc/{ => 
dio}/dcn35/dcn35_dio_stream_encoder.c (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => 
dio}/dcn35/dcn35_dio_stream_encoder.h (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => 
dio}/dcn401/dcn401_dio_link_encoder.c (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => 
dio}/dcn401/dcn401_dio_link_encoder.h (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => 
dio}/dcn401/dcn401_dio_stream_encoder.c (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => 
dio}/dcn401/dcn401_dio_stream_encoder.h (100%)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dwb/Makefile
 rename drivers/gpu/drm/amd/display/dc/{ => dwb}/dcn35/dcn35_dwb.c (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => dwb}/dcn35/dcn35_dwb.h (100%)
 create mode 100644 drivers/gpu/drm/amd/display/dc/hpo/Makefile
 rename drivers/gpu/drm/amd/display/dc/{ => 
hpo}/dcn32/dcn32_hpo_dp_link_encoder.c (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => 
hpo}/dcn32/dcn32_hpo_dp_link_encoder.h (100%)
 create mode 100644 drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile
 rename drivers/gpu/drm/amd/display/dc/{ => mmhubbub}/dcn32/dcn32_mmhubbub.c 
(100%)
 rename drivers/gpu/drm/amd/display/dc/{ => mmhubbub}/dcn32/dcn32_mmhubbub.h 

[PATCH 06/36] drm/amd/display: Remove redundant condition in VBA 314 func

[Hamza Mahfooz]

From: Ivan Lipski 

[WHY]
Coverity analysis this conditional code as DEADCODE.
The conditional statement is never true since
'MacroTileSizeBytes' is either 256 or 65536. Thus, the
code inside is the conditional statement is never reached.

[HOW]
Removed the conditional statement.

Reviewed-by: Aurabindo Pillai 
Reviewed-by: Alex Hung 
Acked-by: Hamza Mahfooz 
Signed-off-by: Ivan Lipski 
---
 .../drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index f52b9e3d2bee..cb50c475746b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -1941,15 +1941,6 @@ static unsigned int CalculateVMAndRowBytes(
*PixelPTEReqWidth = 32768.0 / BytePerPixel;
*PTERequestSize = 64;
FractionOfPTEReturnDrop = 0;
-   } else if (MacroTileSizeBytes == 4096) {
-   PixelPTEReqHeightPTEs = 1;
-   *PixelPTEReqHeight = MacroTileHeight;
-   *PixelPTEReqWidth = 8 * *MacroTileWidth;
-   *PTERequestSize = 64;
-   if (ScanDirection != dm_vert)
-   FractionOfPTEReturnDrop = 0;
-   else
-   FractionOfPTEReturnDrop = 7 / 8;
} else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) {
PixelPTEReqHeightPTEs = 16;
*PixelPTEReqHeight = 16 * BlockHeight256Bytes;
-- 
2.45.1

[PATCH 02/36] drm/amd/display: Enable DCN401 idle optimizations by default

[Hamza Mahfooz]

From: Dillon Varone 

[WHY]
Re-enable idle optimizations by default.

Reviewed-by: Alvin Lee 
Acked-by: Hamza Mahfooz 
Signed-off-by: Dillon Varone 
---
 drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c 
b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index 7781a0342d67..d78dc63f82fd 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -731,7 +731,6 @@ static const struct dc_debug_options debug_defaults_drv = {
}
},
.force_cositing = CHROMA_COSITING_TOPLEFT + 1,
-   .disable_idle_power_optimizations = true,
.edp_oled_no_backlight_enable = true,
 };
 
-- 
2.45.1

[PATCH 01/36] drm/amd/display: DCN401 full power down in HW init if any link enabled

[Hamza Mahfooz]

From: Joshua Aberback 

[Why]
During HW init, certain operations the driver performs are invalid on
enabled hardware in an unknown state (for example, setting all clock
values to minimum when the GPU is actively driving a display). There is
already code present to call HWSS->power_down during init when any link
is enabled in HW, but that function pointer is unpopulated for most asics.
We want to enable this codepath for DCN401, as it resolves the issue with
being unable to drive certain display configs on adapter re-enable, and we
can restore boot optimizations.

[How]
 - add power_down HWSS function for DCN401
 - remove debug bit to disable boot optimizations for DCN401

Reviewed-by: Wenjing Liu 
Acked-by: Hamza Mahfooz 
Signed-off-by: Joshua Aberback 
---
 drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c | 1 +
 drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index dabad7feff03..1cf0608e1980 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -98,6 +98,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = {
.fams2_global_control_lock = dcn401_fams2_global_control_lock,
.fams2_update_config = dcn401_fams2_update_config,
.fams2_global_control_lock_fast = dcn401_fams2_global_control_lock_fast,
+   .power_down = dce110_power_down,
 };
 
 static const struct hwseq_private_funcs dcn401_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c 
b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index ea803df8645e..7781a0342d67 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -733,7 +733,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.force_cositing = CHROMA_COSITING_TOPLEFT + 1,
.disable_idle_power_optimizations = true,
.edp_oled_no_backlight_enable = true,
-   .disable_boot_optimizations = true,
 };
 
 static struct dce_aux *dcn401_aux_engine_create(
-- 
2.45.1

[PATCH 08/36] drm/amd/display: On clock init, maintain DISPCLK freq

[Hamza Mahfooz]

From: Chris Park 

[Why]
On init if a display is connected, we need to maintain the DISPCLK
frequency Even though DPG_EN=1, the display still requires the correct
timing or it could cause audio corruption (if DISPCLK freq is reduced).

[How]
Read the current DISPCLK freq and request the same value to ensure the
timing is valid and unchanged.

Reviewed-by: Alvin Lee 
Acked-by: Hamza Mahfooz 
Signed-off-by: Chris Park 
---
 .../display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c  | 17 +
 .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c   | 11 ++-
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index cd1c30fa783a..70f06a7c882e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -1459,6 +1459,22 @@ static int dcn401_get_dtb_ref_freq_khz(struct clk_mgr 
*clk_mgr_base)
return dtb_ref_clk_khz;
 }
 
+static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
+{
+   struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+   uint32_t dispclk_wdivider;
+   int disp_divider;
+
+   REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, 
_wdivider);
+   disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
+
+   /* Return DISPCLK freq in Khz */
+   if (disp_divider)
+   return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * 
clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
+
+   return 0;
+}
+
 static struct clk_mgr_funcs dcn401_funcs = {
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.get_dtb_ref_clk_frequency = dcn401_get_dtb_ref_freq_khz,
@@ -1472,6 +1488,7 @@ static struct clk_mgr_funcs dcn401_funcs = {
.are_clock_states_equal = dcn401_are_clock_states_equal,
.enable_pme_wa = dcn401_enable_pme_wa,
.is_smu_present = dcn401_is_smu_present,
+   .get_dispclk_from_dentist = dcn401_get_dispclk_from_dentist,
 };
 
 struct clk_mgr_internal *dcn401_clk_mgr_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 4d0c01e866be..e7d6d987e3d3 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -57,7 +57,16 @@ static void dcn401_initialize_min_clocks(struct dc *dc)
clocks->socclk_khz = 
dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;
clocks->dramclk_khz = 
dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;
clocks->dppclk_khz = 
dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;
-   clocks->dispclk_khz = 
dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;
+   if (dc->debug.disable_boot_optimizations) {
+   clocks->dispclk_khz = 
dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;
+   } else {
+   /* Even though DPG_EN = 1 for the connected display, it still 
requires the
+* correct timing so we cannot set DISPCLK to min freq or it 
could cause
+* audio corruption. Read current DISPCLK from DENTIST and 
request the same
+* freq to ensure that the timing is valid and unchanged.
+*/
+   clocks->dispclk_khz = 
dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
+   }
clocks->ref_dtbclk_khz = 
dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
clocks->fclk_p_state_change_support = true;
clocks->p_state_change_support = true;
-- 
2.45.1

[PATCH 00/36] DC Patches June 11, 2024

[Hamza Mahfooz]

Cc: Daniel Wheeler 

Alex Hung (15):
  drm/amd/display: Explicitly extend unsigned 16 bit to 64 bit
  drm/amd/display: Add null checker before passing variables
  drm/amd/display: Check BIOS images before it is used
  drm/amd/display: Skip wbscl_set_scaler_filter if filter is null
  drm/amd/display: Add null checker before access structs
  drm/amd/display: Check dc_stream_state before it is used
  drm/amd/display: Check pipe_ctx before it is used
  drm/amd/display: Covert integers to double before divisions
  drm/amd/display: Remove redundant checks for res_pool->dccg
  drm/amd/display: Remove redundant checks for ctx->dc_bios
  drm/amd/display: Remove redundant null checks
  drm/amd/display: Remove redundant checks for opp
  drm/amd/display: Remove redundant checks for context
  drm/amd/display: Check UnboundedRequestEnabled's value
  drm/amd/display: Remove redundant null checks

Alvin Lee (1):
  drm/amd/display: Make sure to reprogram ODM when resync fifo

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.222.0

Aric Cyr (1):
  drm/amd/display: 3.2.289

Chris Park (1):
  drm/amd/display: On clock init, maintain DISPCLK freq

Dillon Varone (2):
  drm/amd/display: Enable DCN401 idle optimizations by default
  drm/amd/display: Add null check to dml21_find_dc_pipes_for_plane

Ivan Lipski (3):
  drm/amd/display: Remove redundant condition with DEADCODE
  drm/amd/display: Remove redundant condition in VBA 314 func
  drm/amd/display: Remove unused value set from 'min_hratio_fact' in dml

Joshua Aberback (3):
  drm/amd/display: DCN401 full power down in HW init if any link enabled
  Revert "drm/amd/display: workaround for oled eDP not lighting up on
DCN401"
  drm/amd/display: Remove duplicate HWSS interfaces

Michael Strauss (1):
  drm/amd/display: Attempt to avoid empty TUs when endpoint is DPIA

Mounika Adhuri (1):
  drm/amd/display: Refactor DCN3X into component folder

Relja Vojvodic (1):
  drm/amd/display: Add dcn401 DIG fifo enable/disable

Rodrigo Siqueira (3):
  drm/amd/display: Fix NULL pointer dereference for DTN log in DCN401
  drm/amd/display: Fix warning caused by an attempt to configure a
non-otg master
  drm/amd/display: Improve warning log for get OPP for OTG master

Sridevi Arvindekar (1):
  drm/amd/display: mirror case cleanup for cursors

Sung Joon Kim (1):
  drm/amd/display: Send message to notify the DPIA host router bandwidth

Wenjing Liu (1):
  drm/amd/display: fix minor coding errors where dml21 phase 5 uses
wrong variables

 drivers/gpu/drm/amd/display/Makefile  |   7 ++
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  19 +--
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |   2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |   3 -
 drivers/gpu/drm/amd/display/dc/Makefile   |   6 +-
 .../gpu/drm/amd/display/dc/bios/bios_parser.c |  14 +++
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |   2 +-
 .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c|   2 +-
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  |   2 +-
 .../dc/clk_mgr/dcn314/dcn314_clk_mgr.c|   2 +-
 .../dc/clk_mgr/dcn315/dcn315_clk_mgr.c|   2 +-
 .../dc/clk_mgr/dcn316/dcn316_clk_mgr.c|   2 +-
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  |   2 +-
 .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c  |  57 -
 .../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c  |  21 +++-
 .../amd/display/dc/clk_mgr/dcn35/dcn35_smu.h  |   2 +
 .../dc/clk_mgr/dcn401/dcn401_clk_mgr.c|  17 +++
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  21 +++-
 .../drm/amd/display/dc/core/dc_hw_sequencer.c |   2 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  15 ++-
 .../gpu/drm/amd/display/dc/core/dc_state.c|  24 ++--
 drivers/gpu/drm/amd/display/dc/dc.h   |   6 +-
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  |  20 +++-
 .../drm/amd/display/dc/dcn20/dcn20_dwb_scl.c  |   3 +
 drivers/gpu/drm/amd/display/dc/dcn32/Makefile |  19 ---
 .../gpu/drm/amd/display/dc/dcn321/Makefile|  17 ---
 drivers/gpu/drm/amd/display/dc/dcn35/Makefile |  19 ---
 drivers/gpu/drm/amd/display/dc/dio/Makefile   |  63 ++
 .../{ => dio}/dcn32/dcn32_dio_link_encoder.c  |   0
 .../{ => dio}/dcn32/dcn32_dio_link_encoder.h  |   0
 .../dcn32/dcn32_dio_stream_encoder.c  |   0
 .../dcn32/dcn32_dio_stream_encoder.h  |   0
 .../dcn321/dcn321_dio_link_encoder.c  |   0
 .../dcn321/dcn321_dio_link_encoder.h  |   0
 .../{ => dio}/dcn35/dcn35_dio_link_encoder.c  |   0
 .../{ => dio}/dcn35/dcn35_dio_link_encoder.h  |   0
 .../dcn35/dcn35_dio_stream_encoder.c  |   4 +-
 .../dcn35/dcn35_dio_stream_encoder.h  |   6 +
 .../dcn401/dcn401_dio_link_encoder.c  |   0
 .../dcn401/dcn401_dio_link_encoder.h  |   0
 .../dcn401/dcn401_dio_stream_encoder.c|   4 +-
 .../dcn401/dcn401_dio_stream_encoder.h|   0
 .../drm/amd/display/dc/dml/calcs/dcn_calcs.c  |   2 +-
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  |  20 ++--
 

[PATCH 03/36] drm/amd/display: Add dcn401 DIG fifo enable/disable

[Hamza Mahfooz]

From: Relja Vojvodic 

[Why]
Found while hotplugging MST daisy chain displays. Changing dispclk
during this sequence caused SMU hang due to DIG fifo not being disabled
correctly (caused by missing functions).

[How]
Adding disable/enable DIG fifo functions for dcn401

Reviewed-by: Wenjing Liu 
Acked-by: Hamza Mahfooz 
Signed-off-by: Relja Vojvodic 
---
 .../gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c | 4 ++--
 .../gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h | 6 ++
 .../drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c   | 4 +++-
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c
index 1325db3a4ed0..6a179e5ab417 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c
@@ -392,7 +392,7 @@ static void enc35_reset_fifo(struct stream_encoder *enc, 
bool reset)
udelay(10);
 }
 
-static void enc35_disable_fifo(struct stream_encoder *enc)
+void enc35_disable_fifo(struct stream_encoder *enc)
 {
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 
@@ -401,7 +401,7 @@ static void enc35_disable_fifo(struct stream_encoder *enc)
REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 0);
 }
 
-static void enc35_enable_fifo(struct stream_encoder *enc)
+void enc35_enable_fifo(struct stream_encoder *enc)
 {
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h
index 1212fcee38f2..ddb33fdfb4ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h
@@ -322,5 +322,11 @@ void enc3_dp_set_dsc_pps_info_packet(
uint8_t *dsc_packed_pps,
bool immediate_update);
 
+void enc35_disable_fifo(
+   struct stream_encoder *enc);
+
+void enc35_enable_fifo(
+   struct stream_encoder *enc);
+
 
 #endif /* __DC_DIO_STREAM_ENCODER_DCN35_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c
index 2ebfca4769aa..0a27e0942a12 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c
@@ -27,6 +27,7 @@
 #include "dc_bios_types.h"
 #include "dcn30/dcn30_dio_stream_encoder.h"
 #include "dcn32/dcn32_dio_stream_encoder.h"
+#include "dcn35/dcn35_dio_stream_encoder.h"
 
 #include "dcn401_dio_stream_encoder.h"
 #include "reg_helper.h"
@@ -764,7 +765,8 @@ static const struct stream_encoder_funcs 
dcn401_str_enc_funcs = {
.enable_stream = enc401_stream_encoder_enable,
 
.set_input_mode = enc401_set_dig_input_mode,
-   .enable_fifo = enc32_enable_fifo,
+   .enable_fifo = enc35_enable_fifo,
+   .disable_fifo = enc35_disable_fifo,
.map_stream_to_link = enc401_stream_encoder_map_to_link,
 };
 
-- 
2.45.1

Re: [PATCH 5/6] drm/amdgpu: always enable move threshold for BOs

[Tvrtko Ursulin]

Hi Christian,

On 04/06/2024 17:05, Christian König wrote:

This should prevent buffer moves when the threshold is reached during
CS.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 36 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 22 +
  2 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index ec888fc6ead8..9a217932a4fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -784,7 +784,6 @@ static int amdgpu_cs_bo_validate(void *param, struct 
amdgpu_bo *bo)
.no_wait_gpu = false,
.resv = bo->tbo.base.resv
};
-   uint32_t domain;
int r;
  
  	if (bo->tbo.pin_count)

@@ -796,37 +795,28 @@ static int amdgpu_cs_bo_validate(void *param, struct 
amdgpu_bo *bo)
if (p->bytes_moved < p->bytes_moved_threshold &&
(!bo->tbo.base.dma_buf ||
list_empty(>tbo.base.dma_buf->attachments))) {
+
+   /* And don't move a CPU_ACCESS_REQUIRED BO to limited
+* visible VRAM if we've depleted our allowance to do
+* that.
+*/
if (!amdgpu_gmc_vram_full_visible(>gmc) &&
-   (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
-   /* And don't move a CPU_ACCESS_REQUIRED BO to limited
-* visible VRAM if we've depleted our allowance to do
-* that.
-*/
-   if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
-   domain = bo->preferred_domains;
-   else
-   domain = bo->allowed_domains;
-   } else {
-   domain = bo->preferred_domains;
-   }
-   } else {
-   domain = bo->allowed_domains;
+   (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
+   p->bytes_moved_vis < p->bytes_moved_vis_threshold)
+   ctx.move_threshold = p->bytes_moved_vis_threshold -
+   p->bytes_moved_vis;
+   else
+   ctx.move_threshold = p->bytes_moved_vis_threshold -
+   p->bytes_moved;
}
  
-retry:

-   amdgpu_bo_placement_from_domain(bo, domain);
+   amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
r = ttm_bo_validate(>tbo, >placement, );
  
  	p->bytes_moved += ctx.bytes_moved;

if (!amdgpu_gmc_vram_full_visible(>gmc) &&
amdgpu_res_cpu_visible(adev, bo->tbo.resource))
p->bytes_moved_vis += ctx.bytes_moved;
-
-   if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
-   domain = bo->allowed_domains;
-   goto retry;
-   }
-
return r;
  }
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 8c92065c2d52..cae1a5420c58 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -168,13 +168,23 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo 
*abo, u32 domain)
abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ?
AMDGPU_PL_PREEMPT : TTM_PL_TT;
places[c].flags = 0;
-   /*
-* When GTT is just an alternative to VRAM make sure that we
-* only use it as fallback and still try to fill up VRAM first.
-*/
+
if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
-   !(adev->flags & AMD_IS_APU))
-   places[c].flags |= TTM_PL_FLAG_FALLBACK;
+   !(adev->flags & AMD_IS_APU)) {
+   /*
+* When GTT is just an alternative to VRAM make sure 
that we
+* only use it as fallback and still try to fill up 
VRAM first.
+   */
+   if (abo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT)
+   places[c].flags |= TTM_PL_FLAG_FALLBACK;
+
+   /*
+* Enable GTT when the threshold of moved bytes is
+* reached. This prevents any non essential buffer move
+* when the links are already saturated.
+*/
+   places[c].flags |= TTM_PL_FLAG_MOVE_THRESHOLD;
+   }


For the APU case I *think* this works, but for discrete I am not sure yet.

As a side note and disclaimer, the TTM "resource compatible" logic has a 
half-life of about one week in my brain until I need to almost re-figure 
it all out. I don't know if it just me, but I find it really 

Re: [PATCH 2/2] drm/amdgpu: reject gang submit on reserved VMIDs

[Deucher, Alexander]

[AMD Official Use Only - AMD Internal Distribution Only]

Series is:
Reviewed-by: Alex Deucher 

From: Christian König 
Sent: Tuesday, June 11, 2024 7:43 AM
To: Deucher, Alexander 
Cc: amd-gfx@lists.freedesktop.org 
Subject: [PATCH 2/2] drm/amdgpu: reject gang submit on reserved VMIDs

A gang submit won't work if the VMID is reserved and we can't flush out
VM changes from multiple engines at the same time.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 15 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 15 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h |  1 +
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index ec888fc6ead8..916b6b8cf7d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1093,6 +1093,21 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser 
*p)
 unsigned int i;
 int r;

+   /*
+* We can't use gang submit on with reserved VMIDs when the VM changes
+* can't be invalidated by more than one engine at the same time.
+*/
+   if (p->gang_size > 1 && !p->adev->vm_manager.concurrent_flush) {
+   for (i = 0; i < p->gang_size; ++i) {
+   struct drm_sched_entity *entity = p->entities[i];
+   struct drm_gpu_scheduler *sched = entity->rq->sched;
+   struct amdgpu_ring *ring = to_amdgpu_ring(sched);
+
+   if (amdgpu_vmid_uses_reserved(vm, ring->vm_hub))
+   return -EINVAL;
+   }
+   }
+
 r = amdgpu_vm_clear_freed(adev, vm, NULL);
 if (r)
 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index b5b9d4f40f53..b6a8bddada4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -424,7 +424,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct 
amdgpu_ring *ring,
 if (r || !idle)
 goto error;

-   if (vm->reserved_vmid[vmhub] || (enforce_isolation && (vmhub == 
AMDGPU_GFXHUB(0 {
+   if (amdgpu_vmid_uses_reserved(vm, vmhub)) {
 r = amdgpu_vmid_grab_reserved(vm, ring, job, , fence);
 if (r || !id)
 goto error;
@@ -474,6 +474,19 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct 
amdgpu_ring *ring,
 return r;
 }

+/*
+ * amdgpu_vmid_uses_reserved - check if a VM will use a reserved VMID
+ * @vm: the VM to check
+ * @vmhub: the VMHUB which will be used
+ *
+ * Returns: True if the VM will use a reserved VMID.
+ */
+bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub)
+{
+   return vm->reserved_vmid[vmhub] ||
+   (enforce_isolation && (vmhub == AMDGPU_GFXHUB(0)));
+}
+
 int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
unsigned vmhub)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
index fa8c42c83d5d..240fa6751260 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
@@ -78,6 +78,7 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv,

 bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
struct amdgpu_vmid *id);
+bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub);
 int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
 unsigned vmhub);
 void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
--
2.34.1

[PATCH 1/2] drm/amdgpu: fix using the reserved VMID with gang submit

[Christian König]

We need to ensure that even when using a reserved VMID that the gang
members can still run in parallel.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 21 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c| 36 --
 3 files changed, 45 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1f71c7b98d77..e28fc07c7dbc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1450,6 +1450,7 @@ u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device 
*adev,
u32 reg);
 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
u32 reg, u32 v);
+struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev);
 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
struct dma_fence *gang);
 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d549de26f931..94a6c0b1ae8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -6532,6 +6532,22 @@ void amdgpu_device_pcie_port_wreg(struct amdgpu_device 
*adev,
spin_unlock_irqrestore(>pcie_idx_lock, flags);
 }
 
+/**
+ * amdgpu_device_get_gang - return a reference to the current gang
+ * @adev: amdgpu_device pointer
+ *
+ * Returns: A new reference to the current gang leader.
+ */
+struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev)
+{
+   struct dma_fence *fence;
+
+   rcu_read_lock();
+   fence = dma_fence_get_rcu_safe(>gang_submit);
+   rcu_read_unlock();
+   return fence;
+}
+
 /**
  * amdgpu_device_switch_gang - switch to a new gang
  * @adev: amdgpu_device pointer
@@ -6548,10 +6564,7 @@ struct dma_fence *amdgpu_device_switch_gang(struct 
amdgpu_device *adev,
 
do {
dma_fence_put(old);
-   rcu_read_lock();
-   old = dma_fence_get_rcu_safe(>gang_submit);
-   rcu_read_unlock();
-
+   old = amdgpu_device_get_gang(adev);
if (old == gang)
break;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 3d7fcdeaf8cf..b5b9d4f40f53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -290,18 +290,36 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
 !dma_fence_is_signaled((*id)->last_flush))) {
struct dma_fence *tmp;
 
-   /* Don't use per engine and per process VMID at the same time */
-   if (adev->vm_manager.concurrent_flush)
-   ring = NULL;
-
-   /* to prevent one context starved by another context */
-   (*id)->pd_gpu_addr = 0;
-   tmp = amdgpu_sync_peek_fence(&(*id)->active, ring);
-   if (tmp) {
+   /* Wait for the gang to be assembled before using a
+* reserved VMID or otherwise the gang could deadlock.
+*/
+   tmp = amdgpu_device_get_gang(adev);
+   if (!dma_fence_is_signaled(tmp) && tmp != job->gang_submit) {
*id = NULL;
-   *fence = dma_fence_get(tmp);
+   *fence = tmp;
return 0;
}
+   dma_fence_put(tmp);
+
+   /* Make sure the id is owned by the gang before proceeding */
+   if (!job->gang_submit ||
+   (*id)->owner != vm->immediate.fence_context) {
+
+   /* Don't use per engine and per process VMID at the
+* same time
+*/
+   if (adev->vm_manager.concurrent_flush)
+   ring = NULL;
+
+   /* to prevent one context starved by another context */
+   (*id)->pd_gpu_addr = 0;
+   tmp = amdgpu_sync_peek_fence(&(*id)->active, ring);
+   if (tmp) {
+   *id = NULL;
+   *fence = dma_fence_get(tmp);
+   return 0;
+   }
+   }
needs_flush = true;
}
 
-- 
2.34.1

[PATCH 2/2] drm/amdgpu: reject gang submit on reserved VMIDs

[Christian König]

A gang submit won't work if the VMID is reserved and we can't flush out
VM changes from multiple engines at the same time.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 15 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 15 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h |  1 +
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index ec888fc6ead8..916b6b8cf7d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1093,6 +1093,21 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser 
*p)
unsigned int i;
int r;
 
+   /*
+* We can't use gang submit on with reserved VMIDs when the VM changes
+* can't be invalidated by more than one engine at the same time.
+*/
+   if (p->gang_size > 1 && !p->adev->vm_manager.concurrent_flush) {
+   for (i = 0; i < p->gang_size; ++i) {
+   struct drm_sched_entity *entity = p->entities[i];
+   struct drm_gpu_scheduler *sched = entity->rq->sched;
+   struct amdgpu_ring *ring = to_amdgpu_ring(sched);
+
+   if (amdgpu_vmid_uses_reserved(vm, ring->vm_hub))
+   return -EINVAL;
+   }
+   }
+
r = amdgpu_vm_clear_freed(adev, vm, NULL);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index b5b9d4f40f53..b6a8bddada4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -424,7 +424,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct 
amdgpu_ring *ring,
if (r || !idle)
goto error;
 
-   if (vm->reserved_vmid[vmhub] || (enforce_isolation && (vmhub == 
AMDGPU_GFXHUB(0 {
+   if (amdgpu_vmid_uses_reserved(vm, vmhub)) {
r = amdgpu_vmid_grab_reserved(vm, ring, job, , fence);
if (r || !id)
goto error;
@@ -474,6 +474,19 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct 
amdgpu_ring *ring,
return r;
 }
 
+/*
+ * amdgpu_vmid_uses_reserved - check if a VM will use a reserved VMID
+ * @vm: the VM to check
+ * @vmhub: the VMHUB which will be used
+ *
+ * Returns: True if the VM will use a reserved VMID.
+ */
+bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub)
+{
+   return vm->reserved_vmid[vmhub] ||
+   (enforce_isolation && (vmhub == AMDGPU_GFXHUB(0)));
+}
+
 int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
   unsigned vmhub)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
index fa8c42c83d5d..240fa6751260 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
@@ -78,6 +78,7 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv,
 
 bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
   struct amdgpu_vmid *id);
+bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub);
 int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
unsigned vmhub);
 void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
-- 
2.34.1

Fix for reserved VMID handling together with gang submit

[Christian König]

Hey Alex,

I've worked on this back in January but never found time to finish it.

Vitaly already tested the patches on the CI system with some test cases
back then.

Thanks,
Christian.

[PATCH] drm/amdgpu/vcn: port mmsch ctx table size fix from jpeg v4

[Jane Jian]

add jpeg table size to ctx table size rather than override it

Signed-off-by: Jane Jian 
---
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c 
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 04d8966423de..0edfb7754768 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -202,7 +202,7 @@ static int jpeg_v4_0_3_start_sriov(struct amdgpu_device 
*adev)
 
memset(, 0, sizeof(struct mmsch_v4_0_3_init_header));
header.version = MMSCH_VERSION;
-   header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 
2;
+   header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE);
 
table_loc = (uint32_t *)table->cpu_addr;
table_loc += header.total_size;
-- 
2.34.1

[PATCH] drm/amd: force min_input_signal to 0 on Framework AMD 13/16

[Thomas Weißschuh]

The value of "min_input_signal" returned from ATIF on a Framework AMD 13
is "12". This leads to a fairly bright minimum display backlight.

Introduce a quirk to override "min_input_signal" to "0" which leads to a
much lower minimum brightness, which is still readable even in daylight.

Tested on a Framework AMD 13 BIOS 3.05 and Framework AMD 16.

Link: https://community.frame.work/t/25711/9
Link: https://community.frame.work/t/47036
Signed-off-by: Thomas Weißschuh 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 35 
 1 file changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 7099ff9cf8c5..b481889f7491 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -130,6 +131,35 @@ static struct amdgpu_acpi_priv {
struct amdgpu_atcs atcs;
 } amdgpu_acpi_priv;
 
+struct amdgpu_acpi_quirks {
+   bool ignore_min_input_signal;
+};
+
+static const struct dmi_system_id amdgpu_acpi_quirk_table[] = {
+   {
+   /* the Framework Laptop 13 (AMD Ryzen) and 16 (AMD Ryzen) */
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "Framework"),
+   DMI_MATCH(DMI_PRODUCT_NAME, "AMD Ryzen"),
+   DMI_MATCH(DMI_PRODUCT_FAMILY, "Laptop"),
+   },
+   .driver_data = &(struct amdgpu_acpi_quirks) {
+   .ignore_min_input_signal = true,
+   },
+   },
+   {}
+};
+
+static const struct amdgpu_acpi_quirks *amdgpu_acpi_get_quirks(void)
+{
+   const struct dmi_system_id *dmi_id;
+
+   dmi_id = dmi_first_match(amdgpu_acpi_quirk_table);
+   if (!dmi_id)
+   return NULL;
+   return dmi_id->driver_data;
+}
+
 /* Call the ATIF method
  */
 /**
@@ -1388,6 +1418,7 @@ bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device 
*adev)
  */
 void amdgpu_acpi_detect(void)
 {
+   const struct amdgpu_acpi_quirks *quirks = amdgpu_acpi_get_quirks();
struct amdgpu_atif *atif = _acpi_priv.atif;
struct amdgpu_atcs *atcs = _acpi_priv.atcs;
struct pci_dev *pdev = NULL;
@@ -1429,6 +1460,10 @@ void amdgpu_acpi_detect(void)
ret);
atif->backlight_caps.caps_valid = false;
}
+   if (quirks && quirks->ignore_min_input_signal) {
+   DRM_INFO("amdgpu_acpi quirk: min_input_signal=0\n");
+   atif->backlight_caps.min_input_signal = 0;
+   }
} else {
atif->backlight_caps.caps_valid = false;
}

---
base-commit: 83a7eefedc9b56fe7bfeff13b6c7356688ffa670
change-id: 20240610-amdgpu-min-backlight-quirk-8402fd8e736a

Best regards,
-- 
Thomas Weißschuh 

Re: [PATCH] drm/amd: force min_input_signal to 0 on Framework AMD 13/16

[Thomas Weißschuh]

On 2024-06-10 14:58:02+, Mario Limonciello wrote:
> +Kieran
> 
> On 6/10/2024 14:26, Thomas Weißschuh wrote:
> > The value of "min_input_signal" returned from ATIF on a Framework AMD 13
> > is "12". This leads to a fairly bright minimum display backlight.
> > 
> > Introduce a quirk to override "min_input_signal" to "0" which leads to a
> > much lower minimum brightness, which is still readable even in daylight.
> > 
> > Tested on a Framework AMD 13 BIOS 3.05 and Framework AMD 16.
> > 
> > Link: https://community.frame.work/t/25711/9
> > Link: https://community.frame.work/t/47036
> > Signed-off-by: Thomas Weißschuh 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 35 
> > 
> >   1 file changed, 35 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > index 7099ff9cf8c5..b481889f7491 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > @@ -25,6 +25,7 @@
> >   #include 
> >   #include 
> >   #include 
> > +#include 
> >   #include 
> >   #include 
> >   #include 
> > @@ -130,6 +131,35 @@ static struct amdgpu_acpi_priv {
> > struct amdgpu_atcs atcs;
> >   } amdgpu_acpi_priv;
> > +struct amdgpu_acpi_quirks {
> > +   bool ignore_min_input_signal;
> > +};
> > +
> > +static const struct dmi_system_id amdgpu_acpi_quirk_table[] = {
> > +   {
> > +   /* the Framework Laptop 13 (AMD Ryzen) and 16 (AMD Ryzen) */
> > +   .matches = {
> > +   DMI_MATCH(DMI_SYS_VENDOR, "Framework"),
> > +   DMI_MATCH(DMI_PRODUCT_NAME, "AMD Ryzen"),
> > +   DMI_MATCH(DMI_PRODUCT_FAMILY, "Laptop"),
> > +   },
> 
> Two problems I see:
> 
> 1) This really "should" be fixed in the BIOS. I added Kieran to the thread
> for comments if that's viable.

Agreed!

> 2) IMO this is going to match too liberally across all potential Framework
> models.  If they introduce a refreshed motherboard for either product then
> the quirk would apply to both products when we don't know that such a
> deficiency would exist.

Also agreed.
In addition to be really specific this should also match by display type
(via EDID?).

So far this was only tested with the matte panel.
(I forgot to mention that, sorry)

> You can reference drivers/platform/x86/amd/pmc/pmc-quirks.c for what we used
> for a quirk that was matching against a single product and single BIOS.

Will do for the next revision, but let's gather some feedback first.

> But FWIW if that issue isn't fixed in the next BIOS I think we'll end up
> needing to tear out the BIOS string match and match just the platform.

I'm wondering what the longterm strategy will have to be.
Given that there are different kinds of displays, and new ones will be
released, each new display type will require an update to the firmware.

When there are no firmware updates for a device anymore, but new,
compatible displays are released, then the kernel will need the quirks
again.

> > +   .driver_data = &(struct amdgpu_acpi_quirks) {
> > +   .ignore_min_input_signal = true,
> > +   },
> > +   },
> > +   {}
> > +};
> > +
> > +static const struct amdgpu_acpi_quirks *amdgpu_acpi_get_quirks(void)
> > +{
> > +   const struct dmi_system_id *dmi_id;
> > +
> > +   dmi_id = dmi_first_match(amdgpu_acpi_quirk_table);
> > +   if (!dmi_id)
> > +   return NULL;
> > +   return dmi_id->driver_data;
> > +}
> > +
> >   /* Call the ATIF method
> >*/
> >   /**
> > @@ -1388,6 +1418,7 @@ bool amdgpu_acpi_should_gpu_reset(struct 
> > amdgpu_device *adev)
> >*/
> >   void amdgpu_acpi_detect(void)
> >   {
> > +   const struct amdgpu_acpi_quirks *quirks = amdgpu_acpi_get_quirks();
> > struct amdgpu_atif *atif = _acpi_priv.atif;
> > struct amdgpu_atcs *atcs = _acpi_priv.atcs;
> > struct pci_dev *pdev = NULL;
> > @@ -1429,6 +1460,10 @@ void amdgpu_acpi_detect(void)
> > ret);
> > atif->backlight_caps.caps_valid = false;
> > }
> > +   if (quirks && quirks->ignore_min_input_signal) {
> > +   DRM_INFO("amdgpu_acpi quirk: min_input_signal=0\n");
> > +   atif->backlight_caps.min_input_signal = 0;
> > +   }
> > } else {
> > atif->backlight_caps.caps_valid = false;
> > }
> > 
> > ---
> > base-commit: 83a7eefedc9b56fe7bfeff13b6c7356688ffa670
> > change-id: 20240610-amdgpu-min-backlight-quirk-8402fd8e736a
> > 
> > Best regards,
> 

Re: [PATCH] Revert "drm/amdgpu: init iommu after amdkfd device init"

[Armin Wolf]

Am 04.06.24 um 20:28 schrieb Deucher, Alexander:


[AMD Official Use Only - AMD Internal Distribution Only]


-Original Message-
From: Kuehling, Felix 
Sent: Tuesday, June 4, 2024 2:25 PM
To: Armin Wolf ; Deucher, Alexander
; Koenig, Christian
; Pan, Xinhui ;
gre...@linuxfoundation.org; sas...@kernel.org
Cc: sta...@vger.kernel.org; bkau...@gmail.com; Zhang, Yifan
; Liang, Prike ; dri-
de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] Revert "drm/amdgpu: init iommu after amdkfd device
init"


On 2024-06-03 18:19, Armin Wolf wrote:

Am 23.05.24 um 19:30 schrieb Armin Wolf:


This reverts commit 56b522f4668167096a50c39446d6263c96219f5f.

A user reported that this commit breaks the integrated gpu of his
notebook, causing a black screen. He was able to bisect the
problematic commit and verified that by reverting it the notebook works

again.

He also confirmed that kernel 6.8.1 also works on his device, so the
upstream commit itself seems to be ok.

An amdgpu developer (Alex Deucher) confirmed that this patch should
have never been ported to 5.15 in the first place, so revert this
commit from the 5.15 stable series.

Hi,

what is the status of this?

Which branch is this for? This patch won't apply to anything after Linux 6.5.

It's applicable to 5.15 stable only.  The original patch caused a regression on 
5.15 so probably should not have been applied there.

Alex


Correct, and i would be very grateful if this regression could be resolved in 
the near future.
The user already wrote a blog post about the whole issue, see here:

https://bkhome.org/news/202405/kernel-amd-gpu-disaster-fixed.html

Thanks,
Armin Wolf


Support for IOMMUv2 was removed from amdgpu in Linux 6.6 by:

commit c99a2e7ae291e5b19b60443eb6397320ef9e8571
Author: Alex Deucher 
Date:   Fri Jul 28 12:20:12 2023 -0400

  drm/amdkfd: drop IOMMUv2 support

  Now that we use the dGPU path for all APUs, drop the
  IOMMUv2 support.

  v2: drop the now unused queue manager functions for gfx7/8 APUs

  Reviewed-by: Felix Kuehling 
  Acked-by: Christian König 
  Tested-by: Mike Lothian 
  Signed-off-by: Alex Deucher 

Regards,
Felix



Armin Wolf


Reported-by: Barry Kauler 
Signed-off-by: Armin Wolf 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 
   1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 222a1d9ecf16..5f6c32ec674d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2487,6 +2487,10 @@ static int amdgpu_device_ip_init(struct
amdgpu_device *adev)
   if (r)
   goto init_failed;

+r = amdgpu_amdkfd_resume_iommu(adev);
+if (r)
+goto init_failed;
+
   r = amdgpu_device_ip_hw_init_phase1(adev);
   if (r)
   goto init_failed;
@@ -2525,10 +2529,6 @@ static int amdgpu_device_ip_init(struct
amdgpu_device *adev)
   if (!adev->gmc.xgmi.pending_reset)
   amdgpu_amdkfd_device_init(adev);

-r = amdgpu_amdkfd_resume_iommu(adev);
-if (r)
-goto init_failed;
-
   amdgpu_fru_get_product_info(adev);

   init_failed:
--
2.39.2