[PATCH 07/16] drm/amd/display: always blank stream before disable crtc
From: Fudongwang
Garbage will show due to dig is on. So blank stream needed.
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Fudongwang
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c| 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 036cb7e9b5bb..59b2e87317e3 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -519,15 +519,18 @@ static void dcn31_reset_back_end_for_pipe(
dc->hwss.set_abm_immediate_disable(pipe_ctx);
- if ((!pipe_ctx->stream->dpms_off ||
pipe_ctx->stream->link->link_status.link_active)
- && pipe_ctx->stream->sink &&
pipe_ctx->stream->sink->edid_caps.panel_patch.blankstream_before_otg_off) {
+ link = pipe_ctx->stream->link;
+
+ if ((!pipe_ctx->stream->dpms_off || link->link_status.link_active) &&
+ (link->connector_signal == SIGNAL_TYPE_EDP))
dc->hwss.blank_stream(pipe_ctx);
- }
pipe_ctx->stream_res.tg->funcs->set_dsc_config(
pipe_ctx->stream_res.tg,
OPTC_DSC_DISABLED, 0, 0);
+
pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
+
pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg,
false);
if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
@@ -539,7 +542,6 @@ static void dcn31_reset_back_end_for_pipe(
pipe_ctx->stream_res.tg->funcs->set_drr(
pipe_ctx->stream_res.tg, NULL);
- link = pipe_ctx->stream->link;
/* DPMS may already disable or */
/* dpms_off status is incorrect due to fastboot
* feature. When system resume from S4 with second
--
2.46.1
[PATCH 11/16] drm/amd/display: Handle dml allocation failure to avoid crash
From: Ryan Seto
[Why]
In the case where a dml allocation fails for any reason, the
current state's dml contexts would no longer be valid. Then
subsequent calls dc_state_copy_internal would shallow copy
invalid memory and if the new state was released, a double
free would occur.
[How]
Reset dml pointers in new_state to NULL and avoid invalid
pointer
Cc: sta...@vger.kernel.org
Reviewed-by: Dillon Varone
Signed-off-by: Ryan Seto
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index 2597e3fd562b..e006f816ff2f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -265,6 +265,9 @@ struct dc_state *dc_state_create_copy(struct dc_state
*src_state)
dc_state_copy_internal(new_state, src_state);
#ifdef CONFIG_DRM_AMD_DC_FP
+ new_state->bw_ctx.dml2 = NULL;
+ new_state->bw_ctx.dml2_dc_power_source = NULL;
+
if (src_state->bw_ctx.dml2 &&
!dml2_create_copy(&new_state->bw_ctx.dml2,
src_state->bw_ctx.dml2)) {
dc_state_release(new_state);
--
2.46.1
[PATCH 06/16] drm/amd/display: Read DP tunneling support only for DPIA endpoints
From: Aurabindo Pillai
Unconditionally reading DP tunneling support results in extraneous
errors messages on certain devices. Fix this by guarding the DPCD read
for DP tunneling support for USB4 DPIA endpoints.
Reviewed-by: Meenakshikumar Somasundaram
Signed-off-by: Aurabindo Pillai
Signed-off-by: Hamza Mahfooz
---
.../amd/display/dc/link/protocols/link_dp_capability.c| 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 72ef0c3a7ebd..9dabaf682171 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -1633,9 +1633,11 @@ static bool retrieve_link_cap(struct dc_link *link)
}
/* Read DP tunneling information. */
- status = dpcd_get_tunneling_device_data(link);
- if (status != DC_OK)
- dm_error("%s: Read tunneling device data failed.\n", __func__);
+ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
+ status = dpcd_get_tunneling_device_data(link);
+ if (status != DC_OK)
+ dm_error("%s: Read tunneling device data failed.\n",
__func__);
+ }
dpcd_set_source_specific_data(link);
/* Sink may need to configure internals based on vendor, so allow some
--
2.46.1
[PATCH 15/16] drm/amd/display: Adjust VSDB parser for replay feature
From: Rodrigo Siqueira
At some point, the IEEE ID identification for the replay check in the
AMD EDID was added. However, this check causes the following
out-of-bounds issues when using KASAN:
[ 27.804016] BUG: KASAN: slab-out-of-bounds in
amdgpu_dm_update_freesync_caps+0xefa/0x17a0 [amdgpu]
[ 27.804788] Read of size 1 at addr 8881647fdb00 by task systemd-udevd/383
...
[ 27.821207] Memory state around the buggy address:
[ 27.821215] 8881647fda00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00
[ 27.821224] 8881647fda80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00
[ 27.821234] >8881647fdb00: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
fc
[ 27.821243]^
[ 27.821250] 8881647fdb80: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
fc
[ 27.821259] 8881647fdc00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00
[ 27.821268]
==
This is caused because the ID extraction happens outside of the range of
the edid lenght. This commit addresses this issue by considering the
amd_vsdb_block size.
Cc: ChiaHsuan Chung
Reviewed-by: Leo Li
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1d47719e7af1..8381afbe6e4d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -12096,7 +12096,7 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector
*aconnector,
break;
}
- while (j < EDID_LENGTH) {
+ while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) {
struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block
*)&edid_ext[j];
unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) |
(amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
--
2.46.1
[PATCH 13/16] drm/amd/display: update pipe selection policy to check head pipe
From: Yihan Zhu
[Why]
No check on head pipe during the dml to dc hw mapping will allow illegal
pipe usage. This will result in a wrong pipe topology to cause mpcc tree
totally mess up then cause a display hang.
[How]
Avoid to use the pipe is head in all check and avoid ODM slice during
preferred pipe check.
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Yihan Zhu
Signed-off-by: Hamza Mahfooz
---
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
index 6eccf0241d85..9be9ed7e01d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
@@ -258,12 +258,23 @@ static unsigned int find_preferred_pipe_candidates(const
struct dc_state *existi
* However this condition comes with a caveat. We need to ignore pipes
that will
* require a change in OPP but still have the same stream id. For
example during
* an MPC to ODM transiton.
+*
+* Adding check to avoid pipe select on the head pipe by utilizing dc
resource
+* helper function resource_get_primary_dpp_pipe and comparing the pipe
index.
*/
if (existing_state) {
for (i = 0; i < pipe_count; i++) {
if (existing_state->res_ctx.pipe_ctx[i].stream &&
existing_state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) {
+ struct pipe_ctx *head_pipe =
+
resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]);
+
+ // we should always respect the head pipe from
selection
+ if (head_pipe && head_pipe->pipe_idx == i)
+ continue;
if
(existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&
-
existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i)
+
existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i &&
+
(existing_state->res_ctx.pipe_ctx[i].prev_odm_pipe ||
+
existing_state->res_ctx.pipe_ctx[i].next_odm_pipe))
continue;
preferred_pipe_candidates[num_preferred_candidates++] = i;
@@ -292,6 +303,12 @@ static unsigned int find_last_resort_pipe_candidates(const
struct dc_state *exis
*/
if (existing_state) {
for (i = 0; i < pipe_count; i++) {
+ struct pipe_ctx *head_pipe =
+
resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]);
+
+ // we should always respect the head pipe from selection
+ if (head_pipe && head_pipe->pipe_idx == i)
+ continue;
if ((existing_state->res_ctx.pipe_ctx[i].plane_res.hubp
&&
existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) ||
existing_state->res_ctx.pipe_ctx[i].stream_res.tg)
--
2.46.1
[PATCH 16/16] drm/amd/display: 3.2.309
From: Aric Cyr
This version brings along the following:
- DML2 fixes
- DP fixes
- DPMS fix
- HPD fixes
- Misc cleanup
- ODM fix
- Replay fix
- SPL fix
Reviewed-by: Leo Li
Signed-off-by: Aric Cyr
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
.../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 3 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 35 +++
3 files changed, 32 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index ad9ce3d0bfcf..e143fab00a86 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -55,7 +55,7 @@ struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
-#define DC_VER "3.2.308"
+#define DC_VER "3.2.309"
#define MAX_SURFACES 3
#define MAX_PLANES 6
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 59b2e87317e3..03ba01f4ace1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -653,7 +653,8 @@ static void dmub_abm_set_backlight(struct dc_context *dc,
cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT;
cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp =
backlight_level_params->frame_ramp;
cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level =
backlight_level_params->backlight_pwm_u16_16;
- cmd.abm_set_backlight.abm_set_backlight_data.backlight_control_type =
backlight_level_params->control_type;
+ cmd.abm_set_backlight.abm_set_backlight_data.backlight_control_type =
+ (enum dmub_backlight_control_type)
backlight_level_params->control_type;
cmd.abm_set_backlight.abm_set_backlight_data.min_luminance =
backlight_level_params->min_luminance;
cmd.abm_set_backlight.abm_set_backlight_data.max_luminance =
backlight_level_params->max_luminance;
cmd.abm_set_backlight.abm_set_backlight_data.min_backlight_pwm =
backlight_level_params->min_backlight_pwm;
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index a9b90fa00b88..b800a507d1e0 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -4426,6 +4426,24 @@ struct dmub_rb_cmd_abm_set_pipe {
struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
};
+/**
+ * Type of backlight control method to be used by ABM module
+ */
+enum dmub_backlight_control_type {
+ /**
+* PWM Backlight control
+*/
+ DMU_BACKLIGHT_CONTROL_PWM = 0,
+ /**
+* VESA Aux-based backlight control
+*/
+ DMU_BACKLIGHT_CONTROL_VESA_AUX = 1,
+ /**
+* AMD DPCD Aux-based backlight control
+*/
+ DMU_BACKLIGHT_CONTROL_AMD_AUX = 2,
+};
+
/**
* Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
*/
@@ -4452,18 +4470,23 @@ struct dmub_cmd_abm_set_backlight_data {
*/
uint8_t panel_mask;
+ /**
+* AUX HW Instance.
+*/
+ uint8_t aux_inst;
+
+ /**
+* Explicit padding to 4 byte boundary.
+*/
+ uint8_t pad[1];
+
/**
* Backlight control type.
* Value 0 is PWM backlight control.
* Value 1 is VAUX backlight control.
* Value 2 is AMD DPCD AUX backlight control.
*/
- uint8_t backlight_control_type;
-
- /**
-* AUX HW instance.
-*/
- uint8_t aux_inst;
+ enum dmub_backlight_control_type backlight_control_type;
/**
* Minimum luminance in nits.
--
2.46.1
[PATCH 14/16] drm/amd/display: Remove unused code
From: Rodrigo Siqueira
This commit removes a legacy debug_defaults_diags struct.
Reviewed-by: Leo Li
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Hamza Mahfooz
---
.../amd/display/dc/resource/dcn10/dcn10_resource.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
index 4f1bd71b9ad9..770a380cc03d 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
@@ -559,17 +559,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.using_dml2 = false,
};
-static const struct dc_debug_options debug_defaults_diags = {
- .disable_dmcu = false,
- .force_abm_enable = false,
- .clock_trace = true,
- .disable_stutter = true,
- .disable_pplib_clock_request = true,
- .disable_pplib_wm_range = true,
- .underflow_assert_delay_us = 0x,
- .enable_legacy_fast_update = true,
-};
-
static void dcn10_dpp_destroy(struct dpp **dpp)
{
kfree(TO_DCN10_DPP(*dpp));
@@ -1398,8 +1387,6 @@ static bool dcn10_resource_construct(
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
- else
- dc->debug = debug_defaults_diags;
/*
* Create resources *
--
2.46.1
[PATCH 12/16] drm/amd/display: Require minimum VBlank size for stutter optimization
From: Dillon Varone
If the nominal VBlank is too small, optimizing for stutter can cause
the prefetch bandwidth to increase drasticaly, resulting in higher
clock and power requirements. Only optimize if it is >3x the stutter
latency.
Cc: sta...@vger.kernel.org
Reviewed-by: Austin Zheng
Signed-off-by: Dillon Varone
Signed-off-by: Hamza Mahfooz
---
.../dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
index 5a09dd298e6f..92269f0e50ed 100644
---
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+++
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
@@ -8,6 +8,7 @@
#include "dml2_pmo_dcn4_fams2.h"
static const double MIN_VACTIVE_MARGIN_PCT = 0.25; // We need more than
non-zero margin because DET buffer granularity can alter vactive latency hiding
+static const double MIN_BLANK_STUTTER_FACTOR = 3.0;
static const struct dml2_pmo_pstate_strategy base_strategy_list_1_display[] = {
// VActive Preferred
@@ -2140,6 +2141,7 @@ bool pmo_dcn4_fams2_init_for_stutter(struct
dml2_pmo_init_for_stutter_in_out *in
struct dml2_pmo_instance *pmo = in_out->instance;
bool stutter_period_meets_z8_eco = true;
bool z8_stutter_optimization_too_expensive = false;
+ bool stutter_optimization_too_expensive = false;
double line_time_us, vblank_nom_time_us;
unsigned int i;
@@ -2161,10 +2163,15 @@ bool pmo_dcn4_fams2_init_for_stutter(struct
dml2_pmo_init_for_stutter_in_out *in
line_time_us =
(double)in_out->base_display_config->display_config.stream_descriptors[i].timing.h_total
/
(in_out->base_display_config->display_config.stream_descriptors[i].timing.pixel_clock_khz
* 1000) * 100;
vblank_nom_time_us = line_time_us *
in_out->base_display_config->display_config.stream_descriptors[i].timing.vblank_nom;
- if (vblank_nom_time_us <
pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us) {
+ if (vblank_nom_time_us <
pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us *
MIN_BLANK_STUTTER_FACTOR) {
z8_stutter_optimization_too_expensive = true;
break;
}
+
+ if (vblank_nom_time_us <
pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us *
MIN_BLANK_STUTTER_FACTOR) {
+ stutter_optimization_too_expensive = true;
+ break;
+ }
}
pmo->scratch.pmo_dcn4.num_stutter_candidates = 0;
@@ -2180,7 +2187,7 @@ bool pmo_dcn4_fams2_init_for_stutter(struct
dml2_pmo_init_for_stutter_in_out *in
pmo->scratch.pmo_dcn4.z8_vblank_optimizable = false;
}
- if
(pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us >
0) {
+ if (!stutter_optimization_too_expensive &&
pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us >
0) {
pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.num_stutter_candidates]
= (unsigned
int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us;
pmo->scratch.pmo_dcn4.num_stutter_candidates++;
}
--
2.46.1
[PATCH 08/16] drm/amd/display: disabling p-state checks for DCN31 and DCN314
From: Emily Nie
[Why]
IGT displays Dmesg warnings which are likely false
[How]
Disabling p-state checks leading to this warning for DCN31 and DCN314
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Emily Nie
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++
.../dc/resource/dcn31/dcn31_resource.c| 2 +-
.../dc/resource/dcn314/dcn314_resource.c | 2 +-
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fdc1d2d1afd9..1d47719e7af1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1307,6 +1307,29 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
adev->dm.dmcub_fw_version);
+ /* Keeping sanity checks off if
+* DCN31 >= 4.0.59.0
+* DCN314 >= 8.0.16.0
+* Otherwise, turn on sanity checks
+*/
+ switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
+ case IP_VERSION(3, 1, 2):
+ case IP_VERSION(3, 1, 3):
+ if (adev->dm.dmcub_fw_version &&
+ adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
+ adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59))
+ adev->dm.dc->debug.sanity_checks = true;
+ break;
+ case IP_VERSION(3, 1, 4):
+ if (adev->dm.dmcub_fw_version &&
+ adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
+ adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16))
+ adev->dm.dc->debug.sanity_checks = true;
+ break;
+ default:
+ break;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
index f71a5b8286b2..c16cf1c8f7f9 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
@@ -868,7 +868,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.max_downscale_src_width = 4096,/*upto true 4K*/
.disable_pplib_wm_range = false,
.scl_reset_length10 = true,
- .sanity_checks = true,
+ .sanity_checks = false,
.underflow_assert_delay_us = 0x,
.dwb_fi_phase = -1, // -1 = disable,
.dmub_command_table = true,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
index 8aa10da68432..c0f48c78e968 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
@@ -888,7 +888,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.max_downscale_src_width = 4096,/*upto true 4k*/
.disable_pplib_wm_range = false,
.scl_reset_length10 = true,
- .sanity_checks = true,
+ .sanity_checks = false,
.underflow_assert_delay_us = 0x,
.dwb_fi_phase = -1, // -1 = disable,
.dmub_command_table = true,
--
2.46.1
[PATCH 03/16] drm/amd/display: Change some variable name of psr
From: Tom Chung
Panel Replay feature may also use the same variable with PSR.
Change the variable name and make it not specify for PSR.
Reviewed-by: Leo Li
Signed-off-by: Tom Chung
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 +--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +-
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 2 +-
.../display/amdgpu_dm/amdgpu_dm_irq_params.h | 2 +-
4 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7a1b5d5beeaf..570640c25b4b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6790,7 +6790,7 @@ create_stream_for_sink(struct drm_connector *connector,
if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)
tf = TRANSFER_FUNC_GAMMA_22;
mod_build_vsc_infopacket(stream, &stream->vsc_infopacket,
stream->output_color_space, tf);
- aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
+ aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
}
finish:
@@ -9016,7 +9016,7 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
* during the PSR-SU was disabled.
*/
if (acrtc_state->stream->link->psr_settings.psr_version
>= DC_PSR_VERSION_SU_1 &&
- acrtc_attach->dm_irq_params.allow_psr_entry &&
+ acrtc_attach->dm_irq_params.allow_sr_entry &&
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
#endif
@@ -9251,27 +9251,27 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
}
}
- /* Decrement skip count when PSR is enabled and we're doing
fast updates. */
+ /* Decrement skip count when SR is enabled and we're doing fast
updates. */
if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
struct amdgpu_dm_connector *aconn =
(struct amdgpu_dm_connector
*)acrtc_state->stream->dm_stream_context;
- if (aconn->psr_skip_count > 0)
- aconn->psr_skip_count--;
+ if (aconn->sr_skip_count > 0)
+ aconn->sr_skip_count--;
- /* Allow PSR when skip count is 0. */
- acrtc_attach->dm_irq_params.allow_psr_entry =
!aconn->psr_skip_count;
+ /* Allow SR when skip count is 0. */
+ acrtc_attach->dm_irq_params.allow_sr_entry =
!aconn->sr_skip_count;
/*
-* If sink supports PSR SU, there is no need to rely on
-* a vblank event disable request to enable PSR. PSR SU
+* If sink supports PSR SU/Panel Replay, there is no
need to rely on
+* a vblank event disable request to enable PSR/RP. PSR
SU/RP
* can be enabled immediately once OS demonstrates an
* adequate number of fast atomic commits to notify KMD
* of update events. See `vblank_control_worker()`.
*/
if (acrtc_state->stream->link->psr_settings.psr_version
>= DC_PSR_VERSION_SU_1 &&
- acrtc_attach->dm_irq_params.allow_psr_entry &&
+ acrtc_attach->dm_irq_params.allow_sr_entry &&
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
#endif
@@ -9282,7 +9282,7 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
5)
amdgpu_dm_psr_enable(acrtc_state->stream);
} else {
- acrtc_attach->dm_irq_params.allow_psr_entry = false;
+ acrtc_attach->dm_irq_params.allow_sr_entry = false;
}
mutex_unlock(&dm->dc_lock);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 25e95775c45c..6464a8378387 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -727,7 +727,7 @@ struct amdgpu_dm_conn
[PATCH 10/16] drm/amd/display: Use region6 size in fw_meta_info
From: JinZe Xu
[Why]
If driver allocated region6 size is not same as the size in firmware,
dmcub won't enable region6.
[How]
Use region6 size in dmcub_fw_meta instead of a constant value.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: JinZe Xu
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index db16066bc893..a3f3ff5d49ac 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -497,6 +497,7 @@ enum dmub_status
const struct dmub_fw_meta_info *fw_info;
uint32_t fw_state_size = DMUB_FW_STATE_SIZE;
uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;
+ uint32_t shared_state_size = DMUB_FW_HEADER_SHARED_STATE_SIZE;
uint32_t window_sizes[DMUB_WINDOW_TOTAL] = { 0 };
if (!dmub->sw_init)
@@ -514,6 +515,7 @@ enum dmub_status
fw_state_size = fw_info->fw_region_size;
trace_buffer_size = fw_info->trace_buffer_size;
+ shared_state_size = fw_info->shared_state_size;
/**
* If DM didn't fill in a version, then fill it in based on
@@ -534,7 +536,7 @@ enum dmub_status
window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size;
window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size;
window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = DMUB_SCRATCH_MEM_SIZE;
- window_sizes[DMUB_WINDOW_SHARED_STATE] =
DMUB_FW_HEADER_SHARED_STATE_SIZE;
+ window_sizes[DMUB_WINDOW_SHARED_STATE] =
max(DMUB_FW_HEADER_SHARED_STATE_SIZE, shared_state_size);
out->fb_size =
dmub_srv_calc_regions_for_memory_type(params, out,
window_sizes, DMUB_WINDOW_MEMORY_TYPE_FB);
--
2.46.1
[PATCH 04/16] drm/amd/display: Fix Panel Replay not update screen correctly
From: Tom Chung
[Why]
In certain use case such as KDE login screen, there will be no atomic
commit while do the frame update.
If the Panel Replay enabled, it will cause the screen not updated and
looks like system hang.
[How]
Delay few atomic commits before enabled the Panel Replay just like PSR.
Reviewed-by: Leo Li
Signed-off-by: Tom Chung
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 111 +-
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 5 +-
2 files changed, 59 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 570640c25b4b..fdc1d2d1afd9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8863,6 +8863,56 @@ static void amdgpu_dm_update_cursor(struct drm_plane
*plane,
}
}
+static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
+ const struct dm_crtc_state
*acrtc_state,
+ const u64 current_ts)
+{
+ struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
+ struct replay_settings *pr =
&acrtc_state->stream->link->replay_settings;
+ struct amdgpu_dm_connector *aconn =
+ (struct amdgpu_dm_connector
*)acrtc_state->stream->dm_stream_context;
+
+ if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
+ if (pr->config.replay_supported && !pr->replay_feature_enabled)
+ amdgpu_dm_link_setup_replay(acrtc_state->stream->link,
aconn);
+ else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
+!psr->psr_feature_enabled)
+ if (!aconn->disallow_edp_enter_psr)
+ amdgpu_dm_link_setup_psr(acrtc_state->stream);
+ }
+
+ /* Decrement skip count when SR is enabled and we're doing fast
updates. */
+ if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
+ (psr->psr_feature_enabled || pr->config.replay_supported)) {
+ if (aconn->sr_skip_count > 0)
+ aconn->sr_skip_count--;
+
+ /* Allow SR when skip count is 0. */
+ acrtc_attach->dm_irq_params.allow_sr_entry =
!aconn->sr_skip_count;
+
+ /*
+* If sink supports PSR SU/Panel Replay, there is no need to
rely on
+* a vblank event disable request to enable PSR/RP. PSR SU/RP
+* can be enabled immediately once OS demonstrates an
+* adequate number of fast atomic commits to notify KMD
+* of update events. See `vblank_control_worker()`.
+*/
+ if (acrtc_attach->dm_irq_params.allow_sr_entry &&
+#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
+ !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc)
&&
+#endif
+ (current_ts - psr->psr_dirty_rects_change_timestamp_ns) >
5) {
+ if (pr->replay_feature_enabled &&
!pr->replay_allow_active)
+ amdgpu_dm_replay_enable(acrtc_state->stream,
true);
+ if (psr->psr_version >= DC_PSR_VERSION_SU_1 &&
+ !psr->psr_allow_active &&
!aconn->disallow_edp_enter_psr)
+ amdgpu_dm_psr_enable(acrtc_state->stream);
+ }
+ } else {
+ acrtc_attach->dm_irq_params.allow_sr_entry = false;
+ }
+}
+
static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
struct drm_device *dev,
struct amdgpu_display_manager *dm,
@@ -9191,9 +9241,12 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
bundle->stream_update.abm_level =
&acrtc_state->abm_level;
mutex_lock(&dm->dc_lock);
- if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
-
acrtc_state->stream->link->psr_settings.psr_allow_active)
- amdgpu_dm_psr_disable(acrtc_state->stream);
+ if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
+ if
(acrtc_state->stream->link->replay_settings.replay_allow_active)
+ amdgpu_dm_replay_disable(acrtc_state->stream);
+ if
(acrtc_state->stream->link->psr_settings.psr_allow_active)
+ amdgpu_dm_psr_disable(acrtc_state->stream);
+ }
mute
[PATCH 09/16] drm/amd/display: Update SPL Taps Required For Integer Scaling
From: Austin Zheng
Number of taps is incorrectly being set when integer scaling is enabled.
Taps required when src_rect != dst_rect previously not considered.
Perform the calculations when integer scaling is enabled.
Set taps to 1 if the scaling ratio is 1:1.
Reviewed-by: Samson Tam
Signed-off-by: Austin Zheng
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
index a29a9f131e04..614276200aa0 100644
--- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
+++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
@@ -910,6 +910,16 @@ static void spl_get_taps_non_adaptive_scaler(
spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c - 1;
else
spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c;
+
+ if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz))
+ spl_scratch->scl_data.taps.h_taps = 1;
+ if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert))
+ spl_scratch->scl_data.taps.v_taps = 1;
+ if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c))
+ spl_scratch->scl_data.taps.h_taps_c = 1;
+ if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c))
+ spl_scratch->scl_data.taps.v_taps_c = 1;
+
}
/* Calculate optimal number of taps */
@@ -936,10 +946,7 @@ static bool spl_get_optimal_number_of_taps(
/* Disable adaptive scaler and sharpener when integer scaling is
enabled */
if (spl_in->scaling_quality.integer_scaling) {
- spl_scratch->scl_data.taps.h_taps = 1;
- spl_scratch->scl_data.taps.v_taps = 1;
- spl_scratch->scl_data.taps.v_taps_c = 1;
- spl_scratch->scl_data.taps.h_taps_c = 1;
+ spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps);
*enable_easf_v = false;
*enable_easf_h = false;
*enable_isharp = false;
--
2.46.1
[PATCH 02/16] drm/amd/display: Change parameters to fix certain compiler errors
From: Revalla Hari Krishna
[Why]
String literals must be assigned to const char pointers.
[How]
By adding const keyword to fix compilation errors.
Reviewed-by: Lohita Mudimela
Signed-off-by: Revalla Hari Krishna
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c | 2 +-
drivers/gpu/drm/amd/display/dc/dm_services.h| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
index 05df502a54f2..88cf47a5ea75 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
@@ -46,7 +46,7 @@
#include "clk_mgr.h"
__printf(3, 4)
-unsigned int snprintf_count(char *pbuf, unsigned int bufsize, char *fmt, ...)
+unsigned int snprintf_count(char *pbuf, unsigned int bufsize, const char *fmt,
...)
{
int ret_vsnprintf;
unsigned int chars_printed;
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h
b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 9405c47ee2a9..f81e5a4e1d6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -143,7 +143,7 @@ void generic_reg_wait(const struct dc_context *ctx,
unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
const char *func_name, int line);
-unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...);
+unsigned int snprintf_count(char *pBuf, unsigned int bufSize, const char *fmt,
...);
/* These macros need to be used with soc15 registers in order to retrieve
* the actual offset.
--
2.46.1
[PATCH 05/16] drm/amd/display: Adding flag for forced MST blocked discovery
From: Meenakshikumar Somasundaram
[Why]
Need a flag to force MST blocked discovery for certain branch devices.
[How]
Added a flag to force MST blocked discovery in struct dc_panel_patch.
Reviewed-by: PeiChen Huang
Reviewed-by: Wenjing Liu
Signed-off-by: Meenakshikumar Somasundaram
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 1fd030e3f4be..edf4df1d03b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -181,6 +181,7 @@ struct dc_panel_patch {
unsigned int disable_colorimetry;
uint8_t blankstream_before_otg_off;
bool oled_optimize_display_on;
+ unsigned int force_mst_blocked_discovery;
};
struct dc_edid_caps {
--
2.46.1
[PATCH 01/16] drm/amd/display: Refactor HPD IRQ error checking flow
From: Leon Huang
[Why]
HPD error status does not cover Replay desync error status
while executing autotests and CTS tests.
[How]
Refactor the checking flow, reporting the HPD error based on
different eDP feature.
Reviewed-by: Robin Chen
Signed-off-by: Leon Huang
Signed-off-by: Hamza Mahfooz
---
.../dc/link/protocols/link_dp_irq_handler.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
index 96bf135b6f05..48abeaa88678 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
@@ -221,21 +221,11 @@ static void handle_hpd_irq_replay_sink(struct dc_link
*link)
&replay_error_status.raw,
sizeof(replay_error_status.raw));
- link->replay_settings.config.replay_error_status.bits.LINK_CRC_ERROR =
- replay_error_status.bits.LINK_CRC_ERROR;
- link->replay_settings.config.replay_error_status.bits.DESYNC_ERROR =
- replay_configuration.bits.DESYNC_ERROR_STATUS;
-
link->replay_settings.config.replay_error_status.bits.STATE_TRANSITION_ERROR =
- replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS;
-
- if
(link->replay_settings.config.replay_error_status.bits.LINK_CRC_ERROR ||
-
link->replay_settings.config.replay_error_status.bits.DESYNC_ERROR ||
-
link->replay_settings.config.replay_error_status.bits.STATE_TRANSITION_ERROR) {
+ if (replay_error_status.bits.LINK_CRC_ERROR ||
+ replay_configuration.bits.DESYNC_ERROR_STATUS ||
+ replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS) {
bool allow_active;
- if
(link->replay_settings.config.replay_error_status.bits.DESYNC_ERROR)
- link->replay_settings.config.received_desync_error_hpd
= 1;
-
if
(link->replay_settings.config.force_disable_desync_error_check)
return;
--
2.46.1
[PATCH 00/16] DC Patches November 5, 2024
Cc: Daniel Wheeler Aric Cyr (1): drm/amd/display: 3.2.309 Aurabindo Pillai (1): drm/amd/display: Read DP tunneling support only for DPIA endpoints Austin Zheng (1): drm/amd/display: Update SPL Taps Required For Integer Scaling Dillon Varone (1): drm/amd/display: Require minimum VBlank size for stutter optimization Emily Nie (1): drm/amd/display: disabling p-state checks for DCN31 and DCN314 Fudongwang (1): drm/amd/display: always blank stream before disable crtc JinZe Xu (1): drm/amd/display: Use region6 size in fw_meta_info Leon Huang (1): drm/amd/display: Refactor HPD IRQ error checking flow Meenakshikumar Somasundaram (1): drm/amd/display: Adding flag for forced MST blocked discovery Revalla Hari Krishna (1): drm/amd/display: Change parameters to fix certain compiler errors Rodrigo Siqueira (2): drm/amd/display: Remove unused code drm/amd/display: Adjust VSDB parser for replay feature Ryan Seto (1): drm/amd/display: Handle dml allocation failure to avoid crash Tom Chung (2): drm/amd/display: Change some variable name of psr drm/amd/display: Fix Panel Replay not update screen correctly Yihan Zhu (1): drm/amd/display: update pipe selection policy to check head pipe .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 140 +++--- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 5 +- .../display/amdgpu_dm/amdgpu_dm_irq_params.h | 2 +- .../gpu/drm/amd/display/dc/core/dc_state.c| 3 + drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + .../dc/dcn10/dcn10_hw_sequencer_debug.c | 2 +- drivers/gpu/drm/amd/display/dc/dm_services.h | 2 +- .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 11 +- .../display/dc/dml2/dml2_dc_resource_mgmt.c | 19 ++- .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 13 +- .../dc/link/protocols/link_dp_capability.c| 8 +- .../dc/link/protocols/link_dp_irq_handler.c | 16 +- .../dc/resource/dcn10/dcn10_resource.c| 13 -- .../dc/resource/dcn31/dcn31_resource.c| 2 +- .../dc/resource/dcn314/dcn314_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 15 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 35 - .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 4 +- 20 files changed, 182 insertions(+), 115 deletions(-) -- 2.46.1
Re: [PATCH] drm/amd/display: fix hibernate entry for DCN35+
On 10/4/24 16:44, Alex Deucher wrote: On Fri, Oct 4, 2024 at 4:43 PM Hamza Mahfooz wrote: Since, two suspend-resume cycles are required to enter hibernate and, since we only need to enable idle optimizations in the first cycle (which is pretty much equivalent to s2idle). We can check in_s0ix, to prevent the system from entering idle optimizations before it actually enters hibernate (from display's perspective). Cc: sta...@vger.kernel.org # 6.10+ Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4651b884d8d9..546a168a2fbf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2996,10 +2996,11 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block) hpd_rx_irq_work_suspend(dm); - if (adev->dm.dc->caps.ips_support) - dc_allow_idle_optimizations(adev->dm.dc, true); - dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); + + if (dm->dc->caps.ips_support && adev->in_s0ix) + dc_allow_idle_optimizations(dm->dc, true); + Is the ordering change with respect to dc_set_power_state() intended? Yup, it's safer to set idle opts after dc_set_power_state(), since it involves a write to DMUB. Alex dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); return 0; -- 2.46.0 -- Hamza
[PATCH] drm/amd/display: fix hibernate entry for DCN35+
Since, two suspend-resume cycles are required to enter hibernate and, since we only need to enable idle optimizations in the first cycle (which is pretty much equivalent to s2idle). We can check in_s0ix, to prevent the system from entering idle optimizations before it actually enters hibernate (from display's perspective). Cc: sta...@vger.kernel.org # 6.10+ Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4651b884d8d9..546a168a2fbf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2996,10 +2996,11 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block) hpd_rx_irq_work_suspend(dm); - if (adev->dm.dc->caps.ips_support) - dc_allow_idle_optimizations(adev->dm.dc, true); - dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); + + if (dm->dc->caps.ips_support && adev->in_s0ix) + dc_allow_idle_optimizations(dm->dc, true); + dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); return 0; -- 2.46.0
Re: [PATCH v7 10/10] drm/amd/display: Fetch the EDID from _DDC if available for eDP
On 9/19/24 13:29, Alex Deucher wrote:
On Thu, Sep 19, 2024 at 12:06 PM Mario Limonciello
wrote:
On 9/19/2024 11:03, Alex Hung wrote:
A minor comment (see inline below).
Otherwise
Reviewed-by: Alex Hung
On 2024-09-18 15:38, Mario Limonciello wrote:
Some manufacturers have intentionally put an EDID that differs from
the EDID on the internal panel on laptops.
Attempt to fetch this EDID if it exists and prefer it over the EDID
that is provided by the panel. If a user prefers to use the EDID from
the panel, offer a DC debugging parameter that would disable this.
Signed-off-by: Mario Limonciello
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 62 ++-
drivers/gpu/drm/amd/include/amd_shared.h | 5 ++
2 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 8f4be7a1ec45..05d3e00ecce0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -23,6 +23,8 @@
*
*/
+#include
+
#include
#include
#include
@@ -874,6 +876,60 @@ bool dm_helpers_is_dp_sink_present(struct dc_link
*link)
return dp_sink_present;
}
+static int
+dm_helpers_probe_acpi_edid(void *data, u8 *buf, unsigned int block,
size_t len)
+{
+struct drm_connector *connector = data;
+struct acpi_device *acpidev = ACPI_COMPANION(connector->dev->dev);
+unsigned char start = block * EDID_LENGTH;
+void *edid;
+int r;
+
+if (!acpidev)
+return -ENODEV;
+
+/* fetch the entire edid from BIOS */
+r = acpi_video_get_edid(acpidev, ACPI_VIDEO_DISPLAY_LCD, -1, &edid);
+if (r < 0) {
+DRM_DEBUG_KMS("Failed to get EDID from ACPI: %d\n", r);
+return r;
+}
+if (len > r || start > r || start + len > r) {
+r = -EINVAL;
+goto cleanup;
+}
+
+memcpy(buf, edid + start, len);
+r = 0;
+
+cleanup:
+kfree(edid);
+
+return r;
+}
+
+static const struct drm_edid *
+dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector)
+{
+struct drm_connector *connector = &aconnector->base;
+
+if (amdgpu_dc_debug_mask & DC_DISABLE_ACPI_EDID)
+return NULL;
+
+switch (connector->connector_type) {
+case DRM_MODE_CONNECTOR_LVDS:
+case DRM_MODE_CONNECTOR_eDP:
+break;
+default:
+return NULL;
+}
+
+if (connector->force == DRM_FORCE_OFF)
+return NULL;
+
+return drm_edid_read_custom(connector,
dm_helpers_probe_acpi_edid, connector);
+}
+
enum dc_edid_status dm_helpers_read_local_edid(
struct dc_context *ctx,
struct dc_link *link,
@@ -896,7 +952,11 @@ enum dc_edid_status dm_helpers_read_local_edid(
* do check sum and retry to make sure read correct edid.
*/
do {
-drm_edid = drm_edid_read_ddc(connector, ddc);
+drm_edid = dm_helpers_read_acpi_edid(aconnector);
+if (drm_edid)
+DRM_DEBUG_KMS("Using ACPI provided EDID for %s\n",
connector->name);
It is better to always output a message when ACPI's EDID is used without
enabling any debug options. How about DRM_INFO?
Thanks, DRM_INFO makes sense for discoverability and will adjust it.
I'd suggest using dev_info() or one of the newer DRM macros so we know
which device we are talking about if there are multiple GPUs in the
system.
Ya, I'd personally prefer moving amdgpu_dm over to the new(er) drm_.*
family of logging macros.
Alex
+else
+drm_edid = drm_edid_read_ddc(connector, ddc);
drm_edid_connector_update(connector, drm_edid);
aconnector->drm_edid = drm_edid;
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index 3f91926a50e9..1ec7c5e5249e 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -337,6 +337,11 @@ enum DC_DEBUG_MASK {
* @DC_FORCE_IPS_ENABLE: If set, force enable all IPS, all the
time.
*/
DC_FORCE_IPS_ENABLE = 0x4000,
+/**
+ * @DC_DISABLE_ACPI_EDID: If set, don't attempt to fetch EDID for
+ * eDP display from ACPI _DDC method.
+ */
+DC_DISABLE_ACPI_EDID = 0x8000,
};
enum amd_dpm_forced_level;
--
Hamza
[PATCH] drm/amdgpu: enable -Wformat-truncation
It is enabled by W=1 and amdgpu has a clean build with it enabled. So, to make sure we block future instances of it from showing up on our driver, enable it by default for the module. Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/amdgpu/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 34943b866687..64adadb56fd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -41,6 +41,7 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ # Locally disable W=1 warnings enabled in drm subsystem Makefile subdir-ccflags-y += -Wno-override-init +subdir-ccflags-y += $(call cc-option, -Wformat-truncation) subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror amdgpu-y := amdgpu_drv.o -- 2.46.0
Re: [PATCH 3/3] drm/amdgpu: drop redundant W=1 warnings from Makefile
On 5/23/24 09:37, Jani Nikula wrote:
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
across the subsystem"), most of the extra warnings in the driver
Makefile are redundant. Remove them.
Note that -Wmissing-declarations and -Wmissing-prototypes are always
enabled by default in scripts/Makefile.extrawarn.
Signed-off-by: Jani Nikula
Sorry, it took me so long to get to this. But, I guess as they say,
better late than never.
Applied, thanks!
---
drivers/gpu/drm/amd/amdgpu/Makefile | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 1f6b56ec99f6..9508d0b5708e 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -39,23 +39,7 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \
-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \
-I$(FULL_AMD_PATH)/amdkfd
-subdir-ccflags-y := -Wextra
-subdir-ccflags-y += -Wunused
-subdir-ccflags-y += -Wmissing-prototypes
-subdir-ccflags-y += -Wmissing-declarations
-subdir-ccflags-y += -Wmissing-include-dirs
-subdir-ccflags-y += -Wold-style-definition
-subdir-ccflags-y += -Wmissing-format-attribute
-# Need this to avoid recursive variable evaluation issues
-cond-flags := $(call cc-option, -Wunused-but-set-variable) \
- $(call cc-option, -Wunused-const-variable) \
- $(call cc-option, -Wstringop-truncation) \
- $(call cc-option, -Wpacked-not-aligned)
-subdir-ccflags-y += $(cond-flags)
-subdir-ccflags-y += -Wno-unused-parameter
-subdir-ccflags-y += -Wno-type-limits
-subdir-ccflags-y += -Wno-sign-compare
-subdir-ccflags-y += -Wno-missing-field-initializers
+# Locally disable W=1 warnings enabled in drm subsystem Makefile
subdir-ccflags-y += -Wno-override-init
subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror
--
Hamza
Re: [RESEND 3/3] drm/amd/display: switch to guid_gen() to generate valid GUIDs
On 8/28/24 10:06, Jani Nikula wrote:
On Wed, 28 Aug 2024, Hamza Mahfooz wrote:
On 8/12/24 08:23, Jani Nikula wrote:
Instead of just smashing jiffies into a GUID, use guid_gen() to generate
RFC 4122 compliant GUIDs.
Signed-off-by: Jani Nikula
---
Acked-by: Hamza Mahfooz
I would prefer to take this series through the amdgpu tree though,
assuming nobody minds.
How long is it going to take for that to get synced back to
drm-misc-next though?
It might take awhile, so it's probably best to merge it through
drm-misc-next.
BR,
Jani.
Side note, it baffles me why amdgpu has a copy of this instead of
plumbing it into drm mst code.
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ++-
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 72c10fc2c890..ce05e7e2a383 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2568,9 +2568,9 @@ static int dm_late_init(void *handle)
static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
{
+ u8 buf[UUID_SIZE];
+ guid_t guid;
int ret;
- u8 guid[16];
- u64 tmp64;
mutex_lock(&mgr->lock);
if (!mgr->mst_primary)
@@ -2591,26 +2591,27 @@ static void resume_mst_branch_status(struct
drm_dp_mst_topology_mgr *mgr)
}
/* Some hubs forget their guids after they resume */
- ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
- if (ret != 16) {
+ ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf));
+ if (ret != sizeof(buf)) {
drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during
suspend?\n");
goto out_fail;
}
- if (memchr_inv(guid, 0, 16) == NULL) {
- tmp64 = get_jiffies_64();
- memcpy(&guid[0], &tmp64, sizeof(u64));
- memcpy(&guid[8], &tmp64, sizeof(u64));
+ import_guid(&guid, buf);
- ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
+ if (guid_is_null(&guid)) {
+ guid_gen(&guid);
+ export_guid(buf, &guid);
- if (ret != 16) {
+ ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf));
+
+ if (ret != sizeof(buf)) {
drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked
during suspend?\n");
goto out_fail;
}
}
- import_guid(&mgr->mst_primary->guid, guid);
+ guid_copy(&mgr->mst_primary->guid, &guid);
out_fail:
mutex_unlock(&mgr->lock);
--
Hamza
Re: [RESEND 3/3] drm/amd/display: switch to guid_gen() to generate valid GUIDs
On 8/12/24 08:23, Jani Nikula wrote:
Instead of just smashing jiffies into a GUID, use guid_gen() to generate
RFC 4122 compliant GUIDs.
Signed-off-by: Jani Nikula
---
Acked-by: Hamza Mahfooz
I would prefer to take this series through the amdgpu tree though,
assuming nobody minds.
Side note, it baffles me why amdgpu has a copy of this instead of
plumbing it into drm mst code.
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ++-
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 72c10fc2c890..ce05e7e2a383 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2568,9 +2568,9 @@ static int dm_late_init(void *handle)
static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
{
+ u8 buf[UUID_SIZE];
+ guid_t guid;
int ret;
- u8 guid[16];
- u64 tmp64;
mutex_lock(&mgr->lock);
if (!mgr->mst_primary)
@@ -2591,26 +2591,27 @@ static void resume_mst_branch_status(struct
drm_dp_mst_topology_mgr *mgr)
}
/* Some hubs forget their guids after they resume */
- ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
- if (ret != 16) {
+ ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf));
+ if (ret != sizeof(buf)) {
drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during
suspend?\n");
goto out_fail;
}
- if (memchr_inv(guid, 0, 16) == NULL) {
- tmp64 = get_jiffies_64();
- memcpy(&guid[0], &tmp64, sizeof(u64));
- memcpy(&guid[8], &tmp64, sizeof(u64));
+ import_guid(&guid, buf);
- ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
+ if (guid_is_null(&guid)) {
+ guid_gen(&guid);
+ export_guid(buf, &guid);
- if (ret != 16) {
+ ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf));
+
+ if (ret != sizeof(buf)) {
drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked
during suspend?\n");
goto out_fail;
}
}
- import_guid(&mgr->mst_primary->guid, guid);
+ guid_copy(&mgr->mst_primary->guid, &guid);
out_fail:
mutex_unlock(&mgr->lock);
--
Hamza
[PATCH 07/14] drm/amd/display: Refactor dccg35_get_other_enabled_symclk_fe
From: Nicholas Susanto
[Why]
Function used to check the number of FEs connected to the current BE.
This was then used to determine if the symclk could be disabled, if
all FEs were disconnected. However, the function would skip over the
primary FE and return 0 when the primary FE was still connected. This
caused black screens on driver disable with an MST daisy chain hooked
up.
[How]
Refactor the function to correctly return the number of FEs connected
to the input BE. Also, rename it for clarity.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Nicholas Susanto
Signed-off-by: Hamza Mahfooz
---
.../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 65 +++
1 file changed, 25 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 60a84de4c5d1..889f39694cb7 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -1905,47 +1905,32 @@ static void dccg35_enable_symclk_se(struct dccg *dccg,
uint32_t stream_enc_inst,
}
/*get other front end connected to this backend*/
-static uint8_t dccg35_get_other_enabled_symclk_fe(struct dccg *dccg, uint32_t
stream_enc_inst, uint32_t link_enc_inst)
+static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg
*dccg, uint32_t link_enc_inst)
{
uint8_t num_enabled_symclk_fe = 0;
- uint32_t be_clk_en = 0, fe_clk_en[5] = {0}, be_clk_sel[5] = {0};
+ uint32_t fe_clk_en[5] = {0}, be_clk_sel[5] = {0};
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
- switch (link_enc_inst) {
- case 0:
- REG_GET_3(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE,
&be_clk_en,
- SYMCLKA_FE_EN, &fe_clk_en[0],
- SYMCLKA_FE_SRC_SEL, &be_clk_sel[0]);
- break;
- case 1:
- REG_GET_3(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE,
&be_clk_en,
- SYMCLKB_FE_EN, &fe_clk_en[1],
- SYMCLKB_FE_SRC_SEL, &be_clk_sel[1]);
- break;
- case 2:
- REG_GET_3(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE,
&be_clk_en,
- SYMCLKC_FE_EN, &fe_clk_en[2],
- SYMCLKC_FE_SRC_SEL, &be_clk_sel[2]);
- break;
- case 3:
- REG_GET_3(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE,
&be_clk_en,
- SYMCLKD_FE_EN, &fe_clk_en[3],
- SYMCLKD_FE_SRC_SEL, &be_clk_sel[3]);
- break;
- case 4:
- REG_GET_3(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE,
&be_clk_en,
- SYMCLKE_FE_EN, &fe_clk_en[4],
- SYMCLKE_FE_SRC_SEL, &be_clk_sel[4]);
- break;
- }
- if (be_clk_en) {
- /* for DPMST, this backend could be used by multiple front end.
- only disable the backend if this stream_enc_ins is the last active
stream enc connected to this back_end*/
- uint8_t i;
- for (i = 0; i != link_enc_inst && i < ARRAY_SIZE(fe_clk_en);
i++) {
- if (fe_clk_en[i] && be_clk_sel[i] == link_enc_inst)
- num_enabled_symclk_fe++;
- }
+ REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, &fe_clk_en[0],
+ SYMCLKA_FE_SRC_SEL, &be_clk_sel[0]);
+
+ REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, &fe_clk_en[1],
+ SYMCLKB_FE_SRC_SEL, &be_clk_sel[1]);
+
+ REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, &fe_clk_en[2],
+ SYMCLKC_FE_SRC_SEL, &be_clk_sel[2]);
+
+ REG_GET_2(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, &fe_clk_en[3],
+ SYMCLKD_FE_SRC_SEL, &be_clk_sel[3]);
+
+ REG_GET_2(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_EN, &fe_clk_en[4],
+ SYMCLKE_FE_SRC_SEL, &be_clk_sel[4]);
+
+ uint8_t i;
+
+ for (i = 0; i < ARRAY_SIZE(fe_clk_en); i++) {
+ if (fe_clk_en[i] && be_clk_sel[i] == link_enc_inst)
+ num_enabled_symclk_fe++;
}
return num_enabled_symclk_fe;
}
@@ -1993,9 +1978,9 @@ static void dccg35_disable_symclk_se(struct dccg *dccg,
uint32_t stream_enc_inst
break;
}
- /*check other enabled symclk fe */
- num_enabled_symclk_fe = dccg35_get_other_enabled_symclk_fe(dccg,
stream_enc_inst, link_enc_inst);
- /*only turn off backend clk if other front end attachecd to this
backend are all off,
+ /*check other enabled symclk fe connected to this be */
+ num_
[PATCH 12/14] drm/amd/display: Block timing sync for different signals in PMO
From: Dillon Varone
PMO assumes that like timings can be synchronized, but DC only allows
this if the signal types match.
Cc: sta...@vger.kernel.org
Reviewed-by: Austin Zheng
Signed-off-by: Dillon Varone
Signed-off-by: Hamza Mahfooz
---
.../display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
index 3bb5eb2e79ae..d63558ee3135 100644
---
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+++
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
@@ -941,7 +941,8 @@ static void build_synchronized_timing_groups(
for (j = i + 1; j < display_config->display_config.num_streams;
j++) {
if (memcmp(master_timing,
&display_config->display_config.stream_descriptors[j].timing,
- sizeof(struct dml2_timing_cfg)) == 0) {
+ sizeof(struct dml2_timing_cfg)) == 0 &&
+
display_config->display_config.stream_descriptors[i].output.output_encoder ==
display_config->display_config.stream_descriptors[j].output.output_encoder) {
set_bit_in_bitfield(&pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx],
j);
set_bit_in_bitfield(&stream_mapped_mask, j);
}
--
2.46.0
[PATCH 13/14] drm/amd/display: Fix flickering caused by dccg
From: Hansen Dsouza
Always allow un-gating. Follow legacy workaround for repeated
dppclk dto updates
Reviewed-by: Muhammad Ahmed
Signed-off-by: Hansen Dsouza
Signed-off-by: Hamza Mahfooz
---
.../amd/display/dc/dccg/dcn20/dcn20_dccg.h| 11 +++
.../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 89 +--
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 45 --
3 files changed, 72 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
index 6ac2bd86c4db..160c299419b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
@@ -328,6 +328,17 @@
type DPSTREAMCLK1_GATE_DISABLE;\
type DPSTREAMCLK2_GATE_DISABLE;\
type DPSTREAMCLK3_GATE_DISABLE;\
+ type SYMCLKA_FE_GATE_DISABLE;\
+ type SYMCLKB_FE_GATE_DISABLE;\
+ type SYMCLKC_FE_GATE_DISABLE;\
+ type SYMCLKD_FE_GATE_DISABLE;\
+ type SYMCLKE_FE_GATE_DISABLE;\
+ type SYMCLKA_GATE_DISABLE;\
+ type SYMCLKB_GATE_DISABLE;\
+ type SYMCLKC_GATE_DISABLE;\
+ type SYMCLKD_GATE_DISABLE;\
+ type SYMCLKE_GATE_DISABLE;\
+
#define DCCG401_REG_FIELD_LIST(type) \
type OTG0_TMDS_PIXEL_RATE_DIV;\
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 8b3722a0011b..838d72eaa87f 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -24,6 +24,7 @@
#include "reg_helper.h"
#include "core_types.h"
+#include "resource.h"
#include "dcn35_dccg.h"
#define TO_DCN_DCCG(dccg)\
@@ -136,7 +137,7 @@ static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int
inst, bool enable)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
- if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
+ if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && enable)
return;
switch (inst) {
@@ -165,7 +166,7 @@ static void dccg35_set_symclk32_se_rcg(
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
- if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+ if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se &&
enable)
return;
/* SYMCLK32_ROOT_SE#_GATE_DISABLE will clock gate in DCCG */
@@ -204,7 +205,7 @@ static void dccg35_set_symclk32_le_rcg(
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
- if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
+ if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le &&
enable)
return;
switch (inst) {
@@ -231,7 +232,7 @@ static void dccg35_set_physymclk_rcg(
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
- if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
+ if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk &&
enable)
return;
switch (inst) {
@@ -262,35 +263,45 @@ static void dccg35_set_physymclk_rcg(
}
static void dccg35_set_symclk_fe_rcg(
- struct dccg *dccg,
- int inst,
- bool enable)
+ struct dccg *dccg,
+ int inst,
+ bool enable)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
- if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
+ if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe &&
enable)
return;
switch (inst) {
case 0:
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
+ SYMCLKA_FE_GATE_DISABLE, enable ? 0 : 1);
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
- SYMCLKA_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
+ SYMCLKA_FE_ROOT_GATE_DISABLE, enable ? 0 :
1);
break;
case 1:
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
+ SYMCLKB_FE_GATE_DISABLE, enable ? 0 : 1);
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
- SYMCLKB_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
+ SYMCLKB_FE_ROOT_GATE_DISABLE, enable ? 0 :
1);
break;
case 2:
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
+ SYMCLKC_FE_GATE_DISABLE, enable ? 0 : 1);
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
- SYMCLKC_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
+ SYMCLKC_FE_ROOT_GATE_DISABLE, enable ? 0 :
[PATCH 14/14] drm/amd/display: 3.2.299
From: Aric Cyr This version brings along the following: - DCN35 fixes - DML2 fixes - IPS fixes - ODM fixes - Miscellaneous cleanups - MST fixes - SPL fixes Acked-by: Aurabindo Pillai Signed-off-by: Aric Cyr Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1a907ff82336..4c94dd38be4b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.298" +#define DC_VER "3.2.299" #define MAX_SURFACES 3 #define MAX_PLANES 6 diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index f5dda1d69ae0..e20c220aa8b4 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -111,7 +111,7 @@ #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) /* Trace buffer offset for entry */ -#define TRACE_BUFFER_ENTRY_OFFSET 16 +#define TRACE_BUFFER_ENTRY_OFFSET 16 /** * Maximum number of dirty rects supported by FW. -- 2.46.0
[PATCH 10/14] drm/amd/display: Add sharpness control interface
From: Relja Vojvodic
- Add interface for controlling shapness level input into DCN.
- Update SPL to support custom sharpness values.
- Add support for different sharpness values depending on YUV/RGB
content.
Reviewed-by: Samson Tam
Signed-off-by: Relja Vojvodic
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +-
drivers/gpu/drm/amd/display/dc/dc.h | 3 +-
.../gpu/drm/amd/display/dc/dc_spl_translate.c | 46 ++--
drivers/gpu/drm/amd/display/dc/dc_stream.h| 3 +
.../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 24 +-
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 4 +-
.../display/dc/spl/dc_spl_isharp_filters.c| 213 +-
.../display/dc/spl/dc_spl_isharp_filters.h| 2 +-
.../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 27 ++-
9 files changed, 138 insertions(+), 192 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e07e47d74664..ae788154896c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2690,6 +2690,9 @@ static enum surface_update_type
check_update_surfaces_for_stream(
stream_update->vrr_active_variable ||
stream_update->vrr_active_fixed))
su_flags->bits.fams_changed = 1;
+ if (stream_update->scaler_sharpener_update)
+ su_flags->bits.scaler_sharpener = 1;
+
if (su_flags->raw != 0)
overall_type = UPDATE_TYPE_FULL;
@@ -3022,6 +3025,8 @@ static void copy_stream_update_to_stream(struct dc *dc,
update->dsc_config = NULL;
}
}
+ if (update->scaler_sharpener_update)
+ stream->scaler_sharpener_update =
*update->scaler_sharpener_update;
}
static void backup_planes_and_stream_state(
@@ -4713,7 +4718,8 @@ static bool full_update_required(struct dc *dc,
stream_update->func_shaper ||
stream_update->lut3d_func ||
stream_update->pending_test_pattern ||
- stream_update->crtc_timing_adjust))
+ stream_update->crtc_timing_adjust ||
+ stream_update->scaler_sharpener_update))
return true;
if (stream) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index aaf1d7fdb73d..1a907ff82336 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1052,6 +1052,7 @@ struct dc_debug_options {
unsigned int disable_spl;
unsigned int force_easf;
unsigned int force_sharpness;
+ unsigned int force_sharpness_level;
unsigned int force_lls;
bool notify_dpia_hr_bw;
bool enable_ips_visual_confirm;
@@ -1348,7 +1349,7 @@ struct dc_plane_state {
enum mpcc_movable_cm_location mcm_location;
struct dc_csc_transform cursor_csc_color_matrix;
bool adaptive_sharpness_en;
- unsigned int sharpnessX1000;
+ int sharpness_level;
enum linear_light_scaling linear_light_scaling;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
index 328499a77884..cd6de93eb91c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
@@ -139,24 +139,36 @@ void translate_SPL_in_params_from_pipe_ctx(struct
pipe_ctx *pipe_ctx, struct spl
else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 2)
spl_in->disable_easf = true;
/* Translate adaptive sharpening preference */
- if (pipe_ctx->stream->ctx->dc->debug.force_sharpness > 0) {
- spl_in->adaptive_sharpness.enable =
(pipe_ctx->stream->ctx->dc->debug.force_sharpness > 1) ? true : false;
- if (pipe_ctx->stream->ctx->dc->debug.force_sharpness == 2)
- spl_in->adaptive_sharpness.sharpness = SHARPNESS_LOW;
- else if (pipe_ctx->stream->ctx->dc->debug.force_sharpness == 3)
- spl_in->adaptive_sharpness.sharpness = SHARPNESS_MID;
- else if (pipe_ctx->stream->ctx->dc->debug.force_sharpness >= 4)
- spl_in->adaptive_sharpness.sharpness = SHARPNESS_HIGH;
- } else {
- spl_in->adaptive_sharpness.enable =
plane_state->adaptive_sharpness_en;
- if (plane_state->sharpnessX1000 == 0)
+ unsigned int sharpness_setting =
pipe_ctx->stream->ctx->dc->debug.force_sharpness;
+ unsigned int force_sharpness_level =
pipe_ctx->stream->ctx->dc->debug.force_sharpness_level;
+ if
[PATCH 11/14] drm/amd/display: fix graphics hang in multi-display mst case
From: Gabe Teeger
[what]
Graphics hang observed with 3 displays connected to DP2.0 mst dock.
[why]
There's a mismatch in dml and dc between the assignments of hpo link
encoders.
[how]
Add a new array in dml that tracks the current mapping of HPO stream
encoders to HPO link encoders in dc.
Cc: sta...@vger.kernel.org
Reviewed-by: Sung joon Kim
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Gabe Teeger
Signed-off-by: Hamza Mahfooz
---
.../amd/display/dc/dml2/dml2_internal_types.h | 2 +-
.../display/dc/dml2/dml2_translation_helper.c | 67 +--
.../display/dc/dml2/dml2_translation_helper.h | 2 +-
.../gpu/drm/amd/display/dc/dml2/dml2_utils.c | 12 +---
4 files changed, 34 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h
index 3ba184be25d3..140ec01545db 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h
@@ -101,7 +101,7 @@ struct dml2_wrapper_scratch {
struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping;
bool enable_flexible_pipe_mapping;
bool plane_duplicate_exists;
- unsigned int dp2_mst_stream_count;
+ int hpo_stream_to_link_encoder_mapping[MAX_HPO_DP2_ENCODERS];
};
struct dml2_helper_det_policy_scratch {
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 7e39873832bf..bde4250853b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -733,8 +733,7 @@ static void
populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st *
}
static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st
*out, unsigned int location,
- const struct dc_stream_state *in, const struct
pipe_ctx *pipe,
- unsigned int dp2_mst_stream_count)
+ const struct dc_stream_state *in, const struct
pipe_ctx *pipe, struct dml2_context *dml2)
{
unsigned int output_bpc;
@@ -747,8 +746,8 @@ static void
populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *
case SIGNAL_TYPE_DISPLAY_PORT_MST:
case SIGNAL_TYPE_DISPLAY_PORT:
out->OutputEncoder[location] = dml_dp;
- if (is_dp2p0_output_encoder(pipe, dp2_mst_stream_count))
- out->OutputEncoder[location] = dml_dp2p0;
+ if
(dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
+
out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]]
= dml_dp2p0;
break;
case SIGNAL_TYPE_EDP:
out->OutputEncoder[location] = dml_edp;
@@ -1199,36 +1198,6 @@ static void
dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2,
}
}
-static unsigned int calculate_dp2_mst_stream_count(struct dc_state *context)
-{
- int i, j;
- unsigned int dp2_mst_stream_count = 0;
-
- for (i = 0; i < context->stream_count; i++) {
- struct dc_stream_state *stream = context->streams[i];
-
- if (!stream || stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
- continue;
-
- for (j = 0; j < MAX_PIPES; j++) {
- struct pipe_ctx *pipe_ctx =
&context->res_ctx.pipe_ctx[j];
-
- if (!pipe_ctx || !pipe_ctx->stream)
- continue;
-
- if (stream != pipe_ctx->stream)
- continue;
-
- if (pipe_ctx->stream_res.hpo_dp_stream_enc &&
pipe_ctx->link_res.hpo_dp_link_enc) {
- dp2_mst_stream_count++;
- break;
- }
- }
- }
-
- return dp2_mst_stream_count;
-}
-
static void populate_dml_writeback_cfg_from_stream_state(struct
dml_writeback_cfg_st *out,
unsigned int location, const struct dc_stream_state *in)
{
@@ -1269,6 +1238,30 @@ static void
populate_dml_writeback_cfg_from_stream_state(struct dml_writeback_cf
}
}
}
+
+static void dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(struct
dml2_context *dml2, struct dc_state *context)
+{
+ int i;
+ struct pipe_ctx *current_pipe_context;
+
+ /* Scratch gets reset to zero in dml, but link encoder instance can be
zero, so reset to -1 */
+ for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) {
+ dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[i] = -1;
+ }
+
+ /* If an HPO stream encoder is allocated to a pipe, get the instance of
[PATCH 09/14] Revert "drm/amd/display: Wait for all pending cleared before full update"
From: Dillon Varone
This reverts commit 3b837c45668c3026fd09145904692ba1130c5d12.
It is causing graphics hangs.
Reviewed-by: Martin Leung
Signed-off-by: Dillon Varone
Signed-off-by: Hamza Mahfooz
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 9 +---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 4 +-
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 27 ---
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 2 -
.../amd/display/dc/hwss/dcn30/dcn30_init.c| 3 +-
.../amd/display/dc/hwss/dcn301/dcn301_init.c | 1 -
.../amd/display/dc/hwss/dcn32/dcn32_init.c| 1 -
.../amd/display/dc/hwss/dcn401/dcn401_init.c | 1 -
.../drm/amd/display/dc/hwss/hw_sequencer.h| 1 -
.../amd/display/dc/inc/hw/timing_generator.h | 4 +-
.../amd/display/dc/optc/dcn10/dcn10_optc.h| 9
.../amd/display/dc/optc/dcn20/dcn20_optc.h| 7 +--
.../amd/display/dc/optc/dcn30/dcn30_optc.c| 45 ---
.../amd/display/dc/optc/dcn30/dcn30_optc.h| 13 +-
.../amd/display/dc/optc/dcn301/dcn301_optc.c | 3 --
.../amd/display/dc/optc/dcn31/dcn31_optc.h| 9 +---
.../amd/display/dc/optc/dcn314/dcn314_optc.h | 9 +---
.../amd/display/dc/optc/dcn32/dcn32_optc.c| 16 +--
.../amd/display/dc/optc/dcn32/dcn32_optc.h| 7 +--
.../amd/display/dc/optc/dcn35/dcn35_optc.h| 6 +--
.../amd/display/dc/optc/dcn401/dcn401_optc.c | 4 +-
.../amd/display/dc/optc/dcn401/dcn401_optc.h | 6 +--
.../dc/resource/dcn32/dcn32_resource.h| 3 +-
.../dc/resource/dcn401/dcn401_resource.h | 5 +--
24 files changed, 34 insertions(+), 161 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 2cb9253c9bde..7ee2be8f82c4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -1071,13 +1071,8 @@ void hwss_wait_for_outstanding_hw_updates(struct dc *dc,
struct dc_state *dc_con
if (!pipe_ctx->stream)
continue;
- /* For full update we must wait for all double buffer updates,
not just DRR updates. This
-* is particularly important for minimal transitions. Only
check for OTG_MASTER pipes,
-* as non-OTG Master pipes share the same OTG as
-*/
- if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&
dc->hwss.wait_for_all_pending_updates) {
- dc->hwss.wait_for_all_pending_updates(pipe_ctx);
- }
+ if
(pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
+
pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
hubp = pipe_ctx->plane_res.hubp;
if (!hubp)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index b383ed8cb4d4..a80c08582932 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2255,9 +2255,9 @@ void dcn20_post_unlock_program_front_end(
struct timing_generator *tg = pipe->stream_res.tg;
- if (tg->funcs->get_optc_double_buffer_pending) {
+ if (tg->funcs->get_double_buffer_pending) {
for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_US /
polling_interval_us
- &&
tg->funcs->get_optc_double_buffer_pending(tg); j++)
+ && tg->funcs->get_double_buffer_pending(tg);
j++)
udelay(polling_interval_us);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index d5458dae6d30..42c52284a868 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -1185,30 +1185,3 @@ void dcn30_prepare_bandwidth(struct dc *dc,
if (!dc->clk_mgr->clks.fw_based_mclk_switching)
dc_dmub_srv_p_state_delegate(dc, false, context);
}
-
-void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx)
-{
- struct timing_generator *tg = pipe_ctx->stream_res.tg;
- bool pending_updates = false;
- unsigned int i;
-
- if (tg && tg->funcs->is_tg_enabled(tg)) {
- // Poll for 100ms maximum
- for (i = 0; i < 10; i++) {
- pending_updates = false;
- if (tg->funcs->get_optc_double_buffer_pending)
- pending_updates |=
tg->funcs->get_optc_double_buffer_pending
[PATCH 05/14] drm/amd/display: Add dpia debug option to control power management
From: Meenakshikumar Somasundaram
[Why]
To provide option to dpia control power management
[How]
By adding disable_usb4_pm_support bit field in dpia_debug option to
control dpia power management
Reviewed-by: Jun Lei
Signed-off-by: Meenakshikumar Somasundaram
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/dc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 663aa565fc8a..aaf1d7fdb73d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -761,7 +761,8 @@ union dpia_debug_options {
uint32_t extend_aux_rd_interval:1; /* bit 2 */
uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
- uint32_t reserved:27;
+ uint32_t disable_usb4_pm_support:1; /* bit 5 */
+ uint32_t reserved:26;
} bits;
uint32_t raw;
};
--
2.46.0
[PATCH 08/14] drm/amd/display: fix dccg root clock optimization related hang
From: Qili Lu
[Why]
enable dpp rcg before we disable dppclk in hw_init cause system
hang/reboot
[How]
we remove dccg rcg related code from init into a separate function and
call it after we init pipe
Cc: sta...@vger.kernel.org # 6.10+
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Qili Lu
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 14 +-
.../gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h | 1 +
.../drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c| 4
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 1 +
4 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 889f39694cb7..8b3722a0011b 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -1721,10 +1721,6 @@ void dccg35_init(struct dccg *dccg)
dccg35_set_dpstreamclk_root_clock_gating(dccg,
otg_inst, false);
}
- if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
- for (otg_inst = 0; otg_inst < 4; otg_inst++)
- dccg35_set_dppclk_root_clock_gating(dccg, otg_inst, 0);
-
/*
dccg35_enable_global_fgcg_rep(
dccg, dccg->ctx->dc->debug.enable_fine_grain_clock_gating.bits
@@ -2303,6 +2299,14 @@ static void dccg35_disable_symclk_se_cb(
/* DMU PHY sequence switches SYMCLK_BE (link_enc_inst) to ref clock
once PHY is turned off */
}
+void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx,
uint32_t disable_clock_gating)
+{
+
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) {
+ dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx,
disable_clock_gating);
+ }
+}
+
static const struct dccg_funcs dccg35_funcs_new = {
.update_dpp_dto = dccg35_update_dpp_dto_cb,
.dpp_root_clock_control = dccg35_dpp_root_clock_control_cb,
@@ -2363,7 +2367,7 @@ static const struct dccg_funcs dccg35_funcs = {
.enable_symclk_se = dccg35_enable_symclk_se,
.disable_symclk_se = dccg35_disable_symclk_se,
.set_dtbclk_p_src = dccg35_set_dtbclk_p_src,
-
+ .dccg_root_gate_disable_control = dccg35_root_gate_disable_control,
};
struct dccg *dccg35_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
index 1586a45ca3bd..51f98c5c51c4 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
@@ -241,6 +241,7 @@ struct dccg *dccg35_create(
void dccg35_init(struct dccg *dccg);
void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);
+void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx,
uint32_t disable_clock_gating);
#endif //__DCN35_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index fbbb20b9dbee..7ed75c5fe25e 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -271,6 +271,10 @@ void dcn35_init_hw(struct dc *dc)
dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
}
+ if (res_pool->dccg->funcs->dccg_root_gate_disable_control) {
+ for (i = 0; i < res_pool->pipe_count; i++)
+
res_pool->dccg->funcs->dccg_root_gate_disable_control(res_pool->dccg, i, 0);
+ }
for (i = 0; i < res_pool->audio_count; i++) {
struct audio *audio = res_pool->audios[i];
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index d619eb229a62..e94e9ba60f55 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -213,6 +213,7 @@ struct dccg_funcs {
uint32_t otg_inst);
void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst);
void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);
+ void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t
pipe_idx, uint32_t disable_clock_gating);
};
#endif //__DAL_DCCG_H__
--
2.46.0
[PATCH 03/14] drm/amd/display: Lock DC and exit IPS when changing backlight
From: Leo Li
Backlight updates require aux and/or register access. Therefore, driver
needs to disallow IPS beforehand.
So, acquire the dc lock before calling into dc to update backlight - we
should be doing this regardless of IPS. Then, while the lock is held,
disallow IPS before calling into dc, then allow IPS afterwards (if it
was previously allowed).
Cc: sta...@vger.kernel.org # 6.10+
Reviewed-by: Aurabindo Pillai
Reviewed-by: Roman Li
Signed-off-by: Leo Li
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 351f8b0fe7a1..fa26b8d59f23 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4512,7 +4512,7 @@ static void amdgpu_dm_backlight_set_level(struct
amdgpu_display_manager *dm,
struct amdgpu_dm_backlight_caps caps;
struct dc_link *link;
u32 brightness;
- bool rc;
+ bool rc, reallow_idle = false;
amdgpu_dm_update_backlight_caps(dm, bl_idx);
caps = dm->backlight_caps[bl_idx];
@@ -4525,6 +4525,12 @@ static void amdgpu_dm_backlight_set_level(struct
amdgpu_display_manager *dm,
link = (struct dc_link *)dm->backlight_link[bl_idx];
/* Change brightness based on AUX property */
+ mutex_lock(&dm->dc_lock);
+ if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {
+ dc_allow_idle_optimizations(dm->dc, false);
+ reallow_idle = true;
+ }
+
if (caps.aux_support) {
rc = dc_link_set_backlight_level_nits(link, true, brightness,
AUX_BL_DEFAULT_TRANSITION_TIME_MS);
@@ -4536,6 +4542,11 @@ static void amdgpu_dm_backlight_set_level(struct
amdgpu_display_manager *dm,
DRM_DEBUG("DM: Failed to update backlight on
eDP[%d]\n", bl_idx);
}
+ if (dm->dc->caps.ips_support && reallow_idle)
+ dc_allow_idle_optimizations(dm->dc, true);
+
+ mutex_unlock(&dm->dc_lock);
+
if (rc)
dm->actual_brightness[bl_idx] = user_brightness;
}
--
2.46.0
[PATCH 06/14] drm/amd/display: disable sharpness if HDR Multiplier is too large
From: Samson Tam
[Why]
Certain profiles have higher HDR multiplier than SDR boost max which
is not currently supported
[How]
Disable sharpness for these profiles
Fixes: 63697e1d69c7 ("drm/amd/display: add improvements for text display and
HDR DWM and MPO")
Reviewed-by: Martin Leung
Signed-off-by: Samson Tam
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
index 75d00c6a38f4..328499a77884 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
@@ -180,9 +180,13 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx
*pipe_ctx, struct spl
spl_in->is_fullscreen = dm_helpers_is_fullscreen(pipe_ctx->stream->ctx,
pipe_ctx->stream);
spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx,
pipe_ctx->stream);
spl_in->hdr_multx100 = 0;
- if (spl_in->is_hdr_on)
+ if (spl_in->is_hdr_on) {
spl_in->hdr_multx100 =
(uint32_t)dc_fixpt_floor(dc_fixpt_mul(plane_state->hdr_mult,
dc_fixpt_from_int(100)));
+ /* Disable sharpness for HDR Mult > 6.0 */
+ if (spl_in->hdr_multx100 > 600)
+ spl_in->adaptive_sharpness.enable = false;
+ }
}
/// @brief Translate SPL output parameters to pipe context
--
2.46.0
[PATCH 01/14] drm/amd/display: Fix DCN35 set min dispclk logic
From: Nicholas Susanto
[Why]
Setting min dispclk to 50Mhz outside clock lowering function causes
unnecessary calls to SMU to lower dispclk and causes dentist hangs when
there is no stream on the pipes.
[How]
Move the set minimum dispclk logic inside the lowering dispclk if
statement.
Fixes: 2dd29403b206 ("DCN35 set min dispclk to 50Mhz")
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Nicholas Susanto
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c| 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index f50054089da7..97164b5585a8 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -305,9 +305,6 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
new_clocks->ref_dtbclk_khz = 60;
- if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz <
dc->debug.min_disp_clk_khz)
- new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;
-
/*
* if it is safe to lower, but we are already in the lower state, we
don't have to do anything
* also if safe to lower is false, we just go in the higher state
@@ -385,6 +382,9 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz,
clk_mgr_base->clks.dispclk_khz)) {
dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower,
true);
+ if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz <
dc->debug.min_disp_clk_khz)
+ new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;
+
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower,
false);
--
2.46.0
[PATCH 04/14] drm/amd/display: re-enable Dynamic ODM policy
From: Samson Tam [Why] Previous disable ODM policy due to underflow issue with sharpener. Issue is resolved after updating sharpening policy to apply to both windowed and fullscreen video [How] Remove sharpness check disabling Dynamic ODM policy Reviewed-by: Martin Leung Signed-off-by: Samson Tam Signed-off-by: Hamza Mahfooz --- .../drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c index 86a877f9a2ec..b0d9aed0f265 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c @@ -514,8 +514,7 @@ static void populate_dml21_stream_overrides_from_stream_state( break; } if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy || - stream->debug.force_odm_combine_segments > 0 || - stream->ctx->dc->debug.force_sharpness > 1) + stream->debug.force_odm_combine_segments > 0) stream_desc->overrides.disable_dynamic_odm = true; stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp || stream->hw_cursor_req; } -- 2.46.0
[PATCH 02/14] drm/amd/display: only trigger BIOS related assert for older ASICs
From: Daniel Sa
[Why]
Some asserts are always hit on startup/Pnp when they should only be used
to indicate when something has gone wrong.
[How]
Ignore result of getting function from bios cmd table for newer asics.
Reviewed-by: Jun Lei
Signed-off-by: Daniel Sa
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index 4254bdfefe38..7d18f372ce7a 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -227,7 +227,7 @@ static void init_transmitter_control(struct bios_parser *bp)
uint8_t frev;
uint8_t crev = 0;
- if (!BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev))
+ if (!BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) &&
(bp->base.ctx->dc->ctx->dce_version <= DCN_VERSION_2_0))
BREAK_TO_DEBUGGER();
switch (crev) {
--
2.46.0
[PATCH 00/14] DC Patches August 27, 2024
Cc: Daniel Wheeler Aric Cyr (1): drm/amd/display: 3.2.299 Daniel Sa (1): drm/amd/display: only trigger BIOS related assert for older ASICs Dillon Varone (2): Revert "drm/amd/display: Wait for all pending cleared before full update" drm/amd/display: Block timing sync for different signals in PMO Gabe Teeger (1): drm/amd/display: fix graphics hang in multi-display mst case Hansen Dsouza (1): drm/amd/display: Fix flickering caused by dccg Leo Li (1): drm/amd/display: Lock DC and exit IPS when changing backlight Meenakshikumar Somasundaram (1): drm/amd/display: Add dpia debug option to control power management Nicholas Susanto (2): drm/amd/display: Fix DCN35 set min dispclk logic drm/amd/display: Refactor dccg35_get_other_enabled_symclk_fe Qili Lu (1): drm/amd/display: fix dccg root clock optimization related hang Relja Vojvodic (1): drm/amd/display: Add sharpness control interface Samson Tam (2): drm/amd/display: re-enable Dynamic ODM policy drm/amd/display: disable sharpness if HDR Multiplier is too large .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +- .../drm/amd/display/dc/bios/command_table2.c | 2 +- .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 9 +- drivers/gpu/drm/amd/display/dc/dc.h | 8 +- .../gpu/drm/amd/display/dc/dc_spl_translate.c | 52 +++-- drivers/gpu/drm/amd/display/dc/dc_stream.h| 3 + .../amd/display/dc/dccg/dcn20/dcn20_dccg.h| 11 + .../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 168 -- .../amd/display/dc/dccg/dcn35/dcn35_dccg.h| 1 + .../dc/dml2/dml21/dml21_translation_helper.c | 3 +- .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 3 +- .../amd/display/dc/dml2/dml2_internal_types.h | 2 +- .../display/dc/dml2/dml2_translation_helper.c | 67 +++--- .../display/dc/dml2/dml2_translation_helper.h | 2 +- .../gpu/drm/amd/display/dc/dml2/dml2_utils.c | 12 +- .../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 24 +- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 4 +- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 27 --- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 2 - .../amd/display/dc/hwss/dcn30/dcn30_init.c| 3 +- .../amd/display/dc/hwss/dcn301/dcn301_init.c | 1 - .../amd/display/dc/hwss/dcn32/dcn32_init.c| 1 - .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 49 +--- .../amd/display/dc/hwss/dcn401/dcn401_init.c | 1 - .../drm/amd/display/dc/hwss/hw_sequencer.h| 1 - drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 1 + .../amd/display/dc/inc/hw/timing_generator.h | 4 +- .../amd/display/dc/optc/dcn10/dcn10_optc.h| 9 - .../amd/display/dc/optc/dcn20/dcn20_optc.h| 7 +- .../amd/display/dc/optc/dcn30/dcn30_optc.c| 45 .../amd/display/dc/optc/dcn30/dcn30_optc.h| 13 +- .../amd/display/dc/optc/dcn301/dcn301_optc.c | 3 - .../amd/display/dc/optc/dcn31/dcn31_optc.h| 9 +- .../amd/display/dc/optc/dcn314/dcn314_optc.h | 9 +- .../amd/display/dc/optc/dcn32/dcn32_optc.c| 16 +- .../amd/display/dc/optc/dcn32/dcn32_optc.h| 7 +- .../amd/display/dc/optc/dcn35/dcn35_optc.h| 6 +- .../amd/display/dc/optc/dcn401/dcn401_optc.c | 4 +- .../amd/display/dc/optc/dcn401/dcn401_optc.h | 6 +- .../dc/resource/dcn32/dcn32_resource.h| 3 +- .../dc/resource/dcn401/dcn401_resource.h | 5 +- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 4 +- .../display/dc/spl/dc_spl_isharp_filters.c| 213 +- .../display/dc/spl/dc_spl_isharp_filters.h| 2 +- .../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 27 ++- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +- 48 files changed, 346 insertions(+), 532 deletions(-) -- 2.46.0
Re: [PATCH] drm/amd: Don't wake dGPUs while reading sensors
On 8/19/24 22:04, Mario Limonciello wrote:
From: Mario Limonciello
If the dGPU is off, then reading the sysfs files with a sensor monitoring
application will wake it. Change the behavior to return an error when the
dGPU is in D3cold.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 90 +++---
1 file changed, 45 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index c11952a4389bc..d6e38466fbb82 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -142,7 +142,7 @@ static ssize_t amdgpu_get_power_dpm_state(struct device
*dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
Seems like this expression is used rather often, so it might be good to
have an inline function for it. Something like the following:
static inline bool amdgpu_is_d3cold(struct amdgpu_dev *adev)
{
return adev->in_suspend || adev->in_runpm;
}
return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
@@ -173,7 +173,7 @@ static ssize_t amdgpu_set_power_dpm_state(struct device
*dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
return -EPERM;
if (strncmp("battery", buf, strlen("battery")) == 0)
@@ -270,7 +270,7 @@ static ssize_t
amdgpu_get_power_dpm_force_performance_level(struct device *dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
@@ -309,7 +309,7 @@ static ssize_t
amdgpu_set_power_dpm_force_performance_level(struct device *dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
return -EPERM;
if (strncmp("low", buf, strlen("low")) == 0) {
@@ -371,7 +371,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
@@ -409,7 +409,7 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
@@ -448,7 +448,7 @@ static ssize_t amdgpu_get_pp_force_state(struct device *dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
return -EPERM;
if (adev->pm.pp_force_state_enabled)
@@ -471,7 +471,7 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
return -EPERM;
adev->pm.pp_force_state_enabled = false;
@@ -541,7 +541,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
@@ -577,7 +577,7 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
@@ -760,7 +760,7 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device
*dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
return -EPERM;
if (count > 127 || count == 0)
@@ -862,7 +862,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device
*dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
return -EPERM;
ret = pm_runtime_get_sync(ddev->dev);
@@ -922,7 +922,7 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
if (amdgpu_in_reset(adev))
return -EPERM;
- if (adev->in_suspend && !adev->in_runpm)
+ if (adev->in_suspend || adev->in_runpm)
Re: [PATCH 1/1] drm/amdgpu/display: remove unecessary TODO spl_os_types.h
On 8/23/24 00:35, Zaeem Mohamed wrote: Remove TODO from spl_os_types.h Signed-off-by: Zaeem Mohamed s/unecessary TODO/unnecessary TODO in With that addressed: Reviewed-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h b/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h index 058306bb41aa..709706ed4f2c 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h @@ -18,7 +18,6 @@ * general debug capabilities * */ -// TODO: need backport #define SPL_BREAK_TO_DEBUGGER() ASSERT(0) static inline uint64_t spl_div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) -- Hamza
Re: [PATCH 1/1] drm/amdgpu/display: SPDX copyright for spl_os_types.h
On 8/22/24 20:14, Zaeem Mohamed wrote: Use appropriate SPDX copyright for spl_os_types.h Signed-off-by: Zaeem Mohamed Reviewed-by: Hamza Mahfooz --- .../gpu/drm/amd/display/dc/spl/spl_os_types.h | 29 +++ 1 file changed, 4 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h b/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h index 7ebea91c84f6..058306bb41aa 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h @@ -1,28 +1,7 @@ -/* - * Copyright 2012-16 Advanced Micro Devices, Inc. - * Copyright 2019 Raptor Engineering, LLC - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ +/* Copyright 2019 Raptor Engineering, LLC */ #ifndef _SPL_OS_TYPES_H_ #define _SPL_OS_TYPES_H_ -- Hamza
[PATCH v4 0/3] faster vblank disable
Since, drm_crtc_vblank_on_config() was recently introduced, we want to apply laxer vblanking policies across the board, since: 1. It will allow us to shut down interrupts faster for better power savings. 2. As a payment towards tech debt, since drm_vblank_offdelay (which defaults to 5s) isn't necessary on AMD hardware. Also, patches 2-3 in this series provide even laxer policies and they are intentionally separated from patch #1. This way, if issues with them are encountered in the wild, it should be easy to bisect the issue to those patches. Hamza Mahfooz (3): drm/amd/display: use drm_crtc_vblank_on_config() drm/amd/display: use a more lax vblank enable policy for DCN35+ drm/amd/display: use a more lax vblank enable policy for older ASICs .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 39 +-- 1 file changed, 28 insertions(+), 11 deletions(-) -- 2.46.0
[PATCH v4 2/3] drm/amd/display: use a more lax vblank enable policy for DCN35+
Ideally, we want to enable immediate vblank disable, when possible and
we should be able to do so on DCN35+, if PSR isn't supported by a given
CRTC.
Suggested-by: Leo Li
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 00d4c97e8d26..68442cb857fc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8246,7 +8246,8 @@ static void manage_dm_interrupts(struct amdgpu_device
*adev,
if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
IP_VERSION(3, 5, 0)) {
drm_crtc_vblank_on(&acrtc->base);
- } else {
+ } else if (acrtc_state->stream->link->psr_settings.psr_version <
+ DC_PSR_VERSION_UNSUPPORTED) {
timing = &acrtc_state->stream->timing;
/* at least 2 frames */
@@ -8258,6 +8259,10 @@ static void manage_dm_interrupts(struct amdgpu_device
*adev,
config.offdelay_ms = offdelay ?: 30;
drm_crtc_vblank_on_config(&acrtc->base,
&config);
+ } else {
+ config.disable_immediate = true;
+ drm_crtc_vblank_on_config(&acrtc->base,
+ &config);
}
amdgpu_irq_get(
--
2.46.0
[PATCH v4 3/3] drm/amd/display: use a more lax vblank enable policy for older ASICs
Ideally, we want to drop the legacy vblank enable for older ASICs. This
should be possible now, since we can now specify how many frames we need
to wait before disabling vblanking instead of being forced to either
choose between no delay (which can still be buggy) and
drm_vblank_offdelay (which is much longer by default than is required on
AMD hardware).
Suggested-by: Leo Li
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 68442cb857fc..8c34a7756c58 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8244,10 +8244,9 @@ static void manage_dm_interrupts(struct amdgpu_device
*adev,
if (acrtc_state) {
if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
- IP_VERSION(3, 5, 0)) {
- drm_crtc_vblank_on(&acrtc->base);
- } else if (acrtc_state->stream->link->psr_settings.psr_version <
- DC_PSR_VERSION_UNSUPPORTED) {
+ IP_VERSION(3, 5, 0) ||
+ acrtc_state->stream->link->psr_settings.psr_version <
+ DC_PSR_VERSION_UNSUPPORTED) {
timing = &acrtc_state->stream->timing;
/* at least 2 frames */
@@ -8257,14 +8256,13 @@ static void manage_dm_interrupts(struct amdgpu_device
*adev,
timing->pix_clk_100hz);
config.offdelay_ms = offdelay ?: 30;
- drm_crtc_vblank_on_config(&acrtc->base,
- &config);
} else {
config.disable_immediate = true;
- drm_crtc_vblank_on_config(&acrtc->base,
- &config);
}
+ drm_crtc_vblank_on_config(&acrtc->base,
+ &config);
+
amdgpu_irq_get(
adev,
&adev->pageflip_irq,
--
2.46.0
[PATCH v4 1/3] drm/amd/display: use drm_crtc_vblank_on_config()
Hook up drm_crtc_vblank_on_config() in amdgpu_dm. So, that we can enable
PSR and other static screen optimizations more quickly, while avoiding
stuttering issues that are accompanied by the following dmesg error:
[drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle:
status=3
This also allows us to mimic how vblanking is handled by the windows
amdgpu driver.
Signed-off-by: Hamza Mahfooz
---
v3: use a less conservative policy
v4: drop TODO, use simplified calculation from Michel, use
DIV64_U64_ROUND_UP() and use a different policy.
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 36 +--
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7e7929f24ae4..00d4c97e8d26 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4934,12 +4934,6 @@ static int amdgpu_dm_initialize_drm_device(struct
amdgpu_device *adev)
if (psr_feature_enabled)
amdgpu_dm_set_psr_caps(link);
-
- /* TODO: Fix vblank control helpers to delay
PSR entry to allow this when
-* PSR is also supported.
-*/
- if (link->psr_settings.psr_feature_enabled)
-
adev_to_drm(adev)->vblank_disable_immediate = false;
}
}
amdgpu_set_panel_orientation(&aconnector->base);
@@ -8232,7 +8226,7 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev,
static void manage_dm_interrupts(struct amdgpu_device *adev,
struct amdgpu_crtc *acrtc,
-bool enable)
+struct dm_crtc_state *acrtc_state)
{
/*
* We have no guarantee that the frontend index maps to the same
@@ -8244,9 +8238,28 @@ static void manage_dm_interrupts(struct amdgpu_device
*adev,
amdgpu_display_crtc_idx_to_irq_type(
adev,
acrtc->crtc_id);
+ struct drm_vblank_crtc_config config = {0};
+ struct dc_crtc_timing *timing;
+ int offdelay;
+
+ if (acrtc_state) {
+ if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
+ IP_VERSION(3, 5, 0)) {
+ drm_crtc_vblank_on(&acrtc->base);
+ } else {
+ timing = &acrtc_state->stream->timing;
+
+ /* at least 2 frames */
+ offdelay = DIV64_U64_ROUND_UP((u64)20 *
+ timing->v_total *
+ timing->h_total,
+ timing->pix_clk_100hz);
+
+ config.offdelay_ms = offdelay ?: 30;
+ drm_crtc_vblank_on_config(&acrtc->base,
+ &config);
+ }
- if (enable) {
- drm_crtc_vblank_on(&acrtc->base);
amdgpu_irq_get(
adev,
&adev->pageflip_irq,
@@ -9320,7 +9333,7 @@ static void amdgpu_dm_commit_streams(struct
drm_atomic_state *state,
if (old_crtc_state->active &&
(!new_crtc_state->active ||
drm_atomic_crtc_needs_modeset(new_crtc_state))) {
- manage_dm_interrupts(adev, acrtc, false);
+ manage_dm_interrupts(adev, acrtc, NULL);
dc_stream_release(dm_old_crtc_state->stream);
}
}
@@ -9835,7 +9848,8 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
drm_atomic_crtc_needs_modeset(new_crtc_state))) {
dc_stream_retain(dm_new_crtc_state->stream);
acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
- manage_dm_interrupts(adev, acrtc, true);
+ manage_dm_interrupts(adev, acrtc,
+to_dm_crtc_state(new_crtc_state));
}
/* Handle vrr on->off / off->on transitions */
amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
dm_new_crtc_state);
--
2.46.0
Re: [PATCH v2 65/86] drm/amdgpu: Run DRM default client setup
On 8/21/24 09:00, Thomas Zimmermann wrote:
Call drm_client_setup() to run the kernel's default client setup
for DRM. Set fbdev_probe in struct drm_driver, so that the client
setup can start the common fbdev client.
The amdgpu driver specifies a preferred color mode depending on
the available video memory, with a default of 32. Adapt this for
the new client interface.
v2:
- style changes
Signed-off-by: Thomas Zimmermann
Cc: Alex Deucher
Cc: "Christian König"
Cc: Xinhui Pan
Tested-by: Hamza Mahfooz
Acked-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 5dd39e6c6223..849d59e2bca7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include
#include
#include
@@ -2341,11 +2342,15 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
*/
if (adev->mode_info.mode_config_initialized &&
!list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
+ const struct drm_format_info *format;
+
/* select 8 bpp console on low vram cards */
if (adev->gmc.real_vram_size <= (32*1024*1024))
- drm_fbdev_ttm_setup(adev_to_drm(adev), 8);
+ format = drm_format_info(DRM_FORMAT_C8);
else
- drm_fbdev_ttm_setup(adev_to_drm(adev), 32);
+ format = NULL;
+
+ drm_client_setup(adev_to_drm(adev), format);
}
ret = amdgpu_debugfs_init(adev);
@@ -2957,6 +2962,7 @@ static const struct drm_driver amdgpu_kms_driver = {
.num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
.dumb_create = amdgpu_mode_dumb_create,
.dumb_map_offset = amdgpu_mode_dumb_mmap,
+ DRM_FBDEV_TTM_DRIVER_OPS,
.fops = &amdgpu_driver_kms_fops,
.release = &amdgpu_driver_release_kms,
#ifdef CONFIG_PROC_FS
@@ -2983,6 +2989,7 @@ const struct drm_driver amdgpu_partition_driver = {
.num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
.dumb_create = amdgpu_mode_dumb_create,
.dumb_map_offset = amdgpu_mode_dumb_mmap,
+ DRM_FBDEV_TTM_DRIVER_OPS,
.fops = &amdgpu_driver_kms_fops,
.release = &amdgpu_driver_release_kms,
--
Hamza
[PATCH v3] drm/amd/display: use drm_crtc_vblank_on_config()
Hook up drm_crtc_vblank_on_config() in amdgpu_dm. So, that we can enable
PSR and other static screen optimizations more quickly, while avoiding
stuttering issues that are accompanied by the following dmesg error:
[drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle:
status=3
This also allows us to mimic how vblanking is handled by the windows
amdgpu driver.
Signed-off-by: Hamza Mahfooz
---
v3: use a less conservative policy
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 38 ---
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7e7929f24ae4..b8f57b466c35 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8232,7 +8232,7 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev,
static void manage_dm_interrupts(struct amdgpu_device *adev,
struct amdgpu_crtc *acrtc,
-bool enable)
+struct dm_crtc_state *acrtc_state)
{
/*
* We have no guarantee that the frontend index maps to the same
@@ -8244,9 +8244,36 @@ static void manage_dm_interrupts(struct amdgpu_device
*adev,
amdgpu_display_crtc_idx_to_irq_type(
adev,
acrtc->crtc_id);
+ struct drm_vblank_crtc_config config = {0};
+ struct dc_crtc_timing *timing;
+ int vsync_rate_hz;
+ int offdelay = 30;
+
+ if (acrtc_state) {
+ timing = &acrtc_state->stream->timing;
+
+ vsync_rate_hz = div64_u64(div64_u64((timing->pix_clk_100hz *
+(u64)100),
+ timing->v_total),
+ timing->h_total);
+
+ if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
+ IP_VERSION(3, 5, 0) ||
+ acrtc_state->stream->link->psr_settings.psr_version <
+ DC_PSR_VERSION_UNSUPPORTED) {
+ if (vsync_rate_hz)
+ /* at least 2 frames */
+ offdelay = 2000 / vsync_rate_hz + 1;
+
+ config.offdelay_ms = offdelay;
+ drm_crtc_vblank_on_config(&acrtc->base,
+ &config);
+ } else {
+ config.disable_immediate = true;
+ drm_crtc_vblank_on_config(&acrtc->base,
+ &config);
+ }
- if (enable) {
- drm_crtc_vblank_on(&acrtc->base);
amdgpu_irq_get(
adev,
&adev->pageflip_irq,
@@ -9320,7 +9347,7 @@ static void amdgpu_dm_commit_streams(struct
drm_atomic_state *state,
if (old_crtc_state->active &&
(!new_crtc_state->active ||
drm_atomic_crtc_needs_modeset(new_crtc_state))) {
- manage_dm_interrupts(adev, acrtc, false);
+ manage_dm_interrupts(adev, acrtc, NULL);
dc_stream_release(dm_old_crtc_state->stream);
}
}
@@ -9835,7 +9862,8 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
drm_atomic_crtc_needs_modeset(new_crtc_state))) {
dc_stream_retain(dm_new_crtc_state->stream);
acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
- manage_dm_interrupts(adev, acrtc, true);
+ manage_dm_interrupts(adev, acrtc,
+to_dm_crtc_state(new_crtc_state));
}
/* Handle vrr on->off / off->on transitions */
amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
dm_new_crtc_state);
--
2.46.0
[PATCH] drm/amd/display: change the panel power savings level without a modeset
We don't actually need to request that the compositor does a full
modeset to modify the panel power savings level, we can instead
just make a request to DMUB, to set the new level dynamically.
Cc: Harry Wentland
Cc: Leo Li
Cc: Mario Limonciello
Cc: Sebastian Wick
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 +++-
drivers/gpu/drm/amd/display/dc/core/dc.c | 39 +++
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
3 files changed, 41 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index dd8353283bda..00a8a5959aa9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6819,9 +6819,14 @@ static ssize_t panel_power_savings_store(struct device
*device,
const char *buf, size_t count)
{
struct drm_connector *connector = dev_get_drvdata(device);
+ struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
struct drm_device *dev = connector->dev;
+ struct amdgpu_device *adev = drm_to_adev(dev);
+ struct dc *dc = adev->dm.dc;
+ struct pipe_ctx *pipe_ctx;
long val;
int ret;
+ int i;
ret = kstrtol(buf, 0, &val);
@@ -6836,7 +6841,17 @@ static ssize_t panel_power_savings_store(struct device
*device,
ABM_LEVEL_IMMEDIATE_DISABLE;
drm_modeset_unlock(&dev->mode_config.connection_mutex);
- drm_kms_helper_hotplug_event(dev);
+ mutex_lock(&adev->dm.dc_lock);
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe_ctx->stream &&
+ pipe_ctx->stream->link == aconn->dc_link) {
+ dc_set_abm_level(dc, pipe_ctx, val);
+ break;
+ }
+ }
+ mutex_unlock(&adev->dm.dc_lock);
return count;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 3ba2acfdae2a..60081cd978b7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3319,6 +3319,23 @@ static bool update_planes_and_stream_state(struct dc *dc,
}
+void dc_set_abm_level(struct dc *dc, struct pipe_ctx *pipe_ctx, int level)
+{
+ struct timing_generator *tg = pipe_ctx->stream_res.tg;
+ struct abm *abm = pipe_ctx->stream_res.abm;
+
+ if (!abm)
+ return;
+
+ if (tg->funcs->is_blanked && !tg->funcs->is_blanked(tg))
+ tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
+
+ if (level == ABM_LEVEL_IMMEDIATE_DISABLE)
+ dc->hwss.set_abm_immediate_disable(pipe_ctx);
+ else
+ abm->funcs->set_abm_level(abm, level);
+}
+
static void commit_planes_do_stream_update(struct dc *dc,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update,
@@ -3447,22 +3464,12 @@ static void commit_planes_do_stream_update(struct dc
*dc,
dc->link_srv->set_dpms_on(dc->current_state,
pipe_ctx);
}
- if (stream_update->abm_level &&
pipe_ctx->stream_res.abm) {
- bool should_program_abm = true;
-
- // if otg funcs defined check if blanked before
programming
- if (pipe_ctx->stream_res.tg->funcs->is_blanked)
- if
(pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
- should_program_abm = false;
-
- if (should_program_abm) {
- if (*stream_update->abm_level ==
ABM_LEVEL_IMMEDIATE_DISABLE) {
-
dc->hwss.set_abm_immediate_disable(pipe_ctx);
- } else {
-
pipe_ctx->stream_res.abm->funcs->set_abm_level(
-
pipe_ctx->stream_res.abm, stream->abm_level);
- }
- }
+ if (stream_update->abm_level) {
+ dc_set_abm_level(dc, pipe_ctx,
+*stream_update->abm_level ==
+ABM_LEVEL_IMMEDIATE_DISABLE ?
+ABM_LEVEL_IMMEDIATE_DISABLE :
+
[PATCH] drm/amd/display: fix s2idle entry for DCN3.5+
To be able to get to the lowest power state when suspending systems with DCN3.5+, we must be in IPS before the display hardware is put into D3cold. So, to ensure that the system always reaches the lowest power state while suspending force systems that support IPS to enter idle optimizations before entering D3cold. Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a312c74f1e81..1169b0de7760 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2904,6 +2904,9 @@ static int dm_suspend(void *handle) hpd_rx_irq_work_suspend(dm); + if (adev->dm.dc->caps.ips_support) + dc_allow_idle_optimizations(adev->dm.dc, true); + dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); -- 2.45.2
Re: [REGRESSION] Brightness at max level after waking up from sleep on AMD Laptop
On 7/31/24 02:38, Linux regression tracking (Thorsten Leemhuis) wrote:
[+amd-glx, +lkml, +dri-devel]
On 27.07.24 18:52, serg.parti...@gmail.com wrote:
After updating from 6.8.9 to 6.9.1 I noticed a bug on my HP Envy x360
with AMD Ryzen 5 4500U.
[...]
After waking up from sleep brightness is set to max level, ignoring
previous value.
With the help of Arch Linux team, we was able to track bad commit to
this:
https://gitlab.freedesktop.org/agd5f/linux/-/commit/63d0b87213a0ba241b3fcfba3fe7b0aed0cd1cc5
Hamza Mahfooz, in case you missed it, that is a patch of yours:
63d0b87213a0ba ("drm/amd/display: add panel_power_savings sysfs entry to
eDP connectors") [v6.9-rc1].
Um, for the time being you should be able to set `amdgpu.abmlevel=0` in
the kernel's cmdline to avoid the issue.
I have tested this on latest mainline kernel:
Results after waking up:
cat /sys/class/backlight/amdgpu_bl1/{brightness,actual_brightness}
12
252
Then, on exact this commit (63d0b87213a0ba241b3fcfba3fe7b0aed0cd1cc5),
result is the same.
Then, on commit just before this one (aeaf3e6cf842):
cat /sys/class/backlight/amdgpu_bl1/{brightness,actual_brightness}
12
12
I hope I included all relevant information, more info can be found here:
https://gitlab.archlinux.org/archlinux/packaging/packages/linux/-/issues/52
Ciao, Thorsten (wearing his 'the Linux kernel's regression tracker' hat)
--
Everything you wanna know about Linux kernel regression tracking:
https://linux-regtracking.leemhuis.info/about/#tldr
If I did something stupid, please tell me, as explained on that page.
P.S.:
#regzbot introduced: 63d0b87213a0ba241
--
Hamza
[PATCH 2/2] Revert "drm/amd: Add power_saving_policy drm property to eDP connectors"
This reverts commit 9d8c094ddab05db88d183ba82e23be807848cad8.
It was merged without meeting userspace requirements.
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 --
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 52 ++-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 -
3 files changed, 5 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 879b4a04c588..092ec11258cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1407,10 +1407,6 @@ int amdgpu_display_modeset_create_props(struct
amdgpu_device *adev)
"dither",
amdgpu_dither_enum_list, sz);
- if (adev->dc_enabled)
- drm_mode_create_power_saving_policy_property(adev_to_drm(adev),
-
DRM_MODE_POWER_SAVING_POLICY_ALL);
-
return 0;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0ce983ab5d65..7e7929f24ae4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6725,14 +6725,6 @@ int amdgpu_dm_connector_atomic_set_property(struct
drm_connector *connector,
} else if (property == adev->mode_info.underscan_property) {
dm_new_state->underscan_enable = val;
ret = 0;
- } else if (property == dev->mode_config.power_saving_policy) {
- dm_new_state->abm_forbidden = val &
DRM_MODE_REQUIRE_COLOR_ACCURACY;
- dm_new_state->abm_level = (dm_new_state->abm_forbidden ||
- !dm_old_state->abm_level) ?
- ABM_LEVEL_IMMEDIATE_DISABLE :
- dm_old_state->abm_level;
- dm_new_state->psr_forbidden = val &
DRM_MODE_REQUIRE_LOW_LATENCY;
- ret = 0;
}
return ret;
@@ -6775,13 +6767,6 @@ int amdgpu_dm_connector_atomic_get_property(struct
drm_connector *connector,
} else if (property == adev->mode_info.underscan_property) {
*val = dm_state->underscan_enable;
ret = 0;
- } else if (property == dev->mode_config.power_saving_policy) {
- *val = 0;
- if (dm_state->psr_forbidden)
- *val |= DRM_MODE_REQUIRE_LOW_LATENCY;
- if (dm_state->abm_forbidden)
- *val |= DRM_MODE_REQUIRE_COLOR_ACCURACY;
- ret = 0;
}
return ret;
@@ -6808,12 +6793,9 @@ static ssize_t panel_power_savings_show(struct device
*device,
u8 val;
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
- if (to_dm_connector_state(connector->state)->abm_forbidden)
- val = 0;
- else
- val = to_dm_connector_state(connector->state)->abm_level ==
- ABM_LEVEL_IMMEDIATE_DISABLE ? 0 :
- to_dm_connector_state(connector->state)->abm_level;
+ val = to_dm_connector_state(connector->state)->abm_level ==
+ ABM_LEVEL_IMMEDIATE_DISABLE ? 0 :
+ to_dm_connector_state(connector->state)->abm_level;
drm_modeset_unlock(&dev->mode_config.connection_mutex);
return sysfs_emit(buf, "%u\n", val);
@@ -6837,16 +6819,10 @@ static ssize_t panel_power_savings_store(struct device
*device,
return -EINVAL;
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
- if (to_dm_connector_state(connector->state)->abm_forbidden)
- ret = -EBUSY;
- else
- to_dm_connector_state(connector->state)->abm_level = val ?:
- ABM_LEVEL_IMMEDIATE_DISABLE;
+ to_dm_connector_state(connector->state)->abm_level = val ?:
+ ABM_LEVEL_IMMEDIATE_DISABLE;
drm_modeset_unlock(&dev->mode_config.connection_mutex);
- if (ret)
- return ret;
-
drm_kms_helper_hotplug_event(dev);
return count;
@@ -8040,14 +8016,6 @@ void amdgpu_dm_connector_init_helper(struct
amdgpu_display_manager *dm,
aconnector->base.state->max_bpc = 16;
aconnector->base.state->max_requested_bpc =
aconnector->base.state->max_bpc;
- if (connector_type == DRM_MODE_CONNECTOR_eDP &&
- (dc_is_dmcu_initialized(adev->dm.dc) ||
-adev->dm.dc->ctx->dmub_srv)) {
- drm_object_attach_property(&aconnector->base.base,
-
[PATCH 1/2] Revert "drm: Introduce 'power saving policy' drm property"
This reverts commit 76299a557f36d624ca32500173ad7856e1ad93c0.
It was merged without meeting userspace requirements.
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/drm_connector.c | 48 -
include/drm/drm_connector.h | 2 --
include/drm/drm_mode_config.h | 5
include/uapi/drm/drm_mode.h | 7 -
4 files changed, 62 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 7c44e3a1d8e0..b4f4d2f908d1 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1043,11 +1043,6 @@ static const struct drm_prop_enum_list
drm_scaling_mode_enum_list[] = {
{ DRM_MODE_SCALE_ASPECT, "Full aspect" },
};
-static const struct drm_prop_enum_list drm_power_saving_policy_enum_list[] = {
- { __builtin_ffs(DRM_MODE_REQUIRE_COLOR_ACCURACY) - 1, "Require color
accuracy" },
- { __builtin_ffs(DRM_MODE_REQUIRE_LOW_LATENCY) - 1, "Require low
latency" },
-};
-
static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
{ DRM_MODE_PICTURE_ASPECT_NONE, "Automatic" },
{ DRM_MODE_PICTURE_ASPECT_4_3, "4:3" },
@@ -1634,16 +1629,6 @@ EXPORT_SYMBOL(drm_hdmi_connector_get_output_format_name);
*
* Drivers can set up these properties by calling
* drm_mode_create_tv_margin_properties().
- * power saving policy:
- * This property is used to set the power saving policy for the connector.
- * This property is populated with a bitmask of optional requirements set
- * by the drm master for the drm driver to respect:
- * - "Require color accuracy": Disable power saving features that will
- * affect color fidelity.
- * For example: Hardware assisted backlight modulation.
- * - "Require low latency": Disable power saving features that will
- * affect latency.
- * For example: Panel self refresh (PSR)
*/
int drm_connector_create_standard_properties(struct drm_device *dev)
@@ -2146,39 +2131,6 @@ int drm_mode_create_scaling_mode_property(struct
drm_device *dev)
}
EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
-/**
- * drm_mode_create_power_saving_policy_property - create power saving policy
property
- * @dev: DRM device
- * @supported_policies: bitmask of supported power saving policies
- *
- * Called by a driver the first time it's needed, must be attached to desired
- * connectors.
- *
- * Returns: %0
- */
-int drm_mode_create_power_saving_policy_property(struct drm_device *dev,
-uint64_t supported_policies)
-{
- struct drm_property *power_saving;
-
- if (dev->mode_config.power_saving_policy)
- return 0;
- WARN_ON((supported_policies & DRM_MODE_POWER_SAVING_POLICY_ALL) == 0);
-
- power_saving =
- drm_property_create_bitmask(dev, 0, "power saving policy",
- drm_power_saving_policy_enum_list,
-
ARRAY_SIZE(drm_power_saving_policy_enum_list),
- supported_policies);
- if (!power_saving)
- return -ENOMEM;
-
- dev->mode_config.power_saving_policy = power_saving;
-
- return 0;
-}
-EXPORT_SYMBOL(drm_mode_create_power_saving_policy_property);
-
/**
* DOC: Variable refresh properties
*
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 5ad735253413..e3fa43291f44 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -2267,8 +2267,6 @@ int drm_mode_create_dp_colorspace_property(struct
drm_connector *connector,
u32 supported_colorspaces);
int drm_mode_create_content_type_property(struct drm_device *dev);
int drm_mode_create_suggested_offset_properties(struct drm_device *dev);
-int drm_mode_create_power_saving_policy_property(struct drm_device *dev,
-uint64_t supported_policies);
int drm_connector_set_path_property(struct drm_connector *connector,
const char *path);
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index 150f9a3b649f..ab0f167474b1 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -969,11 +969,6 @@ struct drm_mode_config {
*/
struct drm_atomic_state *suspend_state;
- /**
-* @power_saving_policy: bitmask for power saving policy requests.
-*/
- struct drm_property *power_saving_policy;
-
const struct drm_mode_config_helper_funcs *helper_private;
};
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 880303c2ad97..d390011b89b4 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -152,13 +152,
Re: [PATCH] drm/edid: add CTA Video Format Data Block support
On 7/31/24 04:36, Jani Nikula wrote:
On Tue, 30 Jul 2024, Hamza Mahfooz wrote:
Video Format Data Blocks (VFDBs) contain the necessary information that
needs to be fed to the Optimized Video Timings (OVT) Algorithm.
Also, we require OVT support to cover modes that aren't supported by
earlier standards (e.g. CVT). So, parse all of the relevant VFDB data
and feed it to the OVT Algorithm, to extract all of the missing OVT
modes.
Is VFDB new to CTA-861-I? AFAICT the H version doesn't have it.
I believe it first appeared in CTA-861.6.
Is there any particular reason for the two step approach here? I mean
first allocating and storing the modes in drm_parse_cea_ext() and then
adding them in _drm_edid_connector_add_modes()? I think you could just
as well do everything in the latter, without the complications of
allocation. See e.g. add_cea_modes() which also iterates the CTA data
blocks. I think this would simplify everything considerably.
It just seemed like the logical place to put it I guess. But looking at
it again, it would make more sense to just do everything in
_drm_edid_connector_add_modes().
Please find some additional comments inline. I'll do more when I've got
hold of CTA-861-I.
BR,
Jani.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1442
Suggested-by: Karol Herbst
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/drm_edid.c | 426
include/drm/drm_connector.h | 12 +
2 files changed, 438 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f68a41eeb1fa..112a0070c4d5 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -741,6 +742,93 @@ static const struct minimode extra_modes[] = {
{ 2048, 1536, 60, 0 },
};
+struct cta_rid {
+ u16 hactive;
+ u16 vactive;
+ u8 hratio;
+ u8 vratio;
+};
+
+/* CTA-861-I Table 11 - Resolution Identification (RID) */
+static const struct cta_rid rids[] = {
+ /* RID 0-9 */
+ { 0, 0, 0, 0 },
+ { 1280, 720, 16, 9 },
+ { 1280, 720, 64, 27 },
+ { 1680, 720, 64, 27 },
+ { 1920, 1080, 16, 9 },
+ { 1920, 1080, 64, 27 },
+ { 2560, 1080, 64, 27 },
+ { 3840, 1080, 32, 9 },
+ { 2560, 1440, 16, 9 },
+ { 3440, 1440, 64, 27 },
+ /* RID 10-19 */
+ { 5120, 1440, 32, 9 },
+ { 3840, 2160, 16, 9 },
+ { 3840, 2160, 64, 27 },
+ { 5120, 2160, 64, 27 },
+ { 7680, 2160, 32, 9 },
+ { 5120, 2880, 16, 9 },
+ { 5120, 2880, 64, 27 },
+ { 6880, 2880, 64, 27 },
+ { 10240, 2880, 32, 9 },
+ { 7680, 4320, 16, 9 },
+ /* RID 20-28 */
+ { 7680, 4320, 64, 27 },
+ { 10240, 4320, 64, 27 },
+ { 15360, 4320, 32, 9 },
+ { 11520, 6480, 16, 9 },
+ { 11520, 6480, 64, 27 },
+ { 15360, 6480, 64, 27 },
+ { 15360, 8640, 16, 9 },
+ { 15360, 8640, 64, 27 },
+ { 20480, 8640, 64, 27 },
+};
+
+/* CTA-861-I Table 12 - AVI InfoFrame Video Format Frame Rate */
+static const u16 cta_vf_fr[] = {
+ /* Frame Rate 0-7 */
+ 0, 24, 25, 30, 48, 50, 60, 100,
+ /* Frame Rate 8-15 */
+ 120, 144, 200, 240, 300, 360, 400, 480,
+};
+
+/* CTA-861-I Table 13 - RID To VIC Mapping */
+static const u8 rid_to_vic[][8] = {
+ /* RID 0-9 */
+ {},
+ { 60, 61, 62, 108, 19, 4, 41, 47 },
+ { 65, 66, 67, 109, 68, 69, 70, 71 },
+ { 79, 80, 81, 110, 82, 83, 84, 85 },
+ { 32, 33, 34, 111, 31, 16, 64, 63 },
+ { 72, 73, 74, 112, 75, 76, 77, 78 },
+ { 86, 87, 88, 113, 89, 90, 91, 92 },
+ {},
+ {},
+ {},
+ /* RID 10-19 */
+ {},
+ { 93, 94, 95, 114, 96, 97, 117, 118 },
+ { 103, 104, 105, 116, 106, 107, 119, 120 },
+ { 121, 122, 123, 124, 125, 126, 127, 193 },
+ {},
+ {},
+ {},
+ {},
+ {},
+ { 194, 195, 196, 197, 198, 199, 200, 201 },
+ /* RID 20-28 */
+ { 202, 203, 204, 205, 206, 207, 208, 209 },
+ { 210, 211, 212, 213, 214, 215, 216, 217 },
+ {},
+ {},
+ {},
+ {},
+ {},
+ {},
+ {},
+};
+
/*
* From CEA/CTA-861 spec.
*
@@ -4140,6 +4228,7 @@ static int add_detailed_modes(struct drm_connector
*connector,
#define CTA_DB_VIDEO 2
#define CTA_DB_VENDOR 3
#define CTA_DB_SPEAKER4
+#define CTA_DB_VIDEO_FORMAT6
#define CTA_DB_EXTENDED_TAG 7
/* CTA-861-H Table 62 - CTA Extended Tag Codes */
@@ -4981,6 +5070,16 @@ struct cea_db {
u8 data[];
} __packed;
+struct cta_vfd {
+ u8 rid;
+ u8 fr_fact;
+ bool bfr50;
+ bool fr24;
+ bool bfr60;
+ bool fr144;
+ bool fr48;
+};
+
static int cea_db_tag(const struct cea_db *db)
{
return
[PATCH] drm/edid: add CTA Video Format Data Block support
Video Format Data Blocks (VFDBs) contain the necessary information that
needs to be fed to the Optimized Video Timings (OVT) Algorithm.
Also, we require OVT support to cover modes that aren't supported by
earlier standards (e.g. CVT). So, parse all of the relevant VFDB data
and feed it to the OVT Algorithm, to extract all of the missing OVT
modes.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1442
Suggested-by: Karol Herbst
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/drm_edid.c | 426
include/drm/drm_connector.h | 12 +
2 files changed, 438 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f68a41eeb1fa..112a0070c4d5 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -741,6 +742,93 @@ static const struct minimode extra_modes[] = {
{ 2048, 1536, 60, 0 },
};
+struct cta_rid {
+ u16 hactive;
+ u16 vactive;
+ u8 hratio;
+ u8 vratio;
+};
+
+/* CTA-861-I Table 11 - Resolution Identification (RID) */
+static const struct cta_rid rids[] = {
+ /* RID 0-9 */
+ { 0, 0, 0, 0 },
+ { 1280, 720, 16, 9 },
+ { 1280, 720, 64, 27 },
+ { 1680, 720, 64, 27 },
+ { 1920, 1080, 16, 9 },
+ { 1920, 1080, 64, 27 },
+ { 2560, 1080, 64, 27 },
+ { 3840, 1080, 32, 9 },
+ { 2560, 1440, 16, 9 },
+ { 3440, 1440, 64, 27 },
+ /* RID 10-19 */
+ { 5120, 1440, 32, 9 },
+ { 3840, 2160, 16, 9 },
+ { 3840, 2160, 64, 27 },
+ { 5120, 2160, 64, 27 },
+ { 7680, 2160, 32, 9 },
+ { 5120, 2880, 16, 9 },
+ { 5120, 2880, 64, 27 },
+ { 6880, 2880, 64, 27 },
+ { 10240, 2880, 32, 9 },
+ { 7680, 4320, 16, 9 },
+ /* RID 20-28 */
+ { 7680, 4320, 64, 27 },
+ { 10240, 4320, 64, 27 },
+ { 15360, 4320, 32, 9 },
+ { 11520, 6480, 16, 9 },
+ { 11520, 6480, 64, 27 },
+ { 15360, 6480, 64, 27 },
+ { 15360, 8640, 16, 9 },
+ { 15360, 8640, 64, 27 },
+ { 20480, 8640, 64, 27 },
+};
+
+/* CTA-861-I Table 12 - AVI InfoFrame Video Format Frame Rate */
+static const u16 cta_vf_fr[] = {
+ /* Frame Rate 0-7 */
+ 0, 24, 25, 30, 48, 50, 60, 100,
+ /* Frame Rate 8-15 */
+ 120, 144, 200, 240, 300, 360, 400, 480,
+};
+
+/* CTA-861-I Table 13 - RID To VIC Mapping */
+static const u8 rid_to_vic[][8] = {
+ /* RID 0-9 */
+ {},
+ { 60, 61, 62, 108, 19, 4, 41, 47 },
+ { 65, 66, 67, 109, 68, 69, 70, 71 },
+ { 79, 80, 81, 110, 82, 83, 84, 85 },
+ { 32, 33, 34, 111, 31, 16, 64, 63 },
+ { 72, 73, 74, 112, 75, 76, 77, 78 },
+ { 86, 87, 88, 113, 89, 90, 91, 92 },
+ {},
+ {},
+ {},
+ /* RID 10-19 */
+ {},
+ { 93, 94, 95, 114, 96, 97, 117, 118 },
+ { 103, 104, 105, 116, 106, 107, 119, 120 },
+ { 121, 122, 123, 124, 125, 126, 127, 193 },
+ {},
+ {},
+ {},
+ {},
+ {},
+ { 194, 195, 196, 197, 198, 199, 200, 201 },
+ /* RID 20-28 */
+ { 202, 203, 204, 205, 206, 207, 208, 209 },
+ { 210, 211, 212, 213, 214, 215, 216, 217 },
+ {},
+ {},
+ {},
+ {},
+ {},
+ {},
+ {},
+};
+
/*
* From CEA/CTA-861 spec.
*
@@ -4140,6 +4228,7 @@ static int add_detailed_modes(struct drm_connector
*connector,
#define CTA_DB_VIDEO 2
#define CTA_DB_VENDOR 3
#define CTA_DB_SPEAKER 4
+#define CTA_DB_VIDEO_FORMAT6
#define CTA_DB_EXTENDED_TAG7
/* CTA-861-H Table 62 - CTA Extended Tag Codes */
@@ -4981,6 +5070,16 @@ struct cea_db {
u8 data[];
} __packed;
+struct cta_vfd {
+ u8 rid;
+ u8 fr_fact;
+ bool bfr50;
+ bool fr24;
+ bool bfr60;
+ bool fr144;
+ bool fr48;
+};
+
static int cea_db_tag(const struct cea_db *db)
{
return db->tag_length >> 5;
@@ -6018,6 +6117,307 @@ static void parse_cta_vdb(struct drm_connector
*connector, const struct cea_db *
}
}
+/* CTA-861 Video Format Descriptor (CTA VFD) */
+static void parse_cta_vfd(const u8 *data, int vfd_len, struct cta_vfd *vfd)
+{
+ vfd->rid = data[0] & 0x3f;
+ vfd->bfr50 = data[0] >> 7;
+ vfd->fr24 = !!(data[0] & 0x40);
+ vfd->bfr60 = vfd_len > 1 ? (data[1] >> 7) : 0x1;
+ vfd->fr144 = vfd_len > 1 ? !!(data[1] & 0x40) : 0x0;
+ vfd->fr_fact = vfd_len > 1 ? (data[1] & 0x3f) : 0x3;
+ vfd->fr48 = vfd_len > 2 ? !!(data[2] & 0x1) : 0x0;
+}
+
+static bool vfd_has_fr(const struct cta_vfd *vfd, int rate_idx)
+{
+ static const u8 factors[6] = {
+ 1, 2, 4, 8, 12, 16
+ };
+ u16 rate = cta_vf_fr[rate_idx];
+ u16 factor = 0;
+ unsign
Re: [PATCH] drm/amd/display: Add null check for dm_state in create_validate_stream_for_sink
On 7/16/24 11:08, Srinivasan Shanmugam wrote:
This commit adds a null check for the dm_state variable in the
create_validate_stream_for_sink function. Previously, dm_state was being
checked for nullity at line 7194, but then it was being dereferenced
without any nullity check at line 7200. This could potentially lead to a
null pointer dereference error if dm_state is indeed null.
we now ensure that dm_state is not null before dereferencing it. We do
this by adding a nullity check for dm_state before the call to
create_stream_for_sink at line 7200. If dm_state is null, we log an
error message and return NULL immediately.
This fix prevents a null pointer dereference error.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:7201
create_validate_stream_for_sink()
error: we previously assumed 'dm_state' could be null (see line 7194)
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c
7185 struct dc_stream_state *
7186 create_validate_stream_for_sink(struct amdgpu_dm_connector
*aconnector,
7187 const struct drm_display_mode
*drm_mode,
7188 const struct dm_connector_state
*dm_state,
7189 const struct dc_stream_state
*old_stream)
7190 {
7191 struct drm_connector *connector = &aconnector->base;
7192 struct amdgpu_device *adev = drm_to_adev(connector->dev);
7193 struct dc_stream_state *stream;
7194 const struct drm_connector_state *drm_state = dm_state ?
&dm_state->base : NULL;
^ This used check
connector->state but then we changed it to dm_state instead
7195 int requested_bpc = drm_state ? drm_state->max_requested_bpc
: 8;
7196 enum dc_status dc_result = DC_OK;
7197
7198 do {
7199 stream = create_stream_for_sink(connector, drm_mode,
7200 dm_state, old_stream,
But dm_state is dereferenced on the next line without checking. (Presumably
the NULL check can be removed).
--> 7201 requested_bpc);
7202 if (stream == NULL) {
7203 DRM_ERROR("Failed to create stream for
sink!\n");
7204 break;
7205 }
7206
7207 if (aconnector->base.connector_type ==
DRM_MODE_CONNECTOR_WRITEBACK)
Fixes: fa7041d9d2fc ("drm/amd/display: Fix ineffective setting of max bpc
property")
Reported-by: Dan Carpenter
Cc: Tom Chung
Cc: Rodrigo Siqueira
Cc: Roman Li
Cc: Hersen Wu
Cc: Alex Hung
Cc: Aurabindo Pillai
Cc: Harry Wentland
Cc: Hamza Mahfooz
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d1527c2e46a1..b7eaece455c8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7195,6 +7195,11 @@ create_validate_stream_for_sink(struct
amdgpu_dm_connector *aconnector,
int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
enum dc_status dc_result = DC_OK;
+ if (!dm_state) {
+ DRM_ERROR("dm_state is NULL!\n");
Use drm_err() instead, DRM_ERROR() is deprecated.
+ return NULL;
+ }
+
do {
stream = create_stream_for_sink(connector, drm_mode,
dm_state, old_stream,
--
Hamza
Re: [PATCH AUTOSEL 6.9 11/22] drm/amd/display: Reset freesync config before update new state
Hi Sasha,
On 7/16/24 10:24, Sasha Levin wrote:
From: Tom Chung
[ Upstream commit 6b8487cdf9fc7bae707519ac5b5daeca18d1e85b ]
[Why]
Sometimes the new_crtc_state->vrr_infopacket did not sync up with the
current state.
It will affect the update_freesync_state_on_stream() does not update
the state correctly.
[How]
Reset the freesync config before get_freesync_config_for_crtc() to
make sure we have the correct new_crtc_state for VRR.
Please drop this patch from the stable queue entirely, since it has
already been reverted (as of commit dc1000bf463d ("Revert
"drm/amd/display: Reset freesync config before update new state"")).
Reviewed-by: Sun peng Li
Signed-off-by: Jerry Zuo
Signed-off-by: Tom Chung
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f866a02f4f489..53a55270998cc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -10028,6 +10028,7 @@ static int dm_update_crtc_state(struct
amdgpu_display_manager *dm,
}
/* Update Freesync settings. */
+ reset_freesync_config_for_crtc(dm_new_crtc_state);
get_freesync_config_for_crtc(dm_new_crtc_state,
dm_new_conn_state);
--
Hamza
Re: [PATCH 2/2] drm/amd/display: use drm_crtc_set_vblank_offdelay()
On 7/10/24 04:43, Daniel Vetter wrote:
On Tue, Jul 09, 2024 at 10:02:08AM -0400, Hamza Mahfooz wrote:
On 7/9/24 06:09, Daniel Vetter wrote:
On Tue, Jul 09, 2024 at 11:32:11AM +0200, Daniel Vetter wrote:
On Mon, Jul 08, 2024 at 04:29:07PM -0400, Hamza Mahfooz wrote:
Hook up drm_crtc_set_vblank_offdelay() in amdgpu_dm, so that we can
enable PSR more quickly for displays that support it.
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++-
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fdbc9b57a23d..ee6c31e9d3c4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8231,7 +8231,7 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev,
static void manage_dm_interrupts(struct amdgpu_device *adev,
struct amdgpu_crtc *acrtc,
-bool enable)
+struct dm_crtc_state *acrtc_state)
{
/*
* We have no guarantee that the frontend index maps to the same
@@ -8239,12 +8239,25 @@ static void manage_dm_interrupts(struct amdgpu_device
*adev,
*
* TODO: Use a different interrupt or check DC itself for the mapping.
*/
- int irq_type =
- amdgpu_display_crtc_idx_to_irq_type(
- adev,
- acrtc->crtc_id);
+ int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
+ acrtc->crtc_id);
+ struct dc_crtc_timing *timing;
+ int offdelay;
+
+ if (acrtc_state) {
+ timing = &acrtc_state->stream->timing;
+
+ /* at least 2 frames */
+ offdelay = 2000 / div64_u64(div64_u64((timing->pix_clk_100hz *
+ (uint64_t)100),
+ timing->v_total),
+ timing->h_total) + 1;
Yeah, _especially_ when you have a this short timeout your really have to
instead fix the vblank driver code properly so you can enable
vblank_disable_immediate. This is just cheating :-)
Michel mentioned on irc that DC had immediate vblank disabling, but this
was reverted with f64e6e0b6afe ("Revert "drm/amdgpu/display: set
vblank_disable_immediate for DC"").
I haven't looked at the details of the bug report, but stuttering is
exactly what happens when the driver's vblank code has these races. Going
for a very low timeout instead of zero just means it's a bit harder to hit
the issue, and much, much harder to debug properly.
So yeah even more reasons to look at the underlying root-cause here I
think.
-Sima
The issue is that DMUB (display firmware) isn't able to keep up with all of
the requests that the driver is making. The issue is fairly difficult to
reproduce (I've only seen it once after letting the system run with a
program that would engage PSR every so often, after several hours).
It is also worth noting that we have the same 2 idle frame wait on the
windows
driver, for the same reasons. So, in all likelihood if it is your opinion
that
the series should be NAKed, we will probably have to move the wait into the
driver as a workaround.
Well that's an entirely different reason, and needs to be recorded in the
commit log that disabling/enabling vblank is too expensive and why. Also
would be good to record that windows does the same.
Point taken.
I'm also not entirely sure this is a good interface, so some
thoughts/question:
- is the issue only with psr, meaning that if we switch the panel to a
different crtc, do we need to update the off delay.
I can't say definitively, but all of the public reports (that I've seen)
and my local repro are PSR related.
- there's still the question of why vblank_immediate_disable resulted in
stuttering, is that the same bug? I think for consistency it'd be best
if we enable immediate vblank disabling everywhere (for maximum
testing), and then apply the 2 frame delay workaround only where needed
explicitly. Otherwise if there's other issues than DMUB being slow, they
might be mostly hidden and become really hard to track down when they
show up.
Ya, I believe they are all DMUB related since the stuttering issues are
accompanied by the following dmesg log entry:
[drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB
idle: status=3
(which is pretty much an unspecified firmware timeout)
Also, setting vblank_immediate_disable unconditionally for amdgpu, while
only
enabling the delay for cases that we know that we need it seems
reasonable to me.
- I think an interf
Re: [PATCH v4 0/2] Add support for 'power saving policy' property
On 7/3/24 01:17, Mario Limonciello wrote: During the Display Next hackfest 2024 one of the topics discussed was the need for compositor to be able to relay intention to drivers that color fidelity is preferred over power savings. To accomplish this a new optional DRM property is being introduced called "power saving policy". This property is a bit mask that can be configured with requests of "Require color accuracy" or "Require low latency" that can be configured by the compositor. When a driver advertises support for this property and the compositor sets it to "Require color accuracy" then the driver will disable any power saving features that can compromise color fidelity. In practice the main feature this currently applies to is the "Adaptive Backlight Modulation" feature within AMD DCN on eDP panels. When the compositor has marked the property "Require color accuracy" then this feature will be disabled and any userspace that tries to turn it on will get an -EBUSY return code. Compositors can also request that low latency is critical which in practice should cause PSR and PSR2 to be disabled. When the compositor has restored the value back to no requirements then the previous value that would have been programmed will be restored. Applied, thanks! v3->v4: * Fixup for Xaver's reported issue v2->v3: * Updates from Leo's comments (see individual patches) Mario Limonciello (2): drm: Introduce 'power saving policy' drm property drm/amd: Add power_saving_policy drm property to eDP connectors drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 50 +-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 + drivers/gpu/drm/drm_connector.c | 48 ++ include/drm/drm_connector.h | 2 + include/drm/drm_mode_config.h | 5 ++ include/uapi/drm/drm_mode.h | 7 +++ 7 files changed, 113 insertions(+), 5 deletions(-) -- Hamza
Re: [PATCH 2/2] drm/amd/display: use drm_crtc_set_vblank_offdelay()
On 7/9/24 06:09, Daniel Vetter wrote:
On Tue, Jul 09, 2024 at 11:32:11AM +0200, Daniel Vetter wrote:
On Mon, Jul 08, 2024 at 04:29:07PM -0400, Hamza Mahfooz wrote:
Hook up drm_crtc_set_vblank_offdelay() in amdgpu_dm, so that we can
enable PSR more quickly for displays that support it.
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++-
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fdbc9b57a23d..ee6c31e9d3c4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8231,7 +8231,7 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev,
static void manage_dm_interrupts(struct amdgpu_device *adev,
struct amdgpu_crtc *acrtc,
-bool enable)
+struct dm_crtc_state *acrtc_state)
{
/*
* We have no guarantee that the frontend index maps to the same
@@ -8239,12 +8239,25 @@ static void manage_dm_interrupts(struct amdgpu_device
*adev,
*
* TODO: Use a different interrupt or check DC itself for the mapping.
*/
- int irq_type =
- amdgpu_display_crtc_idx_to_irq_type(
- adev,
- acrtc->crtc_id);
+ int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
+ acrtc->crtc_id);
+ struct dc_crtc_timing *timing;
+ int offdelay;
+
+ if (acrtc_state) {
+ timing = &acrtc_state->stream->timing;
+
+ /* at least 2 frames */
+ offdelay = 2000 / div64_u64(div64_u64((timing->pix_clk_100hz *
+ (uint64_t)100),
+ timing->v_total),
+ timing->h_total) + 1;
Yeah, _especially_ when you have a this short timeout your really have to
instead fix the vblank driver code properly so you can enable
vblank_disable_immediate. This is just cheating :-)
Michel mentioned on irc that DC had immediate vblank disabling, but this
was reverted with f64e6e0b6afe ("Revert "drm/amdgpu/display: set
vblank_disable_immediate for DC"").
I haven't looked at the details of the bug report, but stuttering is
exactly what happens when the driver's vblank code has these races. Going
for a very low timeout instead of zero just means it's a bit harder to hit
the issue, and much, much harder to debug properly.
So yeah even more reasons to look at the underlying root-cause here I
think.
-Sima
The issue is that DMUB (display firmware) isn't able to keep up with all of
the requests that the driver is making. The issue is fairly difficult to
reproduce (I've only seen it once after letting the system run with a
program that would engage PSR every so often, after several hours).
It is also worth noting that we have the same 2 idle frame wait on the
windows
driver, for the same reasons. So, in all likelihood if it is your
opinion that
the series should be NAKed, we will probably have to move the wait into the
driver as a workaround.
--
Hamza
[PATCH 2/2] drm/amd/display: use drm_crtc_set_vblank_offdelay()
Hook up drm_crtc_set_vblank_offdelay() in amdgpu_dm, so that we can
enable PSR more quickly for displays that support it.
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++-
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fdbc9b57a23d..ee6c31e9d3c4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8231,7 +8231,7 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev,
static void manage_dm_interrupts(struct amdgpu_device *adev,
struct amdgpu_crtc *acrtc,
-bool enable)
+struct dm_crtc_state *acrtc_state)
{
/*
* We have no guarantee that the frontend index maps to the same
@@ -8239,12 +8239,25 @@ static void manage_dm_interrupts(struct amdgpu_device
*adev,
*
* TODO: Use a different interrupt or check DC itself for the mapping.
*/
- int irq_type =
- amdgpu_display_crtc_idx_to_irq_type(
- adev,
- acrtc->crtc_id);
+ int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
+ acrtc->crtc_id);
+ struct dc_crtc_timing *timing;
+ int offdelay;
+
+ if (acrtc_state) {
+ timing = &acrtc_state->stream->timing;
+
+ /* at least 2 frames */
+ offdelay = 2000 / div64_u64(div64_u64((timing->pix_clk_100hz *
+ (uint64_t)100),
+ timing->v_total),
+ timing->h_total) + 1;
+
+ if (acrtc_state->stream->link->psr_settings.psr_version <
+ DC_PSR_VERSION_UNSUPPORTED &&
+ amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0))
+ drm_crtc_set_vblank_offdelay(&acrtc->base, offdelay);
- if (enable) {
drm_crtc_vblank_on(&acrtc->base);
amdgpu_irq_get(
adev,
@@ -9319,7 +9332,7 @@ static void amdgpu_dm_commit_streams(struct
drm_atomic_state *state,
if (old_crtc_state->active &&
(!new_crtc_state->active ||
drm_atomic_crtc_needs_modeset(new_crtc_state))) {
- manage_dm_interrupts(adev, acrtc, false);
+ manage_dm_interrupts(adev, acrtc, NULL);
dc_stream_release(dm_old_crtc_state->stream);
}
}
@@ -9834,7 +9847,8 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
drm_atomic_crtc_needs_modeset(new_crtc_state))) {
dc_stream_retain(dm_new_crtc_state->stream);
acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
- manage_dm_interrupts(adev, acrtc, true);
+ manage_dm_interrupts(adev, acrtc,
+to_dm_crtc_state(new_crtc_state));
}
/* Handle vrr on->off / off->on transitions */
amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
dm_new_crtc_state);
--
2.45.1
[PATCH 1/2] drm/vblank: allow dynamic per-crtc vblank off delay
We would like to be able to adjust the vblank off delay dynamically for
a given CRTC. Since, it will allow drivers to apply static screen
optimizations more quickly and consequently allow users to benefit more
so from the power savings afforded by the aforementioned optimizations.
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/drm_vblank.c | 31 ++-
include/drm/drm_vblank.h | 7 +++
2 files changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 702a12bc93bd..4f475131a092 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -529,6 +529,7 @@ int drm_vblank_init(struct drm_device *dev, unsigned int
num_crtcs)
vblank->dev = dev;
vblank->pipe = i;
+ vblank->offdelay_ms = drm_vblank_offdelay;
init_waitqueue_head(&vblank->queue);
timer_setup(&vblank->disable_timer, vblank_disable_fn, 0);
seqlock_init(&vblank->seqlock);
@@ -1229,6 +1230,7 @@ EXPORT_SYMBOL(drm_crtc_vblank_get);
void drm_vblank_put(struct drm_device *dev, unsigned int pipe)
{
struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
+ int vblank_offdelay = vblank->offdelay_ms;
if (drm_WARN_ON(dev, pipe >= dev->num_crtcs))
return;
@@ -1238,13 +1240,13 @@ void drm_vblank_put(struct drm_device *dev, unsigned
int pipe)
/* Last user schedules interrupt disable */
if (atomic_dec_and_test(&vblank->refcount)) {
- if (drm_vblank_offdelay == 0)
+ if (!vblank_offdelay)
return;
- else if (drm_vblank_offdelay < 0)
+ else if (vblank_offdelay < 0)
vblank_disable_fn(&vblank->disable_timer);
else if (!dev->vblank_disable_immediate)
mod_timer(&vblank->disable_timer,
- jiffies + ((drm_vblank_offdelay * HZ)/1000));
+ jiffies + ((vblank_offdelay * HZ) / 1000));
}
}
@@ -1455,6 +1457,25 @@ void drm_crtc_set_max_vblank_count(struct drm_crtc *crtc,
}
EXPORT_SYMBOL(drm_crtc_set_max_vblank_count);
+/**
+ * drm_crtc_set_vblank_offdelay - configure the vblank off delay value
+ * @crtc: CRTC in question
+ * @offdelay: off delay value
+ *
+ * If used, must be called before drm_vblank_on().
+ */
+void drm_crtc_set_vblank_offdelay(struct drm_crtc *crtc, int offdelay)
+{
+ struct drm_device *dev = crtc->dev;
+ unsigned int pipe = drm_crtc_index(crtc);
+ struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
+
+ drm_WARN_ON(dev, dev->vblank_disable_immediate);
+
+ vblank->offdelay_ms = offdelay;
+}
+EXPORT_SYMBOL(drm_crtc_set_vblank_offdelay);
+
/**
* drm_crtc_vblank_on - enable vblank events on a CRTC
* @crtc: CRTC in question
@@ -1490,7 +1511,7 @@ void drm_crtc_vblank_on(struct drm_crtc *crtc)
* re-enable interrupts if there are users left, or the
* user wishes vblank interrupts to be enabled all the time.
*/
- if (atomic_read(&vblank->refcount) != 0 || drm_vblank_offdelay == 0)
+ if (atomic_read(&vblank->refcount) != 0 || !vblank->offdelay_ms)
drm_WARN_ON(dev, drm_vblank_enable(dev, pipe));
spin_unlock_irq(&dev->vbl_lock);
}
@@ -1909,7 +1930,7 @@ bool drm_handle_vblank(struct drm_device *dev, unsigned
int pipe)
* drm_handle_vblank_events) so that the timestamp is always accurate.
*/
disable_irq = (dev->vblank_disable_immediate &&
- drm_vblank_offdelay > 0 &&
+ vblank->offdelay_ms > 0 &&
!atomic_read(&vblank->refcount));
drm_handle_vblank_events(dev, pipe);
diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h
index 7f3957943dd1..f92f28b816af 100644
--- a/include/drm/drm_vblank.h
+++ b/include/drm/drm_vblank.h
@@ -187,6 +187,12 @@ struct drm_vblank_crtc {
*/
int linedur_ns;
+ /**
+* @offdelay_ms: Vblank off delay in ms, used to determine how long
+* @disable_timer waits before disabling.
+*/
+ int offdelay_ms;
+
/**
* @hwmode:
*
@@ -255,6 +261,7 @@ void drm_calc_timestamping_constants(struct drm_crtc *crtc,
wait_queue_head_t *drm_crtc_vblank_waitqueue(struct drm_crtc *crtc);
void drm_crtc_set_max_vblank_count(struct drm_crtc *crtc,
u32 max_vblank_count);
+void drm_crtc_set_vblank_offdelay(struct drm_crtc *crtc, int offdelay);
/*
* Helpers for struct drm_crtc_funcs
--
2.45.1
[PATCH] MAINTAINERS: add an entry for AMD DC DML
We want all DML changes to be reviewed by Chaitanya or Jun. So, add an entry for DML to MAINTAINERS. Suggested-by: Rodrigo Siqueira Signed-off-by: Hamza Mahfooz --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7fec8ddb8d5b..d2fb60fee7e8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -950,6 +950,13 @@ S: Supported T: git https://gitlab.freedesktop.org/agd5f/linux.git F: drivers/gpu/drm/amd/display/ +AMD DISPLAY CORE - DML +M: Chaitanya Dhere +M: Jun Lei +S: Supported +F: drivers/gpu/drm/amd/display/dc/dml/ +F: drivers/gpu/drm/amd/display/dc/dml2/ + AMD FAM15H PROCESSOR POWER MONITORING DRIVER M: Huang Rui L: linux-hw...@vger.kernel.org -- 2.45.1
Re: [PATCH] drm/amd/display: Fix Makefile copyright notices
On 6/24/24 09:58, Alex Deucher wrote: Leftover copy pasta from original code. Signed-off-by: Alex Deucher Cc: harry.wentl...@amd.com Reviewed-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/dc/dcn301/Makefile | 11 ++- drivers/gpu/drm/amd/display/dc/dcn31/Makefile | 10 ++ drivers/gpu/drm/amd/display/dc/dcn314/Makefile | 11 ++- drivers/gpu/drm/amd/display/dc/dcn401/Makefile | 5 ++--- 4 files changed, 8 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile index fadf5e872e38..dc37dbf870df 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile @@ -1,12 +1,5 @@ -# -# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved -# -# All rights reserved. This notice is intended as a precaution against -# inadvertent publication and does not imply publication or any waiver -# of confidentiality. The year included in the foregoing notice is the -# year of creation of the work. -# -# Authors: AMD +# SPDX-License-Identifier: MIT +# Copyright © 2024 Advanced Micro Devices, Inc. All rights reserved. # # Makefile for dcn30. diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/Makefile b/drivers/gpu/drm/amd/display/dc/dcn31/Makefile index 62c8ab0e45aa..d9816313c3b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn31/Makefile @@ -1,12 +1,6 @@ +# SPDX-License-Identifier: MIT +# Copyright © 2024 Advanced Micro Devices, Inc. All rights reserved. # -# Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved -# -# All rights reserved. This notice is intended as a precaution against -# inadvertent publication and does not imply publication or any waiver -# of confidentiality. The year included in the foregoing notice is the -# year of creation of the work. -# -# Authors: AMD # # Makefile for dcn31. diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/Makefile b/drivers/gpu/drm/amd/display/dc/dcn314/Makefile index cac756c75b7f..15fdcf7c6466 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn314/Makefile @@ -1,12 +1,5 @@ -# -# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved -# -# All rights reserved. This notice is intended as a precaution against -# inadvertent publication and does not imply publication or any waiver -# of confidentiality. The year included in the foregoing notice is the -# year of creation of the work. -# -# Authors: AMD +# SPDX-License-Identifier: MIT +# Copyright © 2024 Advanced Micro Devices, Inc. All rights reserved. # # Makefile for dcn314. diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/Makefile b/drivers/gpu/drm/amd/display/dc/dcn401/Makefile index 2989e706bccf..ded1f3140beb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn401/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn401/Makefile @@ -1,6 +1,5 @@ -# -# Copyright © 2023 Advanced Micro Devices, Inc. All rights reserved. -# +# SPDX-License-Identifier: MIT +# Copyright © 2024 Advanced Micro Devices, Inc. All rights reserved. DCN401 += dcn401_dio_link_encoder.o DCN401 += dcn401_dio_stream_encoder.o -- Hamza
[PATCH 35/36] drm/amd/display: [FW Promotion] Release 0.0.222.0
From: Anthony Koo
- Add new condition for PSR exit due to ESD recovery
- Add new VB scaling feature for ABM by interpolating between
existing VB parameters, allowing driver to have fine grain
scaled VB levels between 0 - 250
Acked-by: Hamza Mahfooz
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b75653faf40e..78e8698fe378 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -208,6 +208,11 @@ union abm_flags {
* @abm_new_frame: Indicates if a new frame update needed for
ABM to ramp up into steady
*/
unsigned int abm_new_frame : 1;
+
+ /**
+* @vb_scaling_enabled: Indicates variBright Scaling Enable
+*/
+ unsigned int vb_scaling_enabled : 1;
} bitfields;
unsigned int u32All;
@@ -2796,9 +2801,9 @@ struct dmub_cmd_psr_copy_settings_data {
*/
uint8_t relock_delay_frame_cnt;
/**
-* Explicit padding to 4 byte boundary.
+* esd recovery indicate.
*/
- uint8_t pad3;
+ uint8_t esd_recovery;
/**
* DSC Slice height.
*/
--
2.45.1
[PATCH 25/36] drm/amd/display: Fix warning caused by an attempt to configure a non-otg master
From: Rodrigo Siqueira
When booting the system with DCN401, the driver adds the following dmesg
warning:
WARNING: CPU: 8 PID: 175 at
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:1923
resource_get_opp_heads_for_otg_master+0x13/0x70 [amdgpu]
Modules linked in: amdgpu(+) hid_generic amdxcp i2c_algo_bit
drm_ttm_helper ttm drm_exec gpu_sched drm_suballoc_helper drm_buddy
drm_display_helper drm_kms_helper usbhid hid drm i2c_piix4 ahci igc
libahci video wmi
CPU: 8 PID: 175 Comm: systemd-udevd Not tainted 6.8.0-EXTRA-PROMO-MAY-29+ #66
Hardware name: ASUS System Product Name/TUF GAMING X570-PRO (WI-FI),
BIOS 4021 08/10/2021
RIP: 0010:resource_get_opp_heads_for_otg_master+0x13/0x70 [amdgpu]
Code: 8b 66 0f 1f 44 00 00 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90
90 0f 1f 44 00 00 55 48 83 bf f8 07 00 00 00 48 89 e5 74 0c <0f> 0b 31
f6 89 f0 5d e9 0c 65 01 e5 48 83 bf e0 07 00 00 00 75 ea
RSP: 0018:a5f000816ed8 EFLAGS: 00010246
[...]
PKRU: 5554
Call Trace:
? show_regs+0x65/0x70
? __warn+0x85/0x160
? resource_get_opp_heads_for_otg_master+0x13/0x70 [amdgpu]
? report_bug+0x192/0x1c0
? handle_bug+0x44/0x90
? exc_invalid_op+0x18/0x70
[...]
This warning is triggered by a check in the function
resource_get_opp_heads_for_otg_master that validates if the request
operation is in a master OTG pipe; if not, the warning above is
displayed. In other words, another part of the code might be calling
this function in a non-OTG master pipe context, resulting in the log
message.
The reason the ASSERT was triggered is that the current state wasn't
updated after applying the context to the hardware. This means that the
update_dsc_for_odm_change might be called from a non-OTG-MASTER. To
prevent this, it's crucial to check if the current reference is pointing
to an OTG master before operate in the old OTG master reference. If it's
not, the function must set the old OTG reference to NULL and avoid
calling resource_get_opp_heads_for_otg_master before the context is
updated.
Reviewed-by: Wenjing Liu
Acked-by: Hamza Mahfooz
Co-developed-by: Wenjing Liu
Signed-off-by: Wenjing Liu
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 24 ++-
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 0fafbec442b1..cb8e417fb032 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1561,16 +1561,28 @@ static void update_dsc_for_odm_change(struct dc *dc,
struct dc_state *context,
struct pipe_ctx *new_pipe;
struct pipe_ctx *old_opp_heads[MAX_PIPES];
struct dccg *dccg = dc->res_pool->dccg;
- struct pipe_ctx *old_otg_master =
-
&dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];
- int old_opp_head_count = resource_get_opp_heads_for_otg_master(
- old_otg_master, &dc->current_state->res_ctx,
- old_opp_heads);
+ struct pipe_ctx *old_otg_master;
+ int old_opp_head_count = 0;
+
+ old_otg_master =
&dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];
+
+ if (resource_is_pipe_type(old_otg_master, OTG_MASTER)) {
+ old_opp_head_count =
resource_get_opp_heads_for_otg_master(old_otg_master,
+
&dc->current_state->res_ctx,
+
old_opp_heads);
+ } else {
+ // DC cannot assume that the current state and the new state
+ // share the same OTG pipe since this is not true when called
+ // in the context of a commit stream not checked. Hence, set
+ // old_otg_master to NULL to skip the DSC configuration.
+ old_otg_master = NULL;
+ }
+
if (otg_master->stream_res.dsc)
dcn32_update_dsc_on_stream(otg_master,
otg_master->stream->timing.flags.DSC);
- if (old_otg_master->stream_res.dsc) {
+ if (old_otg_master && old_otg_master->stream_res.dsc) {
for (i = 0; i < old_opp_head_count; i++) {
old_pipe = old_opp_heads[i];
new_pipe =
&context->res_ctx.pipe_ctx[old_pipe->pipe_idx];
--
2.45.1
[PATCH 29/36] drm/amd/display: Remove unused value set from 'min_hratio_fact' in dml
From: Ivan Lipski
These portions of code are flagged as 'UNUSED_VALUE' by the
Coverity analysis since the assigned values of these vars
are never used in the code.
Reviewed-by: Alex Hung
Reviewed-by: Aurabindo Pillai
Acked-by: Hamza Mahfooz
Signed-off-by: Ivan Lipski
---
.../drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c| 5 -
.../drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 5 -
.../drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c| 5 -
.../drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c| 5 -
.../drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c| 5 -
.../drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c | 5 -
.../gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c| 5 -
7 files changed, 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
index 548cdef8a8ad..07146569e335 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
@@ -1156,11 +1156,6 @@ static void dml20_rq_dlg_get_dlg_params(struct
display_mode_lib *mode_lib,
swath_width_pixels_ub_c = swath_width_ub_c * 1;
}
- hscale_pixel_rate_l = 0.;
- hscale_pixel_rate_c = 0.;
- min_hratio_fact_l = 1.0;
- min_hratio_fact_c = 1.0;
-
if (htaps_l <= 1)
min_hratio_fact_l = 2.0;
else if (htaps_l <= 6) {
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
index 0fc9f3e3ffae..f4bba1f2aeb6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
@@ -1157,11 +1157,6 @@ static void dml20v2_rq_dlg_get_dlg_params(struct
display_mode_lib *mode_lib,
swath_width_pixels_ub_c = swath_width_ub_c * 1;
}
- hscale_pixel_rate_l = 0.;
- hscale_pixel_rate_c = 0.;
- min_hratio_fact_l = 1.0;
- min_hratio_fact_c = 1.0;
-
if (htaps_l <= 1)
min_hratio_fact_l = 2.0;
else if (htaps_l <= 6) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
index 708e1632170d..c229a9edf82a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
@@ -1205,11 +1205,6 @@ static void dml_rq_dlg_get_dlg_params(
swath_width_pixels_ub_c = swath_width_ub_c * 1;
}
- hscale_pixel_rate_l = 0.;
- hscale_pixel_rate_c = 0.;
- min_hratio_fact_l = 1.0;
- min_hratio_fact_c = 1.0;
-
if (hratio_l <= 1)
min_hratio_fact_l = 2.0;
else if (htaps_l <= 6) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
index 0497a5d74a62..f3ee7baac786 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
@@ -1309,11 +1309,6 @@ static void dml_rq_dlg_get_dlg_params(struct
display_mode_lib *mode_lib,
swath_width_pixels_ub_c = swath_width_ub_c * 1;
}
- hscale_pixel_rate_l = 0.;
- hscale_pixel_rate_c = 0.;
- min_hratio_fact_l = 1.0;
- min_hratio_fact_c = 1.0;
-
if (hratio_l <= 1)
min_hratio_fact_l = 2.0;
else if (htaps_l <= 6) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
index 4113ce79c4af..b6d954d9aa00 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
@@ -1150,11 +1150,6 @@ static void dml_rq_dlg_get_dlg_params(
swath_width_pixels_ub_c = swath_width_ub_c * 1;
}
- hscale_pixel_rate_l = 0.;
- hscale_pixel_rate_c = 0.;
- min_hratio_fact_l = 1.0;
- min_hratio_fact_c = 1.0;
-
if (hratio_l <= 1)
min_hratio_fact_l = 2.0;
else if (htaps_l <= 6) {
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
index b3e8dc08030c..94975b0fa398 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
@@ -1238,11 +1238,6 @@ static void dml_rq_dlg_get_dlg_params(
swath_width_pixels_ub_c = swath_width_ub_c * 1;
[PATCH 33/36] drm/amd/display: Check UnboundedRequestEnabled's value
From: Alex Hung
CalculateSwathAndDETConfiguration_params_st's UnboundedRequestEnabled
is a pointer (i.e. dml_bool_t *UnboundedRequestEnabled), and thus
if (p->UnboundedRequestEnabled) checks its address, not bool value.
This fixes 1 REVERSE_INULL issue reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
index 791f1725b62b..547dfcc80fde 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c
@@ -4283,7 +4283,7 @@ static void CalculateSwathAndDETConfiguration(struct
display_mode_lib_scratch_st
}
*p->compbuf_reserved_space_64b = 2 * p->PixelChunkSizeInKByte * 1024 /
64;
- if (p->UnboundedRequestEnabled) {
+ if (*p->UnboundedRequestEnabled) {
*p->compbuf_reserved_space_64b =
dml_max(*p->compbuf_reserved_space_64b,
(dml_float_t)(p->ROBBufferSizeInKByte * 1024/64)
-
(dml_float_t)(RoundedUpSwathSizeBytesY[SurfaceDoingUnboundedRequest] *
TTUFIFODEPTH / MAXIMUMCOMPRESSION/64));
--
2.45.1
[PATCH 27/36] drm/amd/display: Remove redundant checks for res_pool->dccg
From: Alex Hung
The null checks for res_pool->dccg are redundant as it was already
dereferenced previously, as reported by Coverity; therefore the
null checks are removed.
This fixes 6 REVERSE_INULL issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
index 86d871cc74c7..f96adc689055 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
@@ -240,7 +240,7 @@ void dcn201_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
- if (res_pool->dccg && res_pool->hubbub) {
+ if (res_pool->hubbub) {
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
&res_pool->ref_clocks.dccg_ref_clock_inKhz);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 9ef38a3759b1..567300c3acaa 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -656,7 +656,7 @@ void dcn30_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
- if (res_pool->dccg && res_pool->hubbub) {
+ if (res_pool->hubbub) {
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 1c8abb417b6e..746c522adf84 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -132,7 +132,7 @@ void dcn31_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
- if (res_pool->dccg && res_pool->hubbub) {
+ if (res_pool->hubbub) {
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 33b8df995869..a597b2342472 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -806,7 +806,7 @@ void dcn32_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
- if (res_pool->dccg && res_pool->hubbub) {
+ if (res_pool->hubbub) {
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
&res_pool->ref_clocks.dccg_ref_clock_inKhz);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index d894c52bfdaf..a1e1f76bfde7 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -188,7 +188,7 @@ void dcn35_init_hw(struct dc *dc)
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
- if (res_pool->dccg && res_pool->hubbub) {
+ if (res_pool->hubbub) {
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
dc->ct
[PATCH 34/36] drm/amd/display: Remove redundant null checks
From: Alex Hung
The null checks for aconnector and aconnector->dc_link and
stream redundant as they were already dereferenced previously
as reported by Coverity; therefore the null checks are removed.
This fixes 4 REVERSE_INULL issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 ---
3 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 48a9243ada7d..1fd851b93d40 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3180,7 +3180,7 @@ static int dm_resume(void *handle)
* this is the case when traversing through already created end
sink
* MST connectors, should be skipped
*/
- if (aconnector && aconnector->mst_root)
+ if (aconnector->mst_root)
continue;
mutex_lock(&aconnector->hpd_lock);
@@ -6422,13 +6422,13 @@ static void apply_dsc_policy_for_stream(struct
amdgpu_dm_connector *aconnector,
dc_dsc_policy_set_enable_dsc_when_not_needed(
aconnector->dsc_settings.dsc_force_enable ==
DSC_CLK_FORCE_ENABLE);
- if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
+ if (sink->sink_signal == SIGNAL_TYPE_EDP &&
!aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
dc->caps.edp_dsc_support &&
aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps,
max_dsc_target_bpp_limit_override);
- } else if (aconnector->dc_link && sink->sink_signal ==
SIGNAL_TYPE_DISPLAY_PORT) {
+ } else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
if
(dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
dsc_caps,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 7cfa240a3cea..717d97191dda 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1420,7 +1420,7 @@ static ssize_t trigger_hotplug(struct file *f, const char
__user *buf,
uint8_t param_nums = 0;
bool ret = false;
- if (!aconnector || !aconnector->dc_link)
+ if (!aconnector->dc_link)
return -EINVAL;
if (size == 0)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 8eb2f10f2c38..659dd67be1ba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -807,9 +807,6 @@ bool dm_helpers_dp_write_dsc_enable(
uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
uint8_t ret = 0;
- if (!stream)
- return false;
-
if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
if (!aconnector->dsc_aux)
return false;
--
2.45.1
[PATCH 36/36] drm/amd/display: 3.2.289
From: Aric Cyr This version brings along the following: - DCN401 fixes - DPIA fixes - DML21 fixes - Misc Coverity fixes Acked-by: Hamza Mahfooz Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index fa4e6b09409e..d0d1af451b64 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.288" +#define DC_VER "3.2.289" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.45.1
[PATCH 30/36] drm/amd/display: Remove redundant null checks
From: Alex Hung
The null checks are redundant as they were already dereferenced
previously, as reported by Coverity; therefore the null checks
are removed.
This fixes 7 REVERSE_INULL issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
.../dc/dml2/dml21/dml21_translation_helper.c | 4 +-
.../amd/display/dc/hwss/dce110/dce110_hwseq.c | 8 +-
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 81 +--
6 files changed, 47 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index ee4b02c8c807..06f0c41ad6f1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -553,7 +553,7 @@ static void dcn32_auto_dpm_test_log(
//
// AutoDPMTest: clk1:%d - clk2:%d -
clk3:%d - clk4:%d\n"
- if (new_clocks && active_pipe_count > 0 &&
+ if (active_pipe_count > 0 &&
new_clocks->dramclk_khz > 0 &&
new_clocks->fclk_khz > 0 &&
new_clocks->dcfclk_khz > 0 &&
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index fce1c3e03094..a4ba6f99cd34 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2640,7 +2640,7 @@ static enum surface_update_type det_surface_update(const
struct dc *dc,
if (u->plane_info)
format = u->plane_info->format;
- else if (u->surface)
+ else
format = u->surface->format;
if (dce_use_lut(format))
@@ -2741,7 +2741,7 @@ static enum surface_update_type
check_update_surfaces_for_stream(
if (stream_update->mst_bw_update)
su_flags->bits.mst_bw = 1;
- if (stream_update->stream &&
stream_update->stream->freesync_on_desktop &&
+ if (stream_update->stream->freesync_on_desktop &&
(stream_update->vrr_infopacket ||
stream_update->allow_freesync ||
stream_update->vrr_active_variable ||
stream_update->vrr_active_fixed))
su_flags->bits.fams_changed = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 1cba8f58f1e6..eb053e1791c0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2099,7 +2099,7 @@ int resource_get_odm_slice_dst_width(struct pipe_ctx
*otg_master,
timing->h_border_right;
width = h_active / count;
- if (otg_master->stream_res.tg && otg_master->stream)
+ if (otg_master->stream_res.tg)
two_pixel_alignment_required =
otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) ||
/*
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
index a7d02da16bb5..d5ead0205053 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
@@ -102,9 +102,7 @@ void dml21_apply_soc_bb_overrides(struct
dml2_initialize_instance_in_out *dml_in
struct dml2_soc_state_table *dml_clk_table = &dml_soc_bb->clk_table;
/* override clocks if smu is present */
- if (in_dc->clk_mgr &&
- in_dc->clk_mgr->funcs->is_smu_present &&
- in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr)) {
+ if (in_dc->clk_mgr->funcs->is_smu_present &&
in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr)) {
/* dcfclk */
if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
dml_clk_table->dcfclk.num_clk_values =
dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 871f1e1ca2e0..307af11b4bb6 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/
[PATCH 32/36] drm/amd/display: Remove redundant checks for context
From: Alex Hung
The null checks for context are redundant as it was already
dereferenced previously, as reported by Coverity; therefore
the null checks are removed.
This fixes 2 REVERSE_INULL issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 2 +-
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c| 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 33318a112282..5037474bf95c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -505,7 +505,7 @@ void set_p_state_switch_method(
struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
bool enable_subvp;
- if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba || !context)
+ if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)
return;
if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] !=
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index 17ea15682d3a..19b61290ef9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -573,10 +573,7 @@ static bool dml2_validate_and_build_resource(const struct
dc *in_dc, struct dc_s
bool need_recalculation = false;
uint32_t cstate_enter_plus_exit_z8_ns;
- if (!context)
- return true;
-
- else if (context->stream_count == 0) {
+ if (context->stream_count == 0) {
unsigned int lowest_state_idx = 0;
out_clks.p_state_supported = true;
--
2.45.1
[PATCH 21/36] drm/amd/display: Make sure to reprogram ODM when resync fifo
From: Alvin Lee
Need to reconfigure ODM when resyncing FIFO because on OTG disable we
clear all ODM programming
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hamza Mahfooz
Signed-off-by: Alvin Lee
---
.../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 19 ++-
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 19 ++-
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index 8e68e05e3b72..388404cdeeaa 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -379,8 +379,25 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws,
struct dc *dc, struct dc
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
- if (otg_disabled[i])
+ if (otg_disabled[i]) {
+ int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst
};
+ int opp_cnt = 1;
+ int last_odm_slice_width =
resource_get_odm_slice_dst_width(pipe, true);
+ int odm_slice_width =
resource_get_odm_slice_dst_width(pipe, false);
+ struct pipe_ctx *odm_pipe;
+
+ for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe
= odm_pipe->next_odm_pipe) {
+ opp_inst[opp_cnt] =
odm_pipe->stream_res.opp->inst;
+ opp_cnt++;
+ }
+ if (opp_cnt > 1)
+ pipe->stream_res.tg->funcs->set_odm_combine(
+ pipe->stream_res.tg,
+ opp_inst, opp_cnt,
+ odm_slice_width,
+ last_odm_slice_width);
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
+ }
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 732da5e5c1ba..33b8df995869 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1237,8 +1237,25 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws,
struct dc *dc, struct dc_
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
- if (otg_disabled[i])
+ if (otg_disabled[i]) {
+ int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst
};
+ int opp_cnt = 1;
+ int last_odm_slice_width =
resource_get_odm_slice_dst_width(pipe, true);
+ int odm_slice_width =
resource_get_odm_slice_dst_width(pipe, false);
+ struct pipe_ctx *odm_pipe;
+
+ for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe
= odm_pipe->next_odm_pipe) {
+ opp_inst[opp_cnt] =
odm_pipe->stream_res.opp->inst;
+ opp_cnt++;
+ }
+ if (opp_cnt > 1)
+ pipe->stream_res.tg->funcs->set_odm_combine(
+ pipe->stream_res.tg,
+ opp_inst, opp_cnt,
+ odm_slice_width,
+ last_odm_slice_width);
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
+ }
}
}
--
2.45.1
[PATCH 22/36] drm/amd/display: Check dc_stream_state before it is used
From: Alex Hung
dc_state_get_stream_status dc_state_get_paired_subvp_stream and other
functions can return null, and therefore null must be checked before
status can be used.
This fixes 21 NULL_RETURNS issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 17 +
.../gpu/drm/amd/display/dc/core/dc_state.c| 24 ---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 20 ++--
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 8 +++
.../amd/display/dc/dml2/dml21/dml21_utils.c | 12 +-
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 6 +++--
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 9 ---
.../dc/resource/dcn32/dcn32_resource.c| 2 ++
8 files changed, 74 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 25a498f65c1c..fce1c3e03094 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1233,11 +1233,14 @@ static void disable_dangling_plane(struct dc *dc,
struct dc_state *context)
*/
if (is_phantom) {
if (tg->funcs->enable_crtc) {
- int main_pipe_width, main_pipe_height;
+ int main_pipe_width = 0,
main_pipe_height = 0;
struct dc_stream_state
*old_paired_stream = dc_state_get_paired_subvp_stream(dc->current_state,
old_stream);
- main_pipe_width =
old_paired_stream->dst.width;
- main_pipe_height =
old_paired_stream->dst.height;
+ if (old_paired_stream) {
+ main_pipe_width =
old_paired_stream->dst.width;
+ main_pipe_height =
old_paired_stream->dst.height;
+ }
+
if (dc->hwss.blank_phantom)
dc->hwss.blank_phantom(dc, tg,
main_pipe_width, main_pipe_height);
tg->funcs->enable_crtc(tg);
@@ -1628,6 +1631,9 @@ static void program_timing_sync(
for (k = 0; k < group_size; k++) {
struct dc_stream_status *status =
dc_state_get_stream_status(ctx, pipe_set[k]->stream);
+ if (!status)
+ continue;
+
status->timing_sync_info.group_id = num_group;
status->timing_sync_info.group_size = group_size;
if (k == 0)
@@ -2225,6 +2231,9 @@ enum dc_status dc_commit_streams(struct dc *dc, struct
dc_commit_streams_params
if (dc_is_embedded_signal(params->streams[i]->signal)) {
struct dc_stream_status *status =
dc_state_get_stream_status(context, params->streams[i]);
+ if (!status)
+ continue;
+
if (dc->hwss.is_abm_supported)
status->is_abm_supported =
dc->hwss.is_abm_supported(dc, context, params->streams[i]);
else
@@ -4023,7 +4032,7 @@ static void commit_planes_for_stream(struct dc *dc,
stream_status =
stream_get_status(context, pipe_ctx->stream);
- if (dc->hwss.apply_ctx_for_surface)
+ if (dc->hwss.apply_ctx_for_surface && stream_status)
dc->hwss.apply_ctx_for_surface(
dc, pipe_ctx->stream,
stream_status->plane_count, context);
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index c75dcdc20428..e990346e51f6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -794,11 +794,16 @@ enum dc_status dc_state_add_phantom_stream(const struct
dc *dc,
/* setup subvp meta */
main_stream_status = dc_state_get_stream_status(state, main_stream);
+ if (main_stream_status) {
+ main_stream_status->mall_stream_config.type = SUBVP_MAIN;
+ main_stream_status->mall_stream_config.paired_stream =
phantom_stream;
+ }
+
phantom_stream_status = dc_state_get_stream_status(state,
phantom_stream);
- phantom_stream_status->mall_stream_config.type = SUBVP_PHANTOM;
- phantom_stream_status->mall_str
[PATCH 31/36] drm/amd/display: Remove redundant checks for opp
From: Alex Hung The null checks for opp are redundant as they were already dereferenced previously, as reported by Coverity; therefore the null checks are removed. This fixes 2 REVERSE_INULL issues reported by Coverity. Reviewed-by: Harry Wentland Acked-by: Hamza Mahfooz Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 85f014cae6be..841b6423952c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -1260,7 +1260,7 @@ void dcn10_plane_atomic_disconnect(struct dc *dc, mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove); // Phantom pipes have OTG disabled by default, so MPCC_STATUS will never assert idle, // so don't wait for MPCC_IDLE in the programming sequence - if (opp != NULL && dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM) + if (dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM) opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; dc->optimized_required = true; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c index f96adc689055..1635e5a552ad 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c @@ -408,8 +408,7 @@ void dcn201_plane_atomic_disconnect(struct dc *dc, if (mpcc_removed == false) return; - if (opp != NULL) - opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; + opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; dc->optimized_required = true; -- 2.45.1
[PATCH 20/36] drm/amd/display: Remove duplicate HWSS interfaces
From: Joshua Aberback
[Why]
Some interface functions are defined in both the public and private HWSS
interfaces, which can lead to confusion and runtime issues, therefore
the duplicates should be eliminated.
[How]
- power_down should only be private, because it's only used within HWSS
- update_plane_addr should only be public, as it's used outside HWSS
Reviewed-by: Aric Cyr
Acked-by: Hamza Mahfooz
Signed-off-by: Joshua Aberback
---
.../gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 1 -
.../gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c| 10 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c | 2 --
.../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c| 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c | 1 -
.../gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c | 1 -
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c | 2 --
.../gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c| 8
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c | 1 -
.../gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c | 1 -
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c | 2 --
.../gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c | 2 --
.../gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c| 8
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c | 1 -
.../gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c| 8
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c | 2 --
.../gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c | 2 --
.../gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 8
.../gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c | 2 --
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 1 -
.../gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h | 2 --
21 files changed, 22 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index f489371a3bc6..871f1e1ca2e0 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -3262,7 +3262,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
static const struct hwseq_private_funcs dce110_private_funcs = {
.init_pipes = init_pipes,
- .update_plane_addr = update_plane_addr,
.set_input_transfer_func = dce110_set_input_transfer_func,
.set_output_transfer_func = dce110_set_output_transfer_func,
.power_down = dce110_power_down,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 0bfab66b8038..85f014cae6be 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1712,10 +1712,10 @@ void dcn10_power_down_on_boot(struct dc *dc)
if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&
edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
dc->hwseq->funcs.edp_backlight_control &&
- dc->hwss.power_down &&
+ dc->hwseq->funcs.power_down &&
dc->hwss.edp_power_control) {
dc->hwseq->funcs.edp_backlight_control(edp_link, false);
- dc->hwss.power_down(dc);
+ dc->hwseq->funcs.power_down(dc);
dc->hwss.edp_power_control(edp_link, false);
} else {
for (i = 0; i < dc->link_count; i++) {
@@ -1723,8 +1723,8 @@ void dcn10_power_down_on_boot(struct dc *dc)
if (link->link_enc &&
link->link_enc->funcs->is_dig_enabled &&
link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
- dc->hwss.power_down) {
- dc->hwss.power_down(dc);
+ dc->hwseq->funcs.power_down) {
+ dc->hwseq->funcs.power_down(dc);
break;
}
@@ -2929,7 +2929,7 @@ static void dcn10_update_dchubp_dpp(
hubp->power_gated = false;
- hws->funcs.update_plane_addr(dc, pipe_ctx);
+ dc->hwss.update_plane_addr(dc, pipe_ctx);
if (is_pipe_tree_visible(pipe_ctx))
hubp->funcs->set_blank(hubp, false);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
index a5bdac79a744..5e51e1761707 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
@@ -78,7 +78,6 @@
[PATCH 05/36] drm/amd/display: Remove redundant condition with DEADCODE
From: Ivan Lipski [WHY] Coverity analysis flagged this condition as DEADCODE since the variable 'req128_c' is always false, thus the condition is never true. [HOW] Remove the condition. Reviewed-by: Aurabindo Pillai Acked-by: Hamza Mahfooz Signed-off-by: Ivan Lipski --- .../gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c index 618f4b682ab1..708e1632170d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c @@ -297,9 +297,6 @@ static void handle_det_buf_split( if (swath_height_c > 0) log2_swath_height_c = dml_log2(swath_height_c); - - if (req128_c && log2_swath_height_c > 0) - log2_swath_height_c -= 1; } rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; -- 2.45.1
[PATCH 17/36] drm/amd/display: Add null checker before access structs
From: Alex Hung
Checks null pointer before accessing various structs.
This fixes 5 NULL_RETURNS issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c | 2 ++
.../display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 5 +
.../gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 2 +-
.../gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c | 4 +++-
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
index 4166332b5b89..b97d9abfdbc6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
@@ -360,6 +360,8 @@ static struct dc_plane_state
*dml21_add_phantom_plane(struct dml2_context *dml_c
struct dc_plane_state *phantom_plane;
phantom_plane =
dml_ctx->config.svp_pstate.callbacks.create_phantom_plane(dc, context,
main_plane);
+ if (!phantom_plane)
+ return NULL;
phantom_plane->format = main_plane->format;
phantom_plane->rotation = main_plane->rotation;
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
index 7272a04b9d1d..00fedc00a735 100644
---
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+++
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
@@ -1082,12 +1082,17 @@ static bool is_timing_group_schedulable(
/* init allow start and end lines for timing group */
stream_method_fams2_meta = get_per_method_common_meta(pmo,
per_stream_pstate_strategy[base_stream_idx], base_stream_idx);
+ if (!stream_method_fams2_meta)
+ return false;
+
group_fams2_meta->allow_start_otg_vline =
stream_method_fams2_meta->allow_start_otg_vline;
group_fams2_meta->allow_end_otg_vline =
stream_method_fams2_meta->allow_end_otg_vline;
group_fams2_meta->period_us = stream_method_fams2_meta->period_us;
for (i = base_stream_idx + 1; i <
display_cfg->display_config.num_streams; i++) {
if
(is_bit_set_in_bitfield(pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx],
i)) {
stream_method_fams2_meta =
get_per_method_common_meta(pmo, per_stream_pstate_strategy[i], i);
+ if (!stream_method_fams2_meta)
+ continue;
if (group_fams2_meta->allow_start_otg_vline <
stream_method_fams2_meta->allow_start_otg_vline) {
/* set group allow start to larger otg vline */
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index f93853d434d2..e783afbbb397 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -2628,7 +2628,7 @@ static bool dcn20_resource_construct(
ranges.writer_wm_sets[0].max_drain_clk_mhz =
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
/* Notify PP Lib/SMU which Watermarks to use for which clock
ranges */
- if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
+ if (pool->base.pp_smu &&
pool->base.pp_smu->nv_funcs.set_wm_ranges)
pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu,
&ranges);
}
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
index 070a4efb308b..131d98025bd4 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
@@ -795,11 +795,13 @@ static struct link_encoder *dcn201_link_encoder_create(
{
struct dcn20_link_encoder *enc20 =
kzalloc(sizeof(struct dcn20_link_encoder), GFP_ATOMIC);
- struct dcn10_link_encoder *enc10 = &enc20->enc10;
+ struct dcn10_link_encoder *enc10;
if (!enc20)
return NULL;
+ enc10 = &enc20->enc10;
+
dcn201_link_encoder_construct(enc20,
enc_init_data,
&link_enc_feature,
--
2.45.1
[PATCH 24/36] drm/amd/display: Covert integers to double before divisions
From: Alex Hung
Integer divisions result in loss of fractional and accuracy is lost
when assigned or compared with double. It is necessary to perform
double/integer instead or explicitly cast them to double.
This fixes 54 UNINTENDED_INTEGER_DIVISION issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
.../drm/amd/display/dc/dml/calcs/dcn_calcs.c | 2 +-
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 20 ++---
.../dc/dml/dcn20/display_mode_vba_20.c| 16 +--
.../dc/dml/dcn20/display_mode_vba_20v2.c | 4 +--
.../dc/dml/dcn21/display_mode_vba_21.c| 2 +-
.../dc/dml/dcn30/display_mode_vba_30.c| 2 +-
.../dc/dml/dcn31/display_mode_vba_31.c| 4 +--
.../dc/dml/dcn314/display_mode_vba_314.c | 2 +-
.../dc/dml/dcn32/display_mode_vba_util_32.c | 8 +++---
.../amd/display/dc/dml2/display_mode_core.c | 10 +++
.../src/dml2_core/dml2_core_dcn4_calcs.c | 28 +--
.../dml21/src/dml2_core/dml2_core_shared.c| 24
12 files changed, 61 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
index f1cde1e4265f..39525721c976 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
@@ -690,7 +690,7 @@ static void hack_disable_optional_pipe_split(struct
dcn_bw_internal_vars *v)
static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
unsigned int pixel_rate_100hz)
{
- float pixel_rate_mhz = pixel_rate_100hz / 1;
+ float pixel_rate_mhz = pixel_rate_100hz / 1.0;
/*
* force enabling pipe split by lower dpp clock for DPM0 to just
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 74da9ebda016..54dd7e164635 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1882,10 +1882,10 @@ void dcn20_update_bounding_box(struct dc *dc,
bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk
< min_dcfclk) ?
min_dcfclk : min_fclk_required_by_uclk;
- bb->clock_limits[i].socclk_mhz =
(bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
+ bb->clock_limits[i].socclk_mhz =
(bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000.0) ?
max_clocks->socClockInKhz / 1000 :
bb->clock_limits[i].fabricclk_mhz;
- bb->clock_limits[i].dcfclk_mhz =
(bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
+ bb->clock_limits[i].dcfclk_mhz =
(bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000.0) ?
max_clocks->dcfClockInKhz / 1000 :
bb->clock_limits[i].fabricclk_mhz;
bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz
/ 1000;
@@ -1917,35 +1917,35 @@ void dcn20_cap_soc_clocks(struct
_vcs_dpi_soc_bounding_box_st *bb,
// First pass - cap all clocks higher than the reported max
for (i = 0; i < bb->num_states; i++) {
- if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz
/ 1000))
+ if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz
/ 1000.0))
&& max_clocks.dcfClockInKhz != 0)
bb->clock_limits[i].dcfclk_mhz =
(max_clocks.dcfClockInKhz / 1000);
- if ((bb->clock_limits[i].dram_speed_mts >
(max_clocks.uClockInKhz / 1000) * 16)
+ if ((bb->clock_limits[i].dram_speed_mts >
(max_clocks.uClockInKhz / 1000.0) * 16)
&& max_clocks.uClockInKhz != 0)
bb->clock_limits[i].dram_speed_mts =
(max_clocks.uClockInKhz / 1000) * 16;
- if ((bb->clock_limits[i].fabricclk_mhz >
(max_clocks.fabricClockInKhz / 1000))
+ if ((bb->clock_limits[i].fabricclk_mhz >
(max_clocks.fabricClockInKhz / 1000.0))
&& max_clocks.fabricClockInKhz
!= 0)
bb->clock_limits[i].fabricclk_mhz =
(max_clocks.fabricClockInKhz / 1000);
- if ((bb->clock_limits[i].dispclk_mhz >
(max_clocks.displayClockInKhz / 1000))
+ if ((bb->clock_limits[i].dispclk_mhz >
(max_clocks.displayClockInKhz / 1000.0))
&& max_clocks.displayClockInKhz
!= 0)
bb->clock_limits[i].dispclk_mhz =
(max_clocks.
[PATCH 28/36] drm/amd/display: Remove redundant checks for ctx->dc_bios
From: Alex Hung
The null checks for ctx->dc_bios are redundant as it was already
dereferenced previously, as reported by Coverity; therefore the
null checks are removed.
This fixes 7 REVERSE_INULL issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index a650a9877097..e18097f82091 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -772,7 +772,7 @@ void rn_clk_mgr_construct(
status =
pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
if (status == PP_SMU_RESULT_OK &&
- ctx->dc_bios && ctx->dc_bios->integrated_info) {
+ ctx->dc_bios->integrated_info) {
rn_clk_mgr_helper_populate_bw_params
(clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
/* treat memory config as single channel if memory is
asymmetrics. */
if (ctx->dc->config.is_asymmetric_memory)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
index 148a0e4cdea2..9e2ef0e724fc 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -731,7 +731,7 @@ void vg_clk_mgr_construct(
clk_mgr->base.base.bw_params = &vg_bw_params;
vg_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
- if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
+ if (ctx->dc_bios->integrated_info) {
vg_clk_mgr_helper_populate_bw_params(
&clk_mgr->base,
ctx->dc_bios->integrated_info,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 12a7752758b8..e93df3d6222e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -785,7 +785,7 @@ void dcn31_clk_mgr_construct(
i,
smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
i,
smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
}
- if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
+ if (ctx->dc_bios->integrated_info) {
dcn31_clk_mgr_helper_populate_bw_params(
&clk_mgr->base,
ctx->dc_bios->integrated_info,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
index a84f1e376dee..29eff386505a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -896,7 +896,7 @@ void dcn314_clk_mgr_construct(
i,
smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
}
- if (ctx->dc_bios && ctx->dc_bios->integrated_info &&
ctx->dc->config.use_default_clock_table == false) {
+ if (ctx->dc_bios->integrated_info &&
ctx->dc->config.use_default_clock_table == false) {
dcn314_clk_mgr_helper_populate_bw_params(
&clk_mgr->base,
ctx->dc_bios->integrated_info,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index 5506cf9b3672..a0fb4481d2f1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -712,7 +712,7 @@ void dcn315_clk_mgr_construct(
i,
smu_dpm_clks.dpm_clks->
[PATCH 23/36] drm/amd/display: Check pipe_ctx before it is used
From: Alex Hung
resource_get_odm_slice_count and resource_get_otg_master_for_stream can
return null, and their returns must be checked before used.
This fixes 4 NULL_RETURNS issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 ++-
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 3 +++
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c| 3 ++-
.../gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c| 3 +++
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 76b849bdd914..87e84b0a3d48 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -3127,9 +3127,14 @@ bool resource_update_pipes_for_stream_with_slice_count(
int i;
struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(
&new_ctx->res_ctx, stream);
- int cur_slice_count = resource_get_odm_slice_count(otg_master);
+ int cur_slice_count;
bool result = true;
+ if (!otg_master)
+ return false;
+
+ cur_slice_count = resource_get_odm_slice_count(otg_master);
+
if (new_slice_count == cur_slice_count)
return result;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index a63b5dcba3f5..7abf8b88ca91 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1177,6 +1177,9 @@ static void init_pipe_slice_table_from_context(
stream = context->streams[i];
otg_master = resource_get_otg_master_for_stream(
&context->res_ctx, stream);
+ if (!otg_master)
+ continue;
+
count = resource_get_odm_slice_count(otg_master);
update_slice_table_for_stream(table, stream, count);
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
index 87c7b13391bc..d276458e50fd 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
@@ -120,7 +120,8 @@ int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,
} else {
/* stream was configured with dummy plane, so get pipes from
opp head */
struct pipe_ctx *otg_master_pipe =
dml_ctx->config.callbacks.get_otg_master_for_stream(&context->res_ctx,
dc_main_stream);
- num_pipes =
dml_ctx->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe,
&context->res_ctx, dc_main_pipes);
+ if (otg_master_pipe != NULL)
+ num_pipes =
dml_ctx->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe,
&context->res_ctx, dc_main_pipes);
}
/* if phantom exists, find associated pipes */
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
index 486b222083e0..6eccf0241d85 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
@@ -905,6 +905,9 @@ static unsigned int get_source_odm_factor(const struct
dml2_context *ctx,
{
struct pipe_ctx *otg_master =
ctx->config.callbacks.get_otg_master_for_stream(&state->res_ctx, stream);
+ if (!otg_master)
+ return 0;
+
return ctx->config.callbacks.get_odm_slice_count(otg_master);
}
--
2.45.1
[PATCH 26/36] drm/amd/display: Improve warning log for get OPP for OTG master
From: Rodrigo Siqueira
If some part of the driver tries to call
resource_get_opp_heads_for_otg_master in a non-OTG master context, DC
will trigger a dmesg warning since this situation indicates that some
configuration associated with ODM slices might be wrong. This commit
adds an extra log to describe why the warning was triggered to make the
debugging more straightforward.
Reviewed-by: Wenjing Liu
Acked-by: Hamza Mahfooz
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 87e84b0a3d48..1cba8f58f1e6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1917,9 +1917,15 @@ int resource_get_opp_heads_for_otg_master(const struct
pipe_ctx *otg_master,
struct pipe_ctx *opp_heads[MAX_PIPES])
{
struct pipe_ctx *opp_head = &res_ctx->pipe_ctx[otg_master->pipe_idx];
+ struct dc *dc = otg_master->stream->ctx->dc;
int i = 0;
+ DC_LOGGER_INIT(dc->ctx->logger);
+
if (!resource_is_pipe_type(otg_master, OTG_MASTER)) {
+ DC_LOG_WARNING("%s called from a non OTG master, something "
+ "is wrong in the pipe configuration",
+ __func__);
ASSERT(0);
return 0;
}
--
2.45.1
[PATCH 18/36] drm/amd/display: mirror case cleanup for cursors
From: Sridevi Arvindekar
Mirror case unsupported for cursors. So, remove code for mirror case
with cursors.
Reviewed-by: Nevenko Stupar
Acked-by: Hamza Mahfooz
Signed-off-by: Sridevi Arvindekar
---
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 30 +--
1 file changed, 1 insertion(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index e7d6d987e3d3..ef0a42f2933d 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1209,34 +1209,7 @@ void dcn401_set_cursor_position(struct pipe_ctx
*pipe_ctx)
if (pos_cpy.enable && dcn401_can_pipe_disable_cursor(pipe_ctx))
pos_cpy.enable = false;
- if (param.rotation == ROTATION_ANGLE_0) {
- int recout_width =
- pipe_ctx->plane_res.scl_data.recout.width;
- int recout_x =
- pipe_ctx->plane_res.scl_data.recout.x;
-
- if (param.mirror) {
- if (pipe_split_on || odm_combine_on) {
- if (pos_cpy.x >= recout_width + recout_x) {
- pos_cpy.x = 2 * recout_width
- - pos_cpy.x + 2 * recout_x;
- } else {
- uint32_t temp_x = pos_cpy.x;
-
- pos_cpy.x = 2 * recout_x - pos_cpy.x;
- if (temp_x >= recout_x +
- (int)hubp->curs_attr.width ||
pos_cpy.x
- <= (int)hubp->curs_attr.width +
-
pipe_ctx->plane_state->src_rect.x) {
- pos_cpy.x = 2 * recout_width -
temp_x;
- }
- }
- } else {
- pos_cpy.x = recout_width - pos_cpy.x + 2 *
recout_x;
- }
- }
- } else if (param.rotation == ROTATION_ANGLE_90) {
- } else if (param.rotation == ROTATION_ANGLE_270) {
+ if (param.rotation == ROTATION_ANGLE_270) {
// Swap axis and mirror vertically
uint32_t temp_x = pos_cpy.x;
@@ -1285,7 +1258,6 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
pos_cpy.x =
pipe_ctx->plane_res.scl_data.recout.width + next_odm_width + next_odm_offset -
pos_cpy.y;
pos_cpy.y = temp_x;
}
- } else {
}
} else if (param.rotation == ROTATION_ANGLE_180) {
// Mirror horizontally and vertically
--
2.45.1
[PATCH 16/36] drm/amd/display: Skip wbscl_set_scaler_filter if filter is null
From: Alex Hung
Callers can pass null in filter (i.e. from returned from the function
wbscl_get_filter_coeffs_16p) and a null check is added to ensure that is
not the case.
This fixes 4 NULL_RETURNS issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
index 994fb732a7cb..a0d437f0ce2b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
@@ -690,6 +690,9 @@ static void wbscl_set_scaler_filter(
int pair;
uint16_t odd_coef, even_coef;
+ if (!filter)
+ return;
+
for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
for (pair = 0; pair < tap_pairs; pair++) {
even_coef = filter[phase * taps + 2 * pair];
--
2.45.1
[PATCH 19/36] drm/amd/display: Fix NULL pointer dereference for DTN log in DCN401
From: Rodrigo Siqueira
When users run the command:
cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
The following NULL pointer dereference happens:
[ +0.03] BUG: kernel NULL pointer dereference, address: NULL
[ +0.05] #PF: supervisor instruction fetch in kernel mode
[ +0.02] #PF: error_code(0x0010) - not-present page
[ +0.02] PGD 0 P4D 0
[ +0.04] Oops: 0010 [#1] PREEMPT SMP NOPTI
[ +0.03] RIP: 0010:0x0
[ +0.08] Code: Unable to access opcode bytes at 0xffd6.
[...]
[ +0.02] PKRU: 5554
[ +0.02] Call Trace:
[ +0.02]
[ +0.03] ? show_regs+0x65/0x70
[ +0.06] ? __die+0x24/0x70
[ +0.04] ? page_fault_oops+0x160/0x470
[ +0.06] ? do_user_addr_fault+0x2b5/0x690
[ +0.03] ? prb_read_valid+0x1c/0x30
[ +0.05] ? exc_page_fault+0x8c/0x1a0
[ +0.05] ? asm_exc_page_fault+0x27/0x30
[ +0.12] dcn10_log_color_state+0xf9/0x510 [amdgpu]
[ +0.000306] ? srso_alias_return_thunk+0x5/0xfbef5
[ +0.03] ? vsnprintf+0x2fb/0x600
[ +0.09] dcn10_log_hw_state+0xfd0/0xfe0 [amdgpu]
[ +0.000218] ? __mod_memcg_lruvec_state+0xe8/0x170
[ +0.08] ? srso_alias_return_thunk+0x5/0xfbef5
[ +0.02] ? debug_smp_processor_id+0x17/0x20
[ +0.03] ? srso_alias_return_thunk+0x5/0xfbef5
[ +0.02] ? srso_alias_return_thunk+0x5/0xfbef5
[ +0.02] ? set_ptes.isra.0+0x2b/0x90
[ +0.04] ? srso_alias_return_thunk+0x5/0xfbef5
[ +0.02] ? _raw_spin_unlock+0x19/0x40
[ +0.04] ? srso_alias_return_thunk+0x5/0xfbef5
[ +0.02] ? do_anonymous_page+0x337/0x700
[ +0.04] dtn_log_read+0x82/0x120 [amdgpu]
[ +0.000207] full_proxy_read+0x66/0x90
[ +0.07] vfs_read+0xb0/0x340
[ +0.05] ? __count_memcg_events+0x79/0xe0
[ +0.02] ? srso_alias_return_thunk+0x5/0xfbef5
[ +0.03] ? count_memcg_events.constprop.0+0x1e/0x40
[ +0.03] ? handle_mm_fault+0xb2/0x370
[ +0.03] ksys_read+0x6b/0xf0
[ +0.04] __x64_sys_read+0x19/0x20
[ +0.03] do_syscall_64+0x60/0x130
[ +0.04] entry_SYSCALL_64_after_hwframe+0x6e/0x76
[ +0.03] RIP: 0033:0x7fdf32f147e2
[...]
This error happens when the color log tries to read the gamut remap
information from DCN401 which is not initialized in the dcn401_dpp_funcs
which leads to a null pointer dereference. This commit addresses this
issue by adding a proper guard to access the gamut_remap callback in
case the specific ASIC did not implement this function.
Reviewed-by: Aurabindo Pillai
Acked-by: Hamza Mahfooz
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 49 ++-
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index de6ee6bf0a88..0bfab66b8038 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -289,6 +289,7 @@ static void dcn10_log_color_state(struct dc *dc,
{
struct dc_context *dc_ctx = dc->ctx;
struct resource_pool *pool = dc->res_pool;
+ bool is_gamut_remap_available = false;
int i;
DTN_INFO("DPP:IGAM formatIGAM modeDGAM modeRGAM mode"
@@ -301,16 +302,15 @@ static void dcn10_log_color_state(struct dc *dc,
struct dcn_dpp_state s = {0};
dpp->funcs->dpp_read_state(dpp, &s);
- dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);
+ if (dpp->funcs->dpp_get_gamut_remap) {
+ dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);
+ is_gamut_remap_available = true;
+ }
if (!s.is_enabled)
continue;
- DTN_INFO("[%2d]: %11xh %11s%9s%9s"
-" %12s "
-"%010lld %010lld %010lld %010lld "
-"%010lld %010lld %010lld %010lld "
-"%010lld %010lld %010lld %010lld",
+ DTN_INFO("[%2d]: %11xh %11s%9s%9s",
dpp->inst,
s.igam_input_format,
(s.igam_lut_mode == 0) ? "BypassFixed" :
@@ -329,22 +329,27 @@ static void dcn10_log_color_state(struct dc *dc,
((s.rgam_lut_mode == 2) ? "Ycc" :
((s.rgam_lut_mode == 3) ? "RAM" :
((s.rgam_lut_mode == 4) ? "RAM" :
-"Unknown",
- (s.gamut_remap.gamut_adjust_type == 0) ?
"Bypass" :
-
[PATCH 15/36] drm/amd/display: Check BIOS images before it is used
From: Alex Hung BIOS images may fail to load and null checks are added before they are used. This fixes 6 NULL_RETURNS issues reported by Coverity. Reviewed-by: Harry Wentland Acked-by: Hamza Mahfooz Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 25fe1a124029..3bacf470f7c5 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -665,6 +665,9 @@ static enum bp_result get_ss_info_v3_1( ss_table_header_include = ((ATOM_ASIC_INTERNAL_SS_INFO_V3 *) bios_get_image(&bp->base, DATA_TABLES(ASIC_InternalSS_Info), struct_size(ss_table_header_include, asSpreadSpectrum, 1))); + if (!ss_table_header_include) + return BP_RESULT_UNSUPPORTED; + table_size = (le16_to_cpu(ss_table_header_include->sHeader.usStructureSize) - sizeof(ATOM_COMMON_TABLE_HEADER)) @@ -1034,6 +1037,8 @@ static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1( &bp->base, DATA_TABLES(ASIC_InternalSS_Info), struct_size(header, asSpreadSpectrum, 1))); + if (!header) + return result; memset(info, 0, sizeof(struct spread_spectrum_info)); @@ -1107,6 +1112,8 @@ static enum bp_result get_ss_info_from_ss_info_table( get_atom_data_table_revision(header, &revision); tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO, DATA_TABLES(SS_Info)); + if (!tbl) + return result; if (1 != revision.major || 2 > revision.minor) return result; @@ -1634,6 +1641,8 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl( tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO, DATA_TABLES(SS_Info)); + if (!tbl) + return number; if (1 != revision.major || 2 > revision.minor) return number; @@ -1716,6 +1725,8 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1( &bp->base, DATA_TABLES(ASIC_InternalSS_Info), struct_size(header_include, asSpreadSpectrum, 1))); + if (!header_include) + return 0; size = (le16_to_cpu(header_include->sHeader.usStructureSize) - sizeof(ATOM_COMMON_TABLE_HEADER)) @@ -1755,6 +1766,9 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1( header_include = ((ATOM_ASIC_INTERNAL_SS_INFO_V3 *) bios_get_image(&bp->base, DATA_TABLES(ASIC_InternalSS_Info), struct_size(header_include, asSpreadSpectrum, 1))); + if (!header_include) + return number; + size = (le16_to_cpu(header_include->sHeader.usStructureSize) - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); -- 2.45.1
[PATCH 12/36] drm/amd/display: Send message to notify the DPIA host router bandwidth
From: Sung Joon Kim
[why]
Tell the system about the current host router bandwidth to be used to
measure and calculate the right voltage to be used.
[how]
Send SMU message of each DPIA host router bandwidth.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hamza Mahfooz
Signed-off-by: Sung Joon Kim
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 55 +++
.../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 21 ++-
.../amd/display/dc/clk_mgr/dcn35/dcn35_smu.h | 2 +
drivers/gpu/drm/amd/display/dc/dc.h | 3 +
.../dc/resource/dcn351/dcn351_resource.c | 1 +
5 files changed, 81 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 6c9b4e6491a5..9a414f49f15a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -218,6 +218,57 @@ static void dcn35_update_clocks_update_dpp_dto(struct
clk_mgr_internal *clk_mgr,
}
}
+static uint8_t get_lowest_dpia_index(const struct dc_link *link)
+{
+ const struct dc *dc_struct = link->dc;
+ uint8_t idx = 0xFF;
+ int i;
+
+ for (i = 0; i < MAX_PIPES * 2; ++i) {
+ if (!dc_struct->links[i] || dc_struct->links[i]->ep_type !=
DISPLAY_ENDPOINT_USB4_DPIA)
+ continue;
+
+ if (idx > dc_struct->links[i]->link_index)
+ idx = dc_struct->links[i]->link_index;
+ }
+
+ return idx;
+}
+
+static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct
dc_state *context,
+ bool safe_to_lower)
+{
+ struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };
+ int i;
+
+ for (i = 0; i < context->stream_count; ++i) {
+ const struct dc_stream_state *stream = context->streams[i];
+ const struct dc_link *link = stream->link;
+ uint8_t lowest_dpia_index = 0, hr_index = 0;
+
+ if (!link)
+ continue;
+
+ lowest_dpia_index = get_lowest_dpia_index(link);
+ if (link->link_index < lowest_dpia_index)
+ continue;
+
+ hr_index = (link->link_index - lowest_dpia_index) / 2;
+ host_router_bw_kbps[hr_index] +=
dc_bandwidth_in_kbps_from_timing(
+ &stream->timing,
dc_link_get_highest_encoding_format(link));
+ }
+
+ for (i = 0; i < MAX_HOST_ROUTERS_NUM; ++i) {
+ new_clocks->host_router_bw_kbps[i] = host_router_bw_kbps[i];
+ if (should_set_clock(safe_to_lower,
new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_router_bw_kbps[i]))
{
+ clk_mgr_base->clks.host_router_bw_kbps[i] =
new_clocks->host_router_bw_kbps[i];
+ dcn35_smu_notify_host_router_bw(clk_mgr, i,
new_clocks->host_router_bw_kbps[i]);
+ }
+ }
+}
+
void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
bool safe_to_lower)
@@ -342,6 +393,10 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
dcn35_update_clocks_update_dpp_dto(clk_mgr, context,
safe_to_lower);
}
+ // notify PMFW of bandwidth per DPIA tunnel
+ if (dc->debug.notify_dpia_hr_bw)
+ dcn35_notify_host_router_bw(clk_mgr_base, context,
safe_to_lower);
+
// notify DMCUB of latest clocks
memset(&cmd, 0, sizeof(cmd));
cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index 1399b41dfd1c..f6f0e6a33001 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -89,7 +89,8 @@
#define VBIOSSMC_MSG_DisableLSdma 0x1A ///< Disable LSDMA;
only sent by VBIOS
#define VBIOSSMC_MSG_DpControllerPhyStatus0x1B ///< Inform PMFW about
the pre conditions for turning SLDO2 on/off . bit[0]==1 precondition is met,
bit[1-2] are for DPPHY number
#define VBIOSSMC_MSG_QueryIPS2Support 0x1C ///< Return 1: support;
else not supported
-#define VBIOSSMC_Message_Count0x1D
+#define VBIOSSMC_MSG_NotifyHostRouterBW 0x1D
+#define VBIOSSMC_Message_Count0x1E
#define VBIOSSMC_Status_BUSY 0x0
#define VBIOSSMC_Result_OK0x1
@@ -98,6 +99,14 @@
#define VBIOSSMC_
[PATCH 11/36] drm/amd/display: Add null check to dml21_find_dc_pipes_for_plane
From: Dillon Varone
When a phantom stream is in the process of being deconstructed, there
could be pipes with no associated planes. In that case, ignore the
phantom stream entirely when searching for associated pipes.
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee
Acked-by: Hamza Mahfooz
Signed-off-by: Dillon Varone
---
.../gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
index 4e12810308a4..4166332b5b89 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
@@ -126,10 +126,15 @@ int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,
if (dc_phantom_stream && num_pipes > 0) {
dc_phantom_stream_status =
dml_ctx->config.callbacks.get_stream_status(context, dc_phantom_stream);
- /* phantom plane will have same index as main */
- dc_phantom_plane =
dc_phantom_stream_status->plane_states[dc_plane_index];
+ if (dc_phantom_stream_status) {
+ /* phantom plane will have same index as main */
+ dc_phantom_plane =
dc_phantom_stream_status->plane_states[dc_plane_index];
-
dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_phantom_plane,
&context->res_ctx, dc_phantom_pipes);
+ if (dc_phantom_plane) {
+ /* only care about phantom pipes if they
contain the phantom plane */
+
dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_phantom_plane,
&context->res_ctx, dc_phantom_pipes);
+ }
+ }
}
return num_pipes;
--
2.45.1
[PATCH 14/36] drm/amd/display: Add null checker before passing variables
From: Alex Hung
Checks null pointer before passing variables to functions.
This fixes 3 NULL_RETURNS issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4de50b297035..48a9243ada7d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2875,7 +2875,8 @@ static int dm_suspend(void *handle)
dm->cached_dc_state =
dc_state_create_copy(dm->dc->current_state);
- dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
+ if (dm->cached_dc_state)
+ dm_gpureset_toggle_interrupts(adev,
dm->cached_dc_state, false);
amdgpu_dm_commit_zero_streams(dm->dc);
@@ -7102,7 +7103,8 @@ static void create_eml_sink(struct amdgpu_dm_connector
*aconnector)
aconnector->dc_sink = aconnector->dc_link->local_sink ?
aconnector->dc_link->local_sink :
aconnector->dc_em_sink;
- dc_sink_retain(aconnector->dc_sink);
+ if (aconnector->dc_sink)
+ dc_sink_retain(aconnector->dc_sink);
}
}
@@ -7929,7 +7931,8 @@ static int amdgpu_dm_connector_get_modes(struct
drm_connector *connector)
drm_add_modes_noedid(connector, 1920, 1080);
} else {
amdgpu_dm_connector_ddc_get_modes(connector, edid);
- amdgpu_dm_connector_add_common_modes(encoder, connector);
+ if (encoder)
+ amdgpu_dm_connector_add_common_modes(encoder,
connector);
amdgpu_dm_connector_add_freesync_modes(connector, edid);
}
amdgpu_dm_fbc_init(connector);
--
2.45.1
[PATCH 07/36] drm/amd/display: fix minor coding errors where dml21 phase 5 uses wrong variables
From: Wenjing Liu
There is a coding error which causes incorrect variables to be assigned
in DML21 phase 5.
Reviewed-by: Dillon Varone
Acked-by: Hamza Mahfooz
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c
index 1142fdade334..6f334fdc6eb8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c
@@ -259,7 +259,7 @@ bool dml2_build_mode_programming(struct
dml2_build_mode_programming_in_out *in_o
/*
* Phase 5: Optimize for Stutter
*/
- memset(&l->vmin_phase, 0, sizeof(struct optimization_phase_params));
+ memset(&l->stutter_phase, 0, sizeof(struct optimization_phase_params));
l->stutter_phase.dml = dml;
l->stutter_phase.display_config = &l->base_display_config_with_meta;
l->stutter_phase.init_function =
dml2_top_optimization_init_function_stutter;
@@ -272,7 +272,7 @@ bool dml2_build_mode_programming(struct
dml2_build_mode_programming_in_out *in_o
if (stutter_success) {
memcpy(&l->base_display_config_with_meta,
&l->optimized_display_config_with_meta, sizeof(struct
display_configuation_with_meta));
- l->base_display_config_with_meta.stage4.success = true;
+ l->base_display_config_with_meta.stage5.success = true;
}
/*
--
2.45.1
[PATCH 13/36] drm/amd/display: Explicitly extend unsigned 16 bit to 64 bit
From: Alex Hung
Coverity reports sign extention defects as below:
Suspicious implicit sign extension: mode->htotal with type u16 ... to
int (32 bits, signed), then sign-extended to type unsigned long
(64 bits, unsigned). If mode->htotal * mode->vtotal is greater than
0x7FFF, the upper bits of the result will all be 1.
Cast it to unsigned long to avoid possible overflow.
This fixes 4 SIGN_EXTENSION issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Hamza Mahfooz
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0940c2facb30..4de50b297035 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -977,8 +977,8 @@ static void amdgpu_dm_fbc_init(struct drm_connector
*connector)
list_for_each_entry(mode, &connector->modes, head) {
- if (max_size < mode->htotal * mode->vtotal)
- max_size = mode->htotal * mode->vtotal;
+ if (max_size < (unsigned long) mode->htotal * mode->vtotal)
+ max_size = (unsigned long) mode->htotal * mode->vtotal;
}
if (max_size) {
--
2.45.1
[PATCH 10/36] drm/amd/display: Attempt to avoid empty TUs when endpoint is DPIA
From: Michael Strauss
[WHY]
Empty SST TUs are illegal to transmit over a USB4 DP tunnel.
Current policy is to configure stream encoder to pack 2 pixels per pclk
even when ODM combine is not in use, allowing seamless dynamic ODM
reconfiguration. However, in extreme edge cases where average pixel
count per TU is less than 2, this can lead to unexpected empty TU
generation during compliance testing. For example, VIC 1 with a 1xHBR3
link configuration will average 1.98 pix/TU.
[HOW]
Calculate average pixel count per TU, and block 2 pixels per clock if
endpoint is a DPIA tunnel and pixel clock is low enough that we will
never require 2:1 ODM combine.
Cc: sta...@vger.kernel.org # 6.6+
Reviewed-by: Wenjing Liu
Acked-by: Hamza Mahfooz
Signed-off-by: Michael Strauss
---
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 72 +++
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 2 +
.../amd/display/dc/hwss/dcn35/dcn35_init.c| 2 +-
3 files changed, 75 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 4f87316e1318..0602921399cd 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -1529,3 +1529,75 @@ void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,
}
}
}
+
+static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx)
+{
+ /* Calculate average pixel count per TU, return false if under ~2.00 to
+* avoid empty TUs. This is only required for DPIA tunneling as empty
TUs
+* are legal to generate for native DP links. Assume TU size 64 as there
+* is currently no scenario where it's reprogrammed from HW default.
+* MTPs have no such limitation, so this does not affect MST use cases.
+*/
+ unsigned int pix_clk_mhz;
+ unsigned int symclk_mhz;
+ unsigned int avg_pix_per_tu_x1000;
+ unsigned int tu_size_bytes = 64;
+ struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
+ struct dc_link_settings *link_settings =
&pipe_ctx->link_config.dp_link_settings;
+ const struct dc *dc = pipe_ctx->stream->link->dc;
+
+ if (pipe_ctx->stream->link->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
+ return false;
+
+ // Not necessary for MST configurations
+ if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+ return false;
+
+ pix_clk_mhz = timing->pix_clk_100hz / 1;
+
+ // If this is true, can't block due to dynamic ODM
+ if (pix_clk_mhz >
dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz)
+ return false;
+
+ switch (link_settings->link_rate) {
+ case LINK_RATE_LOW:
+ symclk_mhz = 162;
+ break;
+ case LINK_RATE_HIGH:
+ symclk_mhz = 270;
+ break;
+ case LINK_RATE_HIGH2:
+ symclk_mhz = 540;
+ break;
+ case LINK_RATE_HIGH3:
+ symclk_mhz = 810;
+ break;
+ default:
+ // We shouldn't be tunneling any other rates, something is wrong
+ ASSERT(0);
+ return false;
+ }
+
+ avg_pix_per_tu_x1000 = (1000 * pix_clk_mhz * tu_size_bytes)
+ / (symclk_mhz * link_settings->lane_count);
+
+ // Add small empirically-decided margin to account for potential jitter
+ return (avg_pix_per_tu_x1000 < 2020);
+}
+
+bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
+{
+ struct dc *dc = pipe_ctx->stream->ctx->dc;
+
+ if (!is_h_timing_divisible_by_2(pipe_ctx->stream))
+ return false;
+
+ if (should_avoid_empty_tu(pipe_ctx))
+ return false;
+
+ if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
!dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&
+ dc->debug.enable_dp_dig_pixel_rate_div_policy)
+ return true;
+
+ return false;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
index bc05beba5f2c..e27b3609020f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
@@ -97,4 +97,6 @@ void dcn35_set_static_screen_control(struct pipe_ctx
**pipe_ctx,
void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,
int num_pipes, uint32_t v_total_min, uint32_t v_total_max);
+bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
+
#endif /* __DC_HWSS_DCN35_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index 30e6a6398839..428912f37129 10064
[PATCH 04/36] Revert "drm/amd/display: workaround for oled eDP not lighting up on DCN401"
From: Joshua Aberback
This reverts commit e296c84e7d0561ed626591e1cf9b71a7ba0133f4.
A proper fix for this issue has been implemented in DMUB FW. So, no need
to keep the workaround.
Reviewed-by: Wenjing Liu
Acked-by: Hamza Mahfooz
Signed-off-by: Joshua Aberback
---
drivers/gpu/drm/amd/display/dc/dc.h| 1 -
.../drm/amd/display/dc/link/protocols/link_edp_panel_control.c | 3 ---
.../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 -
3 files changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 35ca38ea2efa..b9c67bac7beb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1045,7 +1045,6 @@ struct dc_debug_options {
unsigned int force_easf;
unsigned int force_sharpness;
unsigned int force_lls;
- bool edp_oled_no_backlight_enable;
};
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index b0e17064a960..455b85adec28 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -248,9 +248,6 @@ bool edp_backlight_enable_aux(struct dc_link *link, bool
enable)
link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
return false;
- if (link->dc->debug.edp_oled_no_backlight_enable &&
link->dpcd_sink_ext_caps.bits.oled)
- return true;
-
if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
&backlight_enable, 1) != DC_OK)
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index d78dc63f82fd..74fb21b88f12 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -731,7 +731,6 @@ static const struct dc_debug_options debug_defaults_drv = {
}
},
.force_cositing = CHROMA_COSITING_TOPLEFT + 1,
- .edp_oled_no_backlight_enable = true,
};
static struct dce_aux *dcn401_aux_engine_create(
--
2.45.1
[PATCH 09/36] drm/amd/display: Refactor DCN3X into component folder
From: Mounika Adhuri
[why]
Move DCN3X files to unique component folder.
[how]
Create respective component folder in dc, move the DCN3X files into
corresponding new folders and made appropriate changes for compilation
in Makefiles.
Reviewed-by: Martin Leung
Acked-by: Hamza Mahfooz
Signed-off-by: Mounika Adhuri
---
drivers/gpu/drm/amd/display/Makefile | 7 +++
drivers/gpu/drm/amd/display/dc/Makefile | 6 +-
drivers/gpu/drm/amd/display/dc/dcn32/Makefile | 19 --
.../gpu/drm/amd/display/dc/dcn321/Makefile| 17 -
drivers/gpu/drm/amd/display/dc/dcn35/Makefile | 19 --
drivers/gpu/drm/amd/display/dc/dio/Makefile | 63 +++
.../{ => dio}/dcn32/dcn32_dio_link_encoder.c | 0
.../{ => dio}/dcn32/dcn32_dio_link_encoder.h | 0
.../dcn32/dcn32_dio_stream_encoder.c | 0
.../dcn32/dcn32_dio_stream_encoder.h | 0
.../dcn321/dcn321_dio_link_encoder.c | 0
.../dcn321/dcn321_dio_link_encoder.h | 0
.../{ => dio}/dcn35/dcn35_dio_link_encoder.c | 0
.../{ => dio}/dcn35/dcn35_dio_link_encoder.h | 0
.../dcn35/dcn35_dio_stream_encoder.c | 0
.../dcn35/dcn35_dio_stream_encoder.h | 0
.../dcn401/dcn401_dio_link_encoder.c | 0
.../dcn401/dcn401_dio_link_encoder.h | 0
.../dcn401/dcn401_dio_stream_encoder.c| 0
.../dcn401/dcn401_dio_stream_encoder.h| 0
drivers/gpu/drm/amd/display/dc/dwb/Makefile | 37 +++
.../display/dc/{ => dwb}/dcn35/dcn35_dwb.c| 0
.../display/dc/{ => dwb}/dcn35/dcn35_dwb.h| 0
drivers/gpu/drm/amd/display/dc/hpo/Makefile | 35 +++
.../dcn32/dcn32_hpo_dp_link_encoder.c | 0
.../dcn32/dcn32_hpo_dp_link_encoder.h | 0
.../gpu/drm/amd/display/dc/mmhubbub/Makefile | 45 +
.../dc/{ => mmhubbub}/dcn32/dcn32_mmhubbub.c | 0
.../dc/{ => mmhubbub}/dcn32/dcn32_mmhubbub.h | 0
.../dc/{ => mmhubbub}/dcn35/dcn35_mmhubbub.c | 0
.../dc/{ => mmhubbub}/dcn35/dcn35_mmhubbub.h | 0
drivers/gpu/drm/amd/display/dc/mpc/Makefile | 45 +
.../display/dc/{ => mpc}/dcn32/dcn32_mpc.c| 0
.../display/dc/{ => mpc}/dcn32/dcn32_mpc.h| 0
.../display/dc/{ => mpc}/dcn401/dcn401_mpc.c | 0
.../display/dc/{ => mpc}/dcn401/dcn401_mpc.h | 0
drivers/gpu/drm/amd/display/dc/opp/Makefile | 35 +++
.../display/dc/{ => opp}/dcn35/dcn35_opp.c| 0
.../display/dc/{ => opp}/dcn35/dcn35_opp.h| 0
drivers/gpu/drm/amd/display/dc/pg/Makefile| 35 +++
.../display/dc/{ => pg}/dcn35/dcn35_pg_cntl.c | 0
.../display/dc/{ => pg}/dcn35/dcn35_pg_cntl.h | 0
.../gpu/drm/amd/display/dc/resource/Makefile | 2 +-
.../dcn32/dcn32_resource_helpers.c| 0
44 files changed, 304 insertions(+), 61 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/Makefile
delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/Makefile
delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn35/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dio/Makefile
rename drivers/gpu/drm/amd/display/dc/{ => dio}/dcn32/dcn32_dio_link_encoder.c
(100%)
rename drivers/gpu/drm/amd/display/dc/{ => dio}/dcn32/dcn32_dio_link_encoder.h
(100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn32/dcn32_dio_stream_encoder.c (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn32/dcn32_dio_stream_encoder.h (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn321/dcn321_dio_link_encoder.c (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn321/dcn321_dio_link_encoder.h (100%)
rename drivers/gpu/drm/amd/display/dc/{ => dio}/dcn35/dcn35_dio_link_encoder.c
(100%)
rename drivers/gpu/drm/amd/display/dc/{ => dio}/dcn35/dcn35_dio_link_encoder.h
(100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn35/dcn35_dio_stream_encoder.c (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn35/dcn35_dio_stream_encoder.h (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn401/dcn401_dio_link_encoder.c (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn401/dcn401_dio_link_encoder.h (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn401/dcn401_dio_stream_encoder.c (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn401/dcn401_dio_stream_encoder.h (100%)
create mode 100644 drivers/gpu/drm/amd/display/dc/dwb/Makefile
rename drivers/gpu/drm/amd/display/dc/{ => dwb}/dcn35/dcn35_dwb.c (100%)
rename drivers/gpu/drm/amd/display/dc/{ => dwb}/dcn35/dcn35_dwb.h (100%)
create mode 100644 drivers/gpu/drm/amd/display/dc/hpo/Makefile
rename drivers/gpu/drm/amd/display/dc/{ =>
hpo}/dcn32/dcn32_hpo_dp_link_encoder.c (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
hpo}/dcn32/dcn32_hpo_dp_link_encoder.h (100%)
create mode 100644 drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile
rename drivers/gpu/drm/amd/display/dc/{ => mmhubb
[PATCH 06/36] drm/amd/display: Remove redundant condition in VBA 314 func
From: Ivan Lipski
[WHY]
Coverity analysis this conditional code as DEADCODE.
The conditional statement is never true since
'MacroTileSizeBytes' is either 256 or 65536. Thus, the
code inside is the conditional statement is never reached.
[HOW]
Removed the conditional statement.
Reviewed-by: Aurabindo Pillai
Reviewed-by: Alex Hung
Acked-by: Hamza Mahfooz
Signed-off-by: Ivan Lipski
---
.../drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index f52b9e3d2bee..cb50c475746b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -1941,15 +1941,6 @@ static unsigned int CalculateVMAndRowBytes(
*PixelPTEReqWidth = 32768.0 / BytePerPixel;
*PTERequestSize = 64;
FractionOfPTEReturnDrop = 0;
- } else if (MacroTileSizeBytes == 4096) {
- PixelPTEReqHeightPTEs = 1;
- *PixelPTEReqHeight = MacroTileHeight;
- *PixelPTEReqWidth = 8 * *MacroTileWidth;
- *PTERequestSize = 64;
- if (ScanDirection != dm_vert)
- FractionOfPTEReturnDrop = 0;
- else
- FractionOfPTEReturnDrop = 7 / 8;
} else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) {
PixelPTEReqHeightPTEs = 16;
*PixelPTEReqHeight = 16 * BlockHeight256Bytes;
--
2.45.1
[PATCH 02/36] drm/amd/display: Enable DCN401 idle optimizations by default
From: Dillon Varone
[WHY&HOW]
Re-enable idle optimizations by default.
Reviewed-by: Alvin Lee
Acked-by: Hamza Mahfooz
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index 7781a0342d67..d78dc63f82fd 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -731,7 +731,6 @@ static const struct dc_debug_options debug_defaults_drv = {
}
},
.force_cositing = CHROMA_COSITING_TOPLEFT + 1,
- .disable_idle_power_optimizations = true,
.edp_oled_no_backlight_enable = true,
};
--
2.45.1
[PATCH 01/36] drm/amd/display: DCN401 full power down in HW init if any link enabled
From: Joshua Aberback
[Why]
During HW init, certain operations the driver performs are invalid on
enabled hardware in an unknown state (for example, setting all clock
values to minimum when the GPU is actively driving a display). There is
already code present to call HWSS->power_down during init when any link
is enabled in HW, but that function pointer is unpopulated for most asics.
We want to enable this codepath for DCN401, as it resolves the issue with
being unable to drive certain display configs on adapter re-enable, and we
can restore boot optimizations.
[How]
- add power_down HWSS function for DCN401
- remove debug bit to disable boot optimizations for DCN401
Reviewed-by: Wenjing Liu
Acked-by: Hamza Mahfooz
Signed-off-by: Joshua Aberback
---
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c | 1 +
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index dabad7feff03..1cf0608e1980 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -98,6 +98,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = {
.fams2_global_control_lock = dcn401_fams2_global_control_lock,
.fams2_update_config = dcn401_fams2_update_config,
.fams2_global_control_lock_fast = dcn401_fams2_global_control_lock_fast,
+ .power_down = dce110_power_down,
};
static const struct hwseq_private_funcs dcn401_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index ea803df8645e..7781a0342d67 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -733,7 +733,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.force_cositing = CHROMA_COSITING_TOPLEFT + 1,
.disable_idle_power_optimizations = true,
.edp_oled_no_backlight_enable = true,
- .disable_boot_optimizations = true,
};
static struct dce_aux *dcn401_aux_engine_create(
--
2.45.1
[PATCH 08/36] drm/amd/display: On clock init, maintain DISPCLK freq
From: Chris Park
[Why]
On init if a display is connected, we need to maintain the DISPCLK
frequency Even though DPG_EN=1, the display still requires the correct
timing or it could cause audio corruption (if DISPCLK freq is reduced).
[How]
Read the current DISPCLK freq and request the same value to ensure the
timing is valid and unchanged.
Reviewed-by: Alvin Lee
Acked-by: Hamza Mahfooz
Signed-off-by: Chris Park
---
.../display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 17 +
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 11 ++-
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index cd1c30fa783a..70f06a7c882e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -1459,6 +1459,22 @@ static int dcn401_get_dtb_ref_freq_khz(struct clk_mgr
*clk_mgr_base)
return dtb_ref_clk_khz;
}
+static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
+{
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ uint32_t dispclk_wdivider;
+ int disp_divider;
+
+ REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER,
&dispclk_wdivider);
+ disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
+
+ /* Return DISPCLK freq in Khz */
+ if (disp_divider)
+ return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR *
clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
+
+ return 0;
+}
+
static struct clk_mgr_funcs dcn401_funcs = {
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.get_dtb_ref_clk_frequency = dcn401_get_dtb_ref_freq_khz,
@@ -1472,6 +1488,7 @@ static struct clk_mgr_funcs dcn401_funcs = {
.are_clock_states_equal = dcn401_are_clock_states_equal,
.enable_pme_wa = dcn401_enable_pme_wa,
.is_smu_present = dcn401_is_smu_present,
+ .get_dispclk_from_dentist = dcn401_get_dispclk_from_dentist,
};
struct clk_mgr_internal *dcn401_clk_mgr_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 4d0c01e866be..e7d6d987e3d3 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -57,7 +57,16 @@ static void dcn401_initialize_min_clocks(struct dc *dc)
clocks->socclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;
clocks->dramclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;
clocks->dppclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;
- clocks->dispclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;
+ if (dc->debug.disable_boot_optimizations) {
+ clocks->dispclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;
+ } else {
+ /* Even though DPG_EN = 1 for the connected display, it still
requires the
+* correct timing so we cannot set DISPCLK to min freq or it
could cause
+* audio corruption. Read current DISPCLK from DENTIST and
request the same
+* freq to ensure that the timing is valid and unchanged.
+*/
+ clocks->dispclk_khz =
dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
+ }
clocks->ref_dtbclk_khz =
dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
clocks->fclk_p_state_change_support = true;
clocks->p_state_change_support = true;
--
2.45.1
[PATCH 00/36] DC Patches June 11, 2024
Cc: Daniel Wheeler
Alex Hung (15):
drm/amd/display: Explicitly extend unsigned 16 bit to 64 bit
drm/amd/display: Add null checker before passing variables
drm/amd/display: Check BIOS images before it is used
drm/amd/display: Skip wbscl_set_scaler_filter if filter is null
drm/amd/display: Add null checker before access structs
drm/amd/display: Check dc_stream_state before it is used
drm/amd/display: Check pipe_ctx before it is used
drm/amd/display: Covert integers to double before divisions
drm/amd/display: Remove redundant checks for res_pool->dccg
drm/amd/display: Remove redundant checks for ctx->dc_bios
drm/amd/display: Remove redundant null checks
drm/amd/display: Remove redundant checks for opp
drm/amd/display: Remove redundant checks for context
drm/amd/display: Check UnboundedRequestEnabled's value
drm/amd/display: Remove redundant null checks
Alvin Lee (1):
drm/amd/display: Make sure to reprogram ODM when resync fifo
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.222.0
Aric Cyr (1):
drm/amd/display: 3.2.289
Chris Park (1):
drm/amd/display: On clock init, maintain DISPCLK freq
Dillon Varone (2):
drm/amd/display: Enable DCN401 idle optimizations by default
drm/amd/display: Add null check to dml21_find_dc_pipes_for_plane
Ivan Lipski (3):
drm/amd/display: Remove redundant condition with DEADCODE
drm/amd/display: Remove redundant condition in VBA 314 func
drm/amd/display: Remove unused value set from 'min_hratio_fact' in dml
Joshua Aberback (3):
drm/amd/display: DCN401 full power down in HW init if any link enabled
Revert "drm/amd/display: workaround for oled eDP not lighting up on
DCN401"
drm/amd/display: Remove duplicate HWSS interfaces
Michael Strauss (1):
drm/amd/display: Attempt to avoid empty TUs when endpoint is DPIA
Mounika Adhuri (1):
drm/amd/display: Refactor DCN3X into component folder
Relja Vojvodic (1):
drm/amd/display: Add dcn401 DIG fifo enable/disable
Rodrigo Siqueira (3):
drm/amd/display: Fix NULL pointer dereference for DTN log in DCN401
drm/amd/display: Fix warning caused by an attempt to configure a
non-otg master
drm/amd/display: Improve warning log for get OPP for OTG master
Sridevi Arvindekar (1):
drm/amd/display: mirror case cleanup for cursors
Sung Joon Kim (1):
drm/amd/display: Send message to notify the DPIA host router bandwidth
Wenjing Liu (1):
drm/amd/display: fix minor coding errors where dml21 phase 5 uses
wrong variables
drivers/gpu/drm/amd/display/Makefile | 7 ++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +--
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +-
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 -
drivers/gpu/drm/amd/display/dc/Makefile | 6 +-
.../gpu/drm/amd/display/dc/bios/bios_parser.c | 14 +++
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
.../display/dc/clk_mgr/dcn301/vg_clk_mgr.c| 2 +-
.../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 2 +-
.../dc/clk_mgr/dcn314/dcn314_clk_mgr.c| 2 +-
.../dc/clk_mgr/dcn315/dcn315_clk_mgr.c| 2 +-
.../dc/clk_mgr/dcn316/dcn316_clk_mgr.c| 2 +-
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 57 -
.../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 21 +++-
.../amd/display/dc/clk_mgr/dcn35/dcn35_smu.h | 2 +
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 17 +++
drivers/gpu/drm/amd/display/dc/core/dc.c | 21 +++-
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 2 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 15 ++-
.../gpu/drm/amd/display/dc/core/dc_state.c| 24 ++--
drivers/gpu/drm/amd/display/dc/dc.h | 6 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 20 +++-
.../drm/amd/display/dc/dcn20/dcn20_dwb_scl.c | 3 +
drivers/gpu/drm/amd/display/dc/dcn32/Makefile | 19 ---
.../gpu/drm/amd/display/dc/dcn321/Makefile| 17 ---
drivers/gpu/drm/amd/display/dc/dcn35/Makefile | 19 ---
drivers/gpu/drm/amd/display/dc/dio/Makefile | 63 ++
.../{ => dio}/dcn32/dcn32_dio_link_encoder.c | 0
.../{ => dio}/dcn32/dcn32_dio_link_encoder.h | 0
.../dcn32/dcn32_dio_stream_encoder.c | 0
.../dcn32/dcn32_dio_stream_encoder.h | 0
.../dcn321/dcn321_dio_link_encoder.c | 0
.../dcn321/dcn321_dio_link_encoder.h | 0
.../{ => dio}/dcn35/dcn35_dio_link_encoder.c | 0
.../{ => dio}/dcn35/dcn35_dio_link_encoder.h | 0
.../dcn35/dcn35_dio_stream_encoder.c | 4 +-
.../dcn35/dcn35_dio_stream_encoder.h | 6 +
.../dcn401/dcn401_dio_link_encoder.c | 0
.../dcn401/dcn401_dio_link_encoder.h | 0
.../dcn401/dcn401_dio_stream_encoder.c| 4 +-
.../dcn401/dcn401_dio_stream_encoder.h| 0
.../drm/amd/display/dc/dml/calcs/dcn_calcs.c | 2 +-
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 20 ++--
.../dc/dml/dcn20/display_m
