from:"Sunil Khatri"

[PATCH v1 3/5] drm/amdgpu: fix the extra space between two functions

2024-07-16 Thread Sunil Khatri

fix extra line space between two functions.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 630b03f2ce3d..66bb85955fa4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1742,6 +1742,7 @@ static void sdma_v5_2_print_ip_state(void *handle, struct 
drm_printer *p)
   adev->sdma.ip_dump[instance_offset + j]);
}
 }
+
 static void sdma_v5_2_dump_ip_state(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-- 
2.34.1

[PATCH v1 5/5] drm/amdgpu: add print support for sdma_v_5_0 ip_dump

2024-07-16 Thread Sunil Khatri

Add support for ip dump for sdma_v_5_0 in devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index cb324a90b310..d5f0dc132a47 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1778,6 +1778,27 @@ static void sdma_v5_0_get_clockgating_state(void 
*handle, u64 *flags)
*flags |= AMD_CG_SUPPORT_SDMA_LS;
 }
 
+static void sdma_v5_0_print_ip_state(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   int i, j;
+   uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);
+   uint32_t instance_offset;
+
+   if (!adev->sdma.ip_dump)
+   return;
+
+   drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   instance_offset = i * reg_count;
+   drm_printf(p, "\nInstance:%d\n", i);
+
+   for (j = 0; j < reg_count; j++)
+   drm_printf(p, "%-50s \t 0x%08x\n", 
sdma_reg_list_5_0[j].reg_name,
+  adev->sdma.ip_dump[instance_offset + j]);
+   }
+}
+
 static void sdma_v5_0_dump_ip_state(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1816,6 +1837,7 @@ const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
.set_powergating_state = sdma_v5_0_set_powergating_state,
.get_clockgating_state = sdma_v5_0_get_clockgating_state,
.dump_ip_state = sdma_v5_0_dump_ip_state,
+   .print_ip_state = sdma_v5_0_print_ip_state,
 };
 
 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
-- 
2.34.1

[PATCH v1 4/5] drm/amdgpu: Add sdma_v5_0 ip dump for devcoredump

2024-07-16 Thread Sunil Khatri

Add ip dump for sdma_v5_0 for devcoredump for all
instances of sdma.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 82 ++
 1 file changed, 82 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index b7d33d78bce0..cb324a90b310 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -59,6 +59,55 @@ MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
 #define SDMA0_HYP_DEC_REG_END 0x5893
 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
 
+static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_0[] = {
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)
+};
+
 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
@@ -1341,6 +1390,8 @@ static int sdma_v5_0_sw_init(void *handle)
struct amdgpu_ring *ring;
int r, i;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);
+   uint32_t *ptr;
 
/* SDMA trap event */
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
@@ -1378,6 +1429,13 @@ static int sdma_v5_0_sw_init(void *handle)
return r;
}
 
+   /* Allocate memory for SDMA IP Dump buffer */
+   ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), 
GFP_KERNEL);
+   if (ptr)
+   adev->sdma.ip_dump = ptr;
+   else
+   DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
+
return r;
 }
 
@@ -1391,6 +1449,8 @@ static int sdma_v5_0_sw_fini(void *handle)
 
amdgpu_sdma_destroy_inst_ctx(adev, false);
 
+   kfree(adev->sdma.ip_dump);
+
return 0;
 }
 
@@ -1718,6 +1778,27 @@ static void sdma_v5_0_get_clockgating_state(void 
*handle, u64 *flags)
*flags |= AMD_CG_SUPPORT_SDMA_LS;
 }
 
+static void sdma_v5_0_dump_ip_state(void *handle)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   int i, j;
+   uint32_t instance_offset;
+   uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);
+
+   if (!adev->sdma

[PATCH v1 2/5] drm/amdgpu: add print support for sdma_v_6_0 ip_dump

2024-07-16 Thread Sunil Khatri

Add print support for ip dump for sdma_v_6_0 in
devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 102de209f120..208a1fa9d4e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1556,6 +1556,27 @@ static void sdma_v6_0_get_clockgating_state(void 
*handle, u64 *flags)
 {
 }
 
+static void sdma_v6_0_print_ip_state(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   int i, j;
+   uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
+   uint32_t instance_offset;
+
+   if (!adev->sdma.ip_dump)
+   return;
+
+   drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   instance_offset = i * reg_count;
+   drm_printf(p, "\nInstance:%d\n", i);
+
+   for (j = 0; j < reg_count; j++)
+   drm_printf(p, "%-50s \t 0x%08x\n", 
sdma_reg_list_6_0[j].reg_name,
+  adev->sdma.ip_dump[instance_offset + j]);
+   }
+}
+
 static void sdma_v6_0_dump_ip_state(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1595,6 +1616,7 @@ const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
.set_powergating_state = sdma_v6_0_set_powergating_state,
.get_clockgating_state = sdma_v6_0_get_clockgating_state,
.dump_ip_state = sdma_v6_0_dump_ip_state,
+   .print_ip_state = sdma_v6_0_print_ip_state,
 };
 
 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
-- 
2.34.1

[PATCH v1 1/5] drm/amdgpu: Add sdma_v6_0 ip dump for devcoredump

2024-07-16 Thread Sunil Khatri

Add ip dump for sdma_v6_0 for devcoredump for all
instances of sdma.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 90 ++
 1 file changed, 90 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index dab4c2db8c9d..102de209f120 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -57,6 +57,63 @@ MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin");
 #define SDMA0_HYP_DEC_REG_END 0x589a
 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
 
+static const struct amdgpu_hwip_reg_entry sdma_reg_list_6_0[] = {
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
+   SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS),
+};
+
 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);
 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);
 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);
@@ -1239,6 +1296,8 @@ static int sdma_v6_0_sw_init(void *handle)
struct amdgpu_ring *ring;
int r, i;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
+   uint32_t *ptr;
 
/* SDMA trap event */
r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
@@ -1274,6 +1333,13 @@ static int sdma_v6_0_sw_init(void *handle)
return -EINVAL;
}
 
+   /* Allocate memory for SDMA IP Dump buffer */
+   ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), 
GFP_KERNEL);
+   if (ptr)
+   adev->sdma.ip_dump = ptr;
+   else
+   DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
+
return

[PATCH v1 0/5] devcoredump for sdma v5.0 and sdma 6.0

2024-07-16 Thread Sunil Khatri

*** BLURB HERE ***

Sunil Khatri (5):
  drm/amdgpu: Add sdma_v6_0 ip dump for devcoredump
  drm/amdgpu: add print support for sdma_v_6_0 ip_dump
  drm/amdgpu: fix the extra space between two functions
  drm/amdgpu: Add sdma_v5_0 ip dump for devcoredump
  drm/amdgpu: add print support for sdma_v_5_0 ip_dump

 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 104 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c |   1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 112 +
 3 files changed, 217 insertions(+)

-- 
2.34.1

[PATCH] drm/amdgpu: fix the print message in devcoredump

2024-07-12 Thread Sunil Khatri

Fix the memory type logged for gtt memory size
which is wrongly logged as visible vram size.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
index f0a44d0dec27..f6806ae1c061 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
@@ -236,7 +236,7 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t 
count,
drm_printf(, "\nSOC Memory Information\n");
drm_printf(, "real vram size: %llu\n", 
coredump->adev->gmc.real_vram_size);
drm_printf(, "visible vram size: %llu\n", 
coredump->adev->gmc.visible_vram_size);
-   drm_printf(, "visible vram size: %llu\n", 
coredump->adev->mman.gtt_mgr.manager.size);
+   drm_printf(, "gtt size: %llu\n", 
coredump->adev->mman.gtt_mgr.manager.size);
 
/* GDS Config */
drm_printf(, "\nGDS Config\n");
-- 
2.34.1

[PATCH v1 2/2] drm/amdgpu: add print support for sdma_v_5_2 ip_dump

2024-07-12 Thread Sunil Khatri

Add support for ip dump for sdma_v_5_2 in devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 05a13086405b..dc1ca2205807 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1722,6 +1722,29 @@ static void sdma_v5_2_ring_end_use(struct amdgpu_ring 
*ring)
amdgpu_gfx_off_ctrl(adev, true);
 }
 
+static void sdma_v5_2_print_ip_state(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   int i, j;
+   uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);
+   uint32_t instance_offset;
+
+   if (adev->sdma.ip_dump == NULL)
+   return;
+
+   drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   instance_offset = i * reg_count;
+   drm_printf(p, "\nInstance:%d\n", i);
+
+   for (j = 0; j < reg_count; j++)
+   drm_printf(p, "%-50s \t 0x%08x\n", 
sdma_reg_list_5_2[j].reg_name,
+  adev->sdma.ip_dump[instance_offset + j]);
+   }
+
+
+
+}
 static void sdma_v5_2_dump_ip_state(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1760,6 +1783,7 @@ const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
.set_powergating_state = sdma_v5_2_set_powergating_state,
.get_clockgating_state = sdma_v5_2_get_clockgating_state,
.dump_ip_state = sdma_v5_2_dump_ip_state,
+   .print_ip_state = sdma_v5_2_print_ip_state,
 };
 
 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
-- 
2.34.1

[PATCH v1 0/2] SDMA v5_2 ip dump support for devcoredump

2024-07-12 Thread Sunil Khatri

 0x
mmSDMA0_PAGE_RB_RPTR_HI  0x
mmSDMA0_PAGE_RB_WPTR 0x
mmSDMA0_PAGE_RB_WPTR_HI  0x
mmSDMA0_PAGE_IB_OFFSET   0x
mmSDMA0_PAGE_IB_BASE_LO  0x
mmSDMA0_PAGE_IB_BASE_HI  0x
mmSDMA0_PAGE_DUMMY_REG   0x000f
mmSDMA0_RLC0_RB_CNTL 0x8007
mmSDMA0_RLC0_RB_RPTR 0x
mmSDMA0_RLC0_RB_RPTR_HI  0x
mmSDMA0_RLC0_RB_WPTR 0x
mmSDMA0_RLC0_RB_WPTR_HI  0x
mmSDMA0_RLC0_IB_OFFSET   0x
mmSDMA0_RLC0_IB_BASE_LO  0x
mmSDMA0_RLC0_IB_BASE_HI  0x
mmSDMA0_RLC0_DUMMY_REG   0x000f
mmSDMA0_INT_STATUS   0x00e0
mmSDMA0_VM_CNTL  0x
mmGRBM_STATUS2   0x


Sunil Khatri (2):
  drm/amdgpu: Add sdma_v5_2 ip dump for devcoredump
  drm/amdgpu: add print support for sdma_v_5_2 ip_dump

 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |   1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   | 106 +++
 2 files changed, 107 insertions(+)

-- 
2.34.1

[PATCH v1 1/2] drm/amdgpu: Add sdma_v5_2 ip dump for devcoredump

2024-07-12 Thread Sunil Khatri

Add ip dump for sdma_v5_2 for devcoredump for all
instances of sdma.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |  1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   | 82 
 2 files changed, 83 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index d3706a484870..087ce0f6fa07 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -115,6 +115,7 @@ struct amdgpu_sdma {
boolhas_page_queue;
struct ras_common_if*ras_if;
struct amdgpu_sdma_ras  *ras;
+   uint32_t*ip_dump;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index cc9e961f0078..05a13086405b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -60,6 +60,55 @@ MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
 #define SDMA0_HYP_DEC_REG_END 0x5893
 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
 
+static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_2[] = {
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)
+};
+
 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
@@ -1214,6 +1263,8 @@ static int sdma_v5_2_sw_init(void *handle)
struct amdgpu_ring *ring;
int r, i;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);
+   uint32_t *ptr;
 
/* SDMA trap event */
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -1245,6 +1296,13 @@ static int sdma_v5_2_sw_init(void *handle)
return r;
}
 
+   /* Allocate memory for SDMA IP Dump buffer */
+   ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), 
GFP_KERNEL);
+   if (ptr)
+   adev->sdma.ip_dump = ptr;
+   else
+   DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
+
return r;
 }
 
@@ -1258,6 +1316,8 @@ static int sdma_v5_2_sw_fini(void *handle)
 
amdgpu_sdma_destroy_inst_ctx(a

[PATCH v1 0/2] SDMA v5_2 ip dump support for devcoredump

2024-07-12 Thread Sunil Khatri

 0x
mmSDMA0_PAGE_RB_RPTR_HI  0x
mmSDMA0_PAGE_RB_WPTR 0x
mmSDMA0_PAGE_RB_WPTR_HI  0x
mmSDMA0_PAGE_IB_OFFSET   0x
mmSDMA0_PAGE_IB_BASE_LO  0x
mmSDMA0_PAGE_IB_BASE_HI  0x
mmSDMA0_PAGE_DUMMY_REG   0x000f
mmSDMA0_RLC0_RB_CNTL 0x8007
mmSDMA0_RLC0_RB_RPTR 0x
mmSDMA0_RLC0_RB_RPTR_HI  0x
mmSDMA0_RLC0_RB_WPTR 0x
mmSDMA0_RLC0_RB_WPTR_HI  0x
mmSDMA0_RLC0_IB_OFFSET   0x
mmSDMA0_RLC0_IB_BASE_LO  0x
mmSDMA0_RLC0_IB_BASE_HI  0x
mmSDMA0_RLC0_DUMMY_REG   0x000f
mmSDMA0_INT_STATUS   0x00e0
mmSDMA0_VM_CNTL  0x
mmGRBM_STATUS2   0x


Sunil Khatri (2):
  drm/amdgpu: Add sdma_v5_2 ip dump for devcoredump
  drm/amdgpu: add print support for sdma_v_5_2 ip_dump

 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |   1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   | 106 +++
 2 files changed, 107 insertions(+)

-- 
2.34.1

[PATCH v1 3/3] drm/amdgpu: select compute ME engines dynamically

2024-07-09 Thread Sunil Khatri

GFX ME right now is one but this could change in
future SOC's. Use no of ME for GFX as start point
for ME for compute for GFX12.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 084b039eb765..f384be0d1800 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -4946,7 +4946,7 @@ static void gfx_v12_ip_dump(void *handle)
for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
/* ME0 is for GFX so start from 1 for CP */
-   soc24_grbm_select(adev, 1+i, j, k, 0);
+   soc24_grbm_select(adev, adev->gfx.me.num_me + 
i, j, k, 0);
for (reg = 0; reg < reg_count; reg++) {
adev->gfx.ip_dump_compute_queues[index 
+ reg] =
RREG32(SOC15_REG_ENTRY_OFFSET(
-- 
2.34.1

[PATCH v1 1/3] drm/amdgpu: select compute ME engines dynamically

2024-07-09 Thread Sunil Khatri

GFX ME right now is one but this could change in
future SOC's. Use no of ME for GFX as start point
for ME for compute for GFX10.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 4bc2abe97087..2957702fca0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9332,7 +9332,7 @@ static void gfx_v10_ip_dump(void *handle)
for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
/* ME0 is for GFX so start from 1 for CP */
-   nv_grbm_select(adev, 1 + i, j, k, 0);
+   nv_grbm_select(adev, adev->gfx.me.num_me + i, 
j, k, 0);
 
for (reg = 0; reg < reg_count; reg++) {
adev->gfx.ip_dump_compute_queues[index 
+ reg] =
-- 
2.34.1

[PATCH v1 2/3] drm/amdgpu: select compute ME engines dynamically

2024-07-09 Thread Sunil Khatri

GFX ME right now is one but this could change in
future SOC's. Use no of ME for GFX as start point
for ME for compute for GFX11.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 4f57cf3dac48..dcef39907449 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6456,7 +6456,7 @@ static void gfx_v11_ip_dump(void *handle)
for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
/* ME0 is for GFX so start from 1 for CP */
-   soc21_grbm_select(adev, 1+i, j, k, 0);
+   soc21_grbm_select(adev, adev->gfx.me.num_me + 
i, j, k, 0);
for (reg = 0; reg < reg_count; reg++) {
adev->gfx.ip_dump_compute_queues[index 
+ reg] =
RREG32(SOC15_REG_ENTRY_OFFSET(
-- 
2.34.1

[PATCH v1 0/3] num_me of gfx as start point for ME for compute

2024-07-09 Thread Sunil Khatri

To support future soc's which could have more than one me engine for GFX

Sunil Khatri (3):
  drm/amdgpu: select compute ME engines dynamically
  drm/amdgpu: select compute ME engines dynamically
  drm/amdgpu: select compute ME engines dynamically

 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

-- 
2.34.1

[PATCH v1 1/2] drm:amdgpu: enable IH ring1 for IH v7.0

2024-07-03 Thread Sunil Khatri

We need IH ring1 for handling the pagefault
interrupts which over flow in default
ring for specific usecases.

Enable ring1 allows software to redirect
high interrupts to ring1 from default IH
ring.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
index aa6235dd4f2b..548b3c63a765 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
@@ -546,8 +546,15 @@ static int ih_v7_0_sw_init(void *handle)
adev->irq.ih.use_doorbell = true;
adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 
-   adev->irq.ih1.ring_size = 0;
-   adev->irq.ih2.ring_size = 0;
+   if (!(adev->flags & AMD_IS_APU)) {
+   r = amdgpu_ih_ring_init(adev, >irq.ih1, IH_RING_SIZE,
+   use_bus_addr);
+   if (r)
+   return r;
+
+   adev->irq.ih1.use_doorbell = true;
+   adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 
1;
+   }
 
/* initialize ih control register offset */
ih_v7_0_init_register_offset(adev);
-- 
2.34.1

[PATCH v1 2/2] drm/amdgpu: enable redirection of irq's for IH v7.0

2024-07-03 Thread Sunil Khatri

Enable redirection of irq for pagefaults for specific
clients to avoid overflow without dropping interrupts.

So here we redirect the interrupts to another IH ring
i.e ring1 where only these interrupts are processed.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
index 548b3c63a765..6852081fcff2 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
@@ -346,6 +346,21 @@ static int ih_v7_0_irq_init(struct amdgpu_device *adev)
DELAY, 3);
WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
 
+   /* Redirect the interrupts to IH RB1 for dGPU */
+   if (adev->irq.ih1.ring_size) {
+   tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
+   WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
+
+   tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 
0xa);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 
0x0);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
+   SOURCE_ID_MATCH_ENABLE, 0x1);
+
+   WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
+   }
+
pci_set_master(adev->pdev);
 
/* enable interrupts */
-- 
2.34.1

[PATCH v1 1/4] drm/amdgpu: add gfx12 register support in ipdump

2024-07-03 Thread Sunil Khatri

Add general registers of gfx12 in ipdump for
devcoredump support.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 101 +
 1 file changed, 101 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index ccb26f78252a..c06d0a2a03e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -63,6 +63,73 @@ MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin");
 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin");
 
+static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = {
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
+   SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
+   SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),
+   SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),
+
+   /* cp header registers */
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+   /* SE status registers */
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)
+};
+
 #define DEFAULT_SH_MEM_CONFIG \
((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << 
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -1129,6 +1196,20 @@ static int gfx_v12_0_rlc_backdoor_autoload_enable(struct 
amdgpu_device *adev)
return 0;
 }
 
+static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev)
+{
+   uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
+   uint32_t *ptr;
+
+   ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
+   adev->gfx.ip_dump_core = NULL;
+   } else {
+   adev->gfx.ip_dump_cor

[PATCH v1 2/4] drm/amdgpu: add print support for gfx12 ipdump

2024-07-03 Thread Sunil Khatri

Add support of gfx12 ipdump print so devcoredump
could trigger it to dump the captured registers
in devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index c06d0a2a03e9..19532409aec3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -4758,6 +4758,21 @@ static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
 }
 
+static void gfx_v12_ip_print(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t i;
+   uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
+
+   if (!adev->gfx.ip_dump_core)
+   return;
+
+   for (i = 0; i < reg_count; i++)
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  gc_reg_list_12_0[i].reg_name,
+  adev->gfx.ip_dump_core[i]);
+}
+
 static void gfx_v12_ip_dump(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -4789,6 +4804,7 @@ static const struct amd_ip_funcs gfx_v12_0_ip_funcs = {
.set_powergating_state = gfx_v12_0_set_powergating_state,
.get_clockgating_state = gfx_v12_0_get_clockgating_state,
.dump_ip_state = gfx_v12_ip_dump,
+   .print_ip_state = gfx_v12_ip_print,
 };
 
 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {
-- 
2.34.1

[PATCH v1 3/4] drm/amdgpu: add cp queue registers for gfx12 ipdump

2024-07-03 Thread Sunil Khatri

Add gfx12 support of CP queue registers for all queues
to be used by devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 111 -
 1 file changed, 109 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 19532409aec3..21b8167f39bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -130,6 +130,49 @@ static const struct amdgpu_hwip_reg_entry 
gc_reg_list_12_0[] = {
SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = {
+   /* compute registers */
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
+};
+
 #define DEFAULT_SH_MEM_CONFIG \
((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << 
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -1200,6 +1243,7 @@ static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device 
*adev)
 {
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
uint32_t *ptr;
+   uint32_t inst;
 
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
@@ -1208,6 +1252,19 @@ static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device 
*adev)
} else {
adev->gfx.ip_dump_core = ptr;
}
+
+   /* Allocate memory for compute queue registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
+   inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
+   adev->gfx.mec.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for Compute Queues IP 
Dump\n");
+   adev->gfx.ip_dump_compute_queues = NULL;
+   } else {
+   adev->gfx.ip_dump_compute_queues = ptr;
+   }
 }
 
 static int gfx_v12_0_sw_init(void *handle)
@@ -1404,6 +1461,7 @@ static int gfx_v12_0_sw_fini(void *handle)
gfx_v12_0_free_microcode(adev);
 
kfree(adev->gfx.ip_dump_core);
+   kfree(adev->gfx.ip_dump_compute_queues);
 
return 0;
 }
@@ -4761,7 +4819,7 @@ static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring 
*ring)
 static void gfx_v12_ip_print(void *handle, struct drm_printer *p)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-   uint32_t i;
+   uint32_t i, j, k, reg, index = 0;
uint32_t reg_count = ARRAY_SIZE(gc_reg_lis

[PATCH v1 4/4] drm/amdgpu: add gfx queue support for gfx12 ipdump

2024-07-03 Thread Sunil Khatri

Add support of all the CP GFX queues for gfx12 ipdump
to be used by devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 94 ++
 1 file changed, 94 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 21b8167f39bd..cf7209b93617 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -173,6 +173,35 @@ static const struct amdgpu_hwip_reg_entry 
gc_cp_reg_list_12[] = {
SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
+   /* gfx queue registers */
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
+};
+
 #define DEFAULT_SH_MEM_CONFIG \
((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << 
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -1265,6 +1294,19 @@ static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device 
*adev)
} else {
adev->gfx.ip_dump_compute_queues = ptr;
}
+
+   /* Allocate memory for gfx queue registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
+   inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
+   adev->gfx.me.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
+   adev->gfx.ip_dump_gfx_queues = NULL;
+   } else {
+   adev->gfx.ip_dump_gfx_queues = ptr;
+   }
 }
 
 static int gfx_v12_0_sw_init(void *handle)
@@ -1462,6 +1504,7 @@ static int gfx_v12_0_sw_fini(void *handle)
 
kfree(adev->gfx.ip_dump_core);
kfree(adev->gfx.ip_dump_compute_queues);
+   kfree(adev->gfx.ip_dump_gfx_queues);
 
return 0;
 }
@@ -4853,6 +4896,31 @@ static void gfx_v12_ip_print(void *handle, struct 
drm_printer *p)
}
}
}
+
+   /* print gfx queue registers for all instances */
+   if (!adev->gfx.ip_dump_gfx_queues)
+   return;
+
+   index = 0;
+   reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
+   drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
+  adev->gfx.me.num_me,
+  adev->gfx.me.num_pipe_per_me,
+  adev->gfx.me.num_queue_per_pipe);
+
+   for (i = 0; i < adev->gfx.me.num_me; i++) {
+   for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+   for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
+   drm_printf(p, "\nme %d, pipe %d, queue %d\n", 
i, j, k);
+   for (reg = 0; reg < reg_count; reg++) {
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  
gc_gfx_queue_reg_list_12[reg].reg_name,
+  
adev->gfx.ip_dump_gfx_queues[index + reg]);
+   }
+   index += reg_count;
+   }
+   }
+   }
 }
 
 static void gfx_v12_ip_dump(void *handle)
@@ -4893,6 +4961,32 @@ static void gfx_v12_ip_dump(void *handle)
soc24_grbm_select(adev, 0

[PATCH v1 0/4] GFX12 ipdump of gfx IP

2024-07-03 Thread Sunil Khatri

Validated on navi48

Sunil Khatri (4):
  drm/amdgpu: add gfx12 register support in ipdump
  drm/amdgpu: add print support for gfx12 ipdump
  drm/amdgpu: add cp queue registers for gfx12 ipdump
  drm/amdgpu: add gfx queue support for gfx12 ipdump

 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 316 +
 1 file changed, 316 insertions(+)

-- 
2.34.1

[PATCH v1 1/2] drm/amdgpu: fix out of bounds access in gfx10 during ip dump

2024-07-02 Thread Sunil Khatri

During ip dump in gfx10 the index variable is reused but is
not reinitialized to 0 and this causes the index calculation
to be wrong and access out of bound access.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 18488c02d1cf..a52c72739b40 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9287,6 +9287,7 @@ static void gfx_v10_ip_print(void *handle, struct 
drm_printer *p)
if (!adev->gfx.ip_dump_gfx_queues)
return;
 
+   index = 0;
reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
   adev->gfx.me.num_me,
@@ -9352,6 +9353,7 @@ static void gfx_v10_ip_dump(void *handle)
if (!adev->gfx.ip_dump_gfx_queues)
return;
 
+   index = 0;
reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(>srbm_mutex);
-- 
2.34.1

[PATCH v1 2/2] drm/amdgpu: fix out of bounds access in gfx11 during ip dump

2024-07-02 Thread Sunil Khatri

During ip dump in gfx11 the index variable is reused but is
not reinitialized to 0 and this causes the index calculation
to be wrong and access out of bound access.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 0d078d0db162..b49e4e85bddf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6401,6 +6401,7 @@ static void gfx_v11_ip_print(void *handle, struct 
drm_printer *p)
if (!adev->gfx.ip_dump_gfx_queues)
return;
 
+   index = 0;
reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);
drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
   adev->gfx.me.num_me,
@@ -6465,6 +6466,7 @@ static void gfx_v11_ip_dump(void *handle)
if (!adev->gfx.ip_dump_gfx_queues)
return;
 
+   index = 0;
reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);
amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(>srbm_mutex);
-- 
2.34.1

[PATCH v2 3/3] drm/amdgpu: add cp queue registers for gfx9 ipdump

2024-05-30 Thread Sunil Khatri

Add gfx9 support of CP queue registers for all queues
to be used by devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 110 +-
 1 file changed, 108 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3df2bca80fd9..59d8f6c4ba25 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -237,6 +237,47 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] 
= {
SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
+   /* compute queue registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ACTIVE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),
+};
+
 enum ta_ras_gfx_subblock {
/*CPC*/
TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
@@ -2086,6 +2127,7 @@ static void gfx_v9_0_alloc_ip_dump(struct amdgpu_device 
*adev)
 {
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);
uint32_t *ptr;
+   uint32_t inst;
 
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
@@ -2094,6 +2136,19 @@ static void gfx_v9_0_alloc_ip_dump(struct amdgpu_device 
*adev)
} else {
adev->gfx.ip_dump_core = ptr;
}
+
+   /* Allocate memory for compute queue registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_cp_reg_list_9);
+   inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
+   adev->gfx.mec.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ip_dump_cp_queues = NULL;
+   } else {
+   adev->gfx.ip_dump_cp_queues = ptr;
+   }
 }
 
 static int gfx_v9_0_sw_init(void *handle)
@@ -2311,6 +2366,7 @@ static int gfx_v9_0_sw_fini(void *handle)
gfx_v9_0_free_microcode(adev);
 
kfree(adev->gfx.ip_dump_core);
+   kfree(adev->gfx.ip_dump_cp_queues);
 
return 0;
 }
@@ -6949,7 +7005,7 @@ static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring 
*ring, bool enable)
 static void gfx_v9_ip_print(void *handle, struct drm_printer *p)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-   uint32_t i;
+   uint32_t i, j, k, reg, index = 0;
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);
 
if (!adev->gfx.ip_dump_core)
@@ -6960,12 +7016,36 @@ static void gfx_v9_ip_print(void *handle, struct 
drm_printer *p)
   gc_reg_list_9[i].reg_name,
   adev->gfx.ip_dump_core[i]);
 
+   /* print compute queue registers for all instances */
+   if (!adev->gf

[PATCH v2 2/3] drm/amdgpu: add print support for gfx9 ipdump

2024-05-30 Thread Sunil Khatri

Add support of gfx9 ipdump print so devcoredump
could trigger it to dump the captured registers
in devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 8e67265ccaf7..3df2bca80fd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -6946,6 +6946,22 @@ static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring 
*ring, bool enable)
}
 }
 
+static void gfx_v9_ip_print(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t i;
+   uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);
+
+   if (!adev->gfx.ip_dump_core)
+   return;
+
+   for (i = 0; i < reg_count; i++)
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  gc_reg_list_9[i].reg_name,
+  adev->gfx.ip_dump_core[i]);
+
+}
+
 static void gfx_v9_ip_dump(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -6979,7 +6995,7 @@ static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
.set_powergating_state = gfx_v9_0_set_powergating_state,
.get_clockgating_state = gfx_v9_0_get_clockgating_state,
.dump_ip_state = gfx_v9_ip_dump,
-   .print_ip_state = NULL,
+   .print_ip_state = gfx_v9_ip_print,
 };
 
 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
-- 
2.34.1

[PATCH v2 1/3] drm/amdgpu: add gfx9 register support in ipdump

2024-05-30 Thread Sunil Khatri

Add general registers of gfx9 in ipdump for
devcoredump support.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 124 +-
 1 file changed, 123 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3c8c5abf35ab..8e67265ccaf7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -149,6 +149,94 @@ MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin");
 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir0x0026
 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX   1
 
+static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = {
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSQ_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
+   /* cp header registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_H

[PATCH v1 1/3] drm/amdgpu: add gfx9 register support in ipdump

2024-05-29 Thread Sunil Khatri

Add general registers of gfx9 in ipdump for
devcoredump support.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 124 +-
 1 file changed, 123 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3c8c5abf35ab..528a20393313 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -149,6 +149,94 @@ MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin");
 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir0x0026
 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX   1
 
+static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = {
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSQ_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
+   /* cp header registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_H

[PATCH v1 2/3] drm/amdgpu: add print support for gfx9 ipdump

2024-05-29 Thread Sunil Khatri

Add support of gfx9 ipdump print so devcoredump
could trigger it to dump the captured registers
in devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 528a20393313..f3d281de2a34 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -6946,6 +6946,22 @@ static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring 
*ring, bool enable)
}
 }
 
+static void gfx_v9_ip_print(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t i;
+   uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);
+
+   if (!adev->gfx.ip_dump_core)
+   return;
+
+   for (i = 0; i < reg_count; i++)
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  gc_reg_list_9[i].reg_name,
+  adev->gfx.ip_dump_core[i]);
+
+}
+
 static void gfx_v9_ip_dump(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -6979,7 +6995,7 @@ static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
.set_powergating_state = gfx_v9_0_set_powergating_state,
.get_clockgating_state = gfx_v9_0_get_clockgating_state,
.dump_ip_state = gfx_v9_ip_dump,
-   .print_ip_state = NULL,
+   .print_ip_state = gfx_v9_ip_print,
 };
 
 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
-- 
2.34.1

[PATCH v1 3/3] drm/amdgpu: add cp queue registers for gfx9 ipdump

2024-05-29 Thread Sunil Khatri

Add gfx9 support of CP queue registers for all queues
to be used by devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 110 +-
 1 file changed, 108 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index f3d281de2a34..f1a7b60e73ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -237,6 +237,47 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] 
= {
SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {
+   /* compute queue registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ACTIVE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),
+};
+
 enum ta_ras_gfx_subblock {
/*CPC*/
TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
@@ -2086,6 +2127,7 @@ static void gfx_v9_0_alloc_ip_dump(struct amdgpu_device 
*adev)
 {
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);
uint32_t *ptr;
+   uint32_t inst;
 
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
@@ -2094,6 +2136,19 @@ static void gfx_v9_0_alloc_ip_dump(struct amdgpu_device 
*adev)
} else {
adev->gfx.ip_dump_core = ptr;
}
+
+   /* Allocate memory for compute queue registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_cp_reg_list_9);
+   inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
+   adev->gfx.mec.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ip_dump_cp_queues = NULL;
+   } else {
+   adev->gfx.ip_dump_cp_queues = ptr;
+   }
 }
 
 static int gfx_v9_0_sw_init(void *handle)
@@ -2311,6 +2366,7 @@ static int gfx_v9_0_sw_fini(void *handle)
gfx_v9_0_free_microcode(adev);
 
kfree(adev->gfx.ip_dump_core);
+   kfree(adev->gfx.ip_dump_cp_queues);
 
return 0;
 }
@@ -6949,7 +7005,7 @@ static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring 
*ring, bool enable)
 static void gfx_v9_ip_print(void *handle, struct drm_printer *p)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-   uint32_t i;
+   uint32_t i, j, k, reg, index = 0;
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);
 
if (!adev->gfx.ip_dump_core)
@@ -6960,12 +7016,36 @@ static void gfx_v9_ip_print(void *handle, struct 
drm_printer *p)
   gc_reg_list_9[i].reg_name,
   adev->gfx.ip_dump_core[i]);
 
+   /* print compute queue registers for all instances */
+   if (!adev->gf

[PATCH v1 0/3] gfx9 ipdump patches

2024-05-29 Thread Sunil Khatri

gfx9 ipdump patches 

Sunil Khatri (3):
  drm/amdgpu: add gfx9 register support in ipdump
  drm/amdgpu: add print support for gfx9 ipdump
  drm/amdgpu: add cp queue registers for gfx9 ipdump

 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 248 +-
 1 file changed, 246 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH v1 00/10] ipdump support for gfx10 and gfx11

2024-05-22 Thread Sunil Khatri

With this support for gfx10 and gfx11 ipdump is complete.
Also added dev_info needed fields for devcoredump.

Sunil Khatri (10):
  drm/amdgpu: rename the ip_dump to ip_dump_core
  drm/amdgpu: Add cp queues support fro gfx10 in ipdump
  drm/amdgpu: add gfx queue support of gfx10 in ipdump
  drm/amdgpu: add prints while ip register dump
  drm/amdgpu: add more device info to the devcoredump
  drm/amdgpu: Add missing offsets in gc_11_0_0_offset.h
  drm/amdgpu: add gfx11 registers support in ipdump
  drm/amdgpu: add print support for gfx11 ipdump
  drm/amdgpu: add cp queue registers for gfx11 ipdump
  drm/amdgpu: add gfx queue support for gfx11 ipdump

 .../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c  |  21 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h   |   4 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 220 +++-
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 323 +-
 .../include/asic_reg/gc/gc_11_0_0_offset.h|  10 +
 6 files changed, 564 insertions(+), 16 deletions(-)

-- 
2.34.1

[PATCH v1 10/10] drm/amdgpu: add gfx queue support for gfx11 ipdump

2024-05-22 Thread Sunil Khatri

Add support of all the CP GFX queues for gfx11 ipdump
to be used by devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 92 ++
 1 file changed, 92 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index fbdb928bb790..aba0a51be960 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -209,6 +209,35 @@ static const struct amdgpu_hwip_reg_entry 
gc_cp_reg_list_11[] = {
SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = {
+   /* gfx queue registers */
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x2000, 0x2000)
 };
@@ -1472,6 +1501,19 @@ static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device 
*adev)
} else {
adev->gfx.ip_dump_cp_queues = ptr;
}
+
+   /* Allocate memory for gfx queue registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);
+   inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
+   adev->gfx.me.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ip_dump_gfx_queues = NULL;
+   } else {
+   adev->gfx.ip_dump_gfx_queues = ptr;
+   }
 }
 
 static int gfx_v11_0_sw_init(void *handle)
@@ -1691,6 +1733,7 @@ static int gfx_v11_0_sw_fini(void *handle)
 
kfree(adev->gfx.ip_dump_core);
kfree(adev->gfx.ip_dump_cp_queues);
+   kfree(adev->gfx.ip_dump_gfx_queues);
 
return 0;
 }
@@ -6343,6 +6386,30 @@ static void gfx_v11_ip_print(void *handle, struct 
drm_printer *p)
}
}
}
+
+   /* print gfx queue registers for all instances */
+   if (!adev->gfx.ip_dump_gfx_queues)
+   return;
+
+   reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);
+   drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
+  adev->gfx.me.num_me,
+  adev->gfx.me.num_pipe_per_me,
+  adev->gfx.me.num_queue_per_pipe);
+
+   for (i = 0; i < adev->gfx.me.num_me; i++) {
+   for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+   for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
+   drm_printf(p, "\nme %d, pipe %d, queue %d\n", 
i, j, k);
+   for (reg = 0; reg < reg_count; reg++) {
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  
gc_gfx_queue_reg_list_11[reg].reg_name,
+  
adev->gfx.ip_dump_gfx_queues[index + reg]);
+   }
+   index += reg_count;
+   }
+   }
+   }
 }
 
 static void gfx_v11_ip_dump(void *handle)
@@ -6383,6 +6450,31 @@ static void gfx_v11_ip_dump(void *handle)
soc21_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
amdgpu_gfx_off_ctrl(adev, t

[PATCH v1 01/10] drm/amdgpu: rename the ip_dump to ip_dump_core

2024-05-22 Thread Sunil Khatri

Rename the memory pointer from ip_dump to ip_dump_core
to make it specific to core registers and rest other
registers to be dumped in their respective memories.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 14 +++---
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 109f471ff315..a28462643b00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -435,7 +435,7 @@ struct amdgpu_gfx {
boolmcbp; /* mid command buffer preemption 
*/
 
/* IP reg dump */
-   uint32_t*ip_dump;
+   uint32_t*ip_dump_core;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 1f516466ac13..73149150fe2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4603,9 +4603,9 @@ static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device 
*adev)
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
DRM_ERROR("Failed to allocate memory for IP Dump\n");
-   adev->gfx.ip_dump = NULL;
+   adev->gfx.ip_dump_core = NULL;
} else {
-   adev->gfx.ip_dump = ptr;
+   adev->gfx.ip_dump_core = ptr;
}
 }
 
@@ -4815,7 +4815,7 @@ static int gfx_v10_0_sw_fini(void *handle)
 
gfx_v10_0_free_microcode(adev);
 
-   kfree(adev->gfx.ip_dump);
+   kfree(adev->gfx.ip_dump_core);
 
return 0;
 }
@@ -9292,13 +9292,13 @@ static void gfx_v10_ip_print(void *handle, struct 
drm_printer *p)
uint32_t i;
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
 
-   if (!adev->gfx.ip_dump)
+   if (!adev->gfx.ip_dump_core)
return;
 
for (i = 0; i < reg_count; i++)
drm_printf(p, "%-50s \t 0x%08x\n",
   gc_reg_list_10_1[i].reg_name,
-  adev->gfx.ip_dump[i]);
+  adev->gfx.ip_dump_core[i]);
 }
 
 static void gfx_v10_ip_dump(void *handle)
@@ -9307,12 +9307,12 @@ static void gfx_v10_ip_dump(void *handle)
uint32_t i;
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
 
-   if (!adev->gfx.ip_dump)
+   if (!adev->gfx.ip_dump_core)
return;
 
amdgpu_gfx_off_ctrl(adev, false);
for (i = 0; i < reg_count; i++)
-   adev->gfx.ip_dump[i] = 
RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
+   adev->gfx.ip_dump_core[i] = 
RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
amdgpu_gfx_off_ctrl(adev, true);
 }
 
-- 
2.34.1

[PATCH v1 05/10] drm/amdgpu: add more device info to the devcoredump

2024-05-22 Thread Sunil Khatri

Adding more device information:
a. PCI info
b. VRAM and GTT info
c. GDC config

Also correct the print layout and section information for
in devcoredump.

Signed-off-by: Sunil Khatri 
---
 .../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c  | 21 +--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
index c1cb62683695..f0a44d0dec27 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
@@ -224,12 +224,29 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, 
size_t count,
   coredump->reset_task_info.process_name,
   coredump->reset_task_info.pid);
 
-   /* GPU IP's information of the SOC */
-   drm_printf(, "\nIP Information\n");
+   /* SOC Information */
+   drm_printf(, "\nSOC Information\n");
+   drm_printf(, "SOC Device id: %d\n", coredump->adev->pdev->device);
+   drm_printf(, "SOC PCI Revision id: %d\n", 
coredump->adev->pdev->revision);
drm_printf(, "SOC Family: %d\n", coredump->adev->family);
drm_printf(, "SOC Revision id: %d\n", coredump->adev->rev_id);
drm_printf(, "SOC External Revision id: %d\n", 
coredump->adev->external_rev_id);
 
+   /* Memory Information */
+   drm_printf(, "\nSOC Memory Information\n");
+   drm_printf(, "real vram size: %llu\n", 
coredump->adev->gmc.real_vram_size);
+   drm_printf(, "visible vram size: %llu\n", 
coredump->adev->gmc.visible_vram_size);
+   drm_printf(, "visible vram size: %llu\n", 
coredump->adev->mman.gtt_mgr.manager.size);
+
+   /* GDS Config */
+   drm_printf(, "\nGDS Config\n");
+   drm_printf(, "gds: total size: %d\n", coredump->adev->gds.gds_size);
+   drm_printf(, "gds: compute partition size: %d\n", 
coredump->adev->gds.gds_size);
+   drm_printf(, "gds: gws per compute partition: %d\n", 
coredump->adev->gds.gws_size);
+   drm_printf(, "gds: os per compute partition: %d\n", 
coredump->adev->gds.oa_size);
+
+   /* HWIP Version Information */
+   drm_printf(, "\nHW IP Version Information\n");
for (int i = 1; i < MAX_HWIP; i++) {
for (int j = 0; j < HWIP_MAX_INSTANCE; j++) {
ver = coredump->adev->ip_versions[i][j];
-- 
2.34.1

[PATCH v1 09/10] drm/amdgpu: add cp queue registers for gfx11 ipdump

2024-05-22 Thread Sunil Khatri

Add gfx11 support of CP queue registers for all queues
to be used by devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 111 -
 1 file changed, 109 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 747e837b29b6..fbdb928bb790 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -166,6 +166,49 @@ static const struct amdgpu_hwip_reg_entry 
gc_reg_list_11_0[] = {
SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = {
+   /* compute registers */
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x2000, 0x2000)
 };
@@ -1407,6 +1450,7 @@ static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device 
*adev)
 {
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);
uint32_t *ptr;
+   uint32_t inst;
 
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
@@ -1415,6 +1459,19 @@ static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device 
*adev)
} else {
adev->gfx.ip_dump_core = ptr;
}
+
+   /* Allocate memory for compute queue registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_cp_reg_list_11);
+   inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
+   adev->gfx.mec.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ip_dump_cp_queues = NULL;
+   } else {
+   adev->gfx.ip_dump_cp_queues = ptr;
+   }
 }
 
 static int gfx_v11_0_sw_init(void *handle)
@@ -1633,6 +1690,7 @@ static int gfx_v11_0_sw_fini(void *handle)
gfx_v11_0_free_microcode(adev);
 
kfree(adev->gfx.ip_dump_core);
+   kfree(adev->gfx.ip_dump_cp_queues);
 
return 0;
 }
@@ -6251,7 +6309,7 @@ static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring 
*ring)
 static void gfx_v11_ip_print(void *handle, struct drm_printer *p)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-   uint32_t i;
+   uint32_t i, j, k, reg, index = 0;
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);
 
if (!adev->gfx.ip_dump_core)
@@ -6261,12 +6319,36 @@ static void

[PATCH v1 04/10] drm/amdgpu: add prints while ip register dump

2024-05-22 Thread Sunil Khatri

add prints before and after ip registers are
dump. It avoids user to think of system being
stuck/hung as register dump takes time after a
gpu hang.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e72e774d17e6..844dbb3d43c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5373,11 +5373,13 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
if (!test_bit(AMDGPU_SKIP_COREDUMP, _context->flags)) {
amdgpu_reset_reg_dumps(tmp_adev);
 
+   dev_info(tmp_adev->dev, "Dumping IP Registers\n");
/* Trigger ip dump before we reset the asic */
for (i = 0; i < tmp_adev->num_ip_blocks; i++)
if 
(tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
tmp_adev->ip_blocks[i].version->funcs
->dump_ip_state((void *)tmp_adev);
+   dev_info(tmp_adev->dev, "Dumping IP Registers Completed\n");
}
 
reset_context->reset_device_list = device_list_handle;
-- 
2.34.1

[PATCH v1 07/10] drm/amdgpu: add gfx11 registers support in ipdump

2024-05-22 Thread Sunil Khatri

Add general registers of gfx11 in ipdump for
devcoredump support.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 107 -
 1 file changed, 106 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index e5882da8332a..6046e3b1b626 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -94,6 +94,78 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin");
 
+static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = {
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),
+   SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),
+   SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
+   SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
+   SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
+   /* cp header registers */
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
+   /* SE status registers */
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4),
+   SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x2000, 0x2000)
 };
@@ -1331,6 +1403,20 @@ static int gfx_v11_0_rlc_backdoor_autoload_enable(struct 
amdgpu_device *adev)
return 0;
 }
 
+static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev)
+{
+   uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);
+   uint32_t *ptr;
+
+   ptr = kcal

[PATCH v1 06/10] drm/amdgpu: Add missing offsets in gc_11_0_0_offset.h

2024-05-22 Thread Sunil Khatri

IB1 registers:
regCP_IB1_CMD_BUFSZ
regCP_IB1_BASE_LO
regCP_IB1_BASE_HI
regCP_IB1_BUFSZ
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR

Above registers are part of the asic but not of
the offset file for gc_11_0_0_offset.h and hence
adding them.

Signed-off-by: Sunil Khatri 
---
 .../gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
index 4bff1ef8a9a6..a3bcdf632066 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
@@ -7085,10 +7085,18 @@
 #define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX 
 1
 #define regCP_GE_MSINVOC_COUNT_HI  
 0x20a7
 #define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX 
 1
+#define regCP_IB1_CMD_BUFSZ
 0x20c0
+#define regCP_IB1_CMD_BUFSZ_BASE_IDX   
 1
 #define regCP_IB2_CMD_BUFSZ
 0x20c1
 #define regCP_IB2_CMD_BUFSZ_BASE_IDX   
 1
 #define regCP_ST_CMD_BUFSZ 
 0x20c2
 #define regCP_ST_CMD_BUFSZ_BASE_IDX
 1
+#define regCP_IB1_BASE_LO  
 0x20cc
+#define regCP_IB1_BASE_LO_BASE_IDX 
 1
+#define regCP_IB1_BASE_HI  
 0x20cd
+#define regCP_IB1_BASE_HI_BASE_IDX 
 1
+#define regCP_IB1_BUFSZ
 0x20ce
+#define regCP_IB1_BUFSZ_BASE_IDX   
 1
 #define regCP_IB2_BASE_LO  
 0x20cf
 #define regCP_IB2_BASE_LO_BASE_IDX 
 1
 #define regCP_IB2_BASE_HI  
 0x20d0
@@ -7541,6 +7549,8 @@
 #define regCP_MES_DOORBELL_CONTROL5_BASE_IDX   
 1
 #define regCP_MES_DOORBELL_CONTROL6
 0x2841
 #define regCP_MES_DOORBELL_CONTROL6_BASE_IDX   
 1
+#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR   
 0x2842
+#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX  
 1
 #define regCP_MES_GP0_LO   
 0x2843
 #define regCP_MES_GP0_LO_BASE_IDX  
 1
 #define regCP_MES_GP0_HI   
 0x2844
-- 
2.34.1

[PATCH v1 08/10] drm/amdgpu: add print support for gfx11 ipdump

2024-05-22 Thread Sunil Khatri

Add support of gfx11 ipdump print so devcoredump
could trigger it to dump the captured registers
in devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 6046e3b1b626..747e837b29b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6248,6 +6248,21 @@ static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
 }
 
+static void gfx_v11_ip_print(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t i;
+   uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);
+
+   if (!adev->gfx.ip_dump_core)
+   return;
+
+   for (i = 0; i < reg_count; i++)
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  gc_reg_list_11_0[i].reg_name,
+  adev->gfx.ip_dump_core[i]);
+}
+
 static void gfx_v11_ip_dump(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -6282,7 +6297,7 @@ static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
.set_powergating_state = gfx_v11_0_set_powergating_state,
.get_clockgating_state = gfx_v11_0_get_clockgating_state,
.dump_ip_state = gfx_v11_ip_dump,
-   .print_ip_state = NULL,
+   .print_ip_state = gfx_v11_ip_print,
 };
 
 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
-- 
2.34.1

[PATCH v1 02/10] drm/amdgpu: Add cp queues support fro gfx10 in ipdump

2024-05-22 Thread Sunil Khatri

Add support to dump registers of all instances of
cp queue registers of gfx10 to devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |   1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 116 +++-
 2 files changed, 113 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index a28462643b00..77ab5d0fd592 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -436,6 +436,7 @@ struct amdgpu_gfx {
 
/* IP reg dump */
uint32_t*ip_dump_core;
+   uint32_t*ip_dump_cp_queues;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 73149150fe2e..ab378d9a74c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -381,6 +381,49 @@ static const struct amdgpu_hwip_reg_entry 
gc_reg_list_10_1[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
+   /* compute registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x, 
0x00400014),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 
0xf8000100),
@@ -4595,10 +4638,11 @@ static int gfx_v10_0_compute_ring_init(struct 
amdgpu_device *adev, int ring_id,
 hw_prio, NULL);
 }
 
-static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev)
+static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
 {
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
uint32_t *ptr;
+   uint32_t inst;
 
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
@@ -4607,6 +4651,19 @@ static void gfx_v10_0_alloc_dump_mem(struct 
amdgpu_device *adev)
} else {
adev->gfx.ip_dump_core = ptr;
}
+
+   /* Allocate memory for compute queue registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
+   inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
+   adev->gfx.mec.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ip_dump_cp_queues = NULL;
+   } el

[PATCH v1 03/10] drm/amdgpu: add gfx queue support of gfx10 in ipdump

2024-05-22 Thread Sunil Khatri

Add gfx queue register for all instances in devcoredump
for gfx10.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 90 +
 2 files changed, 91 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 77ab5d0fd592..a9d9f372a7c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -437,6 +437,7 @@ struct amdgpu_gfx {
/* IP reg dump */
uint32_t*ip_dump_core;
uint32_t*ip_dump_cp_queues;
+   uint32_t*ip_dump_gfx_queues;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ab378d9a74c8..a4bbbf6d5d1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -424,6 +424,33 @@ static const struct amdgpu_hwip_reg_entry 
gc_cp_reg_list_10[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
+   /* gfx queue registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x, 
0x00400014),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 
0xf8000100),
@@ -4664,6 +4691,19 @@ static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device 
*adev)
} else {
adev->gfx.ip_dump_cp_queues = ptr;
}
+
+   /* Allocate memory for gfx queue registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
+   inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
+   adev->gfx.me.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ip_dump_gfx_queues = NULL;
+   } else {
+   adev->gfx.ip_dump_gfx_queues = ptr;
+   }
 }
 
 static int gfx_v10_0_sw_init(void *handle)
@@ -4874,6 +4914,7 @@ static int gfx_v10_0_sw_fini(void *handle)
 
kfree(adev->gfx.ip_dump_core);
kfree(adev->gfx.ip_dump_cp_queues);
+   kfree(adev->gfx.ip_dump_gfx_queues);
 
return 0;
 }
@@ -9381,6 +9422,30 @@ static void gfx_v10_ip_print(void *handle, struct 
drm_printer *p)
}
}
}
+
+   /* print gfx queue registers for all instances */
+   if (!adev->gfx.ip_dump_gfx_queues)
+   return;
+
+   reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
+   drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
+  adev->gfx.me.num_me,
+  adev->gfx.me.num_pipe_per_me,
+  adev->gfx.me.num_queue_per_pipe);
+
+   for (i = 0; i < adev->gfx.me.num_me; i++) {
+   for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+   for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
+   drm_printf(p, "\nme %d, pipe %d, queue %d\n", 
i, j, k);
+   for (reg = 0; reg < reg_count; reg++) {
+   drm_printf(p, "%-50s \t 0x%08x

[PATCH v3 2/4] drm/amdgpu: Add support to dump gfx10 cp registers

2024-05-15 Thread Sunil Khatri

add support to dump registers of all instances of
cp registers in gfx10

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |   1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 117 +++-
 2 files changed, 114 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 30d7f9c29478..d96873c154ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -436,6 +436,7 @@ struct amdgpu_gfx {
 
/* IP reg dump */
uint32_t*ipdump_core;
+   uint32_t*ipdump_cp;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f6d6a4b9802d..daf9a3571183 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -381,6 +381,49 @@ static const struct amdgpu_hwip_reg_entry 
gc_reg_list_10_1[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
+   /* compute registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x, 
0x00400014),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 
0xf8000100),
@@ -4595,10 +4638,11 @@ static int gfx_v10_0_compute_ring_init(struct 
amdgpu_device *adev, int ring_id,
 hw_prio, NULL);
 }
 
-static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev)
+static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
 {
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
uint32_t *ptr;
+   uint32_t inst;
 
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
@@ -4607,6 +4651,19 @@ static void gfx_v10_0_alloc_dump_mem(struct 
amdgpu_device *adev)
} else {
adev->gfx.ipdump_core = ptr;
}
+
+   /* Allocate memory for gfx cp registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
+   inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
+   adev->gfx.mec.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ipdump_cp = NULL;
+   } else {
+   adev->gfx.ipdump_cp =

[PATCH v3 4/4] drm/amdgpu: add prints while ip registr dump

2024-05-15 Thread Sunil Khatri

add prints before and after during ip registers
dump. It avoids user to think of system being
stuck/hung as register dump takes time after a
gpu hang.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e72e774d17e6..844dbb3d43c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5373,11 +5373,13 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
if (!test_bit(AMDGPU_SKIP_COREDUMP, _context->flags)) {
amdgpu_reset_reg_dumps(tmp_adev);
 
+   dev_info(tmp_adev->dev, "Dumping IP Registers\n");
/* Trigger ip dump before we reset the asic */
for (i = 0; i < tmp_adev->num_ip_blocks; i++)
if 
(tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
tmp_adev->ip_blocks[i].version->funcs
->dump_ip_state((void *)tmp_adev);
+   dev_info(tmp_adev->dev, "Dumping IP Registers Completed\n");
}
 
reset_context->reset_device_list = device_list_handle;
-- 
2.34.1

[PATCH v3 3/4] drm/amdgpu: add support to dump gfx10 queue registers

2024-05-15 Thread Sunil Khatri

Add gfx queue register for all instances in ip dump
for gfx10.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 86 +
 2 files changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index d96873c154ed..54232066cd3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -437,6 +437,7 @@ struct amdgpu_gfx {
/* IP reg dump */
uint32_t*ipdump_core;
uint32_t*ipdump_cp;
+   uint32_t*ipdump_gfx_queue;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index daf9a3571183..5b8132ecc039 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -424,6 +424,33 @@ static const struct amdgpu_hwip_reg_entry 
gc_cp_reg_list_10[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
+   /* gfx queue registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x, 
0x00400014),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 
0xf8000100),
@@ -4664,6 +4691,19 @@ static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device 
*adev)
} else {
adev->gfx.ipdump_cp = ptr;
}
+
+   /* Allocate memory for gfx cp queue registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
+   inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
+   adev->gfx.me.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ipdump_gfx_queue = NULL;
+   } else {
+   adev->gfx.ipdump_gfx_queue = ptr;
+   }
 }
 
 static int gfx_v10_0_sw_init(void *handle)
@@ -4874,6 +4914,7 @@ static int gfx_v10_0_sw_fini(void *handle)
 
kfree(adev->gfx.ipdump_core);
kfree(adev->gfx.ipdump_cp);
+   kfree(adev->gfx.ipdump_gfx_queue);
 
return 0;
 }
@@ -9368,6 +9409,26 @@ static void gfx_v10_ip_print(void *handle, struct 
drm_printer *p)
}
}
}
+
+   /* print gfx queue registers for all instances */
+   if (!adev->gfx.ipdump_gfx_queue)
+   return;
+
+   reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
+
+   for (i = 0; i < adev->gfx.me.num_me; i++) {
+   for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+   for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
+   drm_printf(p, "me %d, pipe %d, queue %d\n", i, 
j, k);
+   for (reg = 0; reg < reg_count; reg++) {
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  
gc_gfx_queue_reg_list_10[reg].reg_name,
+  
adev->gfx.ipdump_gfx_queue[index + reg]);
+   }
+   index += reg_count;
+

[PATCH v3 1/4] drm/amdgpu: update the ip_dump to ipdump_core

2024-05-15 Thread Sunil Khatri

Update the memory pointer from ip_dump to ipdump_core
to make it specific to core registers and rest other
registers to be dumped in their respective memories.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 14 +++---
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 109f471ff315..30d7f9c29478 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -435,7 +435,7 @@ struct amdgpu_gfx {
boolmcbp; /* mid command buffer preemption 
*/
 
/* IP reg dump */
-   uint32_t*ip_dump;
+   uint32_t*ipdump_core;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 953df202953a..f6d6a4b9802d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4603,9 +4603,9 @@ static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device 
*adev)
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
DRM_ERROR("Failed to allocate memory for IP Dump\n");
-   adev->gfx.ip_dump = NULL;
+   adev->gfx.ipdump_core = NULL;
} else {
-   adev->gfx.ip_dump = ptr;
+   adev->gfx.ipdump_core = ptr;
}
 }
 
@@ -4815,7 +4815,7 @@ static int gfx_v10_0_sw_fini(void *handle)
 
gfx_v10_0_free_microcode(adev);
 
-   kfree(adev->gfx.ip_dump);
+   kfree(adev->gfx.ipdump_core);
 
return 0;
 }
@@ -9283,13 +9283,13 @@ static void gfx_v10_ip_print(void *handle, struct 
drm_printer *p)
uint32_t i;
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
 
-   if (!adev->gfx.ip_dump)
+   if (!adev->gfx.ipdump_core)
return;
 
for (i = 0; i < reg_count; i++)
drm_printf(p, "%-50s \t 0x%08x\n",
   gc_reg_list_10_1[i].reg_name,
-  adev->gfx.ip_dump[i]);
+  adev->gfx.ipdump_core[i]);
 }
 
 static void gfx_v10_ip_dump(void *handle)
@@ -9298,12 +9298,12 @@ static void gfx_v10_ip_dump(void *handle)
uint32_t i;
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
 
-   if (!adev->gfx.ip_dump)
+   if (!adev->gfx.ipdump_core)
return;
 
amdgpu_gfx_off_ctrl(adev, false);
for (i = 0; i < reg_count; i++)
-   adev->gfx.ip_dump[i] = 
RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
+   adev->gfx.ipdump_core[i] = 
RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
amdgpu_gfx_off_ctrl(adev, true);
 }
 
-- 
2.34.1

[PATCH] drm/amdgpu: add more device info to the devcoredump

2024-05-14 Thread Sunil Khatri

Adding more device information:
a. PCI info
b. VRAM and GTT info
c. GDC config

Also correct the print layout and section information for
in devcoredump.

Signed-off-by: Sunil Khatri 
---
 .../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c  | 21 +--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
index c1cb62683695..f0a44d0dec27 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
@@ -224,12 +224,29 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, 
size_t count,
   coredump->reset_task_info.process_name,
   coredump->reset_task_info.pid);
 
-   /* GPU IP's information of the SOC */
-   drm_printf(, "\nIP Information\n");
+   /* SOC Information */
+   drm_printf(, "\nSOC Information\n");
+   drm_printf(, "SOC Device id: %d\n", coredump->adev->pdev->device);
+   drm_printf(, "SOC PCI Revision id: %d\n", 
coredump->adev->pdev->revision);
drm_printf(, "SOC Family: %d\n", coredump->adev->family);
drm_printf(, "SOC Revision id: %d\n", coredump->adev->rev_id);
drm_printf(, "SOC External Revision id: %d\n", 
coredump->adev->external_rev_id);
 
+   /* Memory Information */
+   drm_printf(, "\nSOC Memory Information\n");
+   drm_printf(, "real vram size: %llu\n", 
coredump->adev->gmc.real_vram_size);
+   drm_printf(, "visible vram size: %llu\n", 
coredump->adev->gmc.visible_vram_size);
+   drm_printf(, "visible vram size: %llu\n", 
coredump->adev->mman.gtt_mgr.manager.size);
+
+   /* GDS Config */
+   drm_printf(, "\nGDS Config\n");
+   drm_printf(, "gds: total size: %d\n", coredump->adev->gds.gds_size);
+   drm_printf(, "gds: compute partition size: %d\n", 
coredump->adev->gds.gds_size);
+   drm_printf(, "gds: gws per compute partition: %d\n", 
coredump->adev->gds.gws_size);
+   drm_printf(, "gds: os per compute partition: %d\n", 
coredump->adev->gds.oa_size);
+
+   /* HWIP Version Information */
+   drm_printf(, "\nHW IP Version Information\n");
for (int i = 1; i < MAX_HWIP; i++) {
for (int j = 0; j < HWIP_MAX_INSTANCE; j++) {
ver = coredump->adev->ip_versions[i][j];
-- 
2.34.1

[PATCH v1 0/4] Add CP and GFX Queue register in ip Dump for

2024-05-13 Thread Sunil Khatri

*** BLURB HERE ***

Sunil Khatri (4):
  drm/amdgpu: update the ip_dump to ipdump_core
  drm/amdgpu: Add support to dump gfx10 cp registers
  drm/amdgpu: add support to dump gfx10 queue registers
  drm/amdgpu: add prints while ip registr dump

 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h|   4 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 214 +++--
 3 files changed, 208 insertions(+), 12 deletions(-)

-- 
2.34.1

[PATCH v2 3/4] drm/amdgpu: add support to dump gfx10 queue registers

2024-05-13 Thread Sunil Khatri

Add gfx queue register for all instances in ip dump
for gfx10.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 86 +
 2 files changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index d96873c154ed..54232066cd3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -437,6 +437,7 @@ struct amdgpu_gfx {
/* IP reg dump */
uint32_t*ipdump_core;
uint32_t*ipdump_cp;
+   uint32_t*ipdump_gfx_queue;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index daf9a3571183..221fbde297e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -424,6 +424,33 @@ static const struct amdgpu_hwip_reg_entry 
gc_cp_reg_list_10[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
+   /* gfx queue registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x, 
0x00400014),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 
0xf8000100),
@@ -4664,6 +4691,19 @@ static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device 
*adev)
} else {
adev->gfx.ipdump_cp = ptr;
}
+
+   /* Allocate memory for gfx cp queue registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
+   inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
+   adev->gfx.me.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ipdump_gfx_queue = NULL;
+   } else {
+   adev->gfx.ipdump_gfx_queue = ptr;
+   }
 }
 
 static int gfx_v10_0_sw_init(void *handle)
@@ -4874,6 +4914,7 @@ static int gfx_v10_0_sw_fini(void *handle)
 
kfree(adev->gfx.ipdump_core);
kfree(adev->gfx.ipdump_cp);
+   kfree(adev->gfx.ipdump_gfx_queue);
 
return 0;
 }
@@ -9368,6 +9409,26 @@ static void gfx_v10_ip_print(void *handle, struct 
drm_printer *p)
}
}
}
+
+   /* print gfx queue registers for all instances */
+   if (!adev->gfx.ipdump_gfx_queue)
+   return;
+
+   reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
+
+   for (i = 0; i < adev->gfx.me.num_me; i++) {
+   for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
+   for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
+   drm_printf(p, "me %d, pipe %d, queue %d\n", i, 
j, k);
+   for (reg = 0; reg < reg_count; reg++) {
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  
gc_gfx_queue_reg_list_10[reg].reg_name,
+  
adev->gfx.ipdump_gfx_queue[index + reg]);
+   }
+   index += reg_count;
+

[PATCH v2 4/4] drm/amdgpu: add prints while ip registr dump

2024-05-13 Thread Sunil Khatri

add prints before and after during ip registers
dump. It avoids user to think of system being
stuck/hung as register dump takes time after a
gpu hang.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 00fe3c2d5431..b0186c61d24a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5373,11 +5373,13 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
if (!test_bit(AMDGPU_SKIP_COREDUMP, _context->flags)) {
amdgpu_reset_reg_dumps(tmp_adev);
 
+   dev_info(tmp_adev->dev, "Dumping IP Registers\n");
/* Trigger ip dump before we reset the asic */
for (i = 0; i < tmp_adev->num_ip_blocks; i++)
if 
(tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
tmp_adev->ip_blocks[i].version->funcs
->dump_ip_state((void *)tmp_adev);
+   dev_info(tmp_adev->dev, "Dumping IP Registers Completed\n");
}
 
reset_context->reset_device_list = device_list_handle;
-- 
2.34.1

[PATCH v2 2/4] drm/amdgpu: Add support to dump gfx10 cp registers

2024-05-13 Thread Sunil Khatri

add support to dump registers of all instances of
cp registers in gfx10

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |   1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 117 +++-
 2 files changed, 114 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 30d7f9c29478..d96873c154ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -436,6 +436,7 @@ struct amdgpu_gfx {
 
/* IP reg dump */
uint32_t*ipdump_core;
+   uint32_t*ipdump_cp;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f6d6a4b9802d..daf9a3571183 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -381,6 +381,49 @@ static const struct amdgpu_hwip_reg_entry 
gc_reg_list_10_1[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
+   /* compute registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x, 
0x00400014),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 
0xf8000100),
@@ -4595,10 +4638,11 @@ static int gfx_v10_0_compute_ring_init(struct 
amdgpu_device *adev, int ring_id,
 hw_prio, NULL);
 }
 
-static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev)
+static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
 {
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
uint32_t *ptr;
+   uint32_t inst;
 
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
@@ -4607,6 +4651,19 @@ static void gfx_v10_0_alloc_dump_mem(struct 
amdgpu_device *adev)
} else {
adev->gfx.ipdump_core = ptr;
}
+
+   /* Allocate memory for gfx cp registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
+   inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
+   adev->gfx.mec.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ipdump_cp = NULL;
+   } else {
+   adev->gfx.ipdump_cp =

[PATCH v2 1/4] drm/amdgpu: update the ip_dump to ipdump_core

2024-05-13 Thread Sunil Khatri

Update the memory pointer from ip_dump to ipdump_core
to make it specific to core registers and rest other
registers to be dumped in their respective memories.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 14 +++---
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 109f471ff315..30d7f9c29478 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -435,7 +435,7 @@ struct amdgpu_gfx {
boolmcbp; /* mid command buffer preemption 
*/
 
/* IP reg dump */
-   uint32_t*ip_dump;
+   uint32_t*ipdump_core;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 953df202953a..f6d6a4b9802d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4603,9 +4603,9 @@ static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device 
*adev)
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
DRM_ERROR("Failed to allocate memory for IP Dump\n");
-   adev->gfx.ip_dump = NULL;
+   adev->gfx.ipdump_core = NULL;
} else {
-   adev->gfx.ip_dump = ptr;
+   adev->gfx.ipdump_core = ptr;
}
 }
 
@@ -4815,7 +4815,7 @@ static int gfx_v10_0_sw_fini(void *handle)
 
gfx_v10_0_free_microcode(adev);
 
-   kfree(adev->gfx.ip_dump);
+   kfree(adev->gfx.ipdump_core);
 
return 0;
 }
@@ -9283,13 +9283,13 @@ static void gfx_v10_ip_print(void *handle, struct 
drm_printer *p)
uint32_t i;
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
 
-   if (!adev->gfx.ip_dump)
+   if (!adev->gfx.ipdump_core)
return;
 
for (i = 0; i < reg_count; i++)
drm_printf(p, "%-50s \t 0x%08x\n",
   gc_reg_list_10_1[i].reg_name,
-  adev->gfx.ip_dump[i]);
+  adev->gfx.ipdump_core[i]);
 }
 
 static void gfx_v10_ip_dump(void *handle)
@@ -9298,12 +9298,12 @@ static void gfx_v10_ip_dump(void *handle)
uint32_t i;
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
 
-   if (!adev->gfx.ip_dump)
+   if (!adev->gfx.ipdump_core)
return;
 
amdgpu_gfx_off_ctrl(adev, false);
for (i = 0; i < reg_count; i++)
-   adev->gfx.ip_dump[i] = 
RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
+   adev->gfx.ipdump_core[i] = 
RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
amdgpu_gfx_off_ctrl(adev, true);
 }
 
-- 
2.34.1

[PATCH v1 3/4] drm/amdgpu: add support to dump gfx10 queue registers

2024-05-09 Thread Sunil Khatri

Add gfx queue register for all instances in ip dump
for gfx10.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 83 +
 2 files changed, 84 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index d6e341b389fb..3495f117b527 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -437,6 +437,7 @@ struct amdgpu_gfx {
/* IP reg dump */
uint32_t*ipdump_core;
uint32_t*ipdump_cp;
+   uint32_t*ipdump_gfx_queue;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index daf9a3571183..b0f38e877c69 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -424,6 +424,33 @@ static const struct amdgpu_hwip_reg_entry 
gc_cp_reg_list_10[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
+   /* gfx queue registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x, 
0x00400014),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 
0xf8000100),
@@ -4664,6 +4691,19 @@ static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device 
*adev)
} else {
adev->gfx.ipdump_cp = ptr;
}
+
+   /* Allocate memory for gfx cp queue registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
+   inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
+   adev->gfx.me.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ipdump_gfx_queue = NULL;
+   } else {
+   adev->gfx.ipdump_gfx_queue = ptr;
+   }
 }
 
 static int gfx_v10_0_sw_init(void *handle)
@@ -4874,6 +4914,7 @@ static int gfx_v10_0_sw_fini(void *handle)
 
kfree(adev->gfx.ipdump_core);
kfree(adev->gfx.ipdump_cp);
+   kfree(adev->gfx.ipdump_gfx_queue);
 
return 0;
 }
@@ -9368,6 +9409,26 @@ static void gfx_v10_ip_print(void *handle, struct 
drm_printer *p)
}
}
}
+
+   /* print gfx queue registers for all instances */
+   if (!adev->gfx.ipdump_gfx_queue)
+   return;
+
+   reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
+
+   for (i = 0; i < adev->gfx.mec.num_mec; i++) {
+   for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
+   for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
+   drm_printf(p, "me %d, pipe %d, queue %d\n", i, 
j, k);
+   for (reg = 0; reg < reg_count; reg++) {
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  
gc_gfx_queue_reg_list_10[reg].reg_name,
+  
adev->gfx.ipdump_gfx_queue[index + reg]);
+   }
+   index += reg_count;
+

[PATCH v1 4/4] drm/amdgpu: add prints while ip registr dump

2024-05-09 Thread Sunil Khatri

add prints before and after during ip registers
dump. It avoids user to think of system being
stuck/hung as register dump takes time after a
gpu hang.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 77f6fd50002a..45cc470058a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5373,11 +5373,13 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
if (!test_bit(AMDGPU_SKIP_COREDUMP, _context->flags)) {
amdgpu_reset_reg_dumps(tmp_adev);
 
+   dev_info(tmp_adev->dev, "Dumping IP Registers\n");
/* Trigger ip dump before we reset the asic */
for (i = 0; i < tmp_adev->num_ip_blocks; i++)
if 
(tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
tmp_adev->ip_blocks[i].version->funcs
->dump_ip_state((void *)tmp_adev);
+   dev_info(tmp_adev->dev, "Dumping IP Registers Completed\n");
}
 
reset_context->reset_device_list = device_list_handle;
-- 
2.34.1

[PATCH v1 2/4] drm/amdgpu: Add support to dump gfx10 cp registers

2024-05-09 Thread Sunil Khatri

add support to dump registers of all instances of
cp registers in gfx10

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |   1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 117 +++-
 2 files changed, 114 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 36f67fe9234d..d6e341b389fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -436,6 +436,7 @@ struct amdgpu_gfx {
 
/* IP reg dump */
uint32_t*ipdump_core;
+   uint32_t*ipdump_cp;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f6d6a4b9802d..daf9a3571183 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -381,6 +381,49 @@ static const struct amdgpu_hwip_reg_entry 
gc_reg_list_10_1[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
 };
 
+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
+   /* compute registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x, 
0x00400014),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 
0xf8000100),
@@ -4595,10 +4638,11 @@ static int gfx_v10_0_compute_ring_init(struct 
amdgpu_device *adev, int ring_id,
 hw_prio, NULL);
 }
 
-static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev)
+static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
 {
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
uint32_t *ptr;
+   uint32_t inst;
 
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
@@ -4607,6 +4651,19 @@ static void gfx_v10_0_alloc_dump_mem(struct 
amdgpu_device *adev)
} else {
adev->gfx.ipdump_core = ptr;
}
+
+   /* Allocate memory for gfx cp registers for all the instances */
+   reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
+   inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
+   adev->gfx.mec.num_queue_per_pipe;
+
+   ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
+   if (ptr == NULL) {
+   DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
+   adev->gfx.ipdump_cp = NULL;
+   } else {
+   adev->gfx.ipdump_cp =

[PATCH v1 1/4] drm/amdgpu: update the ip_dump to ipdump_core

2024-05-09 Thread Sunil Khatri

Update the memory pointer from ip_dump to ipdump_core
to make it specific to core registers and rest other
registers to be dumped in their respective memories.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 14 +++---
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 9a946f0e015c..36f67fe9234d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -435,7 +435,7 @@ struct amdgpu_gfx {
boolmcbp; /* mid command buffer preemption 
*/
 
/* IP reg dump */
-   uint32_t*ip_dump;
+   uint32_t*ipdump_core;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 953df202953a..f6d6a4b9802d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4603,9 +4603,9 @@ static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device 
*adev)
ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
if (ptr == NULL) {
DRM_ERROR("Failed to allocate memory for IP Dump\n");
-   adev->gfx.ip_dump = NULL;
+   adev->gfx.ipdump_core = NULL;
} else {
-   adev->gfx.ip_dump = ptr;
+   adev->gfx.ipdump_core = ptr;
}
 }
 
@@ -4815,7 +4815,7 @@ static int gfx_v10_0_sw_fini(void *handle)
 
gfx_v10_0_free_microcode(adev);
 
-   kfree(adev->gfx.ip_dump);
+   kfree(adev->gfx.ipdump_core);
 
return 0;
 }
@@ -9283,13 +9283,13 @@ static void gfx_v10_ip_print(void *handle, struct 
drm_printer *p)
uint32_t i;
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
 
-   if (!adev->gfx.ip_dump)
+   if (!adev->gfx.ipdump_core)
return;
 
for (i = 0; i < reg_count; i++)
drm_printf(p, "%-50s \t 0x%08x\n",
   gc_reg_list_10_1[i].reg_name,
-  adev->gfx.ip_dump[i]);
+  adev->gfx.ipdump_core[i]);
 }
 
 static void gfx_v10_ip_dump(void *handle)
@@ -9298,12 +9298,12 @@ static void gfx_v10_ip_dump(void *handle)
uint32_t i;
uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
 
-   if (!adev->gfx.ip_dump)
+   if (!adev->gfx.ipdump_core)
return;
 
amdgpu_gfx_off_ctrl(adev, false);
for (i = 0; i < reg_count; i++)
-   adev->gfx.ip_dump[i] = 
RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
+   adev->gfx.ipdump_core[i] = 
RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
amdgpu_gfx_off_ctrl(adev, true);
 }
 
-- 
2.34.1

[PATCH v1 0/4] Add CP and GFX Queue register in ip Dump for

2024-05-09 Thread Sunil Khatri

*** BLURB HERE ***

Sunil Khatri (4):
  drm/amdgpu: update the ip_dump to ipdump_core
  drm/amdgpu: Add support to dump gfx10 cp registers
  drm/amdgpu: add support to dump gfx10 queue registers
  drm/amdgpu: add prints while ip registr dump

 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h|   4 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 214 +++--
 3 files changed, 208 insertions(+), 12 deletions(-)

-- 
2.34.1

[PATCH v1 4/4] drm/amdgpu: add gfx queue registers for gfx10 ip dump

2024-05-03 Thread Sunil Khatri

Add gfx queue registers in the list of registers to
be dumped in ip dump for gfx10

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 00c7a842ea3b..bef7d8ca35df 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -418,7 +418,31 @@ static const struct amdgpu_hwip_reg_entry 
gc_reg_list_10_1[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
-   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS),
+   /* gfx queue registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
-- 
2.34.1

[PATCH v1 2/4] drm/amdgpu: add se registers to ip dump for gfx10

2024-05-03 Thread Sunil Khatri

add the registers of SE block of gfx for ip dump
for gfx10 IP.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 61c1e997f794..953df202953a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -373,7 +373,12 @@ static const struct amdgpu_hwip_reg_entry 
gc_reg_list_10_1[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
-   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP)
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),
+   /* SE status registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
-- 
2.34.1

[PATCH v1 3/4] drm/amdgpu: add compute registers in ip dump for gfx10

2024-05-03 Thread Sunil Khatri

add compute registers in set of registers to dump
during ip dump for gfx10.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 42 +-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 953df202953a..00c7a842ea3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -378,7 +378,47 @@ static const struct amdgpu_hwip_reg_entry 
gc_reg_list_10_1[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
-   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),
+   /* compute registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
-- 
2.34.1

[PATCH v1 0/4] Adding differnt blocks of gfx10 registers for register dump

2024-05-03 Thread Sunil Khatri

*** BLURB HERE ***

Sunil Khatri (4):
  drm/amdgpu: add CP headers registers to gfx10 dump
  drm/amdgpu: add se registers to ip dump for gfx10
  drm/amdgpu: add compute registers in ip dump for gfx10
  drm/amdgpu: add gfx queue registers for gfx10 ip dump

 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 78 +-
 1 file changed, 77 insertions(+), 1 deletion(-)

-- 
2.34.1

[PATCH v1 1/4] drm/amdgpu: add CP headers registers to gfx10 dump

2024-05-03 Thread Sunil Khatri

add registers in the ip dump for CP headers in gfx10

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 3171ed5e5af3..61c1e997f794 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -366,7 +366,14 @@ static const struct amdgpu_hwip_reg_entry 
gc_reg_list_10_1[] = {
SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
-   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST)
+   SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),
+   /* cp header registers */
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
-- 
2.34.1

[PATCH] drm/amdgpu: remove ip dump reg_count variable

2024-05-02 Thread Sunil Khatri

reg_count is not used and the register count is
directly derived from the array size and hence
removed.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 -
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 2 --
 2 files changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 64f197bbc866..9a946f0e015c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -436,7 +436,6 @@ struct amdgpu_gfx {
 
/* IP reg dump */
uint32_t*ip_dump;
-   uint32_treg_count;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 536287ddd2ec..3171ed5e5af3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4592,10 +4592,8 @@ static void gfx_v10_0_alloc_dump_mem(struct 
amdgpu_device *adev)
if (ptr == NULL) {
DRM_ERROR("Failed to allocate memory for IP Dump\n");
adev->gfx.ip_dump = NULL;
-   adev->gfx.reg_count = 0;
} else {
adev->gfx.ip_dump = ptr;
-   adev->gfx.reg_count = reg_count;
}
 }
 
-- 
2.34.1

[PATCH] drm/amdgpu: add function descripion of new functions

2024-04-26 Thread Sunil Khatri

Add function description of the new functions added
in amd_ip_funcs.

new functions added are:
a. dump_ip_state
b. print_ip_state

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/include/amd_shared.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 7536c173a546..36ee9d3d6d9c 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -291,6 +291,8 @@ enum amd_dpm_forced_level;
  * @set_clockgating_state: enable/disable cg for the IP block
  * @set_powergating_state: enable/disable pg for the IP block
  * @get_clockgating_state: get current clockgating status
+ * @dump_ip_state: dump the IP state of the ASIC during a gpu hang
+ * @print_ip_state: print the IP state in devcoredump for each IP of the ASIC
  *
  * These hooks provide an interface for controlling the operational state
  * of IP blocks. After acquiring a list of IP blocks for the GPU in use,
-- 
2.34.1

[PATCH] drm/amdgpu: skip ip dump if devcoredump flag is set

2024-04-25 Thread Sunil Khatri

Do not dump the ip registers during driver reload
in passthrough environment.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 869256394136..b50758482530 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5372,10 +5372,12 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
amdgpu_reset_reg_dumps(tmp_adev);
 
/* Trigger ip dump before we reset the asic */
-   for (i = 0; i < tmp_adev->num_ip_blocks; i++)
-   if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
-   tmp_adev->ip_blocks[i].version->funcs->dump_ip_state(
-   (void *)tmp_adev);
+   if (!test_bit(AMDGPU_SKIP_COREDUMP, _context->flags)) {
+   for (i = 0; i < tmp_adev->num_ip_blocks; i++)
+   if 
(tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
+   tmp_adev->ip_blocks[i].version->funcs
+   ->dump_ip_state((void *)tmp_adev);
+   }
 
reset_context->reset_device_list = device_list_handle;
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
-- 
2.34.1

[PATCH v5 6/6] drm/amdgpu: add ip dump for each ip in devcoredump

2024-04-17 Thread Sunil Khatri

Add ip dump for each ip of the asic in the
devcoredump for all the ips where a callback
is registered for register dump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
index 64fe564b8036..c1cb62683695 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
@@ -262,6 +262,20 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, 
size_t count,
drm_printf(, "Faulty page starting at address: 0x%016llx\n", 
fault_info->addr);
drm_printf(, "Protection fault status register: 0x%x\n\n", 
fault_info->status);
 
+   /* dump the ip state for each ip */
+   drm_printf(, "IP Dump\n");
+   for (int i = 0; i < coredump->adev->num_ip_blocks; i++) {
+   if 
(coredump->adev->ip_blocks[i].version->funcs->print_ip_state) {
+   drm_printf(, "IP: %s\n",
+  coredump->adev->ip_blocks[i]
+  .version->funcs->name);
+   coredump->adev->ip_blocks[i]
+   .version->funcs->print_ip_state(
+   (void *)coredump->adev, );
+   drm_printf(, "\n");
+   }
+   }
+
/* Add ring buffer information */
drm_printf(, "Ring buffer information\n");
for (int i = 0; i < coredump->adev->num_rings; i++) {
-- 
2.34.1

[PATCH v5 5/6] drm/amdgpu: dump ip state before reset for each ip

2024-04-17 Thread Sunil Khatri

Invoke the dump_ip_state function for each ip before
the asic resets and save the register values for
debugging via devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f3b7cb18fd46..f8a34db5d9e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5353,6 +5353,7 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
struct amdgpu_device *tmp_adev = NULL;
bool need_full_reset, skip_hw_reset, vram_lost = false;
int r = 0;
+   uint32_t i;
 
/* Try reset handler method first */
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
@@ -5361,6 +5362,12 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
if (!test_bit(AMDGPU_SKIP_COREDUMP, _context->flags))
amdgpu_reset_reg_dumps(tmp_adev);
 
+   /* Trigger ip dump before we reset the asic */
+   for (i = 0; i < tmp_adev->num_ip_blocks; i++)
+   if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
+   tmp_adev->ip_blocks[i].version->funcs->dump_ip_state(
+   (void *)tmp_adev);
+
reset_context->reset_device_list = device_list_handle;
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
-- 
2.34.1

[PATCH v5 4/6] drm/amdgpu: add support for gfx v10 print

2024-04-17 Thread Sunil Khatri

Add support to print ip information to be
used to print registers in devcoredump
buffer.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ceeeafef668c..9b0b8ce5f5e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9267,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
 }
 
+static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t i;
+   uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
+
+   if (!adev->gfx.ip_dump)
+   return;
+
+   for (i = 0; i < reg_count; i++)
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  gc_reg_list_10_1[i].reg_name,
+  adev->gfx.ip_dump[i]);
+}
+
 static void gfx_v10_ip_dump(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -9299,7 +9314,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.set_powergating_state = gfx_v10_0_set_powergating_state,
.get_clockgating_state = gfx_v10_0_get_clockgating_state,
.dump_ip_state = gfx_v10_ip_dump,
-   .print_ip_state = NULL,
+   .print_ip_state = gfx_v10_ip_print,
 };
 
 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
-- 
2.34.1

[PATCH v5 3/6] drm/amdgpu: add protype for print ip state

2024-04-17 Thread Sunil Khatri

Add the protoype for print ip state to be used
to print the registers in devcoredump during
a gpu reset.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
 drivers/gpu/drm/amd/amdgpu/cz_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/nv.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/si.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc21.c| 1 +
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vi.c   | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 drivers/gpu/drm/amd/include/amd_shared.h  | 2 ++
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c  | 1 +
 64 files changed, 67 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 34a62033a388..bf6c4a0d0525 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -638,6 +638,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
.dump_ip_state = NULL,
+   .print_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 5bb9e0dacbf3..06ad68714172 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -876,6 +876,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
.dump_ip_state = NULL,
+   .print_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c 
b/drivers/gpu/drm/amd/amdgpu

[PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump

2024-04-17 Thread Sunil Khatri

Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   8 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h   |   4 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 130 +-
 drivers/gpu/drm/amd/amdgpu/soc15.h|   2 +
 .../include/asic_reg/gc/gc_10_1_0_offset.h|  12 ++
 5 files changed, 155 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e0d7f4ee7e16..cac0ca64367b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -139,6 +139,14 @@ enum amdgpu_ss {
AMDGPU_SS_DRV_UNLOAD
 };
 
+struct amdgpu_hwip_reg_entry {
+   u32 hwip;
+   u32 inst;
+   u32 seg;
+   u32 reg_offset;
+   const char  *reg_name;
+};
+
 struct amdgpu_watchdog_timer {
bool timeout_fatal_disable;
uint32_t period; /* maxCycles = (1 << period), the number of cycles 
before a timeout */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 04a86dff71e6..64f197bbc866 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -433,6 +433,10 @@ struct amdgpu_gfx {
uint32_tnum_xcc_per_xcp;
struct mutexpartition_mutex;
boolmcbp; /* mid command buffer preemption 
*/
+
+   /* IP reg dump */
+   uint32_t*ip_dump;
+   uint32_treg_count;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a0bc4196ff8b..4a54161f4837 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 
+static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
+   SOC15_REG_

[PATCH v5 1/6] drm/amdgpu: add prototype for ip dump

2024-04-17 Thread Sunil Khatri

Add the prototype to dump ip registers
for all ips of different asics and set
them to NULL for now. Based on the
requirement add a function pointer for
each of them.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
 drivers/gpu/drm/amd/amdgpu/cz_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/nv.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/si.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc21.c| 1 +
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vi.c   | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 drivers/gpu/drm/amd/include/amd_shared.h  | 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c  | 1 +
 64 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 6d72355ac492..34a62033a388 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -637,6 +637,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.soft_reset = acp_soft_reset,
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
+   .dump_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 95f80b9131a8..5bb9e0dacbf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -875,6 +875,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.hw_fini = umsch_mm_hw_fini,
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
+   .dump_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu

[PATCH v4 5/6] drm/amdgpu: dump ip state before reset for each ip

2024-04-17 Thread Sunil Khatri

Invoke the dump_ip_state function for each ip before
the asic resets and save the register values for
debugging via devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f3b7cb18fd46..f8a34db5d9e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5353,6 +5353,7 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
struct amdgpu_device *tmp_adev = NULL;
bool need_full_reset, skip_hw_reset, vram_lost = false;
int r = 0;
+   uint32_t i;
 
/* Try reset handler method first */
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
@@ -5361,6 +5362,12 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
if (!test_bit(AMDGPU_SKIP_COREDUMP, _context->flags))
amdgpu_reset_reg_dumps(tmp_adev);
 
+   /* Trigger ip dump before we reset the asic */
+   for (i = 0; i < tmp_adev->num_ip_blocks; i++)
+   if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
+   tmp_adev->ip_blocks[i].version->funcs->dump_ip_state(
+   (void *)tmp_adev);
+
reset_context->reset_device_list = device_list_handle;
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
-- 
2.34.1

[PATCH v4 6/6] drm/amdgpu: add ip dump for each ip in devcoredump

2024-04-17 Thread Sunil Khatri

Add ip dump for each ip of the asic in the
devcoredump for all the ips where a callback
is registered for register dump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
index 64fe564b8036..c1cb62683695 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
@@ -262,6 +262,20 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, 
size_t count,
drm_printf(, "Faulty page starting at address: 0x%016llx\n", 
fault_info->addr);
drm_printf(, "Protection fault status register: 0x%x\n\n", 
fault_info->status);
 
+   /* dump the ip state for each ip */
+   drm_printf(, "IP Dump\n");
+   for (int i = 0; i < coredump->adev->num_ip_blocks; i++) {
+   if 
(coredump->adev->ip_blocks[i].version->funcs->print_ip_state) {
+   drm_printf(, "IP: %s\n",
+  coredump->adev->ip_blocks[i]
+  .version->funcs->name);
+   coredump->adev->ip_blocks[i]
+   .version->funcs->print_ip_state(
+   (void *)coredump->adev, );
+   drm_printf(, "\n");
+   }
+   }
+
/* Add ring buffer information */
drm_printf(, "Ring buffer information\n");
for (int i = 0; i < coredump->adev->num_rings; i++) {
-- 
2.34.1

[PATCH v4 4/6] drm/amdgpu: add support for gfx v10 print

2024-04-17 Thread Sunil Khatri

Add support to print ip information to be
used to print registers in devcoredump
buffer.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ceeeafef668c..9b0b8ce5f5e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9267,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
 }
 
+static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t i;
+   uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
+
+   if (!adev->gfx.ip_dump)
+   return;
+
+   for (i = 0; i < reg_count; i++)
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  gc_reg_list_10_1[i].reg_name,
+  adev->gfx.ip_dump[i]);
+}
+
 static void gfx_v10_ip_dump(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -9299,7 +9314,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.set_powergating_state = gfx_v10_0_set_powergating_state,
.get_clockgating_state = gfx_v10_0_get_clockgating_state,
.dump_ip_state = gfx_v10_ip_dump,
-   .print_ip_state = NULL,
+   .print_ip_state = gfx_v10_ip_print,
 };
 
 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
-- 
2.34.1

[PATCH v4 3/6] drm/amdgpu: add protype for print ip state

2024-04-17 Thread Sunil Khatri

Add the protoype for print ip state to be used
to print the registers in devcoredump during
a gpu reset.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
 drivers/gpu/drm/amd/amdgpu/cz_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/nv.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/si.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc21.c| 1 +
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vi.c   | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 drivers/gpu/drm/amd/include/amd_shared.h  | 2 ++
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c  | 1 +
 64 files changed, 67 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 34a62033a388..bf6c4a0d0525 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -638,6 +638,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
.dump_ip_state = NULL,
+   .print_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 5bb9e0dacbf3..06ad68714172 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -876,6 +876,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
.dump_ip_state = NULL,
+   .print_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c 
b/drivers/gpu/drm/amd/amdgpu

[PATCH v4 2/6] drm/amdgpu: add support of gfx10 register dump

2024-04-17 Thread Sunil Khatri

Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   8 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h   |   4 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 130 +-
 drivers/gpu/drm/amd/amdgpu/soc15.h|   2 +
 .../include/asic_reg/gc/gc_10_1_0_offset.h|  12 ++
 5 files changed, 155 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e0d7f4ee7e16..210af65a744c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -139,6 +139,14 @@ enum amdgpu_ss {
AMDGPU_SS_DRV_UNLOAD
 };
 
+struct amdgpu_hwip_reg_entry {
+   u32 hwip;
+   u32 inst;
+   u32 seg;
+   u32 reg_offset;
+   charreg_name[50];
+};
+
 struct amdgpu_watchdog_timer {
bool timeout_fatal_disable;
uint32_t period; /* maxCycles = (1 << period), the number of cycles 
before a timeout */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 04a86dff71e6..64f197bbc866 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -433,6 +433,10 @@ struct amdgpu_gfx {
uint32_tnum_xcc_per_xcp;
struct mutexpartition_mutex;
boolmcbp; /* mid command buffer preemption 
*/
+
+   /* IP reg dump */
+   uint32_t*ip_dump;
+   uint32_treg_count;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a0bc4196ff8b..4a54161f4837 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 
+static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
+   SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
+   SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
+   SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS

[PATCH v4 1/6] drm/amdgpu: add prototype for ip dump

2024-04-17 Thread Sunil Khatri

Add the prototype to dump ip registers
for all ips of different asics and set
them to NULL for now. Based on the
requirement add a function pointer for
each of them.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
 drivers/gpu/drm/amd/amdgpu/cz_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/nv.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/si.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc21.c| 1 +
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vi.c   | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 drivers/gpu/drm/amd/include/amd_shared.h  | 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c  | 1 +
 64 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 6d72355ac492..34a62033a388 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -637,6 +637,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.soft_reset = acp_soft_reset,
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
+   .dump_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 95f80b9131a8..5bb9e0dacbf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -875,6 +875,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.hw_fini = umsch_mm_hw_fini,
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
+   .dump_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu

[PATCH v3 2/6] drm/amdgpu: add support of gfx10 register dump

2024-04-16 Thread Sunil Khatri

Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   8 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h   |   4 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 130 +-
 drivers/gpu/drm/amd/amdgpu/soc15.h|   1 +
 .../include/asic_reg/gc/gc_10_1_0_offset.h|  12 ++
 5 files changed, 154 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e0d7f4ee7e16..210af65a744c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -139,6 +139,14 @@ enum amdgpu_ss {
AMDGPU_SS_DRV_UNLOAD
 };
 
+struct amdgpu_hwip_reg_entry {
+   u32 hwip;
+   u32 inst;
+   u32 seg;
+   u32 reg_offset;
+   charreg_name[50];
+};
+
 struct amdgpu_watchdog_timer {
bool timeout_fatal_disable;
uint32_t period; /* maxCycles = (1 << period), the number of cycles 
before a timeout */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 04a86dff71e6..64f197bbc866 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -433,6 +433,10 @@ struct amdgpu_gfx {
uint32_tnum_xcc_per_xcp;
struct mutexpartition_mutex;
boolmcbp; /* mid command buffer preemption 
*/
+
+   /* IP reg dump */
+   uint32_t*ip_dump;
+   uint32_treg_count;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a0bc4196ff8b..3b3fb41b138c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 
+static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
+   { SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT) },
+   { SOC15_REG_ENTRY_

[PATCH v3 4/6] drm/amdgpu: add support for gfx v10 print

2024-04-16 Thread Sunil Khatri

Add support to print ip information to be
used to print registers in devcoredump
buffer.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 1b62f4984025..a6f03b80fa87 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9267,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
 }
 
+static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t i;
+   uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
+
+   if (!adev->gfx.ip_dump)
+   return;
+
+   for (i = 0; i < reg_count; i++)
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  gc_reg_list_10_1[i].reg_name,
+  adev->gfx.ip_dump[i]);
+}
+
 static void gfx_v10_ip_dump(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -9299,7 +9314,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.set_powergating_state = gfx_v10_0_set_powergating_state,
.get_clockgating_state = gfx_v10_0_get_clockgating_state,
.dump_ip_state = gfx_v10_ip_dump,
-   .print_ip_state = NULL,
+   .print_ip_state = gfx_v10_ip_print,
 };
 
 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
-- 
2.34.1

[PATCH v3 5/6] drm/amdgpu: dump ip state before reset for each ip

2024-04-16 Thread Sunil Khatri

Invoke the dump_ip_state function for each ip before
the asic resets and save the register values for
debugging via devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1b2e177bc2d6..b834c9e8adc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5353,12 +5353,19 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
struct amdgpu_device *tmp_adev = NULL;
bool need_full_reset, skip_hw_reset, vram_lost = false;
int r = 0;
+   uint32_t i;
 
/* Try reset handler method first */
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
reset_list);
amdgpu_reset_reg_dumps(tmp_adev);
 
+   /* Trigger ip dump before we reset the asic */
+   for (i = 0; i < tmp_adev->num_ip_blocks; i++)
+   if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
+   tmp_adev->ip_blocks[i].version->funcs->dump_ip_state(
+   (void *)tmp_adev);
+
reset_context->reset_device_list = device_list_handle;
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
-- 
2.34.1

[PATCH v3 6/6] drm/amdgpu: add ip dump for each ip in devcoredump

2024-04-16 Thread Sunil Khatri

Add ip dump for each ip of the asic in the
devcoredump for all the ips where a callback
is registered for register dump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
index 64fe564b8036..c1cb62683695 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
@@ -262,6 +262,20 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, 
size_t count,
drm_printf(, "Faulty page starting at address: 0x%016llx\n", 
fault_info->addr);
drm_printf(, "Protection fault status register: 0x%x\n\n", 
fault_info->status);
 
+   /* dump the ip state for each ip */
+   drm_printf(, "IP Dump\n");
+   for (int i = 0; i < coredump->adev->num_ip_blocks; i++) {
+   if 
(coredump->adev->ip_blocks[i].version->funcs->print_ip_state) {
+   drm_printf(, "IP: %s\n",
+  coredump->adev->ip_blocks[i]
+  .version->funcs->name);
+   coredump->adev->ip_blocks[i]
+   .version->funcs->print_ip_state(
+   (void *)coredump->adev, );
+   drm_printf(, "\n");
+   }
+   }
+
/* Add ring buffer information */
drm_printf(, "Ring buffer information\n");
for (int i = 0; i < coredump->adev->num_rings; i++) {
-- 
2.34.1

[PATCH v3 3/6] drm/amdgpu: add protype for print ip state

2024-04-16 Thread Sunil Khatri

Add the protoype for print ip state to be used
to print the registers in devcoredump during
a gpu reset.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
 drivers/gpu/drm/amd/amdgpu/cz_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/nv.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/si.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc21.c| 1 +
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vi.c   | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 drivers/gpu/drm/amd/include/amd_shared.h  | 2 ++
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c  | 1 +
 64 files changed, 67 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 34a62033a388..bf6c4a0d0525 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -638,6 +638,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
.dump_ip_state = NULL,
+   .print_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 5bb9e0dacbf3..06ad68714172 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -876,6 +876,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
.dump_ip_state = NULL,
+   .print_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c 
b/drivers/gpu/drm/amd/amdgpu

[PATCH v3 1/6] drm/amdgpu: add prototype for ip dump

2024-04-16 Thread Sunil Khatri

Add the prototype to dump ip registers
for all ips of different asics and set
them to NULL for now. Based on the
requirement add a function pointer for
each of them.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
 drivers/gpu/drm/amd/amdgpu/cz_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/nv.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/si.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc21.c| 1 +
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vi.c   | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 drivers/gpu/drm/amd/include/amd_shared.h  | 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c  | 1 +
 64 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 6d72355ac492..34a62033a388 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -637,6 +637,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.soft_reset = acp_soft_reset,
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
+   .dump_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 95f80b9131a8..5bb9e0dacbf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -875,6 +875,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.hw_fini = umsch_mm_hw_fini,
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
+   .dump_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu

[PATCH v2 3/6] drm/amdgpu: add protype for print ip state

2024-04-16 Thread Sunil Khatri

Add the protoype for print ip state to be used
to print the registers in devcoredump during
a gpu reset.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
 drivers/gpu/drm/amd/amdgpu/cz_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/nv.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/si.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc21.c| 1 +
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vi.c   | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 drivers/gpu/drm/amd/include/amd_shared.h  | 2 ++
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c  | 1 +
 64 files changed, 67 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 34a62033a388..bf6c4a0d0525 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -638,6 +638,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
.dump_ip_state = NULL,
+   .print_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 5bb9e0dacbf3..06ad68714172 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -876,6 +876,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
.dump_ip_state = NULL,
+   .print_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c 
b/drivers/gpu/drm/amd/amdgpu

[PATCH v2 6/6] drm/amdgpu: add ip dump for each ip in devcoredump

2024-04-16 Thread Sunil Khatri

Add ip dump for each ip of the asic in the
devcoredump for all the ips where a callback
is registered for register dump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
index 64fe564b8036..c1cb62683695 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
@@ -262,6 +262,20 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, 
size_t count,
drm_printf(, "Faulty page starting at address: 0x%016llx\n", 
fault_info->addr);
drm_printf(, "Protection fault status register: 0x%x\n\n", 
fault_info->status);
 
+   /* dump the ip state for each ip */
+   drm_printf(, "IP Dump\n");
+   for (int i = 0; i < coredump->adev->num_ip_blocks; i++) {
+   if 
(coredump->adev->ip_blocks[i].version->funcs->print_ip_state) {
+   drm_printf(, "IP: %s\n",
+  coredump->adev->ip_blocks[i]
+  .version->funcs->name);
+   coredump->adev->ip_blocks[i]
+   .version->funcs->print_ip_state(
+   (void *)coredump->adev, );
+   drm_printf(, "\n");
+   }
+   }
+
/* Add ring buffer information */
drm_printf(, "Ring buffer information\n");
for (int i = 0; i < coredump->adev->num_rings; i++) {
-- 
2.34.1

[PATCH v2 5/6] drm/amdgpu: dump ip state before reset for each ip

2024-04-16 Thread Sunil Khatri

Invoke the dump_ip_state function for each ip before
the asic resets and save the register values for
debugging via devcoredump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1b2e177bc2d6..b834c9e8adc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5353,12 +5353,19 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
struct amdgpu_device *tmp_adev = NULL;
bool need_full_reset, skip_hw_reset, vram_lost = false;
int r = 0;
+   uint32_t i;
 
/* Try reset handler method first */
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
reset_list);
amdgpu_reset_reg_dumps(tmp_adev);
 
+   /* Trigger ip dump before we reset the asic */
+   for (i = 0; i < tmp_adev->num_ip_blocks; i++)
+   if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
+   tmp_adev->ip_blocks[i].version->funcs->dump_ip_state(
+   (void *)tmp_adev);
+
reset_context->reset_device_list = device_list_handle;
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
-- 
2.34.1

[PATCH v2 1/6] drm/amdgpu: add prototype for ip dump

2024-04-16 Thread Sunil Khatri

Add the prototype to dump ip registers
for all ips of different asics and set
them to NULL for now. Based on the
requirement add a function pointer for
each of them.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
 drivers/gpu/drm/amd/amdgpu/cz_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/nv.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/si.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc21.c| 1 +
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vi.c   | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 drivers/gpu/drm/amd/include/amd_shared.h  | 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c  | 1 +
 64 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 6d72355ac492..34a62033a388 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -637,6 +637,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.soft_reset = acp_soft_reset,
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
+   .dump_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 95f80b9131a8..5bb9e0dacbf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -875,6 +875,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.hw_fini = umsch_mm_hw_fini,
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
+   .dump_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu

[PATCH v2 4/6] drm/amdgpu: add support for gfx v10 print

2024-04-16 Thread Sunil Khatri

Add support to print ip information to be
used to print registers in devcoredump
buffer.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 1b62f4984025..a6f03b80fa87 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9267,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
 }
 
+static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t i;
+   uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
+
+   if (!adev->gfx.ip_dump)
+   return;
+
+   for (i = 0; i < reg_count; i++)
+   drm_printf(p, "%-50s \t 0x%08x\n",
+  gc_reg_list_10_1[i].reg_name,
+  adev->gfx.ip_dump[i]);
+}
+
 static void gfx_v10_ip_dump(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -9299,7 +9314,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.set_powergating_state = gfx_v10_0_set_powergating_state,
.get_clockgating_state = gfx_v10_0_get_clockgating_state,
.dump_ip_state = gfx_v10_ip_dump,
-   .print_ip_state = NULL,
+   .print_ip_state = gfx_v10_ip_print,
 };
 
 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
-- 
2.34.1

[PATCH v2 2/6] drm/amdgpu: add support of gfx10 register dump

2024-04-16 Thread Sunil Khatri

Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   8 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h   |   4 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 130 +-
 drivers/gpu/drm/amd/amdgpu/soc15.h|   1 +
 .../include/asic_reg/gc/gc_10_1_0_offset.h|  12 ++
 5 files changed, 154 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e0d7f4ee7e16..210af65a744c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -139,6 +139,14 @@ enum amdgpu_ss {
AMDGPU_SS_DRV_UNLOAD
 };
 
+struct amdgpu_hwip_reg_entry {
+   u32 hwip;
+   u32 inst;
+   u32 seg;
+   u32 reg_offset;
+   charreg_name[50];
+};
+
 struct amdgpu_watchdog_timer {
bool timeout_fatal_disable;
uint32_t period; /* maxCycles = (1 << period), the number of cycles 
before a timeout */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 04a86dff71e6..64f197bbc866 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -433,6 +433,10 @@ struct amdgpu_gfx {
uint32_tnum_xcc_per_xcp;
struct mutexpartition_mutex;
boolmcbp; /* mid command buffer preemption 
*/
+
+   /* IP reg dump */
+   uint32_t*ip_dump;
+   uint32_treg_count;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a0bc4196ff8b..3b3fb41b138c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 
+static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
+   { SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS) },
+   { SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT) },
+   { SOC15_REG_ENTRY_

[PATCH 0/6] Infrastructure to dump ip registers in devcoredump

2024-04-16 Thread Sunil Khatri

starting with gfx 10 registers here we add the complete infra for ip
dump needed in devcoredump.

Sunil Khatri (6):
  drm/amdgpu: add prototype for ip dump
  drm/amdgpu: add support of gfx10 register dump
  drm/amdgpu: add protype for print ip state
  drm/amdgpu: add support for gfx v10 print
  drm/amdgpu: dump ip state before reset for each ip
  drm/amdgpu: add ip dump for each ip in devcoredump

 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  12 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c   |   2 +
 .../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c  |  15 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h   |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  |   2 +
 drivers/gpu/drm/amd/amdgpu/cik.c  |   2 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c   |   2 +
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c |   2 +
 drivers/gpu/drm/amd/amdgpu/cz_ih.c|   2 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|   2 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|   2 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 146 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c|   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c   |   2 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c   |   2 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c  |   2 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c  |   2 +
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c  |   2 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c|   2 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c|   4 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c|   2 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c|   2 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c  |   2 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c  |   2 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c  |   2 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c|   2 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c|   2 +
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c|   2 +
 drivers/gpu/drm/amd/amdgpu/nv.c   |   2 +
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c|   2 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c|   2 +
 drivers/gpu/drm/amd/amdgpu/si.c   |   2 +
 drivers/gpu/drm/amd/amdgpu/si_dma.c   |   2 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c|   2 +
 drivers/gpu/drm/amd/amdgpu/soc15.c|   2 +
 drivers/gpu/drm/amd/amdgpu/soc21.c|   2 +
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c |   2 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c |   2 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c |   2 +
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c |   4 +
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c   |   2 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c   |   2 +
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c   |   2 +
 drivers/gpu/drm/amd/amdgpu/vi.c   |   2 +
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   2 +
 drivers/gpu/drm/amd/include/amd_shared.h  |   3 +
 .../include/asic_reg/gc/gc_10_1_0_offset.h|  12 ++
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c|   2 +
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c|   2 +
 .../gpu/drm/amd/pm/powerplay/amd_powerplay.c  |   2 +
 69 files changed, 327 insertions(+)

-- 
2.34.1

[PATCH v3 1/5] drm:amdgpu: enable IH RB ring1 for IH v6.0

2024-04-16 Thread Sunil Khatri

We need IH ring1 for handling the pagefault
interrupts which are overflowing the default
ring for specific usecases.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index ad4ad39f128f..26dc99232eb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -549,8 +549,15 @@ static int ih_v6_0_sw_init(void *handle)
adev->irq.ih.use_doorbell = true;
adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 
-   adev->irq.ih1.ring_size = 0;
-   adev->irq.ih2.ring_size = 0;
+   if (!(adev->flags & AMD_IS_APU)) {
+   r = amdgpu_ih_ring_init(adev, >irq.ih1, IH_RING_SIZE,
+   use_bus_addr);
+   if (r)
+   return r;
+
+   adev->irq.ih1.use_doorbell = true;
+   adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 
1;
+   }
 
/* initialize ih control register offset */
ih_v6_0_init_register_offset(adev);
-- 
2.34.1

[PATCH v3 2/5] drm:amdgpu: Enable IH ring1 for IH v6.1

2024-04-16 Thread Sunil Khatri

We need IH ring1 for handling the pagefault
interrupts which over flow in default
ring for specific usecases.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index b8da0fc29378..73dba180fabd 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -550,8 +550,15 @@ static int ih_v6_1_sw_init(void *handle)
adev->irq.ih.use_doorbell = true;
adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 
-   adev->irq.ih1.ring_size = 0;
-   adev->irq.ih2.ring_size = 0;
+   if (!(adev->flags & AMD_IS_APU)) {
+   r = amdgpu_ih_ring_init(adev, >irq.ih1, IH_RING_SIZE,
+   use_bus_addr);
+   if (r)
+   return r;
+
+   adev->irq.ih1.use_doorbell = true;
+   adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 
1;
+   }
 
/* initialize ih control register offset */
ih_v6_1_init_register_offset(adev);
-- 
2.34.1

[PATCH v3 5/5] drm/amdgpu: enable redirection of irq's for IH V6.1

2024-04-16 Thread Sunil Khatri

Enable redirection of irq for pagefaults for specific
clients to avoid overflow without dropping interrupts.

So here we redirect the interrupts to another IH ring
i.e ring1 where only these interrupts are processed.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index 73dba180fabd..29ed78798070 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -346,6 +346,21 @@ static int ih_v6_1_irq_init(struct amdgpu_device *adev)
DELAY, 3);
WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
 
+   /* Redirect the interrupts to IH RB1 for dGPU */
+   if (adev->irq.ih1.ring_size) {
+   tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
+   WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
+
+   tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 
0xa);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 
0x0);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
+   SOURCE_ID_MATCH_ENABLE, 0x1);
+
+   WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
+   }
+
pci_set_master(adev->pdev);
 
/* enable interrupts */
-- 
2.34.1

[PATCH v3 4/5] drm/amdgpu: enable redirection of irq's for IH V6.0

2024-04-16 Thread Sunil Khatri

Enable redirection of irq for pagefaults for specific
clients to avoid overflow without dropping interrupts.

So here we redirect the interrupts to another IH ring
i.e ring1 where only these interrupts are processed.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index 26dc99232eb6..8869aac03b82 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -346,6 +346,21 @@ static int ih_v6_0_irq_init(struct amdgpu_device *adev)
DELAY, 3);
WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
 
+   /* Redirect the interrupts to IH RB1 fpr dGPU */
+   if (adev->irq.ih1.ring_size) {
+   tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
+   WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
+
+   tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 
0xa);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 
0x0);
+   tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
+   SOURCE_ID_MATCH_ENABLE, 0x1);
+
+   WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
+   }
+
pci_set_master(adev->pdev);
 
/* enable interrupts */
-- 
2.34.1

[PATCH v3 3/5] drm/amdgpu: Add IH_RING1_CFG headers for IH v6.0

2024-04-16 Thread Sunil Khatri

Add offsets, mask and shift macros for IH v6.0
which are needed to configure ring1 client irq
redirection.

Signed-off-by: Sunil Khatri 
---
 .../drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h |  4 
 .../amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h| 10 ++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h
index 8b931bbabe70..969e006b859b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h
@@ -237,6 +237,10 @@
 #define regSEM_REGISTER_LAST_PART2_BASE_IDX
 0
 #define regIH_CLIENT_CFG   
 0x0184
 #define regIH_CLIENT_CFG_BASE_IDX  
 0
+#define regIH_RING1_CLIENT_CFG_INDEX   
 0x0185
+#define regIH_RING1_CLIENT_CFG_INDEX_BASE_IDX  
 0
+#define regIH_RING1_CLIENT_CFG_DATA
 0x0186
+#define regIH_RING1_CLIENT_CFG_DATA_BASE_IDX   
 0
 #define regIH_CLIENT_CFG_INDEX 
 0x0188
 #define regIH_CLIENT_CFG_INDEX_BASE_IDX
 0
 #define regIH_CLIENT_CFG_DATA  
 0x0189
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h
index f262f44fa68c..a672a91e58f0 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h
@@ -888,6 +888,16 @@
 //IH_CLIENT_CFG
 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 
   0x0
 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK   
   0x003FL
+//IH_RING1_CLIENT_CFG_INDEX
+#define IH_RING1_CLIENT_CFG_INDEX__INDEX__SHIFT
   0x0
+#define IH_RING1_CLIENT_CFG_INDEX__INDEX_MASK  
   0x0007L
+//IH_RING1_CLIENT_CFG_DATA
+#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID__SHIFT 
   0x0
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID__SHIFT 
   0x8
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT
   0x10
+#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID_MASK   
   0x00FFL
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MASK   
   0xFF00L
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE_MASK  
   0x0001L
 //IH_CLIENT_CFG_INDEX
 #define IH_CLIENT_CFG_INDEX__INDEX__SHIFT  
   0x0
 #define IH_CLIENT_CFG_INDEX__INDEX_MASK
   0x001FL
-- 
2.34.1

[PATCH 4/6] drm/amdgpu: add support for gfx v10 print

2024-04-16 Thread Sunil Khatri

Add support to print ip information to be
used to print registers in devcoredump
buffer.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 822bee932041..a7c2a3ddd613 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9268,6 +9268,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
 }
 
+static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   uint32_t i;
+   uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
+
+   if (!adev->gfx.ip_dump)
+   return;
+
+   for (i = 0; i < reg_count; i++)
+   drm_printf(p, "0x%04x \t 0x%08x\n",
+  adev->gfx.ip_dump[i].offset,
+  adev->gfx.ip_dump[i].value);
+}
+
 static void gfx_v10_ip_dump(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -9300,7 +9315,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.set_powergating_state = gfx_v10_0_set_powergating_state,
.get_clockgating_state = gfx_v10_0_get_clockgating_state,
.dump_ip_state = gfx_v10_ip_dump,
-   .print_ip_state = NULL,
+   .print_ip_state = gfx_v10_ip_print,
 };
 
 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
-- 
2.34.1

[PATCH 3/6] drm/amdgpu: add protype for print ip state

2024-04-16 Thread Sunil Khatri

Add the protoype for print ip state to be used
to print the registers in devcoredump during
a gpu reset.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
 drivers/gpu/drm/amd/amdgpu/cz_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/nv.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/si.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc21.c| 1 +
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vi.c   | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 drivers/gpu/drm/amd/include/amd_shared.h  | 2 ++
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c  | 1 +
 64 files changed, 67 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 34a62033a388..bf6c4a0d0525 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -638,6 +638,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
.dump_ip_state = NULL,
+   .print_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 5bb9e0dacbf3..06ad68714172 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -876,6 +876,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
.dump_ip_state = NULL,
+   .print_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c 
b/drivers/gpu/drm/amd/amdgpu

[PATCH 2/6] drm/amdgpu: add support of gfx10 register dump

2024-04-16 Thread Sunil Khatri

Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  12 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h   |   4 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 131 +-
 .../include/asic_reg/gc/gc_10_1_0_offset.h|  12 ++
 4 files changed, 158 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e0d7f4ee7e16..e016ac33629d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -139,6 +139,18 @@ enum amdgpu_ss {
AMDGPU_SS_DRV_UNLOAD
 };
 
+struct hwip_reg_entry {
+   u32 hwip;
+   u32 inst;
+   u32 seg;
+   u32 reg_offset;
+};
+
+struct reg_pair {
+   u32 offset;
+   u32 value;
+};
+
 struct amdgpu_watchdog_timer {
bool timeout_fatal_disable;
uint32_t period; /* maxCycles = (1 << period), the number of cycles 
before a timeout */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 04a86dff71e6..295a2c8d2e48 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -433,6 +433,10 @@ struct amdgpu_gfx {
uint32_tnum_xcc_per_xcp;
struct mutexpartition_mutex;
boolmcbp; /* mid command buffer preemption 
*/
+
+   /* IP reg dump */
+   struct reg_pair *ip_dump;
+   uint32_treg_count;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a0bc4196ff8b..46e136609ff1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 
+static const struct hwip_reg_entry gc_reg_list_10_1[] = {
+   { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS) },
+   { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2) },
+   { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS3) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_BUSY_STAT) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT2) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT2) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_GFX_ERROR) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_GFX_HPD_STATUS0) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB_BASE) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB_RPTR) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB_WPTR) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB0_BASE) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB0_RPTR) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB0_WPTR) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB1_BASE) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB1_RPTR) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB1_WPTR) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB2_BASE) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB2_WPTR) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_RB2_WPTR) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB1_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB2_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_IB1_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_IB2_CMD_BUFSZ) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB1_BASE_LO) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB1_BASE_HI) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB1_BUFSZ) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB2_BASE_LO) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB2_BASE_HI) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB2_BUFSZ) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_IB1_BASE_LO) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_IB1_BASE_HI) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_IB1_BUFSZ) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_IB2_BASE_LO) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_IB2_BASE_HI) },
+   { SOC15_REG_ENTRY(GC, 0, mmCP_IB2_BUFSZ) },
+   { SOC15_REG_ENTRY(GC, 0, mmCPF_UTCL1_STATUS) },
+   { SOC15_REG_ENTRY(GC, 0, mmCPC_UTCL1_STATUS) },
+   { SOC15_REG_ENTRY(GC, 0, mmCPG_UTCL1_STATUS) },
+   { SOC15_REG_ENTRY(GC, 0, mmGDS_PROTECTION_FAULT) },
+   { SOC15_REG_ENTRY(GC, 0, mmGDS_VM_PROTECTION_FAULT) },
+   { SOC15_REG_ENTRY(GC, 0, mmIA_UTCL1_STATUS) },
+   { SOC15_REG_ENTRY(GC, 0, mmIA_UTCL1_STATUS_2) },
+   { SOC15_REG_ENTRY(GC, 0, mmPA_CL_CNTL_STATUS) },
+   { SOC15

[PATCH 1/6] drm/amdgpu: add prototype for ip dump

2024-04-16 Thread Sunil Khatri

Add the prototype to dump ip registers
for all ips of different asics and set
them to NULL for now. Based on the
requirement add a function pointer for
each of them.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
 drivers/gpu/drm/amd/amdgpu/cz_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/ih_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/nv.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 1 +
 drivers/gpu/drm/amd/amdgpu/si.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c| 1 +
 drivers/gpu/drm/amd/amdgpu/soc21.c| 1 +
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/vi.c   | 1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 drivers/gpu/drm/amd/include/amd_shared.h  | 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c| 1 +
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c  | 1 +
 64 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 6d72355ac492..34a62033a388 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -637,6 +637,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.soft_reset = acp_soft_reset,
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
+   .dump_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 95f80b9131a8..5bb9e0dacbf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -875,6 +875,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.hw_fini = umsch_mm_hw_fini,
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
+   .dump_ip_state = NULL,
 };
 
 const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu

[PATCH 6/6] drm/amdgpu: add ip dump for each ip in devcoredump

2024-04-16 Thread Sunil Khatri

Add ip dump for each ip of the asic in the
devcoredump for all the ips where a callback
is registered for register dump.

Signed-off-by: Sunil Khatri 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
index 64fe564b8036..70167f63b4f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
@@ -262,6 +262,21 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, 
size_t count,
drm_printf(, "Faulty page starting at address: 0x%016llx\n", 
fault_info->addr);
drm_printf(, "Protection fault status register: 0x%x\n\n", 
fault_info->status);
 
+   /* dump the ip state for each ip */
+   drm_printf(, "Register Dump\n");
+   for (int i = 0; i < coredump->adev->num_ip_blocks; i++) {
+   if 
(coredump->adev->ip_blocks[i].version->funcs->print_ip_state) {
+   drm_printf(, "IP: %s\n",
+  coredump->adev->ip_blocks[i]
+  .version->funcs->name);
+   drm_printf(, "Offset \t Value\n");
+   coredump->adev->ip_blocks[i]
+   .version->funcs->print_ip_state(
+   (void *)coredump->adev, );
+   drm_printf(, "\n");
+   }
+   }
+
/* Add ring buffer information */
drm_printf(, "Ring buffer information\n");
for (int i = 0; i < coredump->adev->num_rings; i++) {
-- 
2.34.1

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