[PATCH 63/81] drm/amd/display: fix 4k@30 with 10bit deep color and avi for BT2020

[sunpeng.li]

From: Charlene Liu 

Change-Id: I064a87f09f1254f61bde94b0546855b98f4ab211
Signed-off-by: Charlene Liu 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index a9c086a..00fed61 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1661,7 +1661,8 @@ static void set_avi_info_frame(
 
/* C0, C1 : Colorimetry */
if (color_space == COLOR_SPACE_YCBCR709 ||
-   color_space == COLOR_SPACE_YCBCR709_LIMITED)
+   color_space == COLOR_SPACE_YCBCR709_LIMITED ||
+   color_space == COLOR_SPACE_2020_YCBCR)
hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
else if (color_space == COLOR_SPACE_YCBCR601 ||
color_space == COLOR_SPACE_YCBCR601_LIMITED)
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 69/81] drm/amd/display: Release cached atomic state in S3.

[sunpeng.li]

From: Andrey Grodzovsky 

Fixes memory leak.

Change-Id: I32f68c72d11695f49bb8328a11e89922818fb9fe
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b6a04ad..8377575 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -508,6 +508,7 @@ static int dm_suspend(void *handle)
 
amdgpu_dm_irq_suspend(adev);
 
+   WARN_ON(adev->dm.cached_state);
adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
 
dc_set_power_state(
@@ -607,6 +608,9 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
 
ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
 
+   drm_atomic_state_put(adev->dm.cached_state);
+   adev->dm.cached_state = NULL;
+
amdgpu_dm_irq_resume_late(adev);
 
return ret;
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 29/81] drm/amd/display: Add correct retain/release

[sunpeng.li]

From: Harry Wentland 

Needed by objs in dm_atomic_state

Change-Id: I78ccd1fba5022dd686b5df290534b86fa089e30a
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c   | 10 ++
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c |  6 ++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1b69848..c2a6f2e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -658,9 +658,19 @@ void dm_atomic_state_clear(struct drm_atomic_state *s)
 static void dm_atomic_state_free(struct drm_atomic_state *state)
 {
struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
+   int i, j;
 
drm_atomic_state_default_release(state);
 
+   for (i = 0; i < dm_state->set_count; i++) {
+   for (j = 0; j < dm_state->set[i].surface_count; j++) {
+   dc_surface_release(dm_state->set[i].surfaces[j]);
+   }
+   }
+
+   for (i = 0; i < dm_state->set_count; i++)
+   dc_stream_release(dm_state->set[i].stream);
+
kfree(dm_state);
 }
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 52d1922..13fc497 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3038,11 +3038,15 @@ static uint32_t update_in_val_sets_stream(
}
 
val_sets[i].stream = new_stream;
+   dc_stream_retain(new_stream);
crtcs[i] = crtc;
 
if (i == set_count) {
/* nothing found. add new one to the end */
return set_count + 1;
+   } else {
+   /* update. relase old stream */
+   dc_stream_release(old_stream);
}
 
return set_count;
@@ -3064,6 +3068,7 @@ static uint32_t remove_from_val_sets(
return set_count;
}
 
+   dc_stream_release(stream);
set_count--;
 
for (; i < set_count; i++) {
@@ -3168,6 +3173,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 
if (acrtc->stream) {
+   dc_stream_retain(acrtc->stream);
dm_state->set[dm_state->set_count].stream = 
acrtc->stream;
crtc_set[dm_state->set_count] = crtc;
++dm_state->set_count;
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 70/81] drm/amd/display: add line number to reg_wait timeout print

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: I116b51dce6e496ea5bec51131307890f64985755
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc_helper.c  | 6 +++---
 drivers/gpu/drm/amd/display/dc/dm_services.h| 2 +-
 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c 
b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 8ed1440..87b7f6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -129,7 +129,7 @@ uint32_t generic_reg_get(const struct dc_context *ctx,
 uint32_t generic_reg_wait(const struct dc_context *ctx,
uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,
unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
-   const char *func_name)
+   const char *func_name, int line)
 {
uint32_t field_value;
uint32_t reg_val;
@@ -158,8 +158,8 @@ uint32_t generic_reg_wait(const struct dc_context *ctx,
return reg_val;
}
 
-   dm_error("REG_WAIT timeout %dus * %d tries - %s\n",
-   delay_between_poll_us, time_out_num_tries, func_name);
+   dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
+   delay_between_poll_us, time_out_num_tries, func_name, 
line);
 
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h 
b/drivers/gpu/drm/amd/display/dc/dm_services.h
index fb61e33..ea494a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -194,7 +194,7 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
 unsigned int generic_reg_wait(const struct dc_context *ctx,
uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
-   const char *func_name);
+   const char *func_name, int line);
 
 
 /* These macros need to be used with soc15 registers in order to retrieve
diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h 
b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
index 1828d28..77eb728 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
@@ -188,7 +188,7 @@
 #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \
generic_reg_wait(CTX, \
REG(reg_name), FN(reg_name, field), val,\
-   delay_between_poll_us, max_try, __func__)
+   delay_between_poll_us, max_try, __func__, 
__LINE__)
 
 /* macro to update (read, modify, write) register fields
  */
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 50/81] drm/amd/display: Fix context copy memory leak

[sunpeng.li]

From: Corbin McElhanney 

This change corrects an error introduced in 355f123f. Instead of
using the copy constructor to assign the new context, we swap the
pointer.

Change-Id: Ic765e1ce78cd9f731486c1c44ad10c9c95f2c8ad
Signed-off-by: Corbin McElhanney 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 52077d3..4f93029 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -972,7 +972,9 @@ static bool dc_commit_context_no_check(struct dc *dc, 
struct validate_context *c
 
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
-   dc_resource_validate_ctx_copy_construct(context, 
core_dc->current_context);
+   dc_resource_validate_ctx_destruct(core_dc->current_context);
+   dm_free(core_dc->current_context);
+   core_dc->current_context = context;
 
return (result == DC_OK);
 }
@@ -1057,9 +1059,6 @@ bool dc_commit_streams(
 
result = dc_commit_context_no_check(dc, context);
 
-   dc_resource_validate_ctx_destruct(context);
-   dm_free(context);
-
return (result == DC_OK);
 
 fail:
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 64/81] drm/amd/display: Get freesync properties

[sunpeng.li]

From: Harry Wentland 

Eventually we should create proper atomic properties for freesync
but currently freesync is broken and we still have the legacy
properties. Simply return the legacy properties.

Change-Id: Ie5b8fb77e9886ef9d56b321317f78098522d52f6
Signed-off-by: Harry Wentland 
Reviewed-by: Jordan Lazare 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 15a3d01..cdecd2f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1228,6 +1228,7 @@ int amdgpu_dm_connector_atomic_get_property(
struct dm_connector_state *dm_state =
to_dm_connector_state(state);
int ret = -EINVAL;
+   int i;
 
if (property == dev->mode_config.scaling_mode_property) {
switch (dm_state->scaling) {
@@ -1255,14 +1256,14 @@ int amdgpu_dm_connector_atomic_get_property(
} else if (property == adev->mode_info.underscan_property) {
*val = dm_state->underscan_enable;
ret = 0;
-   } else if (property == adev->mode_info.freesync_property) {
-   //TODO
-   *val = 0;
-   ret = 0;
-   } else if (property == adev->mode_info.freesync_capable_property) {
-   //TODO
-   *val = 0;
-   ret = 0;
+   } else if ((property == adev->mode_info.freesync_property) ||
+  (property == adev->mode_info.freesync_capable_property)) {
+   for (i = 0; i < connector->base.properties->count; i++) {
+   if (connector->base.properties->properties[i] == 
property) {
+   *val = connector->base.properties->values[i];
+   ret = 0;
+   }
+   }
}
return ret;
 }
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 56/81] drm/amd/display: Introduce refcount for dc_validate_context

[sunpeng.li]

From: Andrey Grodzovsky 

Linux requires to be able to release allocated context
in case it was never commited.

Change-Id: I6b0faa72c995d77c0bb21ba8aabb9bdc3b0e2770
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c| 64 ++---
 drivers/gpu/drm/amd/display/dc/dc.h |  4 ++
 drivers/gpu/drm/amd/display/dc/inc/core_types.h |  2 +
 3 files changed, 54 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 4f93029..e81c9d5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -423,7 +423,7 @@ static void allocate_dc_stream_funcs(struct core_dc 
*core_dc)
 
 static void destruct(struct core_dc *dc)
 {
-   dc_resource_validate_ctx_destruct(dc->current_context);
+   dc_release_validate_context(dc->current_context);
 
destroy_links(dc);
 
@@ -467,6 +467,8 @@ static bool construct(struct core_dc *dc,
goto val_ctx_fail;
}
 
+   dc->current_context->ref_count++;
+
dc_ctx->cgs_device = init_params->cgs_device;
dc_ctx->driver_context = init_params->driver;
dc_ctx->dc = >public;
@@ -683,6 +685,8 @@ struct validate_context *dc_get_validate_context(
if (context == NULL)
goto context_alloc_fail;
 
+   ++context->ref_count;
+
if (!is_validation_required(core_dc, set, set_count)) {

dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
return context;
@@ -698,8 +702,7 @@ struct validate_context *dc_get_validate_context(
__func__,
result);
 
-   dc_resource_validate_ctx_destruct(context);
-   dm_free(context);
+   dc_release_validate_context(context);
context = NULL;
}
 
@@ -720,6 +723,8 @@ bool dc_validate_resources(
if (context == NULL)
goto context_alloc_fail;
 
+   ++context->ref_count;
+
result = core_dc->res_pool->funcs->validate_with_context(
core_dc, set, set_count, context, NULL);
 
@@ -731,8 +736,7 @@ bool dc_validate_resources(
result);
}
 
-   dc_resource_validate_ctx_destruct(context);
-   dm_free(context);
+   dc_release_validate_context(context);
context = NULL;
 
return result == DC_OK;
@@ -750,11 +754,12 @@ bool dc_validate_guaranteed(
if (context == NULL)
goto context_alloc_fail;
 
+   ++context->ref_count;
+
result = core_dc->res_pool->funcs->validate_guaranteed(
core_dc, stream, context);
 
-   dc_resource_validate_ctx_destruct(context);
-   dm_free(context);
+   dc_release_validate_context(context);
 
 context_alloc_fail:
if (result != DC_OK) {
@@ -972,8 +977,10 @@ static bool dc_commit_context_no_check(struct dc *dc, 
struct validate_context *c
 
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
-   dc_resource_validate_ctx_destruct(core_dc->current_context);
-   dm_free(core_dc->current_context);
+   dc_release_validate_context(core_dc->current_context);
+
+   dc_retain_validate_context(context);
+
core_dc->current_context = context;
 
return (result == DC_OK);
@@ -1045,6 +1052,8 @@ bool dc_commit_streams(
if (context == NULL)
goto context_alloc_fail;
 
+   ++context->ref_count;
+
result = core_dc->res_pool->funcs->validate_with_context(
core_dc, set, stream_count, context, 
core_dc->current_context);
if (result != DC_OK){
@@ -1053,7 +1062,6 @@ bool dc_commit_streams(
__func__,
result);
BREAK_TO_DEBUGGER();
-   dc_resource_validate_ctx_destruct(context);
goto fail;
}
 
@@ -1062,7 +1070,7 @@ bool dc_commit_streams(
return (result == DC_OK);
 
 fail:
-   dm_free(context);
+   dc_release_validate_context(context);
 
 context_alloc_fail:
return (result == DC_OK);
@@ -1155,6 +1163,23 @@ bool dc_commit_surfaces_to_stream(
return true;
 }
 
+void dc_retain_validate_context(struct validate_context *context)
+{
+   ASSERT(context->ref_count > 0);
+   ++context->ref_count;
+}
+
+void dc_release_validate_context(struct validate_context *context)
+{
+   ASSERT(context->ref_count > 0);
+   --context->ref_count;
+
+   if (context->ref_count == 0) {
+   dc_resource_validate_ctx_destruct(context);
+   dm_free(context);
+   }

[PATCH 43/81] drm/amd/display: Fix MPO visual confirm

[sunpeng.li]

From: Anthony Koo 

1. Need to blend non-active area to show visual confirm borders
2. Set number of Visual Confirm lines based on pipe instance
3. Set Different colors representing surface format of bottom most plan

Change-Id: I800a99f80ed2829e3e18fd8b4cb60ff9b396fd30
Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c  |  6 ---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 16 
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h   |  8 ++--
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  8 +++-
 .../drm/amd/display/dc/dce110/dce110_transform_v.c |  4 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 45 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  5 ++-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  2 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 13 ---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h |  1 +
 10 files changed, 77 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 6cd1e93..7b1f249 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -59,12 +59,6 @@ void color_space_to_black_color(
enum dc_color_space colorspace,
struct tg_color *black_color)
 {
-   if (dc->public.debug.surface_visual_confirm) {
-   *black_color =
-   black_color_format[BLACK_COLOR_FORMAT_DEBUG];
-   return;
-   }
-
switch (colorspace) {
case COLOR_SPACE_YCBCR601:
case COLOR_SPACE_YCBCR709:
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 9202bbe..cb02c7c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -399,11 +399,11 @@ static enum pixel_format 
convert_pixel_format_to_dalsurface(
break;
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-   dal_pixel_format = PIXEL_FORMAT_420BPP12;
+   dal_pixel_format = PIXEL_FORMAT_420BPP8;
break;
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
-   dal_pixel_format = PIXEL_FORMAT_420BPP15;
+   dal_pixel_format = PIXEL_FORMAT_420BPP10;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
default:
@@ -433,8 +433,8 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
struct scaler_data *data = _ctx->scl_data;
struct rect surf_src = surface->src_rect;
struct rect clip = { 0 };
-   int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
-   || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
+   int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
+   || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
bool pri_split = pipe_ctx->bottom_pipe &&
pipe_ctx->bottom_pipe->surface == pipe_ctx->surface;
bool sec_split = pipe_ctx->top_pipe &&
@@ -637,8 +637,8 @@ static void calculate_scaling_ratios(struct pipe_ctx 
*pipe_ctx)
pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
 
-   if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12
-   || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP15) {
+   if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP8
+   || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP10) {
pipe_ctx->scl_data.ratios.horz_c.value /= 2;
pipe_ctx->scl_data.ratios.vert_c.value /= 2;
}
@@ -648,8 +648,8 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx 
*pipe_ctx, struct view *r
 {
struct scaler_data *data = _ctx->scl_data;
struct rect src = pipe_ctx->surface->public.src_rect;
-   int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
-   || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
+   int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
+   || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
 
 
if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 94fb930..05f030e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -214,15 +214,15 @@ enum pixel_format {
PIXEL_FORMAT_ARGB2101010_XRBIAS,
PIXEL_FORMAT_FP16,

[PATCH 46/81] drm/amd/display: dal1.1 opp prog update

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: Ieafde1bbc30f5d4dd06136b9940d8c85d8d669f6
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
index eb99c31..de0b631 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
@@ -138,10 +138,11 @@
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \
OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 
mask_sh), \
OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 
mask_sh), \
+   OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
+   OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \
OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \
OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \
OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \
-   OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \
OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \
OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \
@@ -353,8 +354,7 @@
OPP_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
OPP_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
OPP_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
-   OPP_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
-   OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
+   OPP_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh)
 
 #define OPP_DCN10_REG_FIELD_LIST(type) \
type CM_OCSC_C11; \
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 34/81] drm/amd/display: Remove acrtc->stream

[sunpeng.li]

From: Andrey Grodzovsky 

Remove acrtc->stream and move it into dm_crtc_state.
This allows to get rid of dm_atomic_state->dm_set.
Also reuse streams created in atomic_check during
commit.

Change-Id: I8d9868695a3a530c55e7fa934f9d5ea3800dfb8b
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  33 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 411 +++--
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h|   9 +-
 drivers/gpu/drm/amd/display/dc/dc.h|   2 -
 4 files changed, 232 insertions(+), 223 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d0651b6..e5a27ab 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -100,13 +100,16 @@ static u32 dm_vblank_get_counter(struct amdgpu_device 
*adev, int crtc)
return 0;
else {
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
+   struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
+   acrtc->base.state);
 
-   if (NULL == acrtc->stream) {
+
+   if (acrtc_state->stream == NULL) {
DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc);
return 0;
}
 
-   return dc_stream_get_vblank_counter(acrtc->stream);
+   return dc_stream_get_vblank_counter(acrtc_state->stream);
}
 }
 
@@ -119,8 +122,10 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device 
*adev, int crtc,
return -EINVAL;
else {
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
+   struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
+   acrtc->base.state);
 
-   if (NULL == acrtc->stream) {
+   if (acrtc_state->stream ==  NULL) {
DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc);
return 0;
}
@@ -129,7 +134,7 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device 
*adev, int crtc,
 * TODO rework base driver to use values directly.
 * for now parse it back into reg-format
 */
-   dc_stream_get_scanoutpos(acrtc->stream,
+   dc_stream_get_scanoutpos(acrtc_state->stream,
 _blank_start,
 _blank_end,
 _position,
@@ -652,22 +657,12 @@ dm_atomic_state_alloc(struct drm_device *dev)
 void dm_atomic_state_clear(struct drm_atomic_state *state)
 {
struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-   int i, j;
-
-   for (i = 0; i < dm_state->set_count; i++) {
-   for (j = 0; j < dm_state->set[i].surface_count; j++) {
-   dc_surface_release(dm_state->set[i].surfaces[j]);
-   dm_state->set[i].surfaces[j] = NULL;
-   }
 
-   dc_stream_release(dm_state->set[i].stream);
-   dm_state->set[i].stream = NULL;
+   if (dm_state->context) {
+   dc_resource_validate_ctx_destruct(dm_state->context);
+   dm_free(dm_state->context);
+   dm_state->context = NULL;
}
-   dm_state->set_count = 0;
-
-   dc_resource_validate_ctx_destruct(dm_state->context);
-   dm_free(dm_state->context);
-   dm_state->context = NULL;
 
drm_atomic_state_default_clear(state);
 }
@@ -676,7 +671,7 @@ static const struct drm_mode_config_funcs 
amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
.output_poll_changed = amdgpu_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
-   .atomic_commit = drm_atomic_helper_commit,
+   .atomic_commit = amdgpu_dm_atomic_commit,
.atomic_state_alloc = dm_atomic_state_alloc,
.atomic_state_clear = dm_atomic_state_clear,
 };
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 2a5c7b1..750e095 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -87,6 +87,7 @@ static void dm_set_cursor(
struct drm_crtc *crtc = _crtc->base;
int x, y;
int xorigin = 0, yorigin = 0;
+   struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
 
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
@@ -125,13 +126,13 @@ static void dm_set_cursor(
position.y_hotspot = yorigin;
 
if 

[PATCH 39/81] drm/amd/display: Change how we disable pipe split

[sunpeng.li]

From: Eric Yang 

Before this change, pipe split was disabled by bumping up dpp clock
bounding box for DPM level 0 and 1, this allows validation to pass
without splitting at a lower DPM level. This change reverts this
and instead lowers display clock at DPM level 0, this forces
configurations that need pipe split at DPM level 0 to go to
DPM level 1, where they can be driven without split.

Change-Id: I252b4fcf08cfb4ddf7242fab0d7d49c57b015b7d
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 24f8c44..3118c24 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -822,8 +822,7 @@ bool dcn_validate_bandwidth(
v->phyclk_per_state[0] = v->phyclkv_min0p65;
 
if (dc->public.debug.disable_pipe_split) {
-   v->max_dppclk[1] = v->max_dppclk_vnom0p8;
-   v->max_dppclk[0] = v->max_dppclk_vnom0p8;
+   v->max_dispclk[0] = v->max_dppclk_vmin0p65;
}
 
if (v->voltage_override == dcn_bw_v_max0p9) {
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 47/81] drm/amd/display: dal1.1 ipp prog update

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: Ic61bc0018ddc6fa04c065d1520ed7912d9044fd8
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 99 +++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h |  1 +
 2 files changed, 48 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
index a09226c..4910d4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
@@ -69,7 +69,7 @@ enum dcn10_input_csc_select {
INPUT_CSC_SELECT_COMA
 };
 
-static void dcn10_program_input_csc(
+static void ippn10_program_input_csc(
struct input_pixel_processor *ipp,
enum dc_color_space color_space,
enum dcn10_input_csc_select select)
@@ -159,7 +159,7 @@ static void dcn10_program_input_csc(
 }
 
 /*program de gamma RAM B*/
-static void dcn10_ipp_program_degamma_lutb_settings(
+static void ippn10_program_degamma_lutb_settings(
struct input_pixel_processor *ipp,
const struct pwl_params *params)
 {
@@ -266,7 +266,7 @@ static void dcn10_ipp_program_degamma_lutb_settings(
 }
 
 /*program de gamma RAM A*/
-static void dcn10_ipp_program_degamma_luta_settings(
+static void ippn10_program_degamma_luta_settings(
struct input_pixel_processor *ipp,
const struct pwl_params *params)
 {
@@ -372,7 +372,7 @@ static void dcn10_ipp_program_degamma_luta_settings(
CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
 }
 
-static void ipp_power_on_degamma_lut(
+static void ippn10_power_on_degamma_lut(
struct input_pixel_processor *ipp,
bool power_on)
 {
@@ -383,7 +383,7 @@ static void ipp_power_on_degamma_lut(
 
 }
 
-static void ipp_program_degamma_lut(
+static void ippn10_program_degamma_lut(
struct input_pixel_processor *ipp,
const struct pwl_result_data *rgb,
uint32_t num,
@@ -410,25 +410,19 @@ static void ipp_program_degamma_lut(
CM_DGAM_LUT_DATA, rgb[i].delta_green_reg);
REG_SET(CM_DGAM_LUT_DATA, 0,
CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg);
-
}
-
 }
 
-static void dcn10_ipp_enable_cm_block(
+static void ippn10_enable_cm_block(
struct input_pixel_processor *ipp)
 {
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
 
REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
-   if (ippn10->ipp_mask->CM_BYPASS_EN)
-   REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
-   else
-   REG_UPDATE(CM_CONTROL, CM_BYPASS, 0);
+   REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
 }
 
-
-static void dcn10_ipp_full_bypass(struct input_pixel_processor *ipp)
+static void ippn10_full_bypass(struct input_pixel_processor *ipp)
 {
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
 
@@ -450,12 +444,12 @@ static void dcn10_ipp_full_bypass(struct 
input_pixel_processor *ipp)
REG_SET(CM_IGAM_CONTROL, 0, CM_IGAM_LUT_MODE, 0);
 }
 
-static void dcn10_ipp_set_degamma(
+static void ippn10_set_degamma(
struct input_pixel_processor *ipp,
enum ipp_degamma_mode mode)
 {
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
-   dcn10_ipp_enable_cm_block(ipp);
+   ippn10_enable_cm_block(ipp);
 
switch (mode) {
case IPP_DEGAMMA_MODE_BYPASS:
@@ -474,7 +468,7 @@ static void dcn10_ipp_set_degamma(
}
 }
 
-static bool dcn10_cursor_program_control(
+static bool ippn10_cursor_program_control(
struct dcn10_ipp *ippn10,
bool pixel_data_invert,
enum dc_cursor_color_format color_format)
@@ -520,7 +514,7 @@ enum cursor_lines_per_chunk {
CURSOR_LINE_PER_CHUNK_16
 };
 
-static enum cursor_pitch dcn10_get_cursor_pitch(
+static enum cursor_pitch ippn10_get_cursor_pitch(
unsigned int pitch)
 {
enum cursor_pitch hw_pitch;
@@ -544,7 +538,7 @@ static enum cursor_pitch dcn10_get_cursor_pitch(
return hw_pitch;
 }
 
-static enum cursor_lines_per_chunk dcn10_get_lines_per_chunk(
+static enum cursor_lines_per_chunk ippn10_get_lines_per_chunk(
unsigned int cur_width,
enum dc_cursor_color_format format)
 {
@@ -565,13 +559,13 @@ static enum cursor_lines_per_chunk 
dcn10_get_lines_per_chunk(
return line_per_chunk;
 }
 
-static void dcn10_cursor_set_attributes(
+static void ippn10_cursor_set_attributes(
struct input_pixel_processor *ipp,
const struct dc_cursor_attributes *attr)
 {
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
-   enum cursor_pitch hw_pitch = 

[PATCH 55/81] drm/amd/display: change non_dpm0 state's default SR latency

[sunpeng.li]

From: Charlene Liu 

Change-Id: I007042fc257012639bab29c5df6c7c347239dd3d
Signed-off-by: Charlene Liu 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index a1eabc4..0ea0dab 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -37,8 +37,8 @@
 /* Defaults from spreadsheet rev#247 */
 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
/* latencies */
-   .sr_exit_time = 17, /*us*/
-   .sr_enter_plus_exit_time = 19, /*us*/
+   .sr_exit_time = 13, /*us*/
+   .sr_enter_plus_exit_time = 15, /*us*/
.urgent_latency = 4, /*us*/
.dram_clock_change_latency = 17, /*us*/
.write_back_latency = 12, /*us*/
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 36/81] drm/amd/display: update DPM bounding box

[sunpeng.li]

From: Tony Cheng 

value based on STA  target aligned to FCLK for SS corners with 10% margin

also
- group all latency together
- group all voltage state related together

Change-Id: I16619d3d919e021c5ff233b842e62c34f20e27e3
Signed-off-by: Tony Cheng 
Reviewed-by: Eric Yang 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 71 
 1 file changed, 48 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 4486121..58a4b2e 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -36,40 +36,65 @@
 
 /* Defaults from spreadsheet rev#247 */
 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
-   .sr_exit_time = 17, /*us*/ /*update based on HW Request for 
118773*/
+   /* latencies */
+   .sr_exit_time = 17, /*us*/
.sr_enter_plus_exit_time = 19, /*us*/
.urgent_latency = 4, /*us*/
+   .dram_clock_change_latency = 17, /*us*/
.write_back_latency = 12, /*us*/
.percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
-   .max_request_size = 256, /*bytes*/
-   .dcfclkv_max0p9 = 600, /*MHz*/
-   .dcfclkv_nom0p8 = 600, /*MHz*/
-   .dcfclkv_mid0p72 = 300, /*MHz*/
-   .dcfclkv_min0p65 = 300, /*MHz*/
-   .max_dispclk_vmax0p9 = 1086, /*MHz*/
-   .max_dispclk_vnom0p8 = 661, /*MHz*/
-   .max_dispclk_vmid0p72 = 608, /*MHz*/
-   .max_dispclk_vmin0p65 = 608, /*MHz*/
-   .max_dppclk_vmax0p9 = 661, /*MHz*/
-   .max_dppclk_vnom0p8 = 661, /*MHz*/
-   .max_dppclk_vmid0p72 = 435, /*MHz*/
-   .max_dppclk_vmin0p65 = 435, /*MHz*/
-   .socclk = 208, /*MHz*/
+
+   /* below default clocks derived from STA target base on
+* slow-slow corner + 10% margin with voltages aligned to FCLK.
+*
+* Use these value if fused value doesn't make sense as earlier
+* part don't have correct value fused */
+   /* default DCF CLK DPM on RV*/
+   .dcfclkv_max0p9 = 655,  /* MHz, = 3600/5.5 */
+   .dcfclkv_nom0p8 = 626,  /* MHz, = 3600/5.75 */
+   .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
+   .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
+
+   /* default DISP CLK voltage state on RV */
+   .max_dispclk_vmax0p9 = 1108,/* MHz, = 3600/3.25 */
+   .max_dispclk_vnom0p8 = 1029,/* MHz, = 3600/3.5 */
+   .max_dispclk_vmid0p72 = 960,/* MHz, = 3600/3.75 */
+   .max_dispclk_vmin0p65 = 626,/* MHz, = 3600/5.75 */
+
+   /* default DPP CLK voltage state on RV */
+   .max_dppclk_vmax0p9 = 720,  /* MHz, = 3600/5 */
+   .max_dppclk_vnom0p8 = 686,  /* MHz, = 3600/5.25 */
+   .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */
+   .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */
+
+   /* default PHY CLK voltage state on RV */
+   .phyclkv_max0p9 = 900, /*MHz*/
+   .phyclkv_nom0p8 = 847, /*MHz*/
+   .phyclkv_mid0p72 = 800, /*MHz*/
+   .phyclkv_min0p65 = 600, /*MHz*/
+
+   /* BW depend on FCLK, MCLK, # of channels */
+   /* dual channel BW */
.fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
-   .fabric_and_dram_bandwidth_vnom0p8 = 34.1f, /*GB/s*/
-   .fabric_and_dram_bandwidth_vmid0p72 = 29.8f, /*GB/s*/
+   .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
+   .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
.fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
-   .phyclkv_max0p9 = 810, /*MHz*/
-   .phyclkv_nom0p8 = 810, /*MHz*/
-   .phyclkv_mid0p72 = 540, /*MHz*/
-   .phyclkv_min0p65 = 540, /*MHz*/
+   /* single channel BW
+   .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
+   .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
+   .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
+   .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
+   */
+
+   .number_of_channels = 2,
+
+   .socclk = 208, /*MHz*/
.downspreading = 0.5f, /*%*/
.round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
.urgent_out_of_order_return_per_channel = 256, /*bytes*/
-   .number_of_channels = 2,
.vmm_page_size = 4096, /*bytes*/
-   

[PATCH 59/81] drm/amd/display: Fix eDP power isn't off when lid close

[sunpeng.li]

From: John Wu 

Change-Id: I7acda62e64f358f3a19040cded97e1278b98e5a5
Signed-off-by: John Wu 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 4f46ff1..0092e70 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -112,8 +112,10 @@ void dp_disable_link_phy(struct core_link *link, enum 
signal_type signal)
if (!link->wa_flags.dp_keep_receiver_powered)
dp_receiver_power_ctrl(link, false);
 
-   if (signal == SIGNAL_TYPE_EDP)
+   if (signal == SIGNAL_TYPE_EDP) {
link->link_enc->funcs->backlight_control(link->link_enc, false);
+   link->link_enc->funcs->power_control(link->link_enc, false);
+   }
 
link->link_enc->funcs->disable_output(link->link_enc, signal);
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 03/81] drm/amd/display: Make mode_config_funcs const

[sunpeng.li]

From: Harry Wentland 

Change-Id: I33cb540471368b4013261b658770e6207870f262
Signed-off-by: Harry Wentland 
Reviewed-by: Andrey Grodzovsky 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bd01a45..e856f62 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -634,8 +634,7 @@ const struct amdgpu_ip_block_version dm_ip_block =
.funcs = _dm_funcs,
 };
 
-/* TODO: it is temporary non-const, should fixed later */
-static struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
+static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
.output_poll_changed = amdgpu_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 07/81] drm/amd/display: fix dcn pipe reset sequence

[sunpeng.li]

From: Dmytro Laktyushkin 

This change fixes dcn10 front end reset sequence. Previously we
would reset front end during flip which led to issues
in certain MPO and 4k/5k scenarios. We would also never properly
power gate our front end.

Change-Id: I54d1759c8024eb150e35ee29d29f396b69668d1d
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Charlene Liu 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c|   2 +-
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  19 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  22 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |   7 +
 drivers/gpu/drm/amd/display/dc/dc.h|   3 -
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  17 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 226 ++---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  17 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |   4 +-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  |   6 +-
 .../amd/display/dc/dcn10/dcn10_timing_generator.h  |   4 +
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h|   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   2 +-
 13 files changed, 155 insertions(+), 175 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 10ffe7f..fb5afba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2544,7 +2544,7 @@ static void amdgpu_dm_do_flip(
surface_updates->flip_addr = 
 
 
-   dc_update_surfaces_for_stream(adev->dm.dc, surface_updates, 1, 
acrtc->stream);
+   dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, 
acrtc->stream, NULL);
 
DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
 __func__,
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 3ec702f..00961bc 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -511,12 +511,14 @@ static void split_stream_across_pipes(
struct pipe_ctx *primary_pipe,
struct pipe_ctx *secondary_pipe)
 {
+   int pipe_idx = secondary_pipe->pipe_idx;
+
if (!primary_pipe->surface)
return;
 
-   secondary_pipe->stream = primary_pipe->stream;
-   secondary_pipe->tg = primary_pipe->tg;
+   *secondary_pipe = *primary_pipe;
 
+   secondary_pipe->pipe_idx = pipe_idx;
secondary_pipe->mpcc = pool->mpcc[secondary_pipe->pipe_idx];
secondary_pipe->mi = pool->mis[secondary_pipe->pipe_idx];
secondary_pipe->ipp = pool->ipps[secondary_pipe->pipe_idx];
@@ -528,8 +530,6 @@ static void split_stream_across_pipes(
}
primary_pipe->bottom_pipe = secondary_pipe;
secondary_pipe->top_pipe = primary_pipe;
-   secondary_pipe->surface = primary_pipe->surface;
-   secondary_pipe->pipe_dlg_param = primary_pipe->pipe_dlg_param;
 
resource_build_scaling_params(primary_pipe);
resource_build_scaling_params(secondary_pipe);
@@ -1011,10 +1011,13 @@ bool dcn_validate_bandwidth(
dcn_bw_calc_rq_dlg_ttu(dc, v, 
hsplit_pipe);
} else if (hsplit_pipe && hsplit_pipe->surface 
== pipe->surface) {
/* merge previously split pipe */
-   if (pipe->bottom_pipe->bottom_pipe)
-   
pipe->bottom_pipe->bottom_pipe->top_pipe = pipe;
-   memset(pipe->bottom_pipe, 0, 
sizeof(*pipe->bottom_pipe));
-   pipe->bottom_pipe = 
pipe->bottom_pipe->bottom_pipe;
+   pipe->bottom_pipe = 
hsplit_pipe->bottom_pipe;
+   if (hsplit_pipe->bottom_pipe)
+   
hsplit_pipe->bottom_pipe->top_pipe = pipe;
+   hsplit_pipe->surface = NULL;
+   hsplit_pipe->stream = NULL;
+   hsplit_pipe->top_pipe = NULL;
+   hsplit_pipe->bottom_pipe = NULL;
resource_build_scaling_params(pipe);
}
/* for now important to do this after pipe 
split for building e2e params */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 18fde50..2f481ef 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -963,11 

[PATCH 40/81] drm/amd/display: call pplib to update clocks

[sunpeng.li]

From: Eric Yang 

Allow pplib to update fclk and dcfclk for different voltage levels.
PPlib's values for dispclk and phyclk is not correct, so we are not
getting it from them. fclk is currently not used correctly, although
does not effect the actual fclk we request.

Change-Id: I649ae641f5367507f4a626be9a4f6358e08385fe
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 46 +++-
 1 file changed, 4 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 3118c24..a1eabc4 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1226,28 +1226,13 @@ unsigned int dcn_find_dcfclk_suits_all(
 void dcn_bw_update_from_pplib(struct core_dc *dc)
 {
struct dc_context *ctx = dc->ctx;
-   struct dm_pp_clock_levels_with_latency clks = {0};
-   struct dm_pp_clock_levels_with_voltage clks2 = {0};
+   struct dm_pp_clock_levels_with_voltage clks = {0};
 
kernel_fpu_begin();
 
+   /* TODO: This is not the proper way to obtain 
fabric_and_dram_bandwidth, should be min(fclk, memclk) */
+
if (dm_pp_get_clock_levels_by_type_with_voltage(
-   ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, ) &&
-   clks2.num_levels >= 3) {
-   dc->dcn_soc.max_dispclk_vmin0p65 = clks2.data[0].clocks_in_khz 
/ 1000.0;
-   dc->dcn_soc.max_dispclk_vmid0p72 = clks2.data[clks2.num_levels 
- 3].clocks_in_khz / 1000.0;
-   dc->dcn_soc.max_dispclk_vnom0p8 = clks2.data[clks2.num_levels - 
2].clocks_in_khz / 1000.0;
-   dc->dcn_soc.max_dispclk_vmax0p9 = clks2.data[clks2.num_levels - 
1].clocks_in_khz / 1000.0;
-   } else
-   BREAK_TO_DEBUGGER();
-/*
-   if (dm_pp_get_clock_levels_by_type_with_latency(
-   ctx, DM_PP_CLOCK_TYPE_MEMORY_CLK, ) &&
-   clks.num_levels != 0) {
-   //this  is to get DRAM data_rate
-   //FabricAndDRAMBandwidth = min(64*FCLK , Data rate * 
single_Channel_Width * number of channels);
-   }*/
-   if (dm_pp_get_clock_levels_by_type_with_latency(
ctx, DM_PP_CLOCK_TYPE_FCLK, ) &&
clks.num_levels != 0) {
ASSERT(clks.num_levels >= 3);
@@ -1265,7 +1250,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc)
(clks.data[clks.num_levels - 1].clocks_in_khz / 
1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
} else
BREAK_TO_DEBUGGER();
-   if (dm_pp_get_clock_levels_by_type_with_latency(
+   if (dm_pp_get_clock_levels_by_type_with_voltage(
ctx, DM_PP_CLOCK_TYPE_DCFCLK, ) &&
clks.num_levels >= 3) {
dc->dcn_soc.dcfclkv_min0p65 = clks.data[0].clocks_in_khz / 
1000.0;
@@ -1274,30 +1259,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc)
dc->dcn_soc.dcfclkv_max0p9 = clks.data[clks.num_levels - 
1].clocks_in_khz / 1000.0;
} else
BREAK_TO_DEBUGGER();
-   if (dm_pp_get_clock_levels_by_type_with_voltage(
-   ctx, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, ) &&
-   clks2.num_levels >= 3) {
-   dc->dcn_soc.phyclkv_min0p65 = clks2.data[0].clocks_in_khz / 
1000.0;
-   dc->dcn_soc.phyclkv_mid0p72 = clks2.data[clks2.num_levels - 
3].clocks_in_khz / 1000.0;
-   dc->dcn_soc.phyclkv_nom0p8 = clks2.data[clks2.num_levels - 
2].clocks_in_khz / 1000.0;
-   dc->dcn_soc.phyclkv_max0p9 = clks2.data[clks2.num_levels - 
1].clocks_in_khz / 1000.0;
-   } else
-   BREAK_TO_DEBUGGER();
-   if (dm_pp_get_clock_levels_by_type_with_latency(
-   ctx, DM_PP_CLOCK_TYPE_DPPCLK, ) &&
-   clks.num_levels >= 3) {
-   dc->dcn_soc.max_dppclk_vmin0p65 = clks.data[0].clocks_in_khz / 
1000.0;
-   dc->dcn_soc.max_dppclk_vmid0p72 = clks.data[clks.num_levels - 
3].clocks_in_khz / 1000.0;
-   dc->dcn_soc.max_dppclk_vnom0p8 = clks.data[clks.num_levels - 
2].clocks_in_khz / 1000.0;
-   dc->dcn_soc.max_dppclk_vmax0p9 = clks.data[clks.num_levels - 
1].clocks_in_khz / 1000.0;
-   }
 
-   if (dm_pp_get_clock_levels_by_type_with_latency(
-   ctx, DM_PP_CLOCK_TYPE_SOCCLK, ) &&
-   clks.num_levels >= 3) {
-   dc->dcn_soc.socclk = clks.data[0].clocks_in_khz / 1000.0;
-   } else
-   BREAK_TO_DEBUGGER();
kernel_fpu_end();
 }
 
-- 
2.7.4

[PATCH 28/81] drm/amd/display: Hook dm private state into atomic_check

[sunpeng.li]

From: Harry Wentland 

Change-Id: Ia39ff138e644e6cbe0acaef755a8c77bb5c5919c
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 64 +++---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h|  5 ++
 2 files changed, 37 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index ed48c5e..52d1922 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3126,15 +3126,14 @@ static int do_aquire_global_lock(
 int amdgpu_dm_atomic_check(struct drm_device *dev,
struct drm_atomic_state *state)
 {
+   struct dm_atomic_state *dm_state;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
struct drm_plane *plane;
struct drm_plane_state *plane_state;
int i, j;
int ret;
-   int set_count;
int new_stream_count;
-   struct dc_validation_set set[MAX_STREAMS] = {{ 0 }};
struct dc_stream *new_streams[MAX_STREAMS] = { 0 };
struct drm_crtc *crtc_set[MAX_STREAMS] = { 0 };
struct amdgpu_device *adev = dev->dev_private;
@@ -3159,17 +3158,19 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
ret = -EINVAL;
 
+   dm_state = to_dm_atomic_state(state);
+
/* copy existing configuration */
new_stream_count = 0;
-   set_count = 0;
+   dm_state->set_count = 0;
list_for_each_entry(crtc, >mode_config.crtc_list, head) {
 
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 
if (acrtc->stream) {
-   set[set_count].stream = acrtc->stream;
-   crtc_set[set_count] = crtc;
-   ++set_count;
+   dm_state->set[dm_state->set_count].stream = 
acrtc->stream;
+   crtc_set[dm_state->set_count] = crtc;
+   ++dm_state->set_count;
}
}
 
@@ -3198,16 +3199,16 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
struct dc_stream *new_stream = NULL;
struct drm_connector_state *conn_state = NULL;
-   struct dm_connector_state *dm_state = NULL;
+   struct dm_connector_state *dm_conn_state = NULL;
 
if (aconnector) {
conn_state = 
drm_atomic_get_connector_state(state, >base);
if (IS_ERR(conn_state))
return ret;
-   dm_state = to_dm_connector_state(conn_state);
+   dm_conn_state = 
to_dm_connector_state(conn_state);
}
 
-   new_stream = create_stream_for_sink(aconnector, 
_state->mode, dm_state);
+   new_stream = create_stream_for_sink(aconnector, 
_state->mode, dm_conn_state);
 
/*
 * we can have no stream on ACTION_SET if a display
@@ -3222,10 +3223,10 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
}
 
new_streams[new_stream_count] = new_stream;
-   set_count = update_in_val_sets_stream(
-   set,
+   dm_state->set_count = update_in_val_sets_stream(
+   dm_state->set,
crtc_set,
-   set_count,
+   dm_state->set_count,
acrtc->stream,
new_stream,
crtc);
@@ -3238,9 +3239,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
/* i.e. reset mode */
if (acrtc->stream) {
-   set_count = remove_from_val_sets(
-   set,
-   set_count,
+   dm_state->set_count = remove_from_val_sets(
+   dm_state->set,
+   dm_state->set_count,
acrtc->stream);
aquire_global_lock = true;
}
@@ -3291,10 +3292,10 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
}
 
new_streams[new_stream_count] = new_stream;
-   set_count = update_in_val_sets_stream(
-   set,

[PATCH 18/81] drm/amd/display: Fix for hdmi frame pack stereo

[sunpeng.li]

From: Vitaly Prosyak 

Change-Id: Ifac9634dfbca459afe63fc1e2396ac060c32f7c4
Signed-off-by: Vitaly Prosyak 
Reviewed-by: Charlene Liu 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |   10 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c   |3 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |2 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |   11 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 1615 +++-
 5 files changed, 574 insertions(+), 1067 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 00961bc..4486121 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -987,7 +987,15 @@ bool dcn_validate_bandwidth(
if (pipe->surface) {
struct pipe_ctx *hsplit_pipe = 
pipe->bottom_pipe;
 
-   if (v->dpp_per_plane[input_idx] == 2) {
+   if (v->dpp_per_plane[input_idx] == 2 ||
+   ((pipe->stream->public.view_format ==
+ VIEW_3D_FORMAT_SIDE_BY_SIDE ||
+ pipe->stream->public.view_format ==
+ VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
+   
(pipe->stream->public.timing.timing_3d_format ==
+TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
+
pipe->stream->public.timing.timing_3d_format ==
+TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
if (hsplit_pipe && hsplit_pipe->surface 
== pipe->surface) {
/* update previously split pipe 
*/

hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a9ddd07..1d2e421e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -967,7 +967,6 @@ bool dc_commit_streams(

DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
 
core_dc->hwss.apply_ctx_for_surface(core_dc, surface, 
context);
-   dc_enable_stereo(dc, context, streams, stream_count);
}
 
CONN_MSG_MODE(sink->link, "{%ux%u, %ux%u@%u, %ux%u@%uKhz}",
@@ -982,7 +981,7 @@ bool dc_commit_streams(
context->streams[i]->public.timing.v_total,
context->streams[i]->public.timing.pix_clk_khz);
}
-
+   dc_enable_stereo(dc, context, streams, stream_count);
dc_resource_validate_ctx_destruct(core_dc->current_context);
dm_free(core_dc->current_context);
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 04579d0..9202bbe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -626,7 +626,7 @@ static void calculate_scaling_ratios(struct pipe_ctx 
*pipe_ctx)
 
if (stream->public.view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
pipe_ctx->scl_data.ratios.horz.value *= 2;
-   else if (surface->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
+   else if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
pipe_ctx->scl_data.ratios.vert.value *= 2;
 
pipe_ctx->scl_data.ratios.vert.value = div64_s64(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index cc67707..d38570e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -891,7 +891,6 @@ static void reset_hw_ctx_wrap(
}
 }
 
-
 static bool patch_address_for_sbs_tb_stereo(
struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
 {
@@ -904,11 +903,17 @@ static bool patch_address_for_sbs_tb_stereo(
 pipe_ctx->stream->public.timing.timing_3d_format ==
 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
*addr = surface->public.address.grph_stereo.left_addr;
-   surface->public.address.grph_stereo.left_addr =\
+   surface->public.address.grph_stereo.left_addr =
surface->public.address.grph_stereo.right_addr;
return true;
+   } else {
+   if (pipe_ctx->stream->public.view_format != VIEW_3D_FORMAT_NONE 
&&

[PATCH 23/81] drm/amd/display: Enable ipp compilation

[sunpeng.li]

From: Dmytro Laktyushkin 

Update relevant registers

Change-Id: Ic52d3a87ac72420b9919e0ba81d936e5137a120c
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c   | 19 ++---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h   | 91 +++---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  6 +-
 3 files changed, 54 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
index 1e7a55d..a09226c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
@@ -421,7 +421,10 @@ static void dcn10_ipp_enable_cm_block(
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
 
REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
-   REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
+   if (ippn10->ipp_mask->CM_BYPASS_EN)
+   REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
+   else
+   REG_UPDATE(CM_CONTROL, CM_BYPASS, 0);
 }
 
 
@@ -484,7 +487,7 @@ static bool dcn10_cursor_program_control(
 
REG_UPDATE_2(CURSOR0_CONTROL,
CUR0_MODE, color_format,
-   CUR0_INVERT_MODE, 0);
+   CUR0_EXPANSION_MODE, 0);
 
if (color_format == CURSOR_MODE_MONO) {
/* todo: clarify what to program these to */
@@ -501,18 +504,6 @@ static bool dcn10_cursor_program_control(
ALPHA_EN, 1,
FORMAT_EXPANSION_MODE, 0);
 
-   REG_UPDATE(CURSOR0_CONTROL,
-   CUR0_EXPANSION_MODE, 0);
-
-   if (0 /*attributes->attribute_flags.bits.MIN_MAX_INVERT*/) {
-   REG_UPDATE(CURSOR0_CONTROL,
-   CUR0_MAX,
-   0 /* TODO */);
-   REG_UPDATE(CURSOR0_CONTROL,
-   CUR0_MIN,
-   0 /* TODO */);
-   }
-
return true;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
index 5119935..d608abf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
@@ -31,7 +31,7 @@
 #define TO_DCN10_IPP(ipp)\
container_of(ipp, struct dcn10_ipp, base)
 
-#define IPP_DCN10_REG_LIST(id) \
+#define IPP_REG_LIST_DCN(id) \
SRI(CM_ICSC_CONTROL, CM, id), \
SRI(CM_ICSC_C11_C12, CM, id), \
SRI(CM_ICSC_C13_C14, CM, id), \
@@ -39,12 +39,6 @@
SRI(CM_ICSC_C23_C24, CM, id), \
SRI(CM_ICSC_C31_C32, CM, id), \
SRI(CM_ICSC_C33_C34, CM, id), \
-   SRI(CM_COMA_C11_C12, CM, id), \
-   SRI(CM_COMA_C13_C14, CM, id), \
-   SRI(CM_COMA_C21_C22, CM, id), \
-   SRI(CM_COMA_C23_C24, CM, id), \
-   SRI(CM_COMA_C31_C32, CM, id), \
-   SRI(CM_COMA_C33_C34, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
@@ -86,22 +80,31 @@
SRI(CM_DGAM_RAMA_REGION_12_13, CM, id), \
SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
SRI(CM_MEM_PWR_CTRL, CM, id), \
-   SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
-   SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
-   SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
SRI(CM_DGAM_LUT_INDEX, CM, id), \
SRI(CM_DGAM_LUT_DATA, CM, id), \
SRI(CM_CONTROL, CM, id), \
SRI(CM_DGAM_CONTROL, CM, id), \
-   SRI(CM_IGAM_CONTROL, CM, id), \
+   SRI(FORMAT_CONTROL, CNVC_CFG, id), \
SRI(DPP_CONTROL, DPP_TOP, id), \
SRI(CURSOR_SETTINS, HUBPREQ, id), \
SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
-   SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
-   SRI(FORMAT_CONTROL, CNVC_CFG, id), \
+   SRI(CURSOR0_COLOR1, CNVC_CUR, id)
+
+#define IPP_REG_LIST_DCN10(id) \
+   IPP_REG_LIST_DCN(id), \
+   SRI(CM_IGAM_CONTROL, CM, id), \
+   SRI(CM_COMA_C11_C12, CM, id), \
+   SRI(CM_COMA_C13_C14, CM, id), \
+   SRI(CM_COMA_C21_C22, CM, id), \
+   SRI(CM_COMA_C23_C24, CM, id), \
+   SRI(CM_COMA_C31_C32, CM, id), \
+   SRI(CM_COMA_C33_C34, CM, id), \
+   SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
+   SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
+   SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
SRI(CURSOR_SIZE, CURSOR, id), \
@@ -113,7 +116,7 @@
 #define IPP_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
 

[PATCH 77/81] drm/amd/display: fix aviInfoFrame bar Info and add set_avMute

[sunpeng.li]

From: Charlene Liu 

Change-Id: I8933d7bafe3b3cc18bc5aa41cedd89879d59de5a
Signed-off-by: Charlene Liu 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  | 10 ++
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 37 ++
 .../drm/amd/display/dc/dce/dce_stream_encoder.c| 13 +++-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 13 ++--
 .../amd/display/dc/dce110/dce110_hw_sequencer.h|  1 +
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  3 +-
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|  1 +
 .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h |  3 ++
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  2 ++
 .../display/dc/virtual/virtual_stream_encoder.c|  4 +++
 10 files changed, 77 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fed38fb..036d22f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1911,3 +1911,13 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
 }
 
+void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
+{
+   struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc);
+
+   if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
+   return;
+
+   core_dc->hwss.set_avmute(pipe_ctx, enable);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 00fed61..d196d0d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1607,6 +1607,8 @@ static void set_avi_info_frame(
uint8_t *check_sum = NULL;
uint8_t byte_index = 0;
union hdmi_info_packet *hdmi_info = 
_frame.avi_info_packet.info_packet_hdmi;
+   unsigned int vic = pipe_ctx->stream->public.timing.vic;
+   enum dc_timing_3d_format format;
 
color_space = pipe_ctx->stream->public.output_color_space;
if (color_space == COLOR_SPACE_UNKNOWN)
@@ -1661,8 +1663,7 @@ static void set_avi_info_frame(
 
/* C0, C1 : Colorimetry */
if (color_space == COLOR_SPACE_YCBCR709 ||
-   color_space == COLOR_SPACE_YCBCR709_LIMITED ||
-   color_space == COLOR_SPACE_2020_YCBCR)
+   color_space == COLOR_SPACE_YCBCR709_LIMITED)
hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
else if (color_space == COLOR_SPACE_YCBCR601 ||
color_space == COLOR_SPACE_YCBCR601_LIMITED)
@@ -1722,9 +1723,29 @@ static void set_avi_info_frame(
hdmi_info->bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
}
-
-   hdmi_info->bits.VIC0_VIC7 =
-   stream->public.timing.vic;
+   ///VIC
+   format = stream->public.timing.timing_3d_format;
+   /*todo, add 3DStereo support*/
+   if (format != TIMING_3D_FORMAT_NONE) {
+   // Based on HDMI specs hdmi vic needs to be converted to cea 
vic when 3D is enabled
+   switch (pipe_ctx->stream->public.timing.hdmi_vic) {
+   case 1:
+   vic = 95;
+   break;
+   case 2:
+   vic = 94;
+   break;
+   case 3:
+   vic = 93;
+   break;
+   case 4:
+   vic = 98;
+   break;
+   default:
+   break;
+   }
+   }
+   hdmi_info->bits.VIC0_VIC7 = vic;
 
/* pixel repetition
 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
@@ -1737,7 +1758,7 @@ static void set_avi_info_frame(
 * barLeft:   Pixel Number of End of Left Bar.
 * barRight:  Pixel Number of Start of Right Bar. */
hdmi_info->bits.bar_top = stream->public.timing.v_border_top;
-   hdmi_info->bits.bar_bottom = (stream->public.timing.v_border_top
+   hdmi_info->bits.bar_bottom = (stream->public.timing.v_total
- stream->public.timing.v_border_bottom + 1);
hdmi_info->bits.bar_left  = stream->public.timing.h_border_left;
hdmi_info->bits.bar_right = (stream->public.timing.h_total
@@ -1776,6 +1797,10 @@ static void set_vendor_info_packet(
uint8_t checksum = 0;
uint32_t i = 0;
enum dc_timing_3d_format format;
+   // Can be different depending on packet content /*todo*/
+   // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
+
+   

[PATCH 60/81] drm/amd/display: change order of HUBP and MPC disable according to HW guide

[sunpeng.li]

From: Tony Cheng 

blank hubp first before disconnect MPC

Change-Id: Ibd593dead3fda16e47a79b3c20403b6904aa3981
Signed-off-by: Tony Cheng 
Reviewed-by: Eric Yang 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +++---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |  4 +++-
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ac0d62c..0e90e6c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -477,9 +477,14 @@ static void reset_front_end(
if (mpcc->opp_id == 0xf)
return;
 
-   mi->funcs->dcc_control(mi, false, false);
tg->funcs->lock(tg);
 
+   mi->funcs->dcc_control(mi, false, false);
+   mi->funcs->set_blank(mi, true);
+   REG_WAIT(DCHUBP_CNTL[fe_idx],
+   HUBP_NO_OUTSTANDING_REQ, 1,
+   1, 200);
+
mpcc_cfg.opp_id = 0xf;
mpcc_cfg.top_dpp_id = 0xf;
mpcc_cfg.bot_mpcc_id = 0xf;
@@ -491,8 +496,7 @@ static void reset_front_end(
REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], 
VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 2, 20);
 
mpcc->funcs->wait_for_idle(mpcc);
-   mi->funcs->set_blank(mi, true);
-   REG_WAIT(DCHUBP_CNTL[fe_idx], HUBP_NO_OUTSTANDING_REQ, 1, 2, 
20);
+
REG_UPDATE(HUBP_CLK_CNTL[fe_idx], HUBP_CLOCK_ENABLE, 0);
REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 1c9d5e9..9875d81 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -117,7 +117,9 @@ static void dcn10_mpcc_wait_idle(struct mpcc *mpcc)
 {
struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc);
 
-   REG_WAIT(MPCC_STATUS, MPCC_BUSY, 0, 1000, 1000);
+   REG_WAIT(MPCC_STATUS,
+   MPCC_BUSY, 0,
+   1000, 1000);
 }
 
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 72/81] drm/amd/display: Move view port registers and programming to memory input.

[sunpeng.li]

From: Vitaly Prosyak 

Change-Id: I286753b972379133fa2da57b53a39001c9cf5aa5
Signed-off-by: Vitaly Prosyak 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   | 36 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   | 36 -
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  2 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 37 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 36 +
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |  4 +++
 6 files changed, 78 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 85d3ca3..fff81a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -452,37 +452,6 @@ static void dpp_set_scl_filter(
}
 }
 
-static void dpp_set_viewport(
-   struct dcn10_dpp *xfm,
-   const struct rect *viewport,
-   const struct rect *viewport_c)
-{
-   REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
-   PRI_VIEWPORT_WIDTH, viewport->width,
-   PRI_VIEWPORT_HEIGHT, viewport->height);
-
-   REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
-   PRI_VIEWPORT_X_START, viewport->x,
-   PRI_VIEWPORT_Y_START, viewport->y);
-
-   /*for stereo*/
-   REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
-   SEC_VIEWPORT_WIDTH, viewport->width,
-   SEC_VIEWPORT_HEIGHT, viewport->height);
-
-   REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
-   SEC_VIEWPORT_X_START, viewport->x,
-   SEC_VIEWPORT_Y_START, viewport->y);
-
-   /* DC supports NV12 only at the moment */
-   REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
-   PRI_VIEWPORT_WIDTH_C, viewport_c->width,
-   PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
-
-   REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
-   PRI_VIEWPORT_X_START_C, viewport_c->x,
-   PRI_VIEWPORT_Y_START_C, viewport_c->y);
-}
 
 static int get_lb_depth_bpc(enum lb_pixel_depth depth)
 {
@@ -616,8 +585,6 @@ void dpp_set_scaler_auto_scale(
 
REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
 
-   dpp_set_viewport(xfm, _data->viewport, _data->viewport_c);
-
if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
return;
 
@@ -762,9 +729,6 @@ static void dpp_set_scaler_manual_scale(
/* SCL mode */
REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
 
-   /* Viewport */
-   dpp_set_viewport(xfm, _data->viewport, _data->viewport_c);
-
if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
return;
/* LB */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 9936435..c1124e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -59,12 +59,6 @@
SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
SRI(DSCL_2TAP_CONTROL, DSCL, id), \
-   SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
-   SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
-   SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
-   SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
-   SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
-   SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
SRI(MPC_SIZE, DSCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
@@ -144,18 +138,6 @@
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, 
mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, 
mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
-   TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, 
mask_sh),\
-   TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, 
mask_sh),\
-   TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
-   TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, 
mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, 
mask_sh),\
-   

[PATCH 00/81] DC Linux Patches Jul 25, 2017

[sunpeng.li]

From: "Leo (Sunpeng) Li" 

* Start of cleanup for midlayer abstractions
* Laying down foundations for FBC
* Future-proofing of DCN functions
* Pipe splitting features for Raven
* General bug fixes for Raven

Amy Zhang (1):
  drm/amd/display: Re-enable Vsync Interrupts for Gradual Refresh Ramp

Andrey Grodzovsky (17):
  drm/amd/display: Create dm_crtc_state stubs.
  drm/amd/display: Move dm_plane_state to DAL header.
  drm/amd/display: Remove unblanaced drm_vblank_put.
  drm/amd/display: Update atomic state hooks.
  drm/amd/display: Remove acrtc->stream
  drm/amd/display: Undo dc_update_surfaces_and_stream change.
  drm/amd/display: Refactor dc_commit_streams
  drm/amd/display: Leave all validate_ctx life cycle management to DC.
  drm/amd/display: Clean dm_plane_state hooks.
  drm/amd/display: Attach surface to dm_plane_state.
  drm/amd/display: Introduce refcount for dc_validate_context
  drm/amd/display: Skip DC validation for flips and cursor.
  drm/amd/display: Release dm_state->context when state is cleared.
  drm/amd/display: dc_validate_ctx refocunt fixes.
  drm/amd/display: Preserve refcount for S3 case.
  drm/amd/display: Release cached atomic state in S3.
  drm/amd/display: Fix S3 gamma corruption.

Anthony Koo (3):
  drm/amd/display: add hyst frames for fixed refresh
  drm/amd/display: Fix MPO visual confirm
  drm/amd/display: Add regkey for DRR control for internal panel

Bhawanpreet Lakha (3):
  drm/amd/display: remove unneeded FBC hw programming code
  drm/amd/display: Connect DC resource to FBC compressor
  drm/amd/display: Set static screen register for stoney/carrizo

Charlene Liu (5):
  drm/amd/display: Enabling VSR on 4K display causes black screen
  drm/amd/display: change non_dpm0 state's default SR latency
  drm/amd/display: fix 4k@30 with 10bit deep color and avi for BT2020
  drm/amd/display: fix DVI connected to HDMI connector max tmds clock
  drm/amd/display: fix aviInfoFrame bar Info and add set_avMute

Corbin McElhanney (3):
  drm/amd/display: Add clock info struct
  drm/amd/display: Add extra mode and clock info to DTN logs
  drm/amd/display: Fix context copy memory leak

Ding Wang (1):
  drm/amd/display: link training fallback actions

Dmytro Laktyushkin (17):
  drm/amd/display: fix dcn pipe reset sequence
  drm/amd/display: enable diags compilation
  drm/amd/display: Change max OPP
  drm/amd/display: Rename DCN TG specific function prefixes to tg
  drm/amd/display: Rename DCN mem input specific function prefixes to
min.
  drm/amd/display: Rename DCN opp specific function prefixes to oppn10
  drm/amd/display: Enable ipp compilation
  drm/amd/display: Remove SMU_INTERRUPT_CONTROL
  drm/amd/display: refactor dcn10 hw_sequencer to new reg access style
  drm/amd/display: get dal1.1 to run
  drm/amd/display: minor dcn10_hwseq clean up/refactor
  drm/amd/display: dal1.1 opp prog update
  drm/amd/display: dal1.1 ipp prog update
  drm/amd/display: dal1.1 xfm prog update
  drm/amd/display: dal1.1 hwseq prog update
  drm/amd/display: add line number to reg_wait timeout print
  drm/amd/display: hwseq init sequence update

Eric Yang (7):
  drm/amd/display: move number of memory channel calc out of pplib call
  drm/amd/display: block modes that require read bw greater than 30%
  drm/amd/display: Change how we disable pipe split
  drm/amd/display: call pplib to update clocks
  drm/amd/display: fix mpo exit hang
  drm/amd/display: properly turn off unused mpc before front end
programming
  drm/amd/display: powergate fe of reused pipes to reset ttu

Harry Wentland (8):
  drm/amd/display: Make mode_config_funcs const
  drm/amd/display: Create dm_atomic_state
  drm/amd/display: Hook dm private state into atomic_check
  drm/amd/display: Add correct retain/release
  drm/amd/display: Commit validation set from state
  drm/amd/display: Add validate_context to atomic_state
  drm/amd/display: Use validate_context from atomic_check in commit
  drm/amd/display: Get freesync properties

John Wu (1):
  drm/amd/display: Fix eDP power isn't off when lid close

Ken Chalmers (1):
  drm/amd/display: RV stereo support

Leo (Sunpeng) Li (3):
  drm/amd/display: Move drm_get_vblank from legacy code
  drm/amd/display: Flattening to dc_transfer_func
  drm/amd/display: Do not release state objects on atomic check fail

Tony Cheng (5):
  drm/amd/display: update DPM bounding box
  drm/amd/display: change order of HUBP and MPC disable according to HW
guide
  drm/amd/display: avoid disabling opp clk before hubp is blanked.
  drm/amd/display: ensure OTG is locked before proceeding
  drm/amd/display: revert order change of HUBP and MPC disable

Vikrant Mhaske (1):
  drm/amd/display: Coding for backcompatible tiling support for Gfx7

Vitaly Prosyak (3):
  drm/amd/display: Fix for hdmi frame pack stereo
  drm/amd/display: Rename trasnform to dpp for dcn's
  drm/amd/display:  Move view port registers and programming to memory
input.

Yongqiang Sun (1):
  drm/amd/display: set drr during 

[PATCH 31/81] drm/amd/display: Add validate_context to atomic_state

[sunpeng.li]

From: Harry Wentland 

Change-Id: I702516607ad0682339d41bba627e7f1674d4b050
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 18 ++
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h|  2 +-
 2 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index b0734bb..396fd31 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3145,7 +3145,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
struct amdgpu_device *adev = dev->dev_private;
struct dc *dc = adev->dm.dc;
bool need_to_validate = false;
-   struct validate_context *context;
struct drm_connector *connector;
struct drm_connector_state *conn_state;
/*
@@ -3380,10 +3379,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
}
}
 
-   context = dc_get_validate_context(dc, dm_state->set, 
dm_state->set_count);
-
-   if (need_to_validate == false || dm_state->set_count == 0 || context) {
+   dm_state->context = dc_get_validate_context(dc, dm_state->set, 
dm_state->set_count);
 
+   if (need_to_validate == false || dm_state->set_count == 0 || 
dm_state->context) {
ret = 0;
/*
 * For full updates case when
@@ -3399,18 +3397,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
}
 
-   if (context) {
-   dc_resource_validate_ctx_destruct(context);
-   dm_free(context);
-   }
-
-   for (i = 0; i < dm_state->set_count; i++)
-   for (j = 0; j < dm_state->set[i].surface_count; j++)
-   dc_surface_release(dm_state->set[i].surfaces[j]);
-
-   for (i = 0; i < new_stream_count; i++)
-   dc_stream_release(new_streams[i]);
-
if (ret != 0) {
if (ret == -EDEADLK)
DRM_DEBUG_KMS("Atomic check stopped due to to 
deadlock.\n");
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index a7adf8d..1e444cb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -55,7 +55,7 @@ struct dm_atomic_state {
 
struct dc_validation_set set[MAX_STREAMS];
int set_count;
-
+   struct validate_context *context;
 };
 
 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 24/81] drm/amd/display: Remove SMU_INTERRUPT_CONTROL

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: Iff671ee2c27f85732763cb1293f24949883d67e3
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 8b04996..fd6ba7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -50,7 +50,6 @@
SR(DMCU_IRAM_RD_CTRL), \
SR(DMCU_IRAM_RD_DATA), \
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
-   SR(SMU_INTERRUPT_CONTROL), \
SRI(DIG_BE_CNTL, DIG, id), \
SRI(DIG_BE_EN_CNTL, DIG, id), \
SRI(DP_CONFIG, DP, id), \
@@ -137,7 +136,6 @@ struct dce110_link_enc_registers {
uint32_t DMCU_IRAM_RD_CTRL;
uint32_t DMCU_IRAM_RD_DATA;
uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
-   uint32_t SMU_INTERRUPT_CONTROL;
 
/* Common DP registers */
uint32_t DIG_BE_CNTL;
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 12/81] drm/amd/display: enable diags compilation

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: Iea5cddde246293d3b22b66eb7d3956b167767b3d
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Jordan Lazare 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c|  8 ++---
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h| 41 --
 .../drm/amd/display/dc/dce120/dce120_resource.c| 17 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  | 22 +++-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 23 ++--
 drivers/gpu/drm/amd/display/dc/inc/resource.h  |  1 +
 6 files changed, 27 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 4e3f4e5..f30cd4d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -781,11 +781,7 @@ struct display_clock *dce112_disp_clk_create(
return _dce->base;
 }
 
-struct display_clock *dce120_disp_clk_create(
-   struct dc_context *ctx,
-   const struct dce_disp_clk_registers *regs,
-   const struct dce_disp_clk_shift *clk_shift,
-   const struct dce_disp_clk_mask *clk_mask)
+struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
 {
struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce));
struct dm_pp_clock_levels_with_voltage clk_level_info = {0};
@@ -800,7 +796,7 @@ struct display_clock *dce120_disp_clk_create(
sizeof(dce120_max_clks_by_state));
 
dce_disp_clk_construct(
-   clk_dce, ctx, regs, clk_shift, clk_mask);
+   clk_dce, ctx, NULL, NULL, NULL);
 
clk_dce->base.funcs = _funcs;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
index 103e905..0e717e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
@@ -31,55 +31,30 @@
 
 #define CLK_COMMON_REG_LIST_DCE_BASE() \
.DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
-   .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL, \
-   .MASTER_COMM_DATA_REG1 = mmMASTER_COMM_DATA_REG1, \
-   .MASTER_COMM_CMD_REG = mmMASTER_COMM_CMD_REG, \
-   .MASTER_COMM_CNTL_REG = mmMASTER_COMM_CNTL_REG
+   .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
 
 #define CLK_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
 
 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
-   CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \
-   CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
-   CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
-
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-#define CLK_DCN10_REG_LIST()\
-   SR(DPREFCLK_CNTL), \
-   SR(DENTIST_DISPCLK_CNTL), \
-   SR(MASTER_COMM_DATA_REG1), \
-   SR(MASTER_COMM_CMD_REG), \
-   SR(MASTER_COMM_CNTL_REG)
-#endif
-
-#define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
-   CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
-   CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, 
mask_sh), \
-   CLK_SF(DCCG_DFS_MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 
mask_sh), \
-   CLK_SF(DCCG_DFS_MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
+   CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
 
 #define CLK_REG_FIELD_LIST(type) \
type DPREFCLK_SRC_SEL; \
-   type DENTIST_DPREFCLK_WDIVIDER; \
-   type MASTER_COMM_CMD_REG_BYTE0; \
-   type MASTER_COMM_INTERRUPT
+   type DENTIST_DPREFCLK_WDIVIDER;
 
 struct dce_disp_clk_shift {
-   CLK_REG_FIELD_LIST(uint8_t);
+   CLK_REG_FIELD_LIST(uint8_t)
 };
 
 struct dce_disp_clk_mask {
-   CLK_REG_FIELD_LIST(uint32_t);
+   CLK_REG_FIELD_LIST(uint32_t)
 };
 
 struct dce_disp_clk_registers {
uint32_t DPREFCLK_CNTL;
uint32_t DENTIST_DISPCLK_CNTL;
-   uint32_t MASTER_COMM_DATA_REG1;
-   uint32_t MASTER_COMM_CMD_REG;
-   uint32_t MASTER_COMM_CNTL_REG;
 };
 
 /* Array identifiers and count for the divider ranges.*/
@@ -155,11 +130,7 @@ struct display_clock *dce112_disp_clk_create(
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask);
 
-struct display_clock *dce120_disp_clk_create(
-   struct dc_context *ctx,
-   const struct dce_disp_clk_registers *regs,
-   const struct dce_disp_clk_shift *clk_shift,
-   const struct dce_disp_clk_mask *clk_mask);
+struct display_clock *dce120_disp_clk_create(struct dc_context *ctx);
 
 void dce_disp_clk_destroy(struct display_clock **disp_clk);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 

[PATCH 06/81] drm/amd/display: remove unneeded FBC hw programming code

[sunpeng.li]

From: Bhawanpreet Lakha 

- Removed uneeded FBC code.
- Initial placeholder for FBC implementation on stoney/carrizo

Change-Id: I425164e76d7be44ab397323eac99fba57d1b3826
Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Roman Li 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dce110/dce110_compressor.c  | 534 -
 .../drm/amd/display/dc/dce110/dce110_compressor.h  |   3 +
 drivers/gpu/drm/amd/display/dc/inc/compressor.h|  46 +-
 3 files changed, 137 insertions(+), 446 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 518150a..5fe8304 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -94,199 +94,8 @@ enum fbc_idle_force {
FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x2000,
 };
 
-static uint32_t lpt_size_alignment(struct dce110_compressor *cp110)
-{
-   /*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */
-   return cp110->base.raw_size * cp110->base.banks_num *
-   cp110->base.dram_channels_num;
-}
-
-static uint32_t lpt_memory_control_config(struct dce110_compressor *cp110,
-   uint32_t lpt_control)
-{
-   /*LPT MC Config */
-   if (cp110->base.options.bits.LPT_MC_CONFIG == 1) {
-   /* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS):
-* 00 - 1 CHANNEL
-* 01 - 2 CHANNELS
-* 02 - 4 OR 6 CHANNELS
-* (Only for discrete GPU, N/A for CZ)
-* 03 - 8 OR 12 CHANNELS
-* (Only for discrete GPU, N/A for CZ) */
-   switch (cp110->base.dram_channels_num) {
-   case 2:
-   set_reg_field_value(
-   lpt_control,
-   1,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_PIPES);
-   break;
-   case 1:
-   set_reg_field_value(
-   lpt_control,
-   0,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_PIPES);
-   break;
-   default:
-   dm_logger_write(
-   cp110->base.ctx->logger, LOG_WARNING,
-   "%s: Invalid LPT NUM_PIPES!!!",
-   __func__);
-   break;
-   }
-
-   /* The mapping for LPT NUM_BANKS is in
-* GRPH_CONTROL.GRPH_NUM_BANKS register field
-* Specifies the number of memory banks for tiling
-* purposes. Only applies to 2D and 3D tiling modes.
-* POSSIBLE VALUES:
-* 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK
-* 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK
-* 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK
-* 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */
-   switch (cp110->base.banks_num) {
-   case 16:
-   set_reg_field_value(
-   lpt_control,
-   3,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_BANKS);
-   break;
-   case 8:
-   set_reg_field_value(
-   lpt_control,
-   2,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_BANKS);
-   break;
-   case 4:
-   set_reg_field_value(
-   lpt_control,
-   1,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_BANKS);
-   break;
-   case 2:
-   set_reg_field_value(
-   lpt_control,
-   0,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_BANKS);
-   break;
-   default:
-   dm_logger_write(
-   cp110->base.ctx->logger, LOG_WARNING,
-   "%s: Invalid LPT NUM_BANKS!!!",
-   __func__);
-   break;
-   }
-
-   /* The mapping is in DMIF_ADDR_CALC.
-* ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for
-* 

[PATCH 51/81] drm/amd/display: Leave all validate_ctx life cycle management to DC.

[sunpeng.li]

From: Andrey Grodzovsky 

Follow DC fix.

Change-Id: I6ceb43a7703fca170bb147106ec78b74f73cadb3
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 ---
 1 file changed, 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e5a27ab..88e177e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -653,27 +653,12 @@ dm_atomic_state_alloc(struct drm_device *dev)
return >base;
 }
 
-
-void dm_atomic_state_clear(struct drm_atomic_state *state)
-{
-   struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-
-   if (dm_state->context) {
-   dc_resource_validate_ctx_destruct(dm_state->context);
-   dm_free(dm_state->context);
-   dm_state->context = NULL;
-   }
-
-   drm_atomic_state_default_clear(state);
-}
-
 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
.output_poll_changed = amdgpu_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
.atomic_commit = amdgpu_dm_atomic_commit,
.atomic_state_alloc = dm_atomic_state_alloc,
-   .atomic_state_clear = dm_atomic_state_clear,
 };
 
 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = 
{
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 14/81] drm/amd/display: Add DC interface for custom CSC matrix

[sunpeng.li]

From: Yue Hin Lau 

Change-Id: Idfbcebd90fe9953f7efadb388d246c59120baea8
Signed-off-by: Yue Hin Lau 
Reviewed-by: Vitaly Prosyak 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  26 +
 drivers/gpu/drm/amd/display/dc/dc.h|   3 +
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  23 
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c   | 117 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h   |  76 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c |   5 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h  |   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   5 +
 8 files changed, 252 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c113c1a..a9ddd07 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -221,6 +221,29 @@ static bool set_gamut_remap(struct dc *dc, const struct 
dc_stream *stream)
return ret;
 }
 
+static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream)
+{
+   struct core_dc *core_dc = DC_TO_CORE(dc);
+   struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
+   int i = 0;
+   bool ret = false;
+   struct pipe_ctx *pipes;
+
+   for (i = 0; i < MAX_PIPES; i++) {
+   if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
+   == core_stream) {
+
+   pipes = _dc->current_context->res_ctx.pipe_ctx[i];
+   core_dc->hwss.program_csc_matrix(pipes,
+   core_stream->public.output_color_space,
+   core_stream->public.csc_color_matrix.matrix);
+   ret = true;
+   }
+   }
+
+   return ret;
+}
+
 static void set_static_screen_events(struct dc *dc,
const struct dc_stream **stream,
int num_streams,
@@ -373,6 +396,9 @@ static void allocate_dc_stream_funcs(struct core_dc 
*core_dc)
core_dc->public.stream_funcs.set_gamut_remap =
set_gamut_remap;
 
+   core_dc->public.stream_funcs.program_csc_matrix =
+   program_csc_matrix;
+
core_dc->public.stream_funcs.set_dither_option =
set_dither_option;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 18f6858..3e2ed3d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -118,6 +118,9 @@ struct dc_stream_funcs {
bool (*set_gamut_remap)(struct dc *dc,
const struct dc_stream *stream);
 
+   bool (*program_csc_matrix)(struct dc *dc,
+   const struct dc_stream *stream);
+
void (*set_static_screen_events)(struct dc *dc,
const struct dc_stream **stream,
int num_streams,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d0bddfd..f404e4e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1623,6 +1623,28 @@ static void program_gamut_remap(struct pipe_ctx 
*pipe_ctx)
pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, );
 }
 
+
+static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
+   enum dc_color_space colorspace,
+   uint16_t *matrix)
+{
+   int i;
+   struct out_csc_color_matrix tbl_entry;
+
+   if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
+   == true) {
+   enum dc_color_space color_space =
+   pipe_ctx->stream->public.output_color_space;
+
+   //uint16_t matrix[12];
+   for (i = 0; i < 12; i++)
+   tbl_entry.regval[i] = 
pipe_ctx->stream->public.csc_color_matrix.matrix[i];
+
+   tbl_entry.color_space = color_space;
+   //tbl_entry.regval = matrix;
+   
pipe_ctx->opp->funcs->opp_set_csc_adjustment(pipe_ctx->opp, _entry);
+   }
+}
 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 {
if (pipe_ctx->surface->public.visible)
@@ -2103,6 +2125,7 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx,
 
 static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = program_gamut_remap,
+   .program_csc_matrix = program_csc_matrix,
.init_hw = init_hw,
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
diff --git 

[PATCH 27/81] drm/amd/display: Create dm_atomic_state

[sunpeng.li]

From: Harry Wentland 

We really want to use the new private_atomic_state but can't right now
as we have to maintain some backward compatibility to older kernels. For
now let's follow Intel's approach and extend the drm_atomic_state.

Change-Id: I848bda7aa11d7731684e90e0d9e88191e8db8fb2
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 37 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h|  8 +++--
 2 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e856f62..1b69848 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -634,11 +634,46 @@ const struct amdgpu_ip_block_version dm_ip_block =
.funcs = _dm_funcs,
 };
 
+
+struct drm_atomic_state *
+dm_atomic_state_alloc(struct drm_device *dev)
+{
+   struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
+
+   if (!state || drm_atomic_state_init(dev, >base) < 0) {
+   kfree(state);
+   return NULL;
+   }
+
+   return >base;
+}
+
+void dm_atomic_state_clear(struct drm_atomic_state *s)
+{
+   struct dm_atomic_state *state = to_dm_atomic_state(s);
+   drm_atomic_state_default_clear(>base);
+}
+
+
+static void dm_atomic_state_free(struct drm_atomic_state *state)
+{
+   struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
+
+   drm_atomic_state_default_release(state);
+
+   kfree(dm_state);
+}
+
+
+
 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
.output_poll_changed = amdgpu_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
-   .atomic_commit = drm_atomic_helper_commit
+   .atomic_commit = drm_atomic_helper_commit,
+   .atomic_state_alloc = dm_atomic_state_alloc,
+   .atomic_state_clear = dm_atomic_state_clear,
+   .atomic_state_free = dm_atomic_state_free,
 };
 
 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = 
{
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index f5f4936..9ba7fdd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -27,6 +27,7 @@
 #define __AMDGPU_DM_TYPES_H__
 
 #include 
+#include 
 
 struct amdgpu_framebuffer;
 struct amdgpu_display_manager;
@@ -48,11 +49,12 @@ struct dm_crtc_state {
 
 #define to_dm_crtc_state(x)container_of(x, struct dm_crtc_state, base)
 
-struct dm_plane_state {
-   struct drm_plane_state base;
-   struct dc_surface *dc_surface;
+struct dm_atomic_state {
+   struct drm_atomic_state base;
 };
 
+#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
+
 
 /*TODO Jodan Hersen use the one in amdgpu_dm*/
 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 15/81] drm/amd/display: Re-enable Vsync Interrupts for Gradual Refresh Ramp

[sunpeng.li]

From: Amy Zhang 

- Make sure Vsync interrupts are disabled in static screen case
  and enabled when not to save power
- Create no_static_for_external_dp debug option

Change-Id: I29c90dcd6ea43e15e52a4dacf1e5ce91d32ac9a1
Signed-off-by: Amy Zhang 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h|  1 +
 .../drm/amd/display/modules/freesync/freesync.c| 38 --
 .../gpu/drm/amd/display/modules/inc/mod_freesync.h |  5 +++
 3 files changed, 34 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3e2ed3d..93aff82 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -188,6 +188,7 @@ struct dc_debug {
bool disable_dmcu;
bool disable_psr;
bool force_abm_enable;
+   bool no_static_for_external_dp;
 };
 
 struct dc {
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index c7da90f..4df79f7 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -440,14 +440,11 @@ static void calc_freesync_range(struct core_freesync 
*core_freesync,
}
 
/* Determine whether BTR can be supported */
-   //if (max_frame_duration_in_ns >=
-   //  2 * min_frame_duration_in_ns)
-   //  core_freesync->map[index].caps->btr_supported = true;
-   //else
-   //  core_freesync->map[index].caps->btr_supported = false;
-
-   /* Temp, keep btr disabled */
-   core_freesync->map[index].caps->btr_supported = false;
+   if (max_frame_duration_in_ns >=
+   2 * min_frame_duration_in_ns)
+   core_freesync->map[index].caps->btr_supported = true;
+   else
+   core_freesync->map[index].caps->btr_supported = false;
 
/* Cache the time variables */
state->time.max_render_time_in_us =
@@ -882,8 +879,10 @@ void mod_freesync_update_state(struct mod_freesync 
*mod_freesync,
 * panels. Also change core variables only if there
 * is a change.
 */
-   if (dc_is_embedded_signal(
-   streams[stream_index]->sink->sink_signal) &&
+   if ((dc_is_embedded_signal(
+   streams[stream_index]->sink->sink_signal) ||
+   core_freesync->map[map_index].caps->
+   no_static_for_external_dp == false) &&
state->static_screen !=
freesync_params->enable) {
 
@@ -1035,6 +1034,25 @@ bool mod_freesync_get_user_enable(struct mod_freesync 
*mod_freesync,
return true;
 }
 
+bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
+   const struct dc_stream *stream,
+   bool *is_ramp_active)
+{
+   unsigned int index = 0;
+   struct core_freesync *core_freesync = NULL;
+
+   if (mod_freesync == NULL)
+   return false;
+
+   core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
+   index = map_index_from_stream(core_freesync, stream);
+
+   *is_ramp_active =
+   core_freesync->map[index].state.static_ramp.ramp_is_active;
+
+   return true;
+}
+
 bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
const struct dc_stream *streams,
unsigned int min_refresh,
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h 
b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index f7f5a2c..eae1b34 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -88,6 +88,7 @@ struct mod_freesync_caps {
unsigned int max_refresh_in_micro_hz;
 
bool btr_supported;
+   bool no_static_for_external_dp;
 };
 
 struct mod_freesync_params {
@@ -129,6 +130,10 @@ bool mod_freesync_get_user_enable(struct mod_freesync 
*mod_freesync,
const struct dc_stream *stream,
struct mod_freesync_user_enable *user_enable);
 
+bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
+   const struct dc_stream *stream,
+   bool *is_ramp_active);
+
 bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
const struct dc_stream *streams,
unsigned int min_refresh,
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 05/81] drm/amd/display: Add clock info struct

[sunpeng.li]

From: Corbin McElhanney 

Change-Id: I2cca4d886b0993fc0512312c35c42d08c3ad34be
Signed-off-by: Corbin McElhanney 
Reviewed-by: Logatharshan Thothiralingam 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dm_services_types.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h 
b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index b283045..4c04ec5 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -271,4 +271,10 @@ struct dm_pp_static_clock_info {
enum dm_pp_clocks_state max_clocks_state;
 };
 
+struct dtn_min_clk_info {
+   uint32_t disp_clk_khz;
+   uint32_t min_engine_clock_khz;
+   uint32_t min_memory_clock_khz;
+};
+
 #endif
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 26/81] drm/amd/display: set drr during program timing.

[sunpeng.li]

From: Yongqiang Sun 

Change-Id: Id3b33d30fac6badc1d5b8bb0dbebfb620e7e06cd
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../amd/display/dc/dce110/dce110_timing_generator.c | 21 +
 .../amd/display/dc/dce120/dce120_timing_generator.c | 19 ---
 .../amd/display/dc/dcn10/dcn10_timing_generator.c   |  8 
 3 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index ec59927..7f93d6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -629,6 +629,27 @@ void dce110_timing_generator_program_blanking(
CRTC_V_TOTAL);
dm_write_reg(ctx, addr, value);
 
+   /* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and
+* V_TOTAL_MIN are equal to V_TOTAL.
+*/
+   addr = CRTC_REG(mmCRTC_V_TOTAL_MAX);
+   value = dm_read_reg(ctx, addr);
+   set_reg_field_value(
+   value,
+   timing->v_total - 1,
+   CRTC_V_TOTAL_MAX,
+   CRTC_V_TOTAL_MAX);
+   dm_write_reg(ctx, addr, value);
+
+   addr = CRTC_REG(mmCRTC_V_TOTAL_MIN);
+   value = dm_read_reg(ctx, addr);
+   set_reg_field_value(
+   value,
+   timing->v_total - 1,
+   CRTC_V_TOTAL_MIN,
+   CRTC_V_TOTAL_MIN);
+   dm_write_reg(ctx, addr, value);
+
addr = CRTC_REG(mmCRTC_H_BLANK_START_END);
value = dm_read_reg(ctx, addr);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 03b21e9..58a070d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -441,15 +441,28 @@ void dce120_timing_generator_program_blanking(
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 
CRTC_REG_UPDATE(
-   CRTC0_CRTC_H_TOTAL,
-   CRTC_H_TOTAL,
-   timing->h_total - 1);
+   CRTC0_CRTC_H_TOTAL,
+   CRTC_H_TOTAL,
+   timing->h_total - 1);
 
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL,
CRTC_V_TOTAL,
timing->v_total - 1);
 
+   /* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and
+* V_TOTAL_MIN are equal to V_TOTAL.
+*/
+   CRTC_REG_UPDATE(
+   CRTC0_CRTC_V_TOTAL_MAX,
+   CRTC_V_TOTAL_MAX,
+   timing->v_total - 1);
+
+   CRTC_REG_UPDATE(
+   CRTC0_CRTC_V_TOTAL_MIN,
+   CRTC_V_TOTAL_MIN,
+   timing->v_total - 1);
+
tmp1 = timing->h_total -
(h_sync_start + timing->h_border_left);
tmp2 = tmp1 + timing->h_addressable +
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 5927478..e1899f5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -177,6 +177,14 @@ static void tgn10_program_timing(
REG_SET(OTG_V_TOTAL, 0,
OTG_V_TOTAL, v_total);
 
+   /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
+* OTG_V_TOTAL_MIN are equal to V_TOTAL.
+*/
+   REG_SET(OTG_V_TOTAL_MAX, 0,
+   OTG_V_TOTAL_MAX, v_total);
+   REG_SET(OTG_V_TOTAL_MIN, 0,
+   OTG_V_TOTAL_MIN, v_total);
+
/* v_sync_start = 0, v_sync_end = v_sync_width */
v_sync_end = patched_crtc_timing.v_sync_width * interlace_factor;
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 49/81] drm/amd/display: dal1.1 hwseq prog update

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: I201b96af4efc95077d3cc54c6fbe810b337cf4a1
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 223bb79..4c39bf0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -64,17 +64,13 @@ static void enable_dppclk(
plane_id,
dppclk_div);
 
-   if (dppclk_div) {
-   /* 1/2 DISPCLK*/
+   if (hws->shifts->DPPCLK_RATE_CONTROL)
REG_UPDATE_2(DPP_CONTROL[plane_id],
-   DPPCLK_RATE_CONTROL, 1,
+   DPPCLK_RATE_CONTROL, dppclk_div,
DPP_CLOCK_ENABLE, 1);
-   } else {
-   /* DISPCLK */
-   REG_UPDATE_2(DPP_CONTROL[plane_id],
-   DPPCLK_RATE_CONTROL, 0,
+   else
+   REG_UPDATE(DPP_CONTROL[plane_id],
DPP_CLOCK_ENABLE, 1);
-   }
 }
 
 static void enable_power_gating_plane(
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 10/81] drm/amd/display: Connect DC resource to FBC compressor

[sunpeng.li]

From: Bhawanpreet Lakha 

- Connected DC resource to FBC compressor,
- Initial Implementation of FBC for Stoney/Carrizo
- Code is currently guarded with "ENABLE_FBC" compile time flag

Change-Id: Ie5977bb58febdca4cb25206846d7e81ae528029c
Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Roman Li 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 19 ++
 .../drm/amd/display/dc/dce110/dce110_compressor.c  | 78 +++---
 .../drm/amd/display/dc/dce110/dce110_compressor.h  |  2 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 15 +
 .../drm/amd/display/dc/dce110/dce110_resource.c| 10 +++
 drivers/gpu/drm/amd/display/dc/inc/compressor.h|  6 +-
 drivers/gpu/drm/amd/display/dc/inc/core_dc.h   |  6 ++
 7 files changed, 94 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2f481ef..51e4cb3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -843,6 +843,11 @@ bool dc_enable_stereo(
int i, j;
struct pipe_ctx *pipe;
struct core_dc *core_dc = DC_TO_CORE(dc);
+
+#ifdef ENABLE_FBC
+   struct compressor *fbc_compressor = core_dc->fbc_compressor;
+#endif
+
for (i = 0; i < MAX_PIPES; i++) {
if (context != NULL)
pipe = >res_ctx.pipe_ctx[i];
@@ -854,6 +859,14 @@ bool dc_enable_stereo(
core_dc->hwss.setup_stereo(pipe, core_dc);
}
}
+
+#ifdef ENABLE_FBC
+   if (fbc_compressor != NULL &&
+   fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor,
+   >tg->inst))
+   fbc_compressor->funcs->disable_fbc(fbc_compressor);
+
+#endif
return ret;
 }
 
@@ -1232,6 +1245,12 @@ void dc_update_surfaces_and_stream(struct dc *dc,
if (!stream_status)
return; /* Cannot commit surface to stream that is not 
committed */
 
+#ifdef ENABLE_FBC
+   if (srf_updates->flip_addr) {
+   if (srf_updates->flip_addr->address.grph.addr.low_part == 0)
+   ASSERT(0);
+   }
+#endif
context = core_dc->current_context;
 
/* update current stream with the new updates */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 5fe8304..1e59f4e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -175,7 +175,6 @@ void dce110_compressor_power_up_fbc(struct compressor 
*compressor)
 
 void dce110_compressor_enable_fbc(
struct compressor *compressor,
-   uint32_t paths_num,
struct compr_addr_and_pitch_params *params)
 {
struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
@@ -366,43 +365,6 @@ void dce110_compressor_set_fbc_invalidation_triggers(
dm_write_reg(compressor->ctx, addr, value);
 }
 
-bool dce110_compressor_construct(struct dce110_compressor *compressor,
-struct dc_context *ctx)
-{
-
-   compressor->base.options.bits.FBC_SUPPORT = true;
-
-/* for dce 11 always use one dram channel for lpt */
-   compressor->base.lpt_channels_num = 1;
-   compressor->base.options.bits.DUMMY_BACKEND = false;
-
-   /*
-* check if this system has more than 1 dram channel; if only 1 then lpt
-* should not be supported
-*/
-
-
-   compressor->base.options.bits.CLK_GATING_DISABLED = false;
-
-   compressor->base.ctx = ctx;
-   compressor->base.embedded_panel_h_size = 0;
-   compressor->base.embedded_panel_v_size = 0;
-   compressor->base.memory_bus_width = ctx->asic_id.vram_width;
-   compressor->base.allocated_size = 0;
-   compressor->base.preferred_requested_size = 0;
-   compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
-   compressor->base.options.raw = 0;
-   compressor->base.banks_num = 0;
-   compressor->base.raw_size = 0;
-   compressor->base.channel_interleave_size = 0;
-   compressor->base.dram_channels_num = 0;
-   compressor->base.lpt_channels_num = 0;
-   compressor->base.attached_inst = 0;
-   compressor->base.is_enabled = false;
-
-   return true;
-}
-
 struct compressor *dce110_compressor_create(struct dc_context *ctx)
 {
struct dce110_compressor *cp110 =
@@ -503,3 +465,43 @@ static const struct compressor_funcs 
dce110_compressor_funcs = {
 };
 
 
+bool dce110_compressor_construct(struct dce110_compressor *compressor,
+   struct dc_context *ctx)
+{
+
+   compressor->base.options.bits.FBC_SUPPORT = true;
+
+   /* for dce 11 always use one dram channel for lpt */
+   

[PATCH 25/81] drm/amd/display: Remove unblanaced drm_vblank_put.

[sunpeng.li]

From: Andrey Grodzovsky 

Since drm_vblank_get moved from this function to just
before do_flip no need to release vblank here in case of error.

Change-Id: Iedc900618da2a0c940f49fe63299c6ae3eec260d
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index fb5afba..ed48c5e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1016,8 +1016,7 @@ static int amdgpu_atomic_helper_page_flip(struct drm_crtc 
*crtc,
if (ret == -EDEADLK)
goto backoff;
 
-   if (ret)
-   drm_crtc_vblank_put(crtc);
+   drm_atomic_state_put(state);
 
return ret;
 backoff:
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 19/81] drm/amd/display: Set static screen register for stoney/carrizo

[sunpeng.li]

From: Bhawanpreet Lakha 

-Set CRTC_STATIC_SCREEN_EVENT for stoney/carrizo for FBC implementation
-Code is currently guarded with "ENABLE_FBC" compile time flag

Change-Id: Ia471b516b6b9fd399539be3b349c1970f19fa234
Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Roman Li 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 72d5f75..8778af7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1395,6 +1395,10 @@ static void set_static_screen_control(struct pipe_ctx 
**pipe_ctx,
if (events->cursor_update)
value |= 0x2;
 
+#ifdef ENABLE_FBC
+   value |= 0x84;
+#endif
+
for (i = 0; i < num_pipes; i++)
pipe_ctx[i]->tg->funcs->
set_static_screen_control(pipe_ctx[i]->tg, value);
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 08/81] drm/amd/display: Move dm_plane_state to DAL header.

[sunpeng.li]

From: Andrey Grodzovsky 

Change-Id: I3910605f43577f1dec99dbc50ea1ed82baf1db34
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index 1091725..f5f4936 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -36,6 +36,11 @@ struct dc_surface;
 struct  dc_stream;
 
 
+struct dm_plane_state {
+   struct drm_plane_state base;
+   struct dc_surface *dc_surface;
+};
+
 struct dm_crtc_state {
struct drm_crtc_state base;
struct dc_stream *dc_stream;
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 17/81] drm/amd/display: Coding for backcompatible tiling support for Gfx7

[sunpeng.li]

From: Vikrant Mhaske 

after the diags build error correction.

Change-Id: If851c70ecfad2ebc3dfaea6c0e772406d547d584
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 1615 +---
 1 file changed, 1060 insertions(+), 555 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index 9e2f1bb..b7ecfad 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -1,4 +1,5 @@
-/* Copyright 2012-15 Advanced Micro Devices, Inc.
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -21,573 +22,1077 @@
  * Authors: AMD
  *
  */
+#include "dm_services.h"
+#include "dce_calcs.h"
+#include "dcn10_mem_input.h"
+#include "reg_helper.h"
+#include "basics/conversion.h"
 
-#ifndef __DC_MEM_INPUT_DCN10_H__
-#define __DC_MEM_INPUT_DCN10_H__
-
-#include "mem_input.h"
-
-#define TO_DCN10_MEM_INPUT(mi)\
-   container_of(mi, struct dcn10_mem_input, base)
-
-
-#define MI_DCN10_REG_LIST(id)\
-   SRI(DCHUBP_CNTL, HUBP, id),\
-   SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
-   SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
-   SRI(DCSURF_TILING_CONFIG, HUBP, id),\
-   SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
-   SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
-   SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
-   SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
-   SRI(HUBPRET_CONTROL, HUBPRET, id),\
-   SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
-   SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
-   SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
-   SRI(BLANK_OFFSET_0, HUBPREQ, id),\
-   SRI(BLANK_OFFSET_1, HUBPREQ, id),\
-   SRI(DST_DIMENSIONS, HUBPREQ, id),\
-   SRI(DST_AFTER_SCALER, HUBPREQ, id),\
-   SRI(PREFETCH_SETTINS, HUBPREQ, id),\
-   SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
-   SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
-   SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
-   SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
-   SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
-   SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
-   SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
-   SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
-   SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
-   SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
-   SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
-   SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
-   SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
-   SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
-   SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
-   SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, 

[PATCH 01/81] drm/amd/display: RV stereo support

[sunpeng.li]

From: Ken Chalmers 

Fix moving directly from frame packed to frame sequential mode: disable
OTG_3D_STRUCTURE_EN if the stereo mode is not frame packed.

Change-Id: I67d1a9b112f438b881104f4fe3ab1cdd41fedbdc
Signed-off-by: Ken Chalmers 
Reviewed-by: Vitaly Prosyak 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 83efbec..58fb29f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -1082,11 +1082,11 @@ static void dcn10_enable_stereo(struct timing_generator 
*tg,
REG_UPDATE(OTG_STEREO_CONTROL,
OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
 
-   if (flags->PROGRAM_STEREO && flags->FRAME_PACKED)
+   if (flags->PROGRAM_STEREO)
REG_UPDATE_3(OTG_3D_STRUCTURE_CONTROL,
-   OTG_3D_STRUCTURE_EN, 1,
-   OTG_3D_STRUCTURE_V_UPDATE_MODE, 1,
-   OTG_3D_STRUCTURE_STEREO_SEL_OVR, 1);
+   OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
+   OTG_3D_STRUCTURE_V_UPDATE_MODE, 
flags->FRAME_PACKED,
+   OTG_3D_STRUCTURE_STEREO_SEL_OVR, 
flags->FRAME_PACKED);
 
}
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 04/81] drm/amd/display: Create dm_crtc_state stubs.

[sunpeng.li]

From: Andrey Grodzovsky 

These stubs are initial only since we need to flatten
DC objects (steran at least) to implement deep copy.

Change-Id: I6e16cddf0b937b5f078443924dab286481db2f13
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 74 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h| 10 +++
 2 files changed, 81 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index fd5d643..10ffe7f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1034,16 +1034,84 @@ static int amdgpu_atomic_helper_page_flip(struct 
drm_crtc *crtc,
goto retry;
 }
 
+static void dm_crtc_destroy_state(struct drm_crtc *crtc,
+  struct drm_crtc_state *state)
+{
+   struct dm_crtc_state *cur = to_dm_crtc_state(state);
+
+   if (cur->dc_stream) {
+   /* TODO Destroy dc_stream objects are stream object is 
flattened */
+   dm_free(cur->dc_stream);
+   } else
+   WARN_ON(1);
+
+   __drm_atomic_helper_crtc_destroy_state(state);
+
+
+   kfree(state);
+}
+
+static void dm_crtc_reset_state(struct drm_crtc *crtc)
+{
+   struct dm_crtc_state *state;
+
+   if (crtc->state)
+   dm_crtc_destroy_state(crtc, crtc->state);
+
+   state = kzalloc(sizeof(*state), GFP_KERNEL);
+   if (WARN_ON(!state))
+   return;
+
+
+   crtc->state = >base;
+   crtc->state->crtc = crtc;
+
+   state->dc_stream = dm_alloc(sizeof(*state->dc_stream));
+   WARN_ON(!state->dc_stream);
+}
+
+static struct drm_crtc_state *
+dm_crtc_duplicate_state(struct drm_crtc *crtc)
+{
+   struct dm_crtc_state *state, *cur;
+   struct dc_stream *dc_stream;
+
+   if (WARN_ON(!crtc->state))
+   return NULL;
+
+   cur = to_dm_crtc_state(crtc->state);
+   if (WARN_ON(!cur->dc_stream))
+   return NULL;
+
+   dc_stream = dm_alloc(sizeof(*dc_stream));
+   if (WARN_ON(!dc_stream))
+   return NULL;
+
+   state = dm_alloc(sizeof(*state));
+   if (WARN_ON(!state)) {
+   dm_free(dc_stream);
+   return NULL;
+   }
+
+   __drm_atomic_helper_crtc_duplicate_state(crtc, >base);
+
+   state->dc_stream = dc_stream;
+
+   /* TODO Duplicate dc_stream after objects are stream object is 
flattened */
+
+   return >base;
+}
+
 /* Implemented only the options currently availible for the driver */
 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
-   .reset = drm_atomic_helper_crtc_reset,
+   .reset = dm_crtc_reset_state,
.destroy = amdgpu_dm_crtc_destroy,
.gamma_set = drm_atomic_helper_legacy_gamma_set,
.set_config = drm_atomic_helper_set_config,
.set_property = drm_atomic_helper_crtc_set_property,
.page_flip = amdgpu_atomic_helper_page_flip,
-   .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
-   .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+   .atomic_duplicate_state = dm_crtc_duplicate_state,
+   .atomic_destroy_state = dm_crtc_destroy_state,
 };
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index 6411dd1..1091725 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -32,6 +32,16 @@ struct amdgpu_framebuffer;
 struct amdgpu_display_manager;
 struct dc_validation_set;
 struct dc_surface;
+/* TODO rename to dc_stream_state */
+struct  dc_stream;
+
+
+struct dm_crtc_state {
+   struct drm_crtc_state base;
+   struct dc_stream *dc_stream;
+};
+
+#define to_dm_crtc_state(x)container_of(x, struct dm_crtc_state, base)
 
 struct dm_plane_state {
struct drm_plane_state base;
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 02/81] drm/amd/display: Move drm_get_vblank from legacy code

[sunpeng.li]

From: "Leo (Sunpeng) Li" 

Previously, we assumed that allow_modeset=false => page flip. This
assumption breaks when an atomic commit is submitted with allow_modeset
set to false, since the legacy flip code is never called (the legacy
code grabs the vblank reference).

Fix: Move drm_vblank_get() from amdgpu_atomic_helper_page_flip() to
amdgpu_dm_commit_surfaces().

Change-Id: Ibd429f7efb75aeef6e254e96bb88703f5b3391a0
Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Andrey Grodzovsky 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 88d4f74c..fd5d643 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -977,10 +977,6 @@ static int amdgpu_atomic_helper_page_flip(struct drm_crtc 
*crtc,
if (!state)
return -ENOMEM;
 
-   ret = drm_crtc_vblank_get(crtc);
-   if (ret)
-   return ret;
-
state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
 retry:
crtc_state = drm_atomic_get_crtc_state(state, crtc);
@@ -2551,8 +2547,6 @@ static void amdgpu_dm_commit_surfaces(struct 
drm_atomic_state *state,
if (!con_state)
continue;
 
-
-
add_surface(dm->dc, crtc, plane,
_surfaces_constructed[planes_count]);
if (dc_surfaces_constructed[planes_count] == NULL) {
@@ -2571,6 +2565,10 @@ static void amdgpu_dm_commit_surfaces(struct 
drm_atomic_state *state,
acrtc_attach->flip_flags & 
DRM_MODE_PAGE_FLIP_ASYNC ?
false : true;
 
+   /* TODO: Needs rework for multiplane flip */
+   if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+   drm_crtc_vblank_get(crtc);
+
amdgpu_dm_do_flip(
crtc,
fb,
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 76/81] drm/amd/display: properly turn off unused mpc before front end programming

[sunpeng.li]

From: Eric Yang 

MPCC_OPP_ID must be programmed to 0xf to properly turn off the mpcc.
However the software state of the mpcc must keep track of the opp that
the mpcc is attached to for reset to properly happen. This is kinda
hacky right now, but a good solution may involve a lot of work.

Change-Id: I98274df3226b3f9640ab7c1ab39d1944c2b3f463
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d714422..cadc940 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1572,17 +1572,24 @@ static void dcn10_apply_ctx_for_surface(
if ((!pipe_ctx->surface && old_pipe_ctx->surface)
|| (!pipe_ctx->stream && old_pipe_ctx->stream)) 
{
struct mpcc_cfg mpcc_cfg;
+   int opp_id_cached = old_pipe_ctx->mpcc->opp_id;
 
if (!old_pipe_ctx->top_pipe) {
ASSERT(0);
continue;
}
 
-   mpcc_cfg.opp_id = old_pipe_ctx->mpcc->opp_id;
+   mpcc_cfg.opp_id = 0xf;
mpcc_cfg.top_dpp_id = 0xf;
mpcc_cfg.bot_mpcc_id = 0xf;
mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe;
old_pipe_ctx->mpcc->funcs->set(old_pipe_ctx->mpcc, 
_cfg);
+   /*
+* the mpcc is the only thing that keeps track of the 
mpcc
+* mapping for reset front end right now. Might need 
some
+* rework.
+*/
+   old_pipe_ctx->mpcc->opp_id = opp_id_cached;
 
old_pipe_ctx->top_pipe = NULL;
old_pipe_ctx->bottom_pipe = NULL;
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH i-g-t] tests: Rename I915_MAX_PIPES to IGT_MAX_PIPES

[sunpeng.li]

From: "Leo (Sunpeng) Li" 

Name should not be driver-specific.

Signed-off-by: Leo (Sunpeng) Li 
---
 lib/igt_kms.c |  2 +-
 lib/igt_kms.h |  5 +++--
 tests/kms_atomic_transition.c | 12 ++--
 tests/kms_busy.c  |  4 ++--
 tests/kms_ccs.c   |  4 ++--
 tests/kms_concurrent.c|  2 +-
 tests/kms_cursor_legacy.c |  4 ++--
 tests/kms_pipe_color.c|  2 +-
 tests/kms_plane.c |  2 +-
 tests/kms_plane_lowres.c  |  2 +-
 tests/kms_plane_multiple.c|  2 +-
 tests/kms_universal_plane.c   |  2 +-
 12 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 473094d..a7364b6 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -324,7 +324,7 @@ const char *kmstest_pipe_name(enum pipe pipe)
if (pipe == PIPE_NONE)
return "None";
 
-   if (pipe >= I915_MAX_PIPES)
+   if (pipe >= IGT_MAX_PIPES)
return "invalid";
 
return str[pipe];
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 30bb6ff..f419562 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -46,7 +46,8 @@
  * @PIPE_A: First crtc.
  * @PIPE_B: Second crtc.
  * @PIPE_C: Third crtc.
- * @I915_MAX_PIPES: Max number of pipes allowed.
+ * ... and so on.
+ * @IGT_MAX_PIPES: Max number of pipes allowed.
  */
 enum pipe {
 PIPE_NONE = -1,
@@ -57,7 +58,7 @@ enum pipe {
 PIPE_D,
 PIPE_E,
 PIPE_F,
-I915_MAX_PIPES
+IGT_MAX_PIPES
 };
 const char *kmstest_pipe_name(enum pipe pipe);
 int kmstest_pipe_to_index(char pipe);
diff --git a/tests/kms_atomic_transition.c b/tests/kms_atomic_transition.c
index 8059225..685396c 100644
--- a/tests/kms_atomic_transition.c
+++ b/tests/kms_atomic_transition.c
@@ -634,7 +634,7 @@ static void collect_crcs_mask(igt_pipe_crc_t **pipe_crcs, 
unsigned mask, igt_crc
 {
int i;
 
-   for (i = 0; i < I915_MAX_PIPES; i++) {
+   for (i = 0; i < IGT_MAX_PIPES; i++) {
if (!((1 << i) & mask))
continue;
 
@@ -650,7 +650,7 @@ static void run_modeset_tests(igt_display_t *display, int 
howmany, bool nonblock
struct igt_fb fbs[2];
int i, j;
unsigned iter_max = 1 << display->n_pipes;
-   igt_pipe_crc_t *pipe_crcs[I915_MAX_PIPES] = { 0 };
+   igt_pipe_crc_t *pipe_crcs[IGT_MAX_PIPES] = { 0 };
igt_output_t *output;
unsigned width = 0, height = 0;
bool skip_test = false;
@@ -707,7 +707,7 @@ static void run_modeset_tests(igt_display_t *display, int 
howmany, bool nonblock
igt_display_commit2(display, COMMIT_ATOMIC);
 
for (i = 0; i < iter_max; i++) {
-   igt_crc_t crcs[5][I915_MAX_PIPES];
+   igt_crc_t crcs[5][IGT_MAX_PIPES];
unsigned event_mask;
 
if (hweight32(i) > howmany)
@@ -754,7 +754,7 @@ static void run_modeset_tests(igt_display_t *display, int 
howmany, bool nonblock
if (!is_i915_device(display->drm_fd))
continue;
 
-   for (int k = 0; k < I915_MAX_PIPES; k++) {
+   for (int k = 0; k < IGT_MAX_PIPES; k++) {
if (i & (1 << k)) {
igt_assert_crc_equal([0][k], 
[3][k]);
igt_assert_crc_equal([0][k], 
[4][k]);
@@ -784,7 +784,7 @@ cleanup:
 
 static void run_modeset_transition(igt_display_t *display, int 
requested_outputs, bool nonblocking, bool fencing)
 {
-   igt_output_t *outputs[I915_MAX_PIPES] = {};
+   igt_output_t *outputs[IGT_MAX_PIPES] = {};
int num_outputs = 0;
enum pipe pipe;
 
@@ -871,7 +871,7 @@ igt_main
for_each_pipe_with_valid_output(, pipe, output)
run_transition_test(, pipe, output, 
TRANSITION_MODESET_DISABLE, false, false);
 
-   for (i = 1; i <= I915_MAX_PIPES; i++) {
+   for (i = 1; i <= IGT_MAX_PIPES; i++) {
igt_subtest_f("%ix-modeset-transitions", i)
run_modeset_transition(, i, false, false);
 
diff --git a/tests/kms_busy.c b/tests/kms_busy.c
index d6ef1f1..731ace4 100644
--- a/tests/kms_busy.c
+++ b/tests/kms_busy.c
@@ -284,7 +284,7 @@ static void test_hang(igt_display_t *dpy, unsigned ring,
 
 igt_main
 {
-   igt_display_t display = { .drm_fd = -1, .n_pipes = I915_MAX_PIPES };
+   igt_display_t display = { .drm_fd = -1, .n_pipes = IGT_MAX_PIPES };
const struct intel_execution_engine *e;
 
igt_skip_on_simulation();
@@ -302,7 +302,7 @@ igt_main
 
/* XXX Extend to cover atomic rendering tests to all planes + legacy */
 
-   for (int n = 0; n < I915_MAX_PIPES; n++) {
+   for (int n = 0; n < IGT_MAX_PIPES; n++) {
errno = 0;
 
igt_fixture {
diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 0795e3a..29d676a 

[PATCH i-g-t v3] tests: Increase value of I915_MAX_PIPES to 6

[sunpeng.li]

From: "Leo (Sunpeng) Li" 

Increasing max pipe count to 6 to support AMD GPU's.

Since some tests' behavior depends on this value, small changes are made
to remove this dependency:

* kms_ccs: Early abort if wanted_pipe is out-of-bounds.
* kms_concurrent: Check if pipe is within bounds first.
* kms_pipe_color: Prevent skipping of subsequent tests by placing
generated tests in a 'igt_subtest_group'.
* kms_plane: Move pipe and plane index checking to subtest group level.

v2: Change invalid pipe check on kmstest_pipe_name() to use
I915_MAX_PIPE

v3: Change tabs to spaces in 'enum pipe'

Signed-off-by: Leo (Sunpeng) Li 
---
 lib/igt_kms.c  | 10 --
 lib/igt_kms.h  |  3 +++
 tests/kms_ccs.c|  2 ++
 tests/kms_concurrent.c |  2 +-
 tests/kms_pipe_color.c |  3 ++-
 tests/kms_plane.c  |  8 +---
 6 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index c77716b..473094d 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -319,12 +319,12 @@ const unsigned char* igt_kms_get_alt_edid(void)
  */
 const char *kmstest_pipe_name(enum pipe pipe)
 {
-   const char *str[] = { "A", "B", "C" };
+   const char *str[] = { "A", "B", "C", "D", "E", "F"};
 
if (pipe == PIPE_NONE)
return "None";
 
-   if (pipe > 2)
+   if (pipe >= I915_MAX_PIPES)
return "invalid";
 
return str[pipe];
@@ -344,6 +344,12 @@ int kmstest_pipe_to_index(char pipe)
return 1;
else if (pipe == 'C')
return 2;
+   else if (pipe == 'D')
+   return 3;
+   else if (pipe == 'E')
+   return 4;
+   else if (pipe == 'F')
+   return 5;
else
return -EINVAL;
 }
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 9567a26..30bb6ff 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -54,6 +54,9 @@ enum pipe {
 PIPE_A = 0,
 PIPE_B,
 PIPE_C,
+PIPE_D,
+PIPE_E,
+PIPE_F,
 I915_MAX_PIPES
 };
 const char *kmstest_pipe_name(enum pipe pipe);
diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index d829152..0795e3a 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -250,6 +250,8 @@ static void test(data_t *data)
int valid_tests = 0;
enum pipe wanted_pipe = data->pipe;
 
+   igt_skip_on(wanted_pipe >= display->n_pipes);
+
for_each_pipe_with_valid_output(display, data->pipe, data->output) {
if (wanted_pipe != PIPE_NONE && data->pipe != wanted_pipe)
continue;
diff --git a/tests/kms_concurrent.c b/tests/kms_concurrent.c
index b34540b..db06a37 100644
--- a/tests/kms_concurrent.c
+++ b/tests/kms_concurrent.c
@@ -351,8 +351,8 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
igt_fixture {
int valid_tests = 0;
 
-   igt_require(data->display.pipes[pipe].n_planes > 0);
igt_skip_on(pipe >= data->display.n_pipes);
+   igt_require(data->display.pipes[pipe].n_planes > 0);
 
for_each_valid_output_on_pipe(>display, pipe, output)
valid_tests++;
diff --git a/tests/kms_pipe_color.c b/tests/kms_pipe_color.c
index fd58ac8..da49eb1 100644
--- a/tests/kms_pipe_color.c
+++ b/tests/kms_pipe_color.c
@@ -1180,7 +1180,8 @@ igt_main
}
 
for (int pipe = 0; pipe < I915_MAX_PIPES; pipe++)
-   run_tests_for_pipe(, pipe);
+   igt_subtest_group
+   run_tests_for_pipe(, pipe);
 
igt_subtest_f("invalid-lut-sizes")
invalid_lut_sizes();
diff --git a/tests/kms_plane.c b/tests/kms_plane.c
index e1bd467..34418ca 100644
--- a/tests/kms_plane.c
+++ b/tests/kms_plane.c
@@ -354,9 +354,6 @@ test_plane_panning(data_t *data, enum pipe pipe, int plane,
igt_output_t *output;
int connected_outs = 0;
 
-   igt_skip_on(pipe >= data->display.n_pipes);
-   igt_skip_on(plane >= data->display.pipes[pipe].n_planes);
-
for_each_valid_output_on_pipe(>display, pipe, output) {
test_plane_panning_with_output(data, pipe, plane, output,
flags);
@@ -369,6 +366,11 @@ test_plane_panning(data_t *data, enum pipe pipe, int plane,
 static void
 run_tests_for_pipe_plane(data_t *data, enum pipe pipe)
 {
+   igt_fixture {
+   igt_skip_on(pipe >= data->display.n_pipes);
+   igt_require(data->display.pipes[pipe].n_planes > 0);
+   }
+
igt_subtest_f("plane-position-covered-pipe-%s-planes",
  kmstest_pipe_name(pipe)) {
int n_planes = data->display.pipes[pipe].n_planes;
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH i-g-t v2] tests: Increase value of I915_MAX_PIPES to 6

[sunpeng.li]

From: "Leo (Sunpeng) Li" 

Increasing max pipe count to 6 to support AMD GPU's.

Since some tests' behavior depends on this value, small changes are made
to remove this dependency:

* kms_ccs: Early abort if wanted_pipe is out-of-bounds.
* kms_concurrent: Check if pipe is within bounds first.
* kms_pipe_color: Prevent skipping of subsequent tests by placing
generated tests in a 'igt_subtest_group'.
* kms_plane: Move pipe and plane index checking to subtest group level.

v2: Change invalid pipe check on kmstest_pipe_name() to use
I915_MAX_PIPE

Signed-off-by: Leo (Sunpeng) Li 
---
 lib/igt_kms.c  | 10 --
 lib/igt_kms.h  |  3 +++
 tests/kms_ccs.c|  2 ++
 tests/kms_concurrent.c |  2 +-
 tests/kms_pipe_color.c |  3 ++-
 tests/kms_plane.c  |  8 +---
 6 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index c77716b..473094d 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -319,12 +319,12 @@ const unsigned char* igt_kms_get_alt_edid(void)
  */
 const char *kmstest_pipe_name(enum pipe pipe)
 {
-   const char *str[] = { "A", "B", "C" };
+   const char *str[] = { "A", "B", "C", "D", "E", "F"};
 
if (pipe == PIPE_NONE)
return "None";
 
-   if (pipe > 2)
+   if (pipe >= I915_MAX_PIPES)
return "invalid";
 
return str[pipe];
@@ -344,6 +344,12 @@ int kmstest_pipe_to_index(char pipe)
return 1;
else if (pipe == 'C')
return 2;
+   else if (pipe == 'D')
+   return 3;
+   else if (pipe == 'E')
+   return 4;
+   else if (pipe == 'F')
+   return 5;
else
return -EINVAL;
 }
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 9567a26..8f7c2bb 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -54,6 +54,9 @@ enum pipe {
 PIPE_A = 0,
 PIPE_B,
 PIPE_C,
+   PIPE_D,
+   PIPE_E,
+   PIPE_F,
 I915_MAX_PIPES
 };
 const char *kmstest_pipe_name(enum pipe pipe);
diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index d829152..0795e3a 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -250,6 +250,8 @@ static void test(data_t *data)
int valid_tests = 0;
enum pipe wanted_pipe = data->pipe;
 
+   igt_skip_on(wanted_pipe >= display->n_pipes);
+
for_each_pipe_with_valid_output(display, data->pipe, data->output) {
if (wanted_pipe != PIPE_NONE && data->pipe != wanted_pipe)
continue;
diff --git a/tests/kms_concurrent.c b/tests/kms_concurrent.c
index b34540b..db06a37 100644
--- a/tests/kms_concurrent.c
+++ b/tests/kms_concurrent.c
@@ -351,8 +351,8 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
igt_fixture {
int valid_tests = 0;
 
-   igt_require(data->display.pipes[pipe].n_planes > 0);
igt_skip_on(pipe >= data->display.n_pipes);
+   igt_require(data->display.pipes[pipe].n_planes > 0);
 
for_each_valid_output_on_pipe(>display, pipe, output)
valid_tests++;
diff --git a/tests/kms_pipe_color.c b/tests/kms_pipe_color.c
index fd58ac8..da49eb1 100644
--- a/tests/kms_pipe_color.c
+++ b/tests/kms_pipe_color.c
@@ -1180,7 +1180,8 @@ igt_main
}
 
for (int pipe = 0; pipe < I915_MAX_PIPES; pipe++)
-   run_tests_for_pipe(, pipe);
+   igt_subtest_group
+   run_tests_for_pipe(, pipe);
 
igt_subtest_f("invalid-lut-sizes")
invalid_lut_sizes();
diff --git a/tests/kms_plane.c b/tests/kms_plane.c
index e1bd467..34418ca 100644
--- a/tests/kms_plane.c
+++ b/tests/kms_plane.c
@@ -354,9 +354,6 @@ test_plane_panning(data_t *data, enum pipe pipe, int plane,
igt_output_t *output;
int connected_outs = 0;
 
-   igt_skip_on(pipe >= data->display.n_pipes);
-   igt_skip_on(plane >= data->display.pipes[pipe].n_planes);
-
for_each_valid_output_on_pipe(>display, pipe, output) {
test_plane_panning_with_output(data, pipe, plane, output,
flags);
@@ -369,6 +366,11 @@ test_plane_panning(data_t *data, enum pipe pipe, int plane,
 static void
 run_tests_for_pipe_plane(data_t *data, enum pipe pipe)
 {
+   igt_fixture {
+   igt_skip_on(pipe >= data->display.n_pipes);
+   igt_require(data->display.pipes[pipe].n_planes > 0);
+   }
+
igt_subtest_f("plane-position-covered-pipe-%s-planes",
  kmstest_pipe_name(pipe)) {
int n_planes = data->display.pipes[pipe].n_planes;
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH i-g-t] tests: Increase value of I915_MAX_PIPES to 6

[sunpeng.li]

From: "Leo (Sunpeng) Li" 

Increasing max pipe count to 6 to support AMD GPU's.

Since some tests' behavior depends on this value, small changes are made
to remove this dependency:

* kms_ccs: Early abort if wanted_pipe is out-of-bounds.
* kms_concurrent: Check if pipe is within bounds first.
* kms_pipe_color: Prevent skipping of subsequent tests by placing
generated tests in a 'igt_subtest_group'.
* kms_plane: Move pipe and plane index checking to subtest group level.

Signed-off-by: Leo (Sunpeng) Li 
---
 lib/igt_kms.c  | 10 --
 lib/igt_kms.h  |  3 +++
 tests/kms_ccs.c|  2 ++
 tests/kms_concurrent.c |  2 +-
 tests/kms_pipe_color.c |  3 ++-
 tests/kms_plane.c  |  8 +---
 6 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index c77716b..1bb62f0 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -319,12 +319,12 @@ const unsigned char* igt_kms_get_alt_edid(void)
  */
 const char *kmstest_pipe_name(enum pipe pipe)
 {
-   const char *str[] = { "A", "B", "C" };
+   const char *str[] = { "A", "B", "C", "D", "E", "F"};
 
if (pipe == PIPE_NONE)
return "None";
 
-   if (pipe > 2)
+   if (pipe > 5)
return "invalid";
 
return str[pipe];
@@ -344,6 +344,12 @@ int kmstest_pipe_to_index(char pipe)
return 1;
else if (pipe == 'C')
return 2;
+   else if (pipe == 'D')
+   return 3;
+   else if (pipe == 'E')
+   return 4;
+   else if (pipe == 'F')
+   return 5;
else
return -EINVAL;
 }
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 9567a26..8f7c2bb 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -54,6 +54,9 @@ enum pipe {
 PIPE_A = 0,
 PIPE_B,
 PIPE_C,
+   PIPE_D,
+   PIPE_E,
+   PIPE_F,
 I915_MAX_PIPES
 };
 const char *kmstest_pipe_name(enum pipe pipe);
diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index d829152..0795e3a 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -250,6 +250,8 @@ static void test(data_t *data)
int valid_tests = 0;
enum pipe wanted_pipe = data->pipe;
 
+   igt_skip_on(wanted_pipe >= display->n_pipes);
+
for_each_pipe_with_valid_output(display, data->pipe, data->output) {
if (wanted_pipe != PIPE_NONE && data->pipe != wanted_pipe)
continue;
diff --git a/tests/kms_concurrent.c b/tests/kms_concurrent.c
index b34540b..db06a37 100644
--- a/tests/kms_concurrent.c
+++ b/tests/kms_concurrent.c
@@ -351,8 +351,8 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
igt_fixture {
int valid_tests = 0;
 
-   igt_require(data->display.pipes[pipe].n_planes > 0);
igt_skip_on(pipe >= data->display.n_pipes);
+   igt_require(data->display.pipes[pipe].n_planes > 0);
 
for_each_valid_output_on_pipe(>display, pipe, output)
valid_tests++;
diff --git a/tests/kms_pipe_color.c b/tests/kms_pipe_color.c
index fd58ac8..da49eb1 100644
--- a/tests/kms_pipe_color.c
+++ b/tests/kms_pipe_color.c
@@ -1180,7 +1180,8 @@ igt_main
}
 
for (int pipe = 0; pipe < I915_MAX_PIPES; pipe++)
-   run_tests_for_pipe(, pipe);
+   igt_subtest_group
+   run_tests_for_pipe(, pipe);
 
igt_subtest_f("invalid-lut-sizes")
invalid_lut_sizes();
diff --git a/tests/kms_plane.c b/tests/kms_plane.c
index e1bd467..34418ca 100644
--- a/tests/kms_plane.c
+++ b/tests/kms_plane.c
@@ -354,9 +354,6 @@ test_plane_panning(data_t *data, enum pipe pipe, int plane,
igt_output_t *output;
int connected_outs = 0;
 
-   igt_skip_on(pipe >= data->display.n_pipes);
-   igt_skip_on(plane >= data->display.pipes[pipe].n_planes);
-
for_each_valid_output_on_pipe(>display, pipe, output) {
test_plane_panning_with_output(data, pipe, plane, output,
flags);
@@ -369,6 +366,11 @@ test_plane_panning(data_t *data, enum pipe pipe, int plane,
 static void
 run_tests_for_pipe_plane(data_t *data, enum pipe pipe)
 {
+   igt_fixture {
+   igt_skip_on(pipe >= data->display.n_pipes);
+   igt_require(data->display.pipes[pipe].n_planes > 0);
+   }
+
igt_subtest_f("plane-position-covered-pipe-%s-planes",
  kmstest_pipe_name(pipe)) {
int n_planes = data->display.pipes[pipe].n_planes;
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx