RE: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
[AMD Official Use Only - Internal Distribution Only] On Wed, Apr 01, 2020 at 07:41:12PM +0800, Yuxian Dai wrote: > 1.Using the FCLK DPM table to set the MCLK for DPM states consist of > three entities: > FCLK > UCLK > MEMCLK > All these three clk change together, MEMCLK from FCLK, so use the fclk > frequency. > 2.we should show the current working clock freqency from clock table > metric > > Signed-off-by: Yuxian Dai > Reviewed-by: Alex Deucher > Reviewed-by: Huang Rui > Reviewed-by: Kevin Wang > --- Next time, if you submit the V2 patch, you can generate it as below command: git format-patch --subject-prefix="PATCH v2" And describe the changes from v1 -> v2 in the commit message. This will help everyone to understand your change. > I got it. Reviewed-by: Huang Rui > drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++ > drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c > b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c > index 7bf52ecba01d..c6b39a7026a8 100644 > --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c > +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c > @@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context > *smu, > uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; > DpmClocks_t *clk_table = smu->smu_table.clocks_table; > SmuMetrics_t metrics; > + bool cur_value_match_level = false; > > if (!clk_table || clk_type >= SMU_CLK_COUNT) > return -EINVAL; > @@ -297,8 +298,13 @@ static int renoir_print_clk_levels(struct smu_context > *smu, > GET_DPM_CUR_FREQ(clk_table, clk_type, i, value); > size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, > cur_value == value ? "*" : ""); > + if (cur_value == value) > + cur_value_match_level = true; > } > > + if (!cur_value_match_level) > + size += sprintf(buf + size, " %uMhz *\n", cur_value); > + > return size; > } > > diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > index 2a390ddd37dd..89cd6da118a3 100644 > --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); > freq = table->SocClocks[dpm_level].Freq;\ > break; \ > case SMU_MCLK: \ > - freq = table->MemClocks[dpm_level].Freq;\ > + freq = table->FClocks[dpm_level].Freq; \ > break; \ > case SMU_DCEFCLK: \ > freq = table->DcfClocks[dpm_level].Freq;\ > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cra > y.huang%40amd.com%7Cfa81baf94d2c409e4f0308d7d6319a8f%7C3dd8961fe4884e6 > 08e11a82d994e183d%7C0%7C0%7C637213381443101089sdata=LF2pLZj%2Fq0C > wiMSfvDiofXFKuGVfgje7o4Iti%2FtoNj0%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
On Wed, Apr 01, 2020 at 07:41:12PM +0800, Yuxian Dai wrote: > 1.Using the FCLK DPM table to set the MCLK for DPM states consist of > three entities: > FCLK > UCLK > MEMCLK > All these three clk change together, MEMCLK from FCLK, so use the fclk > frequency. > 2.we should show the current working clock freqency from clock table metric > > Signed-off-by: Yuxian Dai > Reviewed-by: Alex Deucher > Reviewed-by: Huang Rui > Reviewed-by: Kevin Wang > --- Next time, if you submit the V2 patch, you can generate it as below command: git format-patch --subject-prefix="PATCH v2" And describe the changes from v1 -> v2 in the commit message. This will help everyone to understand your change. Reviewed-by: Huang Rui > drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++ > drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c > b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c > index 7bf52ecba01d..c6b39a7026a8 100644 > --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c > +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c > @@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context > *smu, > uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; > DpmClocks_t *clk_table = smu->smu_table.clocks_table; > SmuMetrics_t metrics; > + bool cur_value_match_level = false; > > if (!clk_table || clk_type >= SMU_CLK_COUNT) > return -EINVAL; > @@ -297,8 +298,13 @@ static int renoir_print_clk_levels(struct smu_context > *smu, > GET_DPM_CUR_FREQ(clk_table, clk_type, i, value); > size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, > cur_value == value ? "*" : ""); > + if (cur_value == value) > + cur_value_match_level = true; > } > > + if (!cur_value_match_level) > + size += sprintf(buf + size, " %uMhz *\n", cur_value); > + > return size; > } > > diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > index 2a390ddd37dd..89cd6da118a3 100644 > --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); > freq = table->SocClocks[dpm_level].Freq;\ > break; \ > case SMU_MCLK: \ > - freq = table->MemClocks[dpm_level].Freq;\ > + freq = table->FClocks[dpm_level].Freq; \ > break; \ > case SMU_DCEFCLK: \ > freq = table->DcfClocks[dpm_level].Freq;\ > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cray.huang%40amd.com%7Cfa81baf94d2c409e4f0308d7d6319a8f%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637213381443101089sdata=LF2pLZj%2Fq0CwiMSfvDiofXFKuGVfgje7o4Iti%2FtoNj0%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
1.Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. 2.we should show the current working clock freqency from clock table metric Signed-off-by: Yuxian Dai Reviewed-by: Alex Deucher Reviewed-by: Huang Rui Reviewed-by: Kevin Wang --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++ drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c index 7bf52ecba01d..c6b39a7026a8 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c @@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu, uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; DpmClocks_t *clk_table = smu->smu_table.clocks_table; SmuMetrics_t metrics; + bool cur_value_match_level = false; if (!clk_table || clk_type >= SMU_CLK_COUNT) return -EINVAL; @@ -297,8 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu, GET_DPM_CUR_FREQ(clk_table, clk_type, i, value); size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, cur_value == value ? "*" : ""); + if (cur_value == value) + cur_value_match_level = true; } + if (!cur_value_match_level) + size += sprintf(buf + size, " %uMhz *\n", cur_value); + return size; } diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h index 2a390ddd37dd..89cd6da118a3 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); freq = table->SocClocks[dpm_level].Freq;\ break; \ case SMU_MCLK: \ - freq = table->MemClocks[dpm_level].Freq;\ + freq = table->FClocks[dpm_level].Freq; \ break; \ case SMU_DCEFCLK: \ freq = table->DcfClocks[dpm_level].Freq;\ -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
From: "yuxia...@amd.com" 1,Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. 2,we should show the current working clock freqency from clock table metric Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774 Signed-off-by: Yuxian Dai --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++ drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c index 7bf52ecba01d..5adc25c8f6f4 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c @@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu, uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; DpmClocks_t *clk_table = smu->smu_table.clocks_table; SmuMetrics_t metrics; + bool cur_value_match_level = false; if (!clk_table || clk_type >= SMU_CLK_COUNT) return -EINVAL; @@ -297,7 +298,12 @@ static int renoir_print_clk_levels(struct smu_context *smu, GET_DPM_CUR_FREQ(clk_table, clk_type, i, value); size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, cur_value == value ? "*" : ""); + if (cur_value == value) + cur_value_match_level = true; } + + if (!cur_value_match_level) + size += sprintf(buf + size, " %uMhz *\n",cur_value); return size; } diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h index 2a390ddd37dd..89cd6da118a3 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); freq = table->SocClocks[dpm_level].Freq;\ break; \ case SMU_MCLK: \ - freq = table->MemClocks[dpm_level].Freq;\ + freq = table->FClocks[dpm_level].Freq; \ break; \ case SMU_DCEFCLK: \ freq = table->DcfClocks[dpm_level].Freq;\ -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
[AMD Official Use Only - Internal Distribution Only] From: amd-gfx on behalf of Yuxian Dai Sent: Wednesday, April 1, 2020 3:14 PM To: amd-gfx@lists.freedesktop.org Cc: Dai, Yuxian (David) ; Dai, Yuxian (David) Subject: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK From: "yuxia...@amd.com" 1,Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. 2,we should show the current working clock freqency from clock table metric Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774 Signed-off-by: Yuxian Dai --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 7 +++ drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c index 7bf52ecba01d..3901b20196d7 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c @@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu, uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; DpmClocks_t *clk_table = smu->smu_table.clocks_table; SmuMetrics_t metrics; + bool cur_value_match_level = false; if (!clk_table || clk_type >= SMU_CLK_COUNT) return -EINVAL; @@ -297,7 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu, GET_DPM_CUR_FREQ(clk_table, clk_type, i, value); size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, cur_value == value ? "*" : ""); + if (cur_value == value) + cur_value_match_level = true; } + + if (!cur_value_match_level) + size += sprintf(buf + size, " %uMhz *\n",cur_value); + [kevin]: after remove this unnecessary blank line, Reviewed-by: Kevin Wang return size; } diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h index 2a390ddd37dd..89cd6da118a3 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); freq = table->SocClocks[dpm_level].Freq;\ break; \ case SMU_MCLK: \ - freq = table->MemClocks[dpm_level].Freq;\ + freq = table->FClocks[dpm_level].Freq; \ break; \ case SMU_DCEFCLK: \ freq = table->DcfClocks[dpm_level].Freq;\ -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7CKevin1.Wang%40amd.com%7C7cef28fc315e4a1f705c08d7d60c542f%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637213221059785929sdata=eUFmm4J6hEfV%2FWJtU5s7hqFDSCF0i232Yz6QwoSAj7E%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
From: "yuxia...@amd.com" 1,Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. 2,we should show the current working clock freqency from clock table metric Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774 Signed-off-by: Yuxian Dai --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 7 +++ drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c index 7bf52ecba01d..3901b20196d7 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c @@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu, uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; DpmClocks_t *clk_table = smu->smu_table.clocks_table; SmuMetrics_t metrics; + bool cur_value_match_level = false; if (!clk_table || clk_type >= SMU_CLK_COUNT) return -EINVAL; @@ -297,7 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu, GET_DPM_CUR_FREQ(clk_table, clk_type, i, value); size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, cur_value == value ? "*" : ""); + if (cur_value == value) + cur_value_match_level = true; } + + if (!cur_value_match_level) + size += sprintf(buf + size, " %uMhz *\n",cur_value); + return size; } diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h index 2a390ddd37dd..89cd6da118a3 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); freq = table->SocClocks[dpm_level].Freq;\ break; \ case SMU_MCLK: \ - freq = table->MemClocks[dpm_level].Freq;\ + freq = table->FClocks[dpm_level].Freq; \ break; \ case SMU_DCEFCLK: \ freq = table->DcfClocks[dpm_level].Freq;\ -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
[AMD Official Use Only - Internal Distribution Only]
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai mailto:yuxian@amd.com>>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 8
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..5c5d3f974532 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,6 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if(cur_value == value) {
+ cur_value_match_level = true;
+ }
+ }
+
+ if(!cur_value_match_level) {
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
}
[kevin]:
I have a little suggestion about coding style.
"Do not unnecessarily use braces where a single statement will do."
we'd better fix it.
thanks.
* Ok, I will remove it.
https://www.kernel.org/doc/html/latest/process/coding-style.html
Linux kernel coding style - The Linux Kernel
documentation
Linux kernel coding style¶. This is a short document describing the preferred
coding style for the linux kernel. Coding style is very personal, and I won't
force my views on anybody, but this is what goes for anything that I have to be
able to maintain, and I'd prefer it for most other things too. Please at least
consider the points made here.
www.kernel.org
return size;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq;\
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq;\
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq;\
--
2.17.1
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[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
From: "yuxia...@amd.com" 1,Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. 2,we should show the current working clock freqency from clock table metric Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774 Signed-off-by: Yuxian Dai --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 7 +++ drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c index 7bf52ecba01d..30240fdff840 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c @@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu, uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; DpmClocks_t *clk_table = smu->smu_table.clocks_table; SmuMetrics_t metrics; + bool cur_value_match_level = false; if (!clk_table || clk_type >= SMU_CLK_COUNT) return -EINVAL; @@ -297,7 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu, GET_DPM_CUR_FREQ(clk_table, clk_type, i, value); size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, cur_value == value ? "*" : ""); + if(cur_value == value) + cur_value_match_level = true; } + + if(!cur_value_match_level) + size += sprintf(buf + size, " %uMhz *\n",cur_value); + return size; } diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h index 2a390ddd37dd..89cd6da118a3 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); freq = table->SocClocks[dpm_level].Freq;\ break; \ case SMU_MCLK: \ - freq = table->MemClocks[dpm_level].Freq;\ + freq = table->FClocks[dpm_level].Freq; \ break; \ case SMU_DCEFCLK: \ freq = table->DcfClocks[dpm_level].Freq;\ -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
[AMD Official Use Only - Internal Distribution Only]
From: amd-gfx on behalf of Yuxian Dai
Sent: Wednesday, April 1, 2020 2:02 PM
To: amd-gfx@lists.freedesktop.org
Cc: Dai, Yuxian (David) ; Dai, Yuxian (David)
Subject: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
From: "yuxia...@amd.com"
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 8
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..5c5d3f974532 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,6 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if(cur_value == value) {
+ cur_value_match_level = true;
+ }
+ }
+
+ if(!cur_value_match_level) {
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
}
[kevin]:
I have a little suggestion about coding style.
"Do not unnecessarily use braces where a single statement will do."
we'd better fix it.
thanks.
https://www.kernel.org/doc/html/latest/process/coding-style.html
Linux kernel coding style — The Linux Kernel
documentation
Linux kernel coding style¶. This is a short document describing the preferred
coding style for the linux kernel. Coding style is very personal, and I won’t
force my views on anybody, but this is what goes for anything that I have to be
able to maintain, and I’d prefer it for most other things too. Please at least
consider the points made here.
www.kernel.org
return size;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq;\
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq;\
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq;\
--
2.17.1
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[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
From: "yuxia...@amd.com"
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 8
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..5c5d3f974532 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,6 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if(cur_value == value) {
+ cur_value_match_level = true;
+ }
+ }
+
+ if(!cur_value_match_level) {
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
}
return size;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq;\
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq;\
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq;\
--
2.17.1
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[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
From: "yuxia...@amd.com"
1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric
Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 9 -
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..32e7a3c05cd4 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,7 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
-
+ bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,6 +297,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+ if(cur_value == value) {
+ cur_value_match_level = true;
+ }
+ }
+
+ if(!cur_value_match_level) {
+ size += sprintf(buf + size, " %uMhz *\n",cur_value);
}
return size;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq;\
break; \
case SMU_MCLK: \
- freq = table->MemClocks[dpm_level].Freq;\
+ freq = table->FClocks[dpm_level].Freq; \
break; \
case SMU_DCEFCLK: \
freq = table->DcfClocks[dpm_level].Freq;\
--
2.17.1
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RE: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK for DPM states consist of three entities :FCLK, UCLK, MEMCLK all these three clk change together , MEMCLK from FCLK.
[AMD Official Use Only - Internal Distribution Only] On Tue, Mar 31, 2020 at 09:41:44AM -0400, Alex Deucher wrote: > On Tue, Mar 31, 2020 at 6:10 AM Yuxian Dai wrote: > > > > From: "yuxia...@amd.com" > > Your patch title is too long; it is basically the whole patch > description rather than just a title. Please split it up between the > title and descriptions. E.g., > > drm/amdgpu/powerplay: fix MCLK DPM handling for renoir > > Using the FCLK DPM table to set the MCLK for DPM states consist of > three entities: > FCLK > UCLK > MEMCLK > All these three clk change together, MEMCLK from FCLK, so use the fclk > frequency. > > With that fixed, patch is: > Reviewed-by: Alex Deucher > Yes, and usually, we don't leave the commit message as empty. David, you need describe the detailed info in the commit not the title. > missing a blank line, so the description confuse you . I will update it > according your suggestion. Thanks, Ray > > > > Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774 > > Signed-off-by: Yuxian Dai > > --- > > drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > > b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > > index 2a390ddd37dd..89cd6da118a3 100644 > > --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > > +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > > @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); > > freq = table->SocClocks[dpm_level].Freq;\ > > break; \ > > case SMU_MCLK: \ > > - freq = table->MemClocks[dpm_level].Freq;\ > > + freq = table->FClocks[dpm_level].Freq; \ > > break; \ > > case SMU_DCEFCLK: \ > > freq = table->DcfClocks[dpm_level].Freq;\ > > -- > > 2.17.1 > > > > ___ > > amd-gfx mailing list > > amd-gfx@lists.freedesktop.org > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli > > sts.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01% > > 7Cray.huang%40amd.com%7C541f2e15da804d81c5b508d7d57949d2%7C3dd8961fe > > 4884e608e11a82d994e183d%7C0%7C0%7C637212590166168794sdata=7x4pB > > WEPuVHbb8ro%2Fpy5%2BgiJhrxWbLrxGqHSro9KUV8%3Dreserved=0 > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cra > y.huang%40amd.com%7C541f2e15da804d81c5b508d7d57949d2%7C3dd8961fe4884e6 > 08e11a82d994e183d%7C0%7C0%7C637212590166168794sdata=7x4pBWEPuVHbb > 8ro%2Fpy5%2BgiJhrxWbLrxGqHSro9KUV8%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK for DPM states consist of three entities :FCLK, UCLK, MEMCLK all these three clk change together , MEMCLK from FCLK.
On Tue, Mar 31, 2020 at 09:41:44AM -0400, Alex Deucher wrote: > On Tue, Mar 31, 2020 at 6:10 AM Yuxian Dai wrote: > > > > From: "yuxia...@amd.com" > > Your patch title is too long; it is basically the whole patch > description rather than just a title. Please split it up between the > title and descriptions. E.g., > > drm/amdgpu/powerplay: fix MCLK DPM handling for renoir > > Using the FCLK DPM table to set the MCLK for DPM states consist of > three entities: > FCLK > UCLK > MEMCLK > All these three clk change together, MEMCLK from FCLK, so use the fclk > frequency. > > With that fixed, patch is: > Reviewed-by: Alex Deucher > Yes, and usually, we don't leave the commit message as empty. David, you need describe the detailed info in the commit not the title. Thanks, Ray > > > > Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774 > > Signed-off-by: Yuxian Dai > > --- > > drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > > b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > > index 2a390ddd37dd..89cd6da118a3 100644 > > --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > > +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > > @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); > > freq = table->SocClocks[dpm_level].Freq;\ > > break; \ > > case SMU_MCLK: \ > > - freq = table->MemClocks[dpm_level].Freq;\ > > + freq = table->FClocks[dpm_level].Freq; \ > > break; \ > > case SMU_DCEFCLK: \ > > freq = table->DcfClocks[dpm_level].Freq;\ > > -- > > 2.17.1 > > > > ___ > > amd-gfx mailing list > > amd-gfx@lists.freedesktop.org > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cray.huang%40amd.com%7C541f2e15da804d81c5b508d7d57949d2%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637212590166168794sdata=7x4pBWEPuVHbb8ro%2Fpy5%2BgiJhrxWbLrxGqHSro9KUV8%3Dreserved=0 > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cray.huang%40amd.com%7C541f2e15da804d81c5b508d7d57949d2%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637212590166168794sdata=7x4pBWEPuVHbb8ro%2Fpy5%2BgiJhrxWbLrxGqHSro9KUV8%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK for DPM states consist of three entities :FCLK, UCLK, MEMCLK all these three clk change together , MEMCLK from FCLK.
On Tue, Mar 31, 2020 at 6:10 AM Yuxian Dai wrote: > > From: "yuxia...@amd.com" Your patch title is too long; it is basically the whole patch description rather than just a title. Please split it up between the title and descriptions. E.g., drm/amdgpu/powerplay: fix MCLK DPM handling for renoir Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. With that fixed, patch is: Reviewed-by: Alex Deucher > > Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774 > Signed-off-by: Yuxian Dai > --- > drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > index 2a390ddd37dd..89cd6da118a3 100644 > --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h > @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); > freq = table->SocClocks[dpm_level].Freq;\ > break; \ > case SMU_MCLK: \ > - freq = table->MemClocks[dpm_level].Freq;\ > + freq = table->FClocks[dpm_level].Freq; \ > break; \ > case SMU_DCEFCLK: \ > freq = table->DcfClocks[dpm_level].Freq;\ > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK for DPM states consist of three entities :FCLK, UCLK, MEMCLK all these three clk change together , MEMCLK from FCLK.
From: "yuxia...@amd.com" Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774 Signed-off-by: Yuxian Dai --- drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h index 2a390ddd37dd..89cd6da118a3 100644 --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h @@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); freq = table->SocClocks[dpm_level].Freq;\ break; \ case SMU_MCLK: \ - freq = table->MemClocks[dpm_level].Freq;\ + freq = table->FClocks[dpm_level].Freq; \ break; \ case SMU_DCEFCLK: \ freq = table->DcfClocks[dpm_level].Freq;\ -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
