RE: [PATCH] drm/amdgpu: update gc golden setting for dimgrey_cavefish

2021-07-15 Thread Chen, Guchun 
[Public]

Reviewed-by: Guchun Chen 

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Thursday, July 15, 2021 3:13 PM
To: amd-gfx@lists.freedesktop.org; Chen, Jiansong (Simon) 
; Gui, Jack ; Zhang, Hawking 

Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: update gc golden setting for dimgrey_cavefish

Update gc_10_3_4 golden setting.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 80e7069e12ac..454293ea5b02 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3451,6 +3451,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_4[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 
0x),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x0001, 0x00010020),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x0103, 0x0103),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a0, 0x00a0),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x0020, 0x0020)
-- 
2.17.1

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[PATCH] drm/amdgpu: update gc golden setting for dimgrey_cavefish

2021-07-15 Thread Tao Zhou 
Update gc_10_3_4 golden setting.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 80e7069e12ac..454293ea5b02 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3451,6 +3451,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_4[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 
0x),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x0001, 0x00010020),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x0103, 0x0103),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a0, 0x00a0),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x0020, 0x0020)
-- 
2.17.1

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RE: [PATCH] drm/amdgpu: update GC golden setting for dimgrey_cavefish

2020-11-26 Thread Chen, Jiansong (Simon) 
[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Zhou1, Tao 
Sent: Friday, November 27, 2020 12:28 PM
To: Chen, Jiansong (Simon) ; Gui, Jack 
; Zhang, Hawking ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: update GC golden setting for dimgrey_cavefish

Update GC golden setting for dimgrey_cavefish.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 841d39eb62d9..ffbda6680a68 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3266,6 +3266,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_vangogh[] =

 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =  {
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x7800,
+0x78000100),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x3000, 0x3100),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e00, 0x7e000100),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007, 0xc000),
--
2.17.1

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[PATCH] drm/amdgpu: update GC golden setting for dimgrey_cavefish

2020-11-26 Thread Tao Zhou 
Update GC golden setting for dimgrey_cavefish.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 841d39eb62d9..ffbda6680a68 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3266,6 +3266,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_vangogh[] =
 
 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
 {
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x7800, 
0x78000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x3000, 
0x3100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e00, 
0x7e000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007, 0xc000),
-- 
2.17.1

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