Re: [PATCH 046/100] drm/amdgpu: Add GMC 9.0 support

2017-03-22 Thread Alex Deucher 
On Wed, Mar 22, 2017 at 10:42 PM, Zhang, Jerry (Junwei)
 wrote:
> Hi Alex,
>
> I remember we had a patch to remove the FB location programming in
> gmc/vmhub.
> I saw it's not in gmc v9 in this patch, but pre-gmcv9 still program FB
> register.
>
> Is that any missing for sync here?
> Or it's only supported for gmc v9 now.

I never landed the patches for older asics because I couldn't get vce
to work properly with dal disabled without reprogramming the fb
location.

Alex


>
> Jerry
>
> On 03/21/2017 04:29 AM, Alex Deucher wrote:
>>
>> From: Alex Xie 
>>
>> On SOC-15 parts, the GMC (Graphics Memory Controller) consists
>> of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce).
>>
>> Signed-off-by: Alex Xie 
>> Reviewed-by: Alex Deucher 
>> Signed-off-by: Alex Deucher 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/Makefile  |   6 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  30 ++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |  28 +-
>>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
>>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h |  35 ++
>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 826
>> +++
>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h|  30 ++
>>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 585 ++
>>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h  |  35 ++
>>   drivers/gpu/drm/amd/include/amd_shared.h |   2 +
>>   10 files changed, 2016 insertions(+), 8 deletions(-)
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
>> b/drivers/gpu/drm/amd/amdgpu/Makefile
>> index 69823e8..b5046fd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
>> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
>> @@ -45,7 +45,8 @@ amdgpu-y += \
>>   # add GMC block
>>   amdgpu-y += \
>> gmc_v7_0.o \
>> -   gmc_v8_0.o
>> +   gmc_v8_0.o \
>> +   gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o
>>
>>   # add IH block
>>   amdgpu-y += \
>> @@ -74,7 +75,8 @@ amdgpu-y += \
>>   # add async DMA block
>>   amdgpu-y += \
>> sdma_v2_4.o \
>> -   sdma_v3_0.o
>> +   sdma_v3_0.o \
>> +   sdma_v4_0.o
>>
>>   # add UVD block
>>   amdgpu-y += \
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index aaded8d..d7257b6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -123,6 +123,11 @@ extern int amdgpu_param_buf_per_se;
>>   /* max number of IP instances */
>>   #define AMDGPU_MAX_SDMA_INSTANCES 2
>>
>> +/* max number of VMHUB */
>> +#define AMDGPU_MAX_VMHUBS  2
>> +#define AMDGPU_MMHUB   0
>> +#define AMDGPU_GFXHUB  1
>> +
>>   /* hardcode that limit for now */
>>   #define AMDGPU_VA_RESERVED_SIZE   (8 << 20)
>>
>> @@ -310,6 +315,12 @@ struct amdgpu_gart_funcs {
>>  uint32_t flags);
>>   };
>>
>> +/* provided by the mc block */
>> +struct amdgpu_mc_funcs {
>> +   /* adjust mc addr in fb for APU case */
>> +   u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
>> +};
>> +
>>   /* provided by the ih block */
>>   struct amdgpu_ih_funcs {
>> /* ring read/write ptr handling, called from interrupt context */
>> @@ -559,6 +570,21 @@ int amdgpu_gart_bind(struct amdgpu_device *adev,
>> uint64_t offset,
>>   int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
>>
>>   /*
>> + * VMHUB structures, functions & helpers
>> + */
>> +struct amdgpu_vmhub {
>> +   uint32_tctx0_ptb_addr_lo32;
>> +   uint32_tctx0_ptb_addr_hi32;
>> +   uint32_tvm_inv_eng0_req;
>> +   uint32_tvm_inv_eng0_ack;
>> +   uint32_tvm_context0_cntl;
>> +   uint32_tvm_l2_pro_fault_status;
>> +   uint32_tvm_l2_pro_fault_cntl;
>> +   uint32_t(*get_invalidate_req)(unsigned int vm_id);
>> +   uint32_t(*get_vm_protection_bits)(void);
>> +};
>> +
>> +/*
>>* GPU MC structures, functions & helpers
>>*/
>>   struct amdgpu_mc {
>> @@ -591,6 +617,9 @@ struct amdgpu_mc {
>> u64 shared_aperture_end;
>> u64 private_aperture_start;
>> u64 private_aperture_end;
>> +   /* protects concurrent invalidation */
>> +   spinlock_t  invalidate_lock;
>> +   const struct amdgpu_mc_funcs *mc_funcs;
>>

Re: [PATCH 046/100] drm/amdgpu: Add GMC 9.0 support

2017-03-22 Thread Zhang, Jerry (Junwei) 

Hi Alex,

I remember we had a patch to remove the FB location programming in gmc/vmhub.
I saw it's not in gmc v9 in this patch, but pre-gmcv9 still program FB register.

Is that any missing for sync here?
Or it's only supported for gmc v9 now.

Jerry

On 03/21/2017 04:29 AM, Alex Deucher wrote:

From: Alex Xie 

On SOC-15 parts, the GMC (Graphics Memory Controller) consists
of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce).

Signed-off-by: Alex Xie 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/Makefile  |   6 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  30 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |  28 +-
  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h |  35 ++
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 826 +++
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h|  30 ++
  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 585 ++
  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h  |  35 ++
  drivers/gpu/drm/amd/include/amd_shared.h |   2 +
  10 files changed, 2016 insertions(+), 8 deletions(-)
  create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
  create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
  create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
  create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
  create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
  create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 69823e8..b5046fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -45,7 +45,8 @@ amdgpu-y += \
  # add GMC block
  amdgpu-y += \
gmc_v7_0.o \
-   gmc_v8_0.o
+   gmc_v8_0.o \
+   gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o

  # add IH block
  amdgpu-y += \
@@ -74,7 +75,8 @@ amdgpu-y += \
  # add async DMA block
  amdgpu-y += \
sdma_v2_4.o \
-   sdma_v3_0.o
+   sdma_v3_0.o \
+   sdma_v4_0.o

  # add UVD block
  amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index aaded8d..d7257b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -123,6 +123,11 @@ extern int amdgpu_param_buf_per_se;
  /* max number of IP instances */
  #define AMDGPU_MAX_SDMA_INSTANCES 2

+/* max number of VMHUB */
+#define AMDGPU_MAX_VMHUBS  2
+#define AMDGPU_MMHUB   0
+#define AMDGPU_GFXHUB  1
+
  /* hardcode that limit for now */
  #define AMDGPU_VA_RESERVED_SIZE   (8 << 20)

@@ -310,6 +315,12 @@ struct amdgpu_gart_funcs {
 uint32_t flags);
  };

+/* provided by the mc block */
+struct amdgpu_mc_funcs {
+   /* adjust mc addr in fb for APU case */
+   u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
+};
+
  /* provided by the ih block */
  struct amdgpu_ih_funcs {
/* ring read/write ptr handling, called from interrupt context */
@@ -559,6 +570,21 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t 
offset,
  int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);

  /*
+ * VMHUB structures, functions & helpers
+ */
+struct amdgpu_vmhub {
+   uint32_tctx0_ptb_addr_lo32;
+   uint32_tctx0_ptb_addr_hi32;
+   uint32_tvm_inv_eng0_req;
+   uint32_tvm_inv_eng0_ack;
+   uint32_tvm_context0_cntl;
+   uint32_tvm_l2_pro_fault_status;
+   uint32_tvm_l2_pro_fault_cntl;
+   uint32_t(*get_invalidate_req)(unsigned int vm_id);
+   uint32_t(*get_vm_protection_bits)(void);
+};
+
+/*
   * GPU MC structures, functions & helpers
   */
  struct amdgpu_mc {
@@ -591,6 +617,9 @@ struct amdgpu_mc {
u64 shared_aperture_end;
u64 private_aperture_start;
u64 private_aperture_end;
+   /* protects concurrent invalidation */
+   spinlock_t  invalidate_lock;
+   const struct amdgpu_mc_funcs *mc_funcs;
  };

  /*
@@ -1479,6 +1508,7 @@ struct amdgpu_device {
struct amdgpu_gart  gart;
struct amdgpu_dummy_pagedummy_page;
struct amdgpu_vm_managervm_manager;
+   struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];

/* memory management */
struct amdgpu_mman  mman;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index df615d7..47a8080 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -375,6 +375,16 @@ static

RE: [PATCH 046/100] drm/amdgpu: Add GMC 9.0 support

2017-03-22 Thread Deucher, Alexander 
> -Original Message-
> From: Dave Airlie [mailto:airl...@gmail.com]
> Sent: Wednesday, March 22, 2017 3:48 PM
> To: Alex Deucher
> Cc: amd-gfx mailing list; Deucher, Alexander; Xie, AlexBin
> Subject: Re: [PATCH 046/100] drm/amdgpu: Add GMC 9.0 support
> 
> > +};
> > +
> > +static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device
> *adev,
> > +   struct amdgpu_irq_src *src,
> > +   unsigned type,
> > +   enum amdgpu_interrupt_state state)
> > +{
> > +   struct amdgpu_vmhub *hub;
> > +   u32 tmp, reg, bits, i;
> > +
> > +   switch (state) {
> > +   case AMDGPU_IRQ_STATE_DISABLE:
> > +   /* MM HUB */
> > +   hub = >vmhub[AMDGPU_MMHUB];
> > +   bits = hub->get_vm_protection_bits();
> > +   for (i = 0; i< 16; i++) {
> > +   reg = hub->vm_context0_cntl + i;
> > +   tmp = RREG32(reg);
> > +   tmp &= ~bits;
> > +   WREG32(reg, tmp);
> > +   }
> > +
> > +   /* GFX HUB */
> > +   hub = >vmhub[AMDGPU_GFXHUB];
> > +   bits = hub->get_vm_protection_bits();
> > +   for (i = 0; i < 16; i++) {
> > +   reg = hub->vm_context0_cntl + i;
> > +   tmp = RREG32(reg);
> > +   tmp &= ~bits;
> > +   WREG32(reg, tmp);
> > +   }
> > +   break;
> > +   case AMDGPU_IRQ_STATE_ENABLE:
> > +   /* MM HUB */
> > +   hub = >vmhub[AMDGPU_MMHUB];
> > +   bits = hub->get_vm_protection_bits();
> > +   for (i = 0; i< 16; i++) {
> > +   reg = hub->vm_context0_cntl + i;
> > +   tmp = RREG32(reg);
> > +   tmp |= bits;
> > +   WREG32(reg, tmp);
> > +   }
> > +
> > +   /* GFX HUB */
> > +   hub = >vmhub[AMDGPU_GFXHUB];
> > +   bits = hub->get_vm_protection_bits();
> > +   for (i = 0; i < 16; i++) {
> > +   reg = hub->vm_context0_cntl + i;
> > +   tmp = RREG32(reg);
> > +   tmp |= bits;
> > +   WREG32(reg, tmp);
> > +   }
> > +   break;
> > +   default:
> > +   break;
> > +   }
> > +
> > +   return 0;
> > +   return 0;
> > +}
> > +
> 
> Probably only need one :-)

Fixed locally.  Thanks!

Alex

> 
> Dave.
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Re: [PATCH 046/100] drm/amdgpu: Add GMC 9.0 support

2017-03-22 Thread Dave Airlie 
> +};
> +
> +static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
> +   struct amdgpu_irq_src *src,
> +   unsigned type,
> +   enum amdgpu_interrupt_state state)
> +{
> +   struct amdgpu_vmhub *hub;
> +   u32 tmp, reg, bits, i;
> +
> +   switch (state) {
> +   case AMDGPU_IRQ_STATE_DISABLE:
> +   /* MM HUB */
> +   hub = >vmhub[AMDGPU_MMHUB];
> +   bits = hub->get_vm_protection_bits();
> +   for (i = 0; i< 16; i++) {
> +   reg = hub->vm_context0_cntl + i;
> +   tmp = RREG32(reg);
> +   tmp &= ~bits;
> +   WREG32(reg, tmp);
> +   }
> +
> +   /* GFX HUB */
> +   hub = >vmhub[AMDGPU_GFXHUB];
> +   bits = hub->get_vm_protection_bits();
> +   for (i = 0; i < 16; i++) {
> +   reg = hub->vm_context0_cntl + i;
> +   tmp = RREG32(reg);
> +   tmp &= ~bits;
> +   WREG32(reg, tmp);
> +   }
> +   break;
> +   case AMDGPU_IRQ_STATE_ENABLE:
> +   /* MM HUB */
> +   hub = >vmhub[AMDGPU_MMHUB];
> +   bits = hub->get_vm_protection_bits();
> +   for (i = 0; i< 16; i++) {
> +   reg = hub->vm_context0_cntl + i;
> +   tmp = RREG32(reg);
> +   tmp |= bits;
> +   WREG32(reg, tmp);
> +   }
> +
> +   /* GFX HUB */
> +   hub = >vmhub[AMDGPU_GFXHUB];
> +   bits = hub->get_vm_protection_bits();
> +   for (i = 0; i < 16; i++) {
> +   reg = hub->vm_context0_cntl + i;
> +   tmp = RREG32(reg);
> +   tmp |= bits;
> +   WREG32(reg, tmp);
> +   }
> +   break;
> +   default:
> +   break;
> +   }
> +
> +   return 0;
> +   return 0;
> +}
> +

Probably only need one :-)

Dave.
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Re: [PATCH 046/100] drm/amdgpu: Add GMC 9.0 support

2017-03-22 Thread Alex Deucher 
On Tue, Mar 21, 2017 at 4:49 AM, Christian König
 wrote:
> Am 20.03.2017 um 21:29 schrieb Alex Deucher:
>>
>> From: Alex Xie 
>>
>> On SOC-15 parts, the GMC (Graphics Memory Controller) consists
>> of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce).
>>
>> Signed-off-by: Alex Xie 
>> Reviewed-by: Alex Deucher 
>> Signed-off-by: Alex Deucher 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/Makefile  |   6 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  30 ++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |  28 +-
>>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
>>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h |  35 ++
>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 826
>> +++
>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h|  30 ++
>>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 585 ++
>>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h  |  35 ++
>>   drivers/gpu/drm/amd/include/amd_shared.h |   2 +
>>   10 files changed, 2016 insertions(+), 8 deletions(-)
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
>> b/drivers/gpu/drm/amd/amdgpu/Makefile
>> index 69823e8..b5046fd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
>> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
>> @@ -45,7 +45,8 @@ amdgpu-y += \
>>   # add GMC block
>>   amdgpu-y += \
>> gmc_v7_0.o \
>> -   gmc_v8_0.o
>> +   gmc_v8_0.o \
>> +   gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o
>> # add IH block
>>   amdgpu-y += \
>> @@ -74,7 +75,8 @@ amdgpu-y += \
>>   # add async DMA block
>>   amdgpu-y += \
>> sdma_v2_4.o \
>> -   sdma_v3_0.o
>> +   sdma_v3_0.o \
>> +   sdma_v4_0.o
>
>
> That change doesn't belong into this patch.

Fixed.

>
>> # add UVD block
>>   amdgpu-y += \
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index aaded8d..d7257b6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -123,6 +123,11 @@ extern int amdgpu_param_buf_per_se;
>>   /* max number of IP instances */
>>   #define AMDGPU_MAX_SDMA_INSTANCES 2
>>   +/* max number of VMHUB */
>> +#define AMDGPU_MAX_VMHUBS  2
>> +#define AMDGPU_MMHUB   0
>> +#define AMDGPU_GFXHUB  1
>> +
>>   /* hardcode that limit for now */
>>   #define AMDGPU_VA_RESERVED_SIZE   (8 << 20)
>>   @@ -310,6 +315,12 @@ struct amdgpu_gart_funcs {
>>  uint32_t flags);
>>   };
>>   +/* provided by the mc block */
>> +struct amdgpu_mc_funcs {
>> +   /* adjust mc addr in fb for APU case */
>> +   u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
>> +};
>> +
>
>
> That isn't hardware specific and actually incorrectly implemented.
>
> The calculation depends on the NB on APUs, not the GPU part and the current
> implementation probably breaks it for Carizzo and others APUs.

The behavior shouldn't change for existing asics.
amdgpu_vm_adjust_mc_addr() just passes the address through directly if
there is no callback defined which matches the current behavior.  If
that is wrong, the current code would be broken.

>
> I suggest to just remove the callback and move the calculation into
> amdgpu_vm_adjust_mc_addr().
>
> Then rename amdgpu_vm_adjust_mc_addr() to amdgpu_vm_get_pde() and call it
> from amdgpu_vm_update_page_directory() as well as the GFX9 specifc flush
> functions.

I'm not sure I follow what you are suggesting. The rename makes sense,
but why move the logic from asic specific code to generic code?  That
will break older asics.

>
>>   /* provided by the ih block */
>>   struct amdgpu_ih_funcs {
>> /* ring read/write ptr handling, called from interrupt context */
>> @@ -559,6 +570,21 @@ int amdgpu_gart_bind(struct amdgpu_device *adev,
>> uint64_t offset,
>>   int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
>> /*
>> + * VMHUB structures, functions & helpers
>> + */
>> +struct amdgpu_vmhub {
>> +   uint32_tctx0_ptb_addr_lo32;
>> +   uint32_tctx0_ptb_addr_hi32;
>> +   uint32_tvm_inv_eng0_req;
>> +   uint32_tvm_inv_eng0_ack;
>> +   uint32_tvm_context0_cntl;
>> +   uint32_tvm_l2_pro_fault_status;
>> +   uint32_tvm_l2_pro_fault_cntl;
>> +   uint32_t(*get_invalidate_req)(unsigned int vm_id);
>> +   uint32_t

Re: [PATCH 046/100] drm/amdgpu: Add GMC 9.0 support

2017-03-22 Thread Christian König 

Am 21.03.2017 um 16:09 schrieb Deucher, Alexander:

[SNIP]
Those two callbacks aren't a good idea either.

The invalidation request bits are defined by the RTL of the HUB which is
just instantiated twice, see the register database for details.

We should probably make those functions in the gmc_v9_0.c which are
called from the device specific flush methods.

Didn't you have some patches to clean up the gfxhub/mmhub split?  I don't think 
they ever landed.


Yeah, a good part of that landed.

But some patches broke horrible because I didn't had hardware to test at 
that time. So I didn't pursued working on that till we have hardware.


Most of the stuff can land later on, it's just that this looks like it 
will break Carrizo/Kaveri/Kabini because of the incorrect handling.


We should make sure those still work before we push this upstream.

Christian.



Alex


Regards,
Christian.


+};
+
+/*
* GPU MC structures, functions & helpers
*/
   struct amdgpu_mc {
@@ -591,6 +617,9 @@ struct amdgpu_mc {
u64 shared_aperture_end;
u64 private_aperture_start;
u64 private_aperture_end;
+   /* protects concurrent invalidation */
+   spinlock_t  invalidate_lock;
+   const struct amdgpu_mc_funcs *mc_funcs;
   };

   /*
@@ -1479,6 +1508,7 @@ struct amdgpu_device {
struct amdgpu_gart  gart;
struct amdgpu_dummy_pagedummy_page;
struct amdgpu_vm_managervm_manager;
+   struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];

/* memory management */
struct amdgpu_mman  mman;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index df615d7..47a8080 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -375,6 +375,16 @@ static bool

amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)

return false;
   }

+static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev,

u64 mc_addr)

+{
+   u64 addr = mc_addr;
+
+   if (adev->mc.mc_funcs && adev->mc.mc_funcs->adjust_mc_addr)
+   addr = adev->mc.mc_funcs->adjust_mc_addr(adev, addr);
+
+   return addr;
+}
+
   /**
* amdgpu_vm_flush - hardware flush the vm
*
@@ -405,9 +415,10 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,

struct amdgpu_job *job)

if (ring->funcs->emit_vm_flush && (job->vm_needs_flush ||
amdgpu_vm_is_gpu_reset(adev, id))) {
struct fence *fence;
+   u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job-
vm_pd_addr);

-   trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job-
vm_id);
-   amdgpu_ring_emit_vm_flush(ring, job->vm_id, job-
vm_pd_addr);
+   trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
+   amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);

r = amdgpu_fence_emit(ring, );
if (r)
@@ -643,15 +654,18 @@ int amdgpu_vm_update_page_directory(struct

amdgpu_device *adev,

(count == AMDGPU_VM_MAX_UPDATE_SIZE)) {

if (count) {
+   uint64_t pt_addr =
+   amdgpu_vm_adjust_mc_addr(adev,

last_pt);

+
if (shadow)
amdgpu_vm_do_set_ptes(,
  last_shadow,
- last_pt, count,
+ pt_addr, count,
  incr,


AMDGPU_PTE_VALID);

amdgpu_vm_do_set_ptes(,

last_pde,

- last_pt, count, incr,
+ pt_addr, count, incr,
  AMDGPU_PTE_VALID);
}

@@ -665,11 +679,13 @@ int amdgpu_vm_update_page_directory(struct

amdgpu_device *adev,

}

if (count) {
+   uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev,

last_pt);

+
if (vm->page_directory->shadow)
-   amdgpu_vm_do_set_ptes(, last_shadow,

last_pt,

+   amdgpu_vm_do_set_ptes(, last_shadow,

pt_addr,

  count, incr,

AMDGPU_PTE_VALID);

-   amdgpu_vm_do_set_ptes(, last_pde, last_pt,
+   amdgpu_vm_do_set_ptes(, last_pde, pt_addr,
  count, incr, AMDGPU_PTE_VALID);
}

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

new file mode 100644
index 000..1ff019c
--- /dev/null

Re: [PATCH 046/100] drm/amdgpu: Add GMC 9.0 support

2017-03-21 Thread Christian König 

Am 20.03.2017 um 21:29 schrieb Alex Deucher:

From: Alex Xie 

On SOC-15 parts, the GMC (Graphics Memory Controller) consists
of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce).

Signed-off-by: Alex Xie 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/Makefile  |   6 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  30 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |  28 +-
  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h |  35 ++
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 826 +++
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h|  30 ++
  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 585 ++
  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h  |  35 ++
  drivers/gpu/drm/amd/include/amd_shared.h |   2 +
  10 files changed, 2016 insertions(+), 8 deletions(-)
  create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
  create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
  create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
  create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
  create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
  create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 69823e8..b5046fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -45,7 +45,8 @@ amdgpu-y += \
  # add GMC block
  amdgpu-y += \
gmc_v7_0.o \
-   gmc_v8_0.o
+   gmc_v8_0.o \
+   gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o
  
  # add IH block

  amdgpu-y += \
@@ -74,7 +75,8 @@ amdgpu-y += \
  # add async DMA block
  amdgpu-y += \
sdma_v2_4.o \
-   sdma_v3_0.o
+   sdma_v3_0.o \
+   sdma_v4_0.o


That change doesn't belong into this patch.

  
  # add UVD block

  amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index aaded8d..d7257b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -123,6 +123,11 @@ extern int amdgpu_param_buf_per_se;
  /* max number of IP instances */
  #define AMDGPU_MAX_SDMA_INSTANCES 2
  
+/* max number of VMHUB */

+#define AMDGPU_MAX_VMHUBS  2
+#define AMDGPU_MMHUB   0
+#define AMDGPU_GFXHUB  1
+
  /* hardcode that limit for now */
  #define AMDGPU_VA_RESERVED_SIZE   (8 << 20)
  
@@ -310,6 +315,12 @@ struct amdgpu_gart_funcs {

 uint32_t flags);
  };
  
+/* provided by the mc block */

+struct amdgpu_mc_funcs {
+   /* adjust mc addr in fb for APU case */
+   u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
+};
+


That isn't hardware specific and actually incorrectly implemented.

The calculation depends on the NB on APUs, not the GPU part and the 
current implementation probably breaks it for Carizzo and others APUs.


I suggest to just remove the callback and move the calculation into 
amdgpu_vm_adjust_mc_addr().


Then rename amdgpu_vm_adjust_mc_addr() to amdgpu_vm_get_pde() and call 
it from amdgpu_vm_update_page_directory() as well as the GFX9 specifc 
flush functions.



  /* provided by the ih block */
  struct amdgpu_ih_funcs {
/* ring read/write ptr handling, called from interrupt context */
@@ -559,6 +570,21 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t 
offset,
  int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
  
  /*

+ * VMHUB structures, functions & helpers
+ */
+struct amdgpu_vmhub {
+   uint32_tctx0_ptb_addr_lo32;
+   uint32_tctx0_ptb_addr_hi32;
+   uint32_tvm_inv_eng0_req;
+   uint32_tvm_inv_eng0_ack;
+   uint32_tvm_context0_cntl;
+   uint32_tvm_l2_pro_fault_status;
+   uint32_tvm_l2_pro_fault_cntl;
+   uint32_t(*get_invalidate_req)(unsigned int vm_id);
+   uint32_t(*get_vm_protection_bits)(void);


Those two callbacks aren't a good idea either.

The invalidation request bits are defined by the RTL of the HUB which is 
just instantiated twice, see the register database for details.


We should probably make those functions in the gmc_v9_0.c which are 
called from the device specific flush methods.


Regards,
Christian.


+};
+
+/*
   * GPU MC structures, functions & helpers
   */
  struct amdgpu_mc {
@@ -591,6 +617,9 @@ struct amdgpu_mc {
u64 shared_aperture_end;
u64 private_aperture_start;
u64 private_aperture_end;
+   /* protects concurrent invalidation */
+   spinlock_t  invalidate_lock;
+   const struct

[PATCH 046/100] drm/amdgpu: Add GMC 9.0 support

2017-03-20 Thread Alex Deucher 
From: Alex Xie 

On SOC-15 parts, the GMC (Graphics Memory Controller) consists
of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce).

Signed-off-by: Alex Xie 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/Makefile  |   6 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  30 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |  28 +-
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h |  35 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 826 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h|  30 ++
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 585 ++
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h  |  35 ++
 drivers/gpu/drm/amd/include/amd_shared.h |   2 +
 10 files changed, 2016 insertions(+), 8 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 69823e8..b5046fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -45,7 +45,8 @@ amdgpu-y += \
 # add GMC block
 amdgpu-y += \
gmc_v7_0.o \
-   gmc_v8_0.o
+   gmc_v8_0.o \
+   gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o
 
 # add IH block
 amdgpu-y += \
@@ -74,7 +75,8 @@ amdgpu-y += \
 # add async DMA block
 amdgpu-y += \
sdma_v2_4.o \
-   sdma_v3_0.o
+   sdma_v3_0.o \
+   sdma_v4_0.o
 
 # add UVD block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index aaded8d..d7257b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -123,6 +123,11 @@ extern int amdgpu_param_buf_per_se;
 /* max number of IP instances */
 #define AMDGPU_MAX_SDMA_INSTANCES  2
 
+/* max number of VMHUB */
+#define AMDGPU_MAX_VMHUBS  2
+#define AMDGPU_MMHUB   0
+#define AMDGPU_GFXHUB  1
+
 /* hardcode that limit for now */
 #define AMDGPU_VA_RESERVED_SIZE(8 << 20)
 
@@ -310,6 +315,12 @@ struct amdgpu_gart_funcs {
 uint32_t flags);
 };
 
+/* provided by the mc block */
+struct amdgpu_mc_funcs {
+   /* adjust mc addr in fb for APU case */
+   u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
+};
+
 /* provided by the ih block */
 struct amdgpu_ih_funcs {
/* ring read/write ptr handling, called from interrupt context */
@@ -559,6 +570,21 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t 
offset,
 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
 
 /*
+ * VMHUB structures, functions & helpers
+ */
+struct amdgpu_vmhub {
+   uint32_tctx0_ptb_addr_lo32;
+   uint32_tctx0_ptb_addr_hi32;
+   uint32_tvm_inv_eng0_req;
+   uint32_tvm_inv_eng0_ack;
+   uint32_tvm_context0_cntl;
+   uint32_tvm_l2_pro_fault_status;
+   uint32_tvm_l2_pro_fault_cntl;
+   uint32_t(*get_invalidate_req)(unsigned int vm_id);
+   uint32_t(*get_vm_protection_bits)(void);
+};
+
+/*
  * GPU MC structures, functions & helpers
  */
 struct amdgpu_mc {
@@ -591,6 +617,9 @@ struct amdgpu_mc {
u64 shared_aperture_end;
u64 private_aperture_start;
u64 private_aperture_end;
+   /* protects concurrent invalidation */
+   spinlock_t  invalidate_lock;
+   const struct amdgpu_mc_funcs *mc_funcs;
 };
 
 /*
@@ -1479,6 +1508,7 @@ struct amdgpu_device {
struct amdgpu_gart  gart;
struct amdgpu_dummy_pagedummy_page;
struct amdgpu_vm_managervm_manager;
+   struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
 
/* memory management */
struct amdgpu_mman  mman;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index df615d7..47a8080 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -375,6 +375,16 @@ static bool amdgpu_vm_ring_has_compute_vm_bug(struct 
amdgpu_ring *ring)
return false;
 }
 
+static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
+{
+   u64 addr = mc_addr;
+
+   if (adev->mc.mc_funcs && adev->mc.mc_funcs->adjust_mc_addr)
+   addr =